diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual')
5 files changed, 0 insertions, 2586 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini deleted file mode 100644 index 55e1410b6..000000000 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ /dev/null @@ -1,1442 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=true -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=LinuxAlphaSystem -children=bridge clk_domain cpu0 cpu1 cpu_clk_domain disk0 disk2 dvfs_handler intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami voltage_domain -boot_cpu_frequency=500 -boot_osflags=root=/dev/hda1 console=ttyS0 -cache_line_size=64 -clk_domain=system.clk_domain -console=/arm/projectscratch/randd/systems/dist/binaries/console -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=atomic -mem_ranges=0:134217727 -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal -power_model=Null -readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh -symbolfile= -system_rev=1024 -system_type=34 -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.bridge] -type=Bridge -clk_domain=system.clk_domain -default_p_state=UNDEFINED -delay=50000 -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -ranges=8796093022208:18446744073709551615 -req_size=16 -resp_size=16 -master=system.iobus.slave[0] -slave=system.membus.master[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu0] -type=AtomicSimpleCPU -children=dcache dtb icache interrupts isa itb tracer -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu0.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu0.interrupts -isa=system.cpu0.isa -itb=system.cpu0.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -system=system -tracer=system.cpu0.tracer -width=1 -workload= -dcache_port=system.cpu0.dcache.cpu_side -icache_port=system.cpu0.icache.cpu_side - -[system.cpu0.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu0.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu0.dcache_port -mem_side=system.toL2Bus.slave[1] - -[system.cpu0.dcache.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu0.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu0.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=1 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu0.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu0.icache_port -mem_side=system.toL2Bus.slave[0] - -[system.cpu0.icache.tags] -type=LRU -assoc=1 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu0.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu0.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu0.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu0.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu1] -type=AtomicSimpleCPU -children=dcache dtb icache interrupts isa itb tracer -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=1 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu1.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu1.interrupts -isa=system.cpu1.isa -itb=system.cpu1.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -system=system -tracer=system.cpu1.tracer -width=1 -workload= -dcache_port=system.cpu1.dcache.cpu_side -icache_port=system.cpu1.icache.cpu_side - -[system.cpu1.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu1.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu1.dcache_port -mem_side=system.toL2Bus.slave[3] - -[system.cpu1.dcache.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu1.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu1.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=1 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu1.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu1.icache_port -mem_side=system.toL2Bus.slave[2] - -[system.cpu1.icache.tags] -type=LRU -assoc=1 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu1.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu1.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu1.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu1.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.disk0] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=system.disk0.image - -[system.disk0.image] -type=CowDiskImage -children=child -child=system.disk0.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[system.disk0.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img -read_only=true - -[system.disk2] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=system.disk2.image - -[system.disk2.image] -type=CowDiskImage -children=child -child=system.disk2.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[system.disk2.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-bigswap2.img -read_only=true - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.intrctrl] -type=IntrControl -eventq_index=0 -sys=system - -[system.iobus] -type=NoncoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=1 -frontend_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -response_latency=2 -use_default_range=false -width=16 -master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side -slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma - -[system.iocache] -type=Cache -children=tags -addr_ranges=0:134217727 -assoc=8 -clk_domain=system.clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=50 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=50 -sequential_access=false -size=1024 -system=system -tags=system.iocache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.iobus.master[27] -mem_side=system.membus.slave[2] - -[system.iocache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=50 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=1024 - -[system.l2c] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=4194304 -system=system -tags=system.l2c.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.l2c.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=4194304 - -[system.membus] -type=CoherentXBar -children=badaddr_responder snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.physmem.port -slave=system.system_port system.l2c.mem_side system.iocache.mem_side - -[system.membus.badaddr_responder] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=0 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=true -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.membus.default - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727 -port=system.membus.master[1] - -[system.simple_disk] -type=SimpleDisk -children=disk -disk=system.simple_disk.disk -eventq_index=0 -system=system - -[system.simple_disk.disk] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img -read_only=true - -[system.terminal] -type=Terminal -eventq_index=0 -intr_control=system.intrctrl -number=0 -output=true -port=3456 - -[system.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.l2c.cpu_side -slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side - -[system.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.tsunami] -type=Tsunami -children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart -eventq_index=0 -intrctrl=system.intrctrl -system=system - -[system.tsunami.backdoor] -type=AlphaBackdoor -clk_domain=system.clk_domain -cpu=system.cpu0 -default_p_state=UNDEFINED -disk=system.simple_disk -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804682956800 -pio_latency=100000 -platform=system.tsunami -power_model=Null -system=system -terminal=system.terminal -pio=system.iobus.master[24] - -[system.tsunami.cchip] -type=TsunamiCChip -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8803072344064 -pio_latency=100000 -power_model=Null -system=system -tsunami=system.tsunami -pio=system.iobus.master[0] - -[system.tsunami.ethernet] -type=NSGigE -BAR0=1 -BAR0LegacyIO=false -BAR0Size=256 -BAR1=0 -BAR1LegacyIO=false -BAR1Size=4096 -BAR2=0 -BAR2LegacyIO=false -BAR2Size=0 -BAR3=0 -BAR3LegacyIO=false -BAR3Size=0 -BAR4=0 -BAR4LegacyIO=false -BAR4Size=0 -BAR5=0 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=2 -Command=0 -DeviceID=34 -ExpansionROM=0 -HeaderType=0 -InterruptLine=30 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=52 -MinimumGrant=176 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=0 -Revision=0 -Status=656 -SubClassCode=0 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=4107 -clk_domain=system.clk_domain -config_latency=20000 -default_p_state=UNDEFINED -dma_data_free=false -dma_desc_free=false -dma_no_allocate=true -dma_read_delay=0 -dma_read_factor=0 -dma_write_delay=0 -dma_write_factor=0 -eventq_index=0 -hardware_address=00:90:00:00:00:01 -host=system.tsunami.pchip -intr_delay=10000000 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=1 -pci_func=0 -pio_latency=30000 -power_model=Null -rss=false -rx_delay=1000000 -rx_fifo_size=524288 -rx_filter=true -rx_thread=false -system=system -tx_delay=1000000 -tx_fifo_size=524288 -tx_thread=false -dma=system.iobus.slave[2] -pio=system.iobus.master[26] - -[system.tsunami.fake_OROM] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8796093677568 -pio_latency=100000 -pio_size=393216 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[8] - -[system.tsunami.fake_ata0] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848432 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[19] - -[system.tsunami.fake_ata1] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848304 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[20] - -[system.tsunami.fake_pnp_addr] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848569 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[9] - -[system.tsunami.fake_pnp_read0] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848451 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[11] - -[system.tsunami.fake_pnp_read1] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848515 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[12] - -[system.tsunami.fake_pnp_read2] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848579 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[13] - -[system.tsunami.fake_pnp_read3] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848643 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[14] - -[system.tsunami.fake_pnp_read4] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848707 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[15] - -[system.tsunami.fake_pnp_read5] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848771 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[16] - -[system.tsunami.fake_pnp_read6] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848835 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[17] - -[system.tsunami.fake_pnp_read7] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848899 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[18] - -[system.tsunami.fake_pnp_write] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615850617 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[10] - -[system.tsunami.fake_ppc] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848891 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[7] - -[system.tsunami.fake_sm_chip] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848816 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[2] - -[system.tsunami.fake_uart1] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848696 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[3] - -[system.tsunami.fake_uart2] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848936 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[4] - -[system.tsunami.fake_uart3] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848680 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[5] - -[system.tsunami.fake_uart4] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848944 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[6] - -[system.tsunami.fb] -type=BadDevice -clk_domain=system.clk_domain -default_p_state=UNDEFINED -devicename=FrameBuffer -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848912 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[21] - -[system.tsunami.ide] -type=IdeController -BAR0=1 -BAR0LegacyIO=false -BAR0Size=8 -BAR1=1 -BAR1LegacyIO=false -BAR1Size=4 -BAR2=1 -BAR2LegacyIO=false -BAR2Size=8 -BAR3=1 -BAR3LegacyIO=false -BAR3Size=4 -BAR4=1 -BAR4LegacyIO=false -BAR4Size=16 -BAR5=1 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=1 -Command=0 -DeviceID=28945 -ExpansionROM=0 -HeaderType=0 -InterruptLine=31 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=0 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=133 -Revision=0 -Status=640 -SubClassCode=1 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -ctrl_offset=0 -default_p_state=UNDEFINED -disks=system.disk0 system.disk2 -eventq_index=0 -host=system.tsunami.pchip -io_shift=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=0 -pci_func=0 -pio_latency=30000 -power_model=Null -system=system -dma=system.iobus.slave[1] -pio=system.iobus.master[25] - -[system.tsunami.io] -type=TsunamiIO -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -frequency=976562500 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615847936 -pio_latency=100000 -power_model=Null -system=system -time=Thu Jan 1 00:00:00 2009 -tsunami=system.tsunami -year_is_bcd=false -pio=system.iobus.master[22] - -[system.tsunami.pchip] -type=TsunamiPChip -clk_domain=system.clk_domain -conf_base=8804649402368 -conf_device_bits=8 -conf_size=16777216 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_dma_base=0 -pci_mem_base=8796093022208 -pci_pio_base=8804615847936 -pio_addr=8802535473152 -pio_latency=100000 -platform=system.tsunami -power_model=Null -system=system -tsunami=system.tsunami -pio=system.iobus.master[1] - -[system.tsunami.uart] -type=Uart8250 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848952 -pio_latency=100000 -platform=system.tsunami -power_model=Null -system=system -terminal=system.terminal -pio=system.iobus.master[23] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr deleted file mode 100755 index 25e6a47e4..000000000 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr +++ /dev/null @@ -1,6 +0,0 @@ -warn: Sockets disabled, not accepting terminal connections -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout deleted file mode 100755 index a53acdd5f..000000000 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout +++ /dev/null @@ -1,16 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 19 2016 12:24:26 -gem5 executing on e108600-lin, pid 39599 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual - -Global frequency set at 1000000000000 ticks per second -info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 97861500 -Exiting @ tick 1869357999000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt deleted file mode 100644 index 54bff4f85..000000000 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ /dev/null @@ -1,1010 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 1.869358 # Number of seconds simulated -sim_ticks 1869358054000 # Number of ticks simulated -final_tick 1869358054000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2951277 # Simulator instruction rate (inst/s) -host_op_rate 2951276 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 84876880961 # Simulator tick rate (ticks/s) -host_mem_usage 336132 # Number of bytes of host memory used -host_seconds 22.02 # Real time elapsed on the host -sim_insts 64999904 # Number of instructions simulated -sim_ops 64999904 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.inst 758272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 66535744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 106112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 766400 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 68167488 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 758272 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 106112 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 864384 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7837888 # Number of bytes written to this memory -system.physmem.bytes_written::total 7837888 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11848 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 1039621 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1658 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 11975 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1065117 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122467 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122467 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 405632 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 35592830 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 56764 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 409980 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 514 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36465720 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 405632 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 56764 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 462396 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4192823 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4192823 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4192823 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 405632 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 35592830 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 56764 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 409980 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40658544 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dtb.fetch_hits 0 # ITB hits -system.cpu0.dtb.fetch_misses 0 # ITB misses -system.cpu0.dtb.fetch_acv 0 # ITB acv -system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7758808 # DTB read hits -system.cpu0.dtb.read_misses 7155 # DTB read misses -system.cpu0.dtb.read_acv 152 # DTB read access violations -system.cpu0.dtb.read_accesses 531148 # DTB read accesses -system.cpu0.dtb.write_hits 4740251 # DTB write hits -system.cpu0.dtb.write_misses 732 # DTB write misses -system.cpu0.dtb.write_acv 102 # DTB write access violations -system.cpu0.dtb.write_accesses 201714 # DTB write accesses -system.cpu0.dtb.data_hits 12499059 # DTB hits -system.cpu0.dtb.data_misses 7887 # DTB misses -system.cpu0.dtb.data_acv 254 # DTB access violations -system.cpu0.dtb.data_accesses 732862 # DTB accesses -system.cpu0.itb.fetch_hits 3525726 # ITB hits -system.cpu0.itb.fetch_misses 3572 # ITB misses -system.cpu0.itb.fetch_acv 127 # ITB acv -system.cpu0.itb.fetch_accesses 3529298 # ITB accesses -system.cpu0.itb.read_hits 0 # DTB read hits -system.cpu0.itb.read_misses 0 # DTB read misses -system.cpu0.itb.read_acv 0 # DTB read access violations -system.cpu0.itb.read_accesses 0 # DTB read accesses -system.cpu0.itb.write_hits 0 # DTB write hits -system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.write_acv 0 # DTB write access violations -system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.data_hits 0 # DTB hits -system.cpu0.itb.data_misses 0 # DTB misses -system.cpu0.itb.data_acv 0 # DTB access violations -system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numPwrStateTransitions 13588 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 6794 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 271506712.952752 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 434955679.637595 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 6794 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 21000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 6794 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 24741446199 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 1844616607801 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 3738722903 # number of cpu cycles simulated -system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 150435 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 51398 40.00% 40.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 243 0.19% 40.19% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1907 1.48% 41.67% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 514 0.40% 42.07% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 74446 57.93% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 128508 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 51050 48.97% 48.97% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 243 0.23% 49.20% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1907 1.83% 51.03% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 514 0.49% 51.52% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 50536 48.48% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 104250 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1853222787000 99.14% 99.14% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.14% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 82001000 0.00% 99.14% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 57621500 0.00% 99.15% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 15975327000 0.85% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1869357846500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.993229 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.678828 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.811234 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 616 0.45% 0.45% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.45% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.46% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.46% # number of callpals executed -system.cpu0.kern.callpal::swpctx 2743 2.02% 2.47% # number of callpals executed -system.cpu0.kern.callpal::tbi 39 0.03% 2.50% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.01% 2.51% # number of callpals executed -system.cpu0.kern.callpal::swpipl 121668 89.51% 92.02% # number of callpals executed -system.cpu0.kern.callpal::rdps 6149 4.52% 96.54% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.54% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.54% # number of callpals executed -system.cpu0.kern.callpal::rdusp 7 0.01% 96.55% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.55% # number of callpals executed -system.cpu0.kern.callpal::rti 4175 3.07% 99.62% # number of callpals executed -system.cpu0.kern.callpal::callsys 369 0.27% 99.89% # number of callpals executed -system.cpu0.kern.callpal::imb 146 0.11% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 135929 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6593 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1173 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1172 -system.cpu0.kern.mode_good::user 1173 -system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.177764 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.301957 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1868349218500 99.95% 99.95% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1008627000 0.05% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 2744 # number of times the context was actually changed -system.cpu0.committedInsts 49477745 # Number of instructions committed -system.cpu0.committedOps 49477745 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 46201705 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 197598 # Number of float alu accesses -system.cpu0.num_func_calls 1124633 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 6043603 # number of instructions that are conditional controls -system.cpu0.num_int_insts 46201705 # number of integer instructions -system.cpu0.num_fp_insts 197598 # number of float instructions -system.cpu0.num_int_register_reads 64003225 # number of times the integer registers were read -system.cpu0.num_int_register_writes 34834421 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 97440 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 98967 # number of times the floating registers were written -system.cpu0.num_mem_refs 12536107 # number of memory refs -system.cpu0.num_load_insts 7783754 # Number of load instructions -system.cpu0.num_store_insts 4752353 # Number of store instructions -system.cpu0.num_idle_cycles 3689239920.666412 # Number of idle cycles -system.cpu0.num_busy_cycles 49482982.333588 # Number of busy cycles -system.cpu0.not_idle_fraction 0.013235 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.986765 # Percentage of idle cycles -system.cpu0.Branches 7530826 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2589816 5.23% 5.23% # Class of executed instruction -system.cpu0.op_class::IntAlu 33436017 67.57% 72.80% # Class of executed instruction -system.cpu0.op_class::IntMult 50540 0.10% 72.90% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 72.90% # Class of executed instruction -system.cpu0.op_class::FloatAdd 27840 0.06% 72.96% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::FloatMultAcc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::FloatDiv 2233 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::FloatMisc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::MemRead 7859946 15.88% 88.85% # Class of executed instruction -system.cpu0.op_class::MemWrite 4676411 9.45% 98.30% # Class of executed instruction -system.cpu0.op_class::FloatMemRead 85644 0.17% 98.47% # Class of executed instruction -system.cpu0.op_class::FloatMemWrite 81881 0.17% 98.63% # Class of executed instruction -system.cpu0.op_class::IprAccess 675558 1.37% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 49485886 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 1781367 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.187332 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10705767 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1781879 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 6.008134 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.187332 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988647 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.988647 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 446 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51822038 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51822038 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 6068885 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6068885 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4360096 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4360096 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 127592 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 127592 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 132871 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 132871 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10428981 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10428981 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10428981 # number of overall hits -system.cpu0.dcache.overall_hits::total 10428981 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1560065 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1560065 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 236527 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 236527 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 12626 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 12626 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6899 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 6899 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1796592 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1796592 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1796592 # number of overall misses -system.cpu0.dcache.overall_misses::total 1796592 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7628950 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7628950 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4596623 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4596623 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 140218 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 140218 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 139770 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 139770 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12225573 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12225573 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12225573 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12225573 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.204493 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.204493 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051457 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051457 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.090046 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.090046 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049360 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.049360 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.146954 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.146954 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.146954 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.146954 # miss rate for overall accesses -system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 633925 # number of writebacks -system.cpu0.dcache.writebacks::total 633925 # number of writebacks -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 618292 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.240644 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 48866947 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 618804 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 78.969992 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 9786048500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.240644 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998517 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998517 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 333 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 50104825 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 50104825 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 48866947 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 48866947 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 48866947 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 48866947 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 48866947 # number of overall hits -system.cpu0.icache.overall_hits::total 48866947 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 618939 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 618939 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 618939 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 618939 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 618939 # number of overall misses -system.cpu0.icache.overall_misses::total 618939 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 49485886 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 49485886 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 49485886 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 49485886 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 49485886 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 49485886 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012507 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.012507 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012507 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.012507 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012507 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.012507 # miss rate for overall accesses -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 618292 # number of writebacks -system.cpu0.icache.writebacks::total 618292 # number of writebacks -system.cpu1.dtb.fetch_hits 0 # ITB hits -system.cpu1.dtb.fetch_misses 0 # ITB misses -system.cpu1.dtb.fetch_acv 0 # ITB acv -system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2831559 # DTB read hits -system.cpu1.dtb.read_misses 3191 # DTB read misses -system.cpu1.dtb.read_acv 58 # DTB read access violations -system.cpu1.dtb.read_accesses 198160 # DTB read accesses -system.cpu1.dtb.write_hits 2101673 # DTB write hits -system.cpu1.dtb.write_misses 412 # DTB write misses -system.cpu1.dtb.write_acv 55 # DTB write access violations -system.cpu1.dtb.write_accesses 90619 # DTB write accesses -system.cpu1.dtb.data_hits 4933232 # DTB hits -system.cpu1.dtb.data_misses 3603 # DTB misses -system.cpu1.dtb.data_acv 113 # DTB access violations -system.cpu1.dtb.data_accesses 288779 # DTB accesses -system.cpu1.itb.fetch_hits 1950883 # ITB hits -system.cpu1.itb.fetch_misses 1451 # ITB misses -system.cpu1.itb.fetch_acv 57 # ITB acv -system.cpu1.itb.fetch_accesses 1952334 # ITB accesses -system.cpu1.itb.read_hits 0 # DTB read hits -system.cpu1.itb.read_misses 0 # DTB read misses -system.cpu1.itb.read_acv 0 # DTB read access violations -system.cpu1.itb.read_accesses 0 # DTB read accesses -system.cpu1.itb.write_hits 0 # DTB write hits -system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.write_acv 0 # DTB write access violations -system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.data_hits 0 # DTB hits -system.cpu1.itb.data_misses 0 # DTB misses -system.cpu1.itb.data_acv 0 # DTB access violations -system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numPwrStateTransitions 5407 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2704 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 688459953.587278 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 437290552.872181 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 2704 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 400000 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 976035500 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2704 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 7762339500 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 1861595714500 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 3738296719 # number of cpu cycles simulated -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2704 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 92290 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 31964 39.34% 39.34% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1906 2.35% 41.68% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 616 0.76% 42.44% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 46769 57.56% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 81255 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 30935 48.51% 48.51% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1906 2.99% 51.49% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 616 0.97% 52.46% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 30319 47.54% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 63776 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1856123556500 99.30% 99.30% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 81958000 0.00% 99.31% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 70736500 0.00% 99.31% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 12870743500 0.69% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1869146994500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.967808 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.648271 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.784887 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 514 0.61% 0.61% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.61% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.61% # number of callpals executed -system.cpu1.kern.callpal::swpctx 2506 2.96% 3.58% # number of callpals executed -system.cpu1.kern.callpal::tbi 14 0.02% 3.59% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.60% # number of callpals executed -system.cpu1.kern.callpal::swpipl 74617 88.26% 91.86% # number of callpals executed -system.cpu1.kern.callpal::rdps 2575 3.05% 94.91% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.91% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.00% 94.91% # number of callpals executed -system.cpu1.kern.callpal::rdusp 2 0.00% 94.91% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.92% # number of callpals executed -system.cpu1.kern.callpal::rti 4115 4.87% 99.79% # number of callpals executed -system.cpu1.kern.callpal::callsys 146 0.17% 99.96% # number of callpals executed -system.cpu1.kern.callpal::imb 34 0.04% 100.00% # number of callpals executed -system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 84542 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2548 # number of protection mode switches -system.cpu1.kern.mode_switch::user 564 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 3056 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 1106 -system.cpu1.kern.mode_good::user 564 -system.cpu1.kern.mode_good::idle 542 -system.cpu1.kern.mode_switch_good::kernel 0.434066 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.177356 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.358625 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 5986368000 0.32% 0.32% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 456602000 0.02% 0.34% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1862102446500 99.66% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 2507 # number of times the context was actually changed -system.cpu1.committedInsts 15522159 # Number of instructions committed -system.cpu1.committedOps 15522159 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 14295544 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 198941 # Number of float alu accesses -system.cpu1.num_func_calls 493140 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1540068 # number of instructions that are conditional controls -system.cpu1.num_int_insts 14295544 # number of integer instructions -system.cpu1.num_fp_insts 198941 # number of float instructions -system.cpu1.num_int_register_reads 19514289 # number of times the integer registers were read -system.cpu1.num_int_register_writes 10457600 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 101734 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 104129 # number of times the floating registers were written -system.cpu1.num_mem_refs 4961786 # number of memory refs -system.cpu1.num_load_insts 2849090 # Number of load instructions -system.cpu1.num_store_insts 2112696 # Number of store instructions -system.cpu1.num_idle_cycles 3722773781.474732 # Number of idle cycles -system.cpu1.num_busy_cycles 15522937.525268 # Number of busy cycles -system.cpu1.not_idle_fraction 0.004152 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.995848 # Percentage of idle cycles -system.cpu1.Branches 2214163 # Number of branches fetched -system.cpu1.op_class::No_OpClass 856043 5.51% 5.51% # Class of executed instruction -system.cpu1.op_class::IntAlu 9156766 58.98% 64.49% # Class of executed instruction -system.cpu1.op_class::IntMult 25065 0.16% 64.65% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.65% # Class of executed instruction -system.cpu1.op_class::FloatAdd 12426 0.08% 64.73% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.73% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.73% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.73% # Class of executed instruction -system.cpu1.op_class::FloatMultAcc 0 0.00% 64.73% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1409 0.01% 64.74% # Class of executed instruction -system.cpu1.op_class::FloatMisc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::MemRead 2842559 18.31% 83.05% # Class of executed instruction -system.cpu1.op_class::MemWrite 2023248 13.03% 96.08% # Class of executed instruction -system.cpu1.op_class::FloatMemRead 94457 0.61% 96.69% # Class of executed instruction -system.cpu1.op_class::FloatMemWrite 90649 0.58% 97.27% # Class of executed instruction -system.cpu1.op_class::IprAccess 423253 2.73% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 15525875 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 201757 # number of replacements -system.cpu1.dcache.tags.tagsinuse 497.601957 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 4718401 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 202065 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 23.350907 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 15869420000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 497.601957 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.971879 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.971879 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.601562 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 20020608 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 20020608 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 2632688 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2632688 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1954647 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1954647 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 61098 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 61098 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 64211 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 64211 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 4587335 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 4587335 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 4587335 # number of overall hits -system.cpu1.dcache.overall_hits::total 4587335 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 140885 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 140885 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 78313 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 78313 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11000 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 11000 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 7304 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 7304 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 219198 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 219198 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 219198 # number of overall misses -system.cpu1.dcache.overall_misses::total 219198 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2773573 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2773573 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 2032960 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 2032960 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 72098 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 72098 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 71515 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 71515 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4806533 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4806533 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4806533 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4806533 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050795 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.050795 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.038522 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.038522 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.152570 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.152570 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.102132 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.102132 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.045604 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.045604 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.045604 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.045604 # miss rate for overall accesses -system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 144832 # number of writebacks -system.cpu1.dcache.writebacks::total 144832 # number of writebacks -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 380647 # number of replacements -system.cpu1.icache.tags.tagsinuse 453.133721 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 15144687 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 381159 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 39.733253 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1859777228500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 453.133721 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.885027 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.885027 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 509 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 15907063 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 15907063 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 15144687 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 15144687 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 15144687 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 15144687 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 15144687 # number of overall hits -system.cpu1.icache.overall_hits::total 15144687 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 381188 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 381188 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 381188 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 381188 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 381188 # number of overall misses -system.cpu1.icache.overall_misses::total 381188 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 15525875 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 15525875 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 15525875 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 15525875 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 15525875 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 15525875 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024552 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024552 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024552 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024552 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024552 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024552 # miss rate for overall accesses -system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 380647 # number of writebacks -system.cpu1.icache.writebacks::total 380647 # number of writebacks -system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. -system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_txs 395 # Number of DMA write transactions. -system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. -system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. -system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 7628 # Transaction distribution -system.iobus.trans_dist::ReadResp 7628 # Transaction distribution -system.iobus.trans_dist::WriteReq 56140 # Transaction distribution -system.iobus.trans_dist::WriteResp 56140 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14686 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1014 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18036 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 44074 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83462 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83462 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 127536 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 58744 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2749 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 1392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9018 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 86162 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661656 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2747818 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 41699 # number of replacements -system.iocache.tags.tagsinuse 0.434096 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1685787164517 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.434096 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.027131 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.027131 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375579 # Number of tag accesses -system.iocache.tags.data_accesses 375579 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses -system.iocache.ReadReq_misses::total 179 # number of ReadReq misses -system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 41731 # number of demand (read+write) misses -system.iocache.demand_misses::total 41731 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41731 # number of overall misses -system.iocache.overall_misses::total 41731 # number of overall misses -system.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41731 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41731 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41731 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41731 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses -system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 41520 # number of writebacks -system.iocache.writebacks::total 41520 # number of writebacks -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 999962 # number of replacements -system.l2c.tags.tagsinuse 65520.418445 # Cycle average of tags in use -system.l2c.tags.total_refs 4560627 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1065470 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.280390 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 618103500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 304.654012 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4865.757484 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 58473.870624 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 175.171542 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1700.964784 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.004649 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.074246 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.892240 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002673 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.025955 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.999762 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65508 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 674 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 2411 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2462 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 9328 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 50633 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.999573 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 46077150 # Number of tag accesses -system.l2c.tags.data_accesses 46077150 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 778757 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 778757 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 721479 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 721479 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 3102 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 2744 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 5846 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 1187 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 1121 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 2308 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 111978 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 56627 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 168605 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 607070 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 379530 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 986600 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 626251 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 128790 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 755041 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 607070 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 738229 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 379530 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 185417 # number of demand (read+write) hits -system.l2c.demand_hits::total 1910246 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 607070 # number of overall hits -system.l2c.overall_hits::cpu0.data 738229 # number of overall hits -system.l2c.overall_hits::cpu1.inst 379530 # number of overall hits -system.l2c.overall_hits::cpu1.data 185417 # number of overall hits -system.l2c.overall_hits::total 1910246 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 4 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 2 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 6 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 113307 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 11044 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 124351 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 11848 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 1658 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 13506 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 926616 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 1036 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 927652 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.inst 11848 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 1039923 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1658 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 12080 # number of demand (read+write) misses -system.l2c.demand_misses::total 1065509 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 11848 # number of overall misses -system.l2c.overall_misses::cpu0.data 1039923 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1658 # number of overall misses -system.l2c.overall_misses::cpu1.data 12080 # number of overall misses -system.l2c.overall_misses::total 1065509 # number of overall misses -system.l2c.WritebackDirty_accesses::writebacks 778757 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 778757 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 721479 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 721479 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 3106 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 2746 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 5852 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 1187 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1122 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2309 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 225285 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 67671 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 292956 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 618918 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 381188 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1000106 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 1552867 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 129826 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 1682693 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 618918 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1778152 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 381188 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 197497 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2975755 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 618918 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1778152 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 381188 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 197497 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2975755 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.001288 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.000728 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.001025 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.000891 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.000433 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.502950 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.163201 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.424470 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.019143 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004350 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.013505 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596713 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.007980 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.551290 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.019143 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.584834 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.004350 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.061165 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.358063 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.019143 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.584834 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.004350 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.061165 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.358063 # miss rate for overall accesses -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 80947 # number of writebacks -system.l2c.writebacks::total 80947 # number of writebacks -system.membus.snoop_filter.tot_requests 2174394 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1068314 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 544 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 7449 # Transaction distribution -system.membus.trans_dist::ReadResp 948786 # Transaction distribution -system.membus.trans_dist::WriteReq 14588 # Transaction distribution -system.membus.trans_dist::WriteResp 14588 # Transaction distribution -system.membus.trans_dist::WritebackDirty 122467 # Transaction distribution -system.membus.trans_dist::CleanEvict 918018 # Transaction distribution -system.membus.trans_dist::UpgradeReq 13880 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11895 # Transaction distribution -system.membus.trans_dist::UpgradeResp 135 # Transaction distribution -system.membus.trans_dist::ReadExReq 125245 # Transaction distribution -system.membus.trans_dist::ReadExResp 124223 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 941337 # Transaction distribution -system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 44074 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3156480 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3200554 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125161 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 125161 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3325715 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 86162 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73364992 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 73451154 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2668736 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2668736 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 76119890 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2196431 # Request fanout histogram -system.membus.snoop_fanout::mean 0.000560 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.023658 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2195201 99.94% 99.94% # Request fanout histogram -system.membus.snoop_fanout::1 1230 0.06% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2196431 # Request fanout histogram -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 6035809 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 3010644 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 386637 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1627 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1537 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 90 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 7449 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2732152 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14588 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 778757 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 998939 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1204367 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 19598 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 14203 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 33801 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 295242 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 295242 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1000127 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1724576 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1856170 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5450061 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1143023 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 684375 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 9133629 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 79182784 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155817595 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 48757440 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23377367 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 307135186 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1001076 # Total snoops (count) -system.toL2Bus.snoopTraffic 5203008 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 7058756 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.107956 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.310579 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 6297275 89.21% 89.21% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 760929 10.78% 99.99% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 550 0.01% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 7058756 # Request fanout histogram -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal deleted file mode 100644 index 6129834bd..000000000 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal +++ /dev/null @@ -1,112 +0,0 @@ -M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 -
Got Configuration 623 -
memsize 8000000 pages 4000 -
First free page after ROM 0xFFFFFC0000018000 -
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 -
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x2 -
CPU Clock at 2000 MHz IntrClockFrequency=1024 -
Booting with 2 processor(s) -
KSP: 0x20043FE8 PTBR 0x20 -
KSP: 0x20043FE8 PTBR 0x20 -
Console Callback at 0x0, fixup at 0x0, crb offset: 0x790 -
Memory cluster 0 [0 - 392] -
Memory cluster 1 [392 - 15992] -
Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 -
ConsoleDispatch at virt 100008D8 phys 188D8 val FFFFFC00000100A8 -
Bootstraping CPU 1 with sp=0xFFFFFC0000076000 -
unix_boot_mem ends at FFFFFC0000078000 -
k_argc = 0 -
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) -
CallbackFixup 0 18000, t7=FFFFFC000070C000 -
Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400 -
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 -
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM -
Major Options: SMP LEGACY_START VERBOSE_MCHECK -
Command line: root=/dev/hda1 console=ttyS0 -
memcluster 0, usage 1, start 0, end 392 -
memcluster 1, usage 0, start 392, end 16384 -
freeing pages 1069:16384 -
reserving pages 1069:1070 -
SMP: 2 CPUs probed -- cpu_present_mask = 3 -
Built 1 zonelists -
Kernel command line: root=/dev/hda1 console=ttyS0 -
PID hash table entries: 1024 (order: 10, 32768 bytes) -
Using epoch = 1900 -
Console: colour dummy device 80x25 -
Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) -
Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) -
Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) -
Mount-cache hash table entries: 512 -
SMP starting up secondaries. -
Slave CPU 1 console command START
-SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb FFFFFC0000018400 my_rpb_phys 18400 -
Brought up 2 CPUs -
SMP: Total of 2 processors activated (8000.15 BogoMIPS). -
NET: Registered protocol family 16 -
EISA bus registered -
pci: enabling save/restore of SRM state -
SCSI subsystem initialized -
srm_env: version 0.0.5 loaded successfully -
Installing knfsd (copyright (C) 1996 okir@monad.swb.de). -
Initializing Cryptographic API -
rtc: Standard PC (1900) epoch (1900) detected -
Real Time Clock Driver v1.12 -
Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled -
ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 -
io scheduler noop registered -
io scheduler anticipatory registered -
io scheduler deadline registered -
io scheduler cfq registered -
loop: loaded (max 8 devices) -
nbd: registered device at major 43 -
ns83820.c: National Semiconductor DP83820 10/100/1000 driver. -
PCI: Setting latency timer of device 0000:00:01.0 to 64 -
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 -
eth0: enabling optical transceiver -
eth0: using 64 bit addressing. -
eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg -
tun: Universal TUN/TAP device driver, 1.6 -
tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com> -
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 -
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx -
PIIX4: IDE controller at PCI slot 0000:00:00.0 -
PIIX4: chipset revision 0 -
PIIX4: 100% native mode on irq 31 -
PCI: Setting latency timer of device 0000:00:00.0 to 64 -
ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA -
ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA -
hda: M5 IDE Disk, ATA DISK drive -
hdb: M5 IDE Disk, ATA DISK drive -
ide0 at 0x8410-0x8417,0x8422 on irq 31 -
hda: max request size: 128KiB -
hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33) -
hda: cache flushes not supported -
hda: hda1 -
hdb: max request size: 128KiB -
hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) -
hdb: cache flushes not supported -
hdb: unknown partition table -
mice: PS/2 mouse device common for all mice -
NET: Registered protocol family 2 -
IP route cache hash table entries: 4096 (order: 2, 32768 bytes) -
TCP established hash table entries: 16384 (order: 5, 262144 bytes) -
TCP bind hash table entries: 16384 (order: 5, 262144 bytes) -
TCP: Hash tables configured (established 16384 bind 16384) -
TCP reno registered -
ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack -
ip_tables: (C) 2000-2002 Netfilter core team -
arp_tables: (C) 2002 David S. Miller -
TCP bic registered -
Initializing IPsec netlink socket -
NET: Registered protocol family 1 -
NET: Registered protocol family 17 -
NET: Registered protocol family 15 -
Bridge firewalling registered -
802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com> -
All bugs added by David S. Miller <davem@redhat.com> -
VFS: Mounted root (ext2 filesystem) readonly. -
Freeing unused kernel memory: 224k freed -
init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary
-mounting filesystems...
-EXT2-fs warning: checktime reached, running e2fsck is recommended -
loading script...
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