diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt | 264 |
1 files changed, 136 insertions, 128 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 3fe61f3f7..60a4f6e98 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -4,42 +4,42 @@ sim_seconds 1.829332 # Nu sim_ticks 1829332273500 # Number of ticks simulated final_tick 1829332273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2059947 # Simulator instruction rate (inst/s) -host_op_rate 2059945 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62765242809 # Simulator tick rate (ticks/s) -host_mem_usage 317596 # Number of bytes of host memory used -host_seconds 29.15 # Real time elapsed on the host +host_inst_rate 2495393 # Simulator instruction rate (inst/s) +host_op_rate 2495392 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 76033049021 # Simulator tick rate (ticks/s) +host_mem_usage 371696 # Number of bytes of host memory used +host_seconds 24.06 # Real time elapsed on the host sim_insts 60038341 # Number of instructions simulated sim_ops 60038341 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 66839040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 856000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 66836224 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 67697984 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7411008 # Number of bytes written to this memory -system.physmem.bytes_written::total 7411008 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13406 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1044360 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 67693184 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 856000 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 856000 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7414144 # Number of bytes written to this memory +system.physmem.bytes_written::total 7414144 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13375 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1044316 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1057781 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115797 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115797 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 469015 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 36537397 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 1057706 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115846 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115846 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 467930 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 36535858 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 37006937 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 469015 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 469015 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4051209 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4051209 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4051209 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 469015 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 36537397 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 37004313 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 467930 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 467930 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4052924 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4052924 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4052924 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 467930 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 36535858 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 525 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 41058146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 41057237 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -284,8 +284,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 833501 # number of writebacks -system.cpu.dcache.writebacks::total 833501 # number of writebacks +system.cpu.dcache.writebacks::writebacks 833493 # number of writebacks +system.cpu.dcache.writebacks::total 833493 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 919605 # number of replacements system.cpu.icache.tags.tagsinuse 511.215260 # Cycle average of tags in use @@ -336,84 +336,88 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 992295 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65424.374284 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2433284 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1057458 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.301069 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 992219 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65424.374112 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4561879 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1057382 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.314315 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 56310.352234 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4866.099732 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4247.922318 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.859228 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074251 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 56252.896873 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4923.444270 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 4248.032969 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.858351 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.075126 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.064820 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 781 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3260 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4024 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3055 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54043 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3053 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54045 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 31737815 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 31737815 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 906808 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 811247 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1718055 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 833501 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 833501 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 48768396 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 48768396 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 833493 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 833493 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187243 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187243 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 906808 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 998490 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1905298 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 906808 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 998490 # number of overall hits -system.cpu.l2cache.overall_hits::total 1905298 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 941046 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_hits::cpu.data 187288 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187288 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 906839 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 906839 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 811246 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 811246 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 906839 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 998534 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1905373 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 906839 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 998534 # number of overall hits +system.cpu.l2cache.overall_hits::total 1905373 # number of overall hits system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 117111 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 117111 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 13406 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1044751 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1058157 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 13406 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1044751 # number of overall misses -system.cpu.l2cache.overall_misses::total 1058157 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 920214 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1738887 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2659101 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 833501 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 833501 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 117066 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 117066 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13375 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 13375 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 927641 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 927641 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 13375 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1044707 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1058082 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 13375 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1044707 # number of overall misses +system.cpu.l2cache.overall_misses::total 1058082 # number of overall misses +system.cpu.l2cache.Writeback_accesses::writebacks 833493 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 833493 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 304354 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 304354 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 920214 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 920214 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1738887 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1738887 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 920214 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 2043241 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 2963455 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 920214 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2043241 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 2963455 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014568 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533468 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.353896 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384785 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.384785 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014568 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.511320 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.357069 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014568 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.511320 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.357069 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384638 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.384638 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014535 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014535 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.533468 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.533468 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014535 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.511299 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.357043 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014535 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.511299 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.357043 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -422,36 +426,39 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 74285 # number of writebacks -system.cpu.l2cache.writebacks::total 74285 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 74334 # number of writebacks +system.cpu.l2cache.writebacks::total 74334 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2666303 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 7184 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 2666303 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 833501 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 833493 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2128840 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 304354 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 304354 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1840464 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4954059 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6794523 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 920232 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1738887 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2760069 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6163286 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8923355 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58894848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184157614 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 243052462 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184157102 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 243051950 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 41883 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3855738 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.010822 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.103463 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 5984570 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.006972 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.083208 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3814012 98.92% 98.92% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41726 1.08% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5942844 99.30% 99.30% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 41726 0.70% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3855738 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5984570 # Request fanout histogram system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -467,8 +474,7 @@ system.disk2.dma_write_txs 1 # Nu system.iobus.trans_dist::ReadReq 7358 # Transaction distribution system.iobus.trans_dist::ReadResp 7358 # Transaction distribution system.iobus.trans_dist::WriteReq 51390 # Transaction distribution -system.iobus.trans_dist::WriteResp 9838 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.iobus.trans_dist::WriteResp 51390 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5248 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) @@ -517,24 +523,24 @@ system.iocache.tags.tag_accesses 375534 # Nu system.iocache.tags.data_accesses 375534 # Number of data accesses system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses system.iocache.ReadReq_misses::total 174 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses system.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses system.iocache.demand_misses::total 174 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 174 # number of overall misses system.iocache.overall_misses::total 174 # number of overall misses system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses system.iocache.demand_accesses::total 174 # number of demand (read+write) accesses system.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses system.iocache.overall_accesses::total 174 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses @@ -550,41 +556,43 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 948404 # Transaction distribution -system.membus.trans_dist::ReadResp 948404 # Transaction distribution +system.membus.trans_dist::ReadReq 7184 # Transaction distribution +system.membus.trans_dist::ReadResp 948374 # Transaction distribution system.membus.trans_dist::WriteReq 9838 # Transaction distribution system.membus.trans_dist::WriteResp 9838 # Transaction distribution -system.membus.trans_dist::Writeback 115797 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.membus.trans_dist::Writeback 115846 # Transaction distribution +system.membus.trans_dist::CleanEvict 918371 # Transaction distribution system.membus.trans_dist::UpgradeReq 132 # Transaction distribution system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 116991 # Transaction distribution -system.membus.trans_dist::ReadExResp 116991 # Transaction distribution +system.membus.trans_dist::ReadExReq 116946 # Transaction distribution +system.membus.trans_dist::ReadExResp 116946 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 941190 # Transaction distribution +system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2190623 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 2224667 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124964 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124964 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2349631 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3108719 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3142763 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125138 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 125138 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3267901 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72468608 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72514734 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5327232 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 5327232 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 77841966 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72466944 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72513070 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2667904 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2667904 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 75180974 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 1232714 # Request fanout histogram +system.membus.snoop_fanout::samples 2151059 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 1232714 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2151059 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 1232714 # Request fanout histogram +system.membus.snoop_fanout::total 2151059 # Request fanout histogram system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA |