diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt | 67 |
1 files changed, 51 insertions, 16 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 1b6d7ca40..4492aa0b0 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -4,23 +4,40 @@ sim_seconds 1.829332 # Nu sim_ticks 1829332258000 # Number of ticks simulated final_tick 1829332258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1921293 # Simulator instruction rate (inst/s) -host_op_rate 1921291 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58540553267 # Simulator tick rate (ticks/s) -host_mem_usage 295828 # Number of bytes of host memory used -host_seconds 31.25 # Real time elapsed on the host +host_inst_rate 2878195 # Simulator instruction rate (inst/s) +host_op_rate 2878193 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 87696777763 # Simulator tick rate (ticks/s) +host_mem_usage 296144 # Number of bytes of host memory used +host_seconds 20.86 # Real time elapsed on the host sim_insts 60038305 # Number of instructions simulated sim_ops 60038305 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 71650816 # Number of bytes read from this memory -system.physmem.bytes_inst_read 955904 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10156864 # Number of bytes written to this memory -system.physmem.num_reads 1119544 # Number of read requests responded to by this memory -system.physmem.num_writes 158701 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 39167743 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 522543 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 5552225 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 44719968 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 955904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 68042304 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652608 # Number of bytes read from this memory +system.physmem.bytes_read::total 71650816 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 955904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 955904 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10156864 # Number of bytes written to this memory +system.physmem.bytes_written::total 10156864 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 14936 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1063161 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41447 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1119544 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 158701 # Number of write requests responded to by this memory +system.physmem.num_writes::total 158701 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 522543 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 37195159 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1450042 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 39167743 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 522543 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 522543 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 5552225 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5552225 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 5552225 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 522543 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 37195159 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1450042 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 44719968 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 1045877 # number of replacements system.l2c.tagsinuse 33807.015903 # Cycle average of tags in use system.l2c.total_refs 2291835 # Total number of references to valid blocks. @@ -79,12 +96,17 @@ system.l2c.overall_accesses::cpu.data 2043063 # nu system.l2c.overall_accesses::total 2963266 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu.inst 0.016231 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.data 0.543295 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.360895 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu.data 0.923077 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.923077 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu.data 0.390673 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.390673 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu.inst 0.016231 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.data 0.520567 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.363952 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu.inst 0.016231 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.data 0.520567 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.363952 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -122,9 +144,13 @@ system.iocache.demand_accesses::total 41726 # nu system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -224,6 +250,7 @@ system.cpu.kern.ipl_used::0 0.981732 # fr system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::31 0.695521 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.816353 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -281,7 +308,7 @@ system.cpu.kern.mode_good::idle 171 system.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 1.402439 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.390229 # fraction of useful protection mode switches system.cpu.kern.mode_ticks::kernel 26834202500 1.47% 1.47% # number of ticks spent at the given mode system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode system.cpu.kern.mode_ticks::idle 1801032773000 98.45% 100.00% # number of ticks spent at the given mode @@ -345,8 +372,11 @@ system.cpu.icache.demand_accesses::total 60050143 # nu system.cpu.icache.overall_accesses::cpu.inst 60050143 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 60050143 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.015324 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.015324 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.015324 # miss rate for overall accesses system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -402,10 +432,15 @@ system.cpu.dcache.demand_accesses::total 15682061 # nu system.cpu.dcache.overall_accesses::cpu.data 15682061 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 15682061 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180671 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.180671 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.129196 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.129196 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.129196 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.129196 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked |