diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt | 2099 |
1 files changed, 1052 insertions, 1047 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 9ca2241e2..7159169af 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,118 +1,118 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.962845 # Number of seconds simulated -sim_ticks 1962844580000 # Number of ticks simulated -final_tick 1962844580000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.962843 # Number of seconds simulated +sim_ticks 1962842856000 # Number of ticks simulated +final_tick 1962842856000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1184099 # Simulator instruction rate (inst/s) -host_op_rate 1184098 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38148129943 # Simulator tick rate (ticks/s) -host_mem_usage 318172 # Number of bytes of host memory used -host_seconds 51.45 # Real time elapsed on the host -sim_insts 60925667 # Number of instructions simulated -sim_ops 60925667 # Number of ops (including micro ops) simulated +host_inst_rate 1228880 # Simulator instruction rate (inst/s) +host_op_rate 1228880 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 39594262798 # Simulator tick rate (ticks/s) +host_mem_usage 373652 # Number of bytes of host memory used +host_seconds 49.57 # Real time elapsed on the host +sim_insts 60920382 # Number of instructions simulated +sim_ops 60920382 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 823168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24882816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 41728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 386368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 823232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24883392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 41664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 386496 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26135040 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 823168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 41728 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 26135744 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 823232 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 41664 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 864896 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7758336 # Number of bytes written to this memory -system.physmem.bytes_written::total 7758336 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12862 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 388794 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 652 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6037 # Number of read requests responded to by this memory +system.physmem.bytes_written::writebacks 7759040 # Number of bytes written to this memory +system.physmem.bytes_written::total 7759040 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12863 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 388803 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 651 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6039 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 408360 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 121224 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121224 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 419375 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12676916 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 21259 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 196841 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 408371 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 121235 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121235 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 419408 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12677221 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 21226 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 196906 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13314880 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 419375 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 21259 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13315250 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 419408 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 21226 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 440634 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3952598 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3952598 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3952598 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 419375 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12676916 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 21259 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 196841 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 3952960 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3952960 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3952960 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 419408 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12677221 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 21226 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 196906 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 489 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17267478 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 408360 # Number of read requests accepted -system.physmem.writeReqs 162776 # Number of write requests accepted -system.physmem.readBursts 408360 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 162776 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26127936 # Total number of bytes read from DRAM +system.physmem.bw_total::total 17268211 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 408371 # Number of read requests accepted +system.physmem.writeReqs 162787 # Number of write requests accepted +system.physmem.readBursts 408371 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 162787 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26128640 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue -system.physmem.bytesWritten 10271680 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26135040 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10417664 # Total written bytes from the system interface side +system.physmem.bytesWritten 10277440 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26135744 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10418368 # Total written bytes from the system interface side system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2254 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 7048 # Number of requests that are neither read nor write +system.physmem.mergedWrBursts 2175 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 7051 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 25705 # Per bank write bursts system.physmem.perBankRdBursts::1 25985 # Per bank write bursts -system.physmem.perBankRdBursts::2 25732 # Per bank write bursts -system.physmem.perBankRdBursts::3 25537 # Per bank write bursts +system.physmem.perBankRdBursts::2 25737 # Per bank write bursts +system.physmem.perBankRdBursts::3 25534 # Per bank write bursts system.physmem.perBankRdBursts::4 24847 # Per bank write bursts -system.physmem.perBankRdBursts::5 24747 # Per bank write bursts +system.physmem.perBankRdBursts::5 24754 # Per bank write bursts system.physmem.perBankRdBursts::6 25534 # Per bank write bursts -system.physmem.perBankRdBursts::7 25495 # Per bank write bursts +system.physmem.perBankRdBursts::7 25489 # Per bank write bursts system.physmem.perBankRdBursts::8 25150 # Per bank write bursts system.physmem.perBankRdBursts::9 25518 # Per bank write bursts system.physmem.perBankRdBursts::10 25462 # Per bank write bursts -system.physmem.perBankRdBursts::11 25292 # Per bank write bursts +system.physmem.perBankRdBursts::11 25296 # Per bank write bursts system.physmem.perBankRdBursts::12 25577 # Per bank write bursts system.physmem.perBankRdBursts::13 25454 # Per bank write bursts system.physmem.perBankRdBursts::14 26241 # Per bank write bursts -system.physmem.perBankRdBursts::15 25973 # Per bank write bursts -system.physmem.perBankWrBursts::0 10613 # Per bank write bursts -system.physmem.perBankWrBursts::1 10753 # Per bank write bursts -system.physmem.perBankWrBursts::2 9796 # Per bank write bursts -system.physmem.perBankWrBursts::3 9387 # Per bank write bursts -system.physmem.perBankWrBursts::4 8893 # Per bank write bursts -system.physmem.perBankWrBursts::5 9110 # Per bank write bursts -system.physmem.perBankWrBursts::6 9958 # Per bank write bursts -system.physmem.perBankWrBursts::7 9669 # Per bank write bursts -system.physmem.perBankWrBursts::8 9689 # Per bank write bursts -system.physmem.perBankWrBursts::9 9901 # Per bank write bursts -system.physmem.perBankWrBursts::10 9876 # Per bank write bursts -system.physmem.perBankWrBursts::11 10215 # Per bank write bursts -system.physmem.perBankWrBursts::12 10815 # Per bank write bursts -system.physmem.perBankWrBursts::13 10652 # Per bank write bursts -system.physmem.perBankWrBursts::14 10531 # Per bank write bursts -system.physmem.perBankWrBursts::15 10637 # Per bank write bursts +system.physmem.perBankRdBursts::15 25977 # Per bank write bursts +system.physmem.perBankWrBursts::0 10598 # Per bank write bursts +system.physmem.perBankWrBursts::1 10761 # Per bank write bursts +system.physmem.perBankWrBursts::2 9727 # Per bank write bursts +system.physmem.perBankWrBursts::3 9433 # Per bank write bursts +system.physmem.perBankWrBursts::4 8910 # Per bank write bursts +system.physmem.perBankWrBursts::5 9140 # Per bank write bursts +system.physmem.perBankWrBursts::6 9908 # Per bank write bursts +system.physmem.perBankWrBursts::7 9771 # Per bank write bursts +system.physmem.perBankWrBursts::8 9710 # Per bank write bursts +system.physmem.perBankWrBursts::9 9867 # Per bank write bursts +system.physmem.perBankWrBursts::10 9923 # Per bank write bursts +system.physmem.perBankWrBursts::11 10306 # Per bank write bursts +system.physmem.perBankWrBursts::12 10733 # Per bank write bursts +system.physmem.perBankWrBursts::13 10678 # Per bank write bursts +system.physmem.perBankWrBursts::14 10553 # Per bank write bursts +system.physmem.perBankWrBursts::15 10567 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1962839541500 # Total gap between requests +system.physmem.totGap 1962837817500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 408360 # Read request sizes (log2) +system.physmem.readPktSize::6 408371 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 162776 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 408168 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 68 # What read queue length does an incoming req see +system.physmem.writePktSize::6 162787 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 408177 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 70 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see @@ -158,173 +158,178 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 8312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 9464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 10119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11871 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10784 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8090 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6890 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4404 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 8320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 9433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 10077 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10961 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 11550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11941 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 12017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8581 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6888 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 130 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 59 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 26 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 69162 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 526.295017 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 318.923666 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 416.254848 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16035 23.18% 23.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 12178 17.61% 40.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5186 7.50% 48.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3086 4.46% 52.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3308 4.78% 57.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1800 2.60% 60.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1507 2.18% 62.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1316 1.90% 64.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24746 35.78% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 69162 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5880 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 69.428401 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2107.963348 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 5875 99.91% 99.91% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 69318 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 525.203843 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 317.866807 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 416.347675 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16137 23.28% 23.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 12161 17.54% 40.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5284 7.62% 48.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3087 4.45% 52.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3309 4.77% 57.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1757 2.53% 60.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1519 2.19% 62.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1296 1.87% 64.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 24768 35.73% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 69318 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5881 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 69.418466 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2107.784288 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 5876 99.91% 99.91% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-8191 1 0.02% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-45055 1 0.02% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::73728-77823 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::122880-126975 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5880 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5880 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.295068 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.802481 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 33.368634 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4837 82.26% 82.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 186 3.16% 85.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 281 4.78% 90.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 57 0.97% 91.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 98 1.67% 92.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 42 0.71% 93.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 21 0.36% 93.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 12 0.20% 94.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 21 0.36% 94.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 6 0.10% 94.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 10 0.17% 94.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 8 0.14% 94.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 13 0.22% 95.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 5 0.09% 95.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 22 0.37% 95.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 44 0.75% 96.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 23 0.39% 96.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 6 0.10% 96.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 80 1.36% 98.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 40 0.68% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 14 0.24% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 24 0.41% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 14 0.24% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 2 0.03% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 5 0.09% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5881 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5881 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.305730 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.811619 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 33.369719 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4828 82.09% 82.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 189 3.21% 85.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 283 4.81% 90.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 60 1.02% 91.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 106 1.80% 92.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 43 0.73% 93.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 17 0.29% 93.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 8 0.14% 94.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 22 0.37% 94.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 7 0.12% 94.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 14 0.24% 94.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 3 0.05% 94.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 16 0.27% 95.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 2 0.03% 95.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 15 0.26% 95.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 48 0.82% 96.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 18 0.31% 96.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 12 0.20% 96.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 85 1.45% 98.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 44 0.75% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 9 0.15% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 24 0.41% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 10 0.17% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 3 0.05% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 5 0.09% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 2 0.03% 99.86% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::224-231 2 0.03% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 4 0.07% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5880 # Writes before turning the bus around for reads -system.physmem.totQLat 2202002500 # Total ticks spent queuing -system.physmem.totMemAccLat 9856671250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2041245000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5393.77 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::232-239 2 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 3 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5881 # Writes before turning the bus around for reads +system.physmem.totQLat 2189518000 # Total ticks spent queuing +system.physmem.totMemAccLat 9844393000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2041300000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5363.05 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24143.77 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 24113.05 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.31 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 5.23 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.31 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBW 5.24 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.32 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 5.31 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.11 # Average write queue length when enqueuing -system.physmem.readRowHits 365785 # Number of row buffer hits during reads -system.physmem.writeRowHits 133797 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.60 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.35 # Row buffer hit rate for writes -system.physmem.avgGap 3436728.80 # Average gap between requests -system.physmem.pageHitRate 87.84 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1840639787000 # Time in different power states -system.physmem.memoryStateTime::REF 65543660000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 56660375500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 257115600 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 265749120 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 140291250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 145002000 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1587939600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1596402600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 506599920 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 533407680 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 128203398960 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 128203398960 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 65563204050 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 65997539775 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1120194702750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1119813706500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1316453252130 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1316555206635 # Total energy per rank (pJ) -system.physmem.averagePower::0 670.686708 # Core power per rank (mW) -system.physmem.averagePower::1 670.738650 # Core power per rank (mW) +system.physmem.avgWrQLen 25.78 # Average write queue length when enqueuing +system.physmem.readRowHits 365775 # Number of row buffer hits during reads +system.physmem.writeRowHits 133752 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.59 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 83.28 # Row buffer hit rate for writes +system.physmem.avgGap 3436593.41 # Average gap between requests +system.physmem.pageHitRate 87.81 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 258098400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 140827500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1587963000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 507047040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 128202890400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 65554579665 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1120197596250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1316449002255 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.687203 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1863305388500 # Time in different power states +system.physmem_0.memoryStateTime::REF 65543400000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 33987247750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 265945680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 145109250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1596465000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 533543760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 128202890400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 65970100260 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1119833096250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1316547150600 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.737211 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1862702158750 # Time in different power states +system.physmem_1.memoryStateTime::REF 65543400000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 34590463750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7534386 # DTB read hits +system.cpu0.dtb.read_hits 7535038 # DTB read hits system.cpu0.dtb.read_misses 7765 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 524069 # DTB read accesses -system.cpu0.dtb.write_hits 5126601 # DTB write hits +system.cpu0.dtb.write_hits 5127057 # DTB write hits system.cpu0.dtb.write_misses 910 # DTB write misses system.cpu0.dtb.write_acv 133 # DTB write access violations system.cpu0.dtb.write_accesses 202595 # DTB write accesses -system.cpu0.dtb.data_hits 12660987 # DTB hits +system.cpu0.dtb.data_hits 12662095 # DTB hits system.cpu0.dtb.data_misses 8675 # DTB misses system.cpu0.dtb.data_acv 343 # DTB access violations system.cpu0.dtb.data_accesses 726664 # DTB accesses @@ -344,32 +349,32 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3925689160 # number of cpu cycles simulated +system.cpu0.numCycles 3925685712 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 47974635 # Number of instructions committed -system.cpu0.committedOps 47974635 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 44501266 # Number of integer alu accesses +system.cpu0.committedInsts 47981838 # Number of instructions committed +system.cpu0.committedOps 47981838 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44508329 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 212945 # Number of float alu accesses -system.cpu0.num_func_calls 1202793 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5632199 # number of instructions that are conditional controls -system.cpu0.num_int_insts 44501266 # number of integer instructions +system.cpu0.num_func_calls 1202945 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5633344 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44508329 # number of integer instructions system.cpu0.num_fp_insts 212945 # number of float instructions -system.cpu0.num_int_register_reads 61193579 # number of times the integer registers were read -system.cpu0.num_int_register_writes 33138119 # number of times the integer registers were written +system.cpu0.num_int_register_reads 61205329 # number of times the integer registers were read +system.cpu0.num_int_register_writes 33143507 # number of times the integer registers were written system.cpu0.num_fp_register_reads 104073 # number of times the floating registers were read system.cpu0.num_fp_register_writes 105864 # number of times the floating registers were written -system.cpu0.num_mem_refs 12702031 # number of memory refs -system.cpu0.num_load_insts 7562183 # Number of load instructions -system.cpu0.num_store_insts 5139848 # Number of store instructions -system.cpu0.num_idle_cycles 3702096779.998114 # Number of idle cycles -system.cpu0.num_busy_cycles 223592380.001886 # Number of busy cycles +system.cpu0.num_mem_refs 12703139 # number of memory refs +system.cpu0.num_load_insts 7562835 # Number of load instructions +system.cpu0.num_store_insts 5140304 # Number of store instructions +system.cpu0.num_idle_cycles 3702094605.998114 # Number of idle cycles +system.cpu0.num_busy_cycles 223591106.001886 # Number of busy cycles system.cpu0.not_idle_fraction 0.056956 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.943044 # Percentage of idle cycles -system.cpu0.Branches 7223323 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2734296 5.70% 5.70% # Class of executed instruction -system.cpu0.op_class::IntAlu 31541688 65.73% 71.43% # Class of executed instruction -system.cpu0.op_class::IntMult 52334 0.11% 71.54% # Class of executed instruction +system.cpu0.Branches 7224625 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2734428 5.70% 5.70% # Class of executed instruction +system.cpu0.op_class::IntAlu 31547561 65.74% 71.43% # Class of executed instruction +system.cpu0.op_class::IntMult 52422 0.11% 71.54% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 71.54% # Class of executed instruction system.cpu0.op_class::FloatAdd 26783 0.06% 71.60% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 71.60% # Class of executed instruction @@ -397,11 +402,11 @@ system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.60% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 71.60% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.60% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::MemRead 7738218 16.13% 87.73% # Class of executed instruction -system.cpu0.op_class::MemWrite 5145965 10.72% 98.45% # Class of executed instruction +system.cpu0.op_class::MemRead 7738872 16.13% 87.73% # Class of executed instruction +system.cpu0.op_class::MemWrite 5146421 10.72% 98.45% # Class of executed instruction system.cpu0.op_class::IprAccess 742486 1.55% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 47983653 # Class of executed instruction +system.cpu0.op_class::total 47990856 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed system.cpu0.kern.inst.hwrei 165589 # number of hwrei instructions executed @@ -417,12 +422,12 @@ system.cpu0.kern.ipl_good::22 1976 1.72% 50.92% # nu system.cpu0.kern.ipl_good::30 424 0.37% 51.29% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 55969 48.71% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 114892 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1903342573000 96.97% 96.97% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 94358500 0.00% 96.97% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 767882500 0.04% 97.01% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 314406500 0.02% 97.03% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 58324587500 2.97% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1962843808000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1903333022000 96.97% 96.97% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 94388000 0.00% 96.97% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 768238500 0.04% 97.01% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 314332500 0.02% 97.03% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 58332103000 2.97% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1962842084000 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.990637 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl @@ -487,98 +492,98 @@ system.cpu0.kern.mode_switch_good::kernel 0.195209 # f system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total 0.326733 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1959059969000 99.81% 99.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3783834500 0.19% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 1959061538500 99.81% 99.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3780541000 0.19% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 3098 # number of times the context was actually changed -system.cpu0.dcache.tags.replacements 1190018 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.199068 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11465472 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1190530 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.630561 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1190069 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.197532 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11466522 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1190581 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.631031 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 108210250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.199068 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986717 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986717 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.197532 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986714 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986714 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 328 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51888213 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51888213 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6450398 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6450398 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4712072 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4712072 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140773 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 140773 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148356 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 148356 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11162470 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11162470 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11162470 # number of overall hits -system.cpu0.dcache.overall_hits::total 11162470 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 942246 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 942246 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 257610 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 257610 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13707 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13707 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5575 # 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number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 42660894 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 42660894 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 37574847938 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 37574847938 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 37574847938 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 37574847938 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7392644 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7392644 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4969682 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4969682 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154480 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 154480 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153931 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 153931 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12362326 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12362326 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12362326 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12362326 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127457 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.127457 # miss rate for ReadReq accesses +system.cpu0.dcache.tags.tag_accesses 51892703 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 51892703 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6451021 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6451021 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4712504 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4712504 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140772 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 140772 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148353 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 148353 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11163525 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11163525 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11163525 # number of overall hits +system.cpu0.dcache.overall_hits::total 11163525 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 942274 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 942274 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 257633 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 257633 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13709 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13709 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5579 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 5579 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1199907 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1199907 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1199907 # number of overall misses +system.cpu0.dcache.overall_misses::total 1199907 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27224956000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 27224956000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10342084186 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 10342084186 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150000000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 150000000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 42703895 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 42703895 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 37567040186 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 37567040186 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 37567040186 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 37567040186 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7393295 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7393295 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4970137 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4970137 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154481 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 154481 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153932 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 153932 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12363432 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12363432 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12363432 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12363432 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127450 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.127450 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051836 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.051836 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088730 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088730 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.036218 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.036218 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097057 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.097057 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097057 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097057 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28895.114705 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 28895.114705 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40171.350833 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 40171.350833 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10922.083607 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10922.083607 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7652.178296 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7652.178296 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31316.131217 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 31316.131217 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31316.131217 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 31316.131217 # average overall miss latency +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088742 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088742 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.036243 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.036243 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097053 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.097053 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097053 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.097053 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28892.823107 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 28892.823107 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40142.699833 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 40142.699833 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10941.717120 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10941.717120 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7654.399534 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7654.399534 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31308.293214 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 31308.293214 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31308.293214 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 31308.293214 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -587,62 +592,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 685854 # number of writebacks -system.cpu0.dcache.writebacks::total 685854 # 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number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31544105 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31544105 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34988626814 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 34988626814 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34988626814 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 34988626814 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1461501000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1461501000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2267119000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2267119000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3728620000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3728620000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127450 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127450 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051836 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051836 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088730 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088730 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.036218 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.036218 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097057 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097057 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097057 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097057 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26761.931332 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26761.931332 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37965.045270 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37965.045270 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8921.062231 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8921.062231 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5651.857578 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5651.857578 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29167.248455 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29167.248455 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29167.248455 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29167.248455 # average overall mshr miss latency +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088742 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088742 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.036243 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.036243 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097053 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097053 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097053 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097053 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26759.661203 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26759.661203 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37936.498096 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37936.498096 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8940.695893 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8940.695893 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5654.078688 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5654.078688 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29159.448869 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29159.448869 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29159.448869 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29159.448869 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -650,13 +655,13 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 699671 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.391653 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 47283349 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 700182 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.530084 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 699791 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.391652 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 47290432 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 700302 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.528626 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 40276505250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.391653 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.391652 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992952 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.992952 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id @@ -665,44 +670,44 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 system.cpu0.icache.tags.age_task_id_blocks_1024::2 436 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 48683959 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 48683959 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 47283349 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 47283349 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 47283349 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 47283349 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 47283349 # number of overall hits -system.cpu0.icache.overall_hits::total 47283349 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 700305 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 700305 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 700305 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 700305 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 700305 # number of overall misses -system.cpu0.icache.overall_misses::total 700305 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9967517496 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 9967517496 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 9967517496 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 9967517496 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 9967517496 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 9967517496 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47983654 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47983654 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47983654 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47983654 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47983654 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47983654 # number of overall (read+write) accesses +system.cpu0.icache.tags.tag_accesses 48691282 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 48691282 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 47290432 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 47290432 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 47290432 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 47290432 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 47290432 # number of overall hits +system.cpu0.icache.overall_hits::total 47290432 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 700425 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 700425 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 700425 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 700425 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 700425 # number of overall misses +system.cpu0.icache.overall_misses::total 700425 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9965953746 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 9965953746 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 9965953746 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 9965953746 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 9965953746 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 9965953746 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47990857 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47990857 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47990857 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47990857 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47990857 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47990857 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014595 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.014595 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014595 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.014595 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014595 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.014595 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14233.109140 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14233.109140 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14233.109140 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14233.109140 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14233.109140 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14233.109140 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14228.438085 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14228.438085 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14228.438085 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14228.438085 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14228.438085 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14228.438085 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -711,51 +716,51 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 700305 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 700305 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 700305 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 700305 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 700305 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 700305 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8561918504 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 8561918504 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8561918504 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 8561918504 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8561918504 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 8561918504 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 700425 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 700425 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 700425 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 700425 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 700425 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 700425 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8560109254 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 8560109254 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8560109254 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 8560109254 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8560109254 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 8560109254 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014595 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.014595 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.014595 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12225.985112 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12225.985112 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12225.985112 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12225.985112 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12225.985112 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12225.985112 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12221.307426 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12221.307426 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12221.307426 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12221.307426 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12221.307426 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12221.307426 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2382379 # DTB read hits +system.cpu1.dtb.read_hits 2381610 # DTB read hits system.cpu1.dtb.read_misses 2620 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 205337 # DTB read accesses -system.cpu1.dtb.write_hits 1702197 # DTB write hits +system.cpu1.dtb.write_hits 1701782 # DTB write hits system.cpu1.dtb.write_misses 235 # DTB write misses system.cpu1.dtb.write_acv 24 # DTB write access violations system.cpu1.dtb.write_accesses 89739 # DTB write accesses -system.cpu1.dtb.data_hits 4084576 # DTB hits +system.cpu1.dtb.data_hits 4083392 # DTB hits system.cpu1.dtb.data_misses 2855 # DTB misses system.cpu1.dtb.data_acv 24 # DTB access violations system.cpu1.dtb.data_accesses 295076 # DTB accesses -system.cpu1.itb.fetch_hits 1808740 # ITB hits +system.cpu1.itb.fetch_hits 1808769 # ITB hits system.cpu1.itb.fetch_misses 1064 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1809804 # ITB accesses +system.cpu1.itb.fetch_accesses 1809833 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -768,87 +773,87 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3923834014 # number of cpu cycles simulated +system.cpu1.numCycles 3923834021 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 12951032 # Number of instructions committed -system.cpu1.committedOps 12951032 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 11936898 # Number of integer alu accesses +system.cpu1.committedInsts 12938544 # Number of instructions committed +system.cpu1.committedOps 12938544 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 11924615 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 171199 # Number of float alu accesses -system.cpu1.num_func_calls 411532 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1284277 # number of instructions that are conditional controls -system.cpu1.num_int_insts 11936898 # number of integer instructions +system.cpu1.num_func_calls 411382 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1282019 # number of instructions that are conditional controls +system.cpu1.num_int_insts 11924615 # number of integer instructions system.cpu1.num_fp_insts 171199 # number of float instructions -system.cpu1.num_int_register_reads 16412569 # number of times the integer registers were read -system.cpu1.num_int_register_writes 8783541 # number of times the integer registers were written +system.cpu1.num_int_register_reads 16391744 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8774012 # number of times the integer registers were written system.cpu1.num_fp_register_reads 88996 # number of times the floating registers were read system.cpu1.num_fp_register_writes 90942 # number of times the floating registers were written -system.cpu1.num_mem_refs 4107226 # number of memory refs -system.cpu1.num_load_insts 2395961 # Number of load instructions -system.cpu1.num_store_insts 1711265 # Number of store instructions -system.cpu1.num_idle_cycles 3874307298.691787 # Number of idle cycles -system.cpu1.num_busy_cycles 49526715.308213 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012622 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987378 # Percentage of idle cycles -system.cpu1.Branches 1849703 # Number of branches fetched -system.cpu1.op_class::No_OpClass 699491 5.40% 5.40% # Class of executed instruction -system.cpu1.op_class::IntAlu 7680347 59.29% 64.69% # Class of executed instruction -system.cpu1.op_class::IntMult 22457 0.17% 64.86% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.86% # Class of executed instruction -system.cpu1.op_class::FloatAdd 13113 0.10% 64.96% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1759 0.01% 64.98% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::MemRead 2467292 19.05% 84.02% # Class of executed instruction -system.cpu1.op_class::MemWrite 1712246 13.22% 97.24% # Class of executed instruction -system.cpu1.op_class::IprAccess 357206 2.76% 100.00% # Class of executed instruction +system.cpu1.num_mem_refs 4106042 # number of memory refs +system.cpu1.num_load_insts 2395192 # Number of load instructions +system.cpu1.num_store_insts 1710850 # Number of store instructions +system.cpu1.num_idle_cycles 3874343491.006502 # Number of idle cycles +system.cpu1.num_busy_cycles 49490529.993498 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012613 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987387 # Percentage of idle cycles +system.cpu1.Branches 1847277 # Number of branches fetched +system.cpu1.op_class::No_OpClass 699299 5.40% 5.40% # Class of executed instruction +system.cpu1.op_class::IntAlu 7669413 59.26% 64.67% # Class of executed instruction +system.cpu1.op_class::IntMult 22263 0.17% 64.84% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.84% # Class of executed instruction +system.cpu1.op_class::FloatAdd 13113 0.10% 64.94% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1759 0.01% 64.95% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::MemRead 2466523 19.06% 84.01% # Class of executed instruction +system.cpu1.op_class::MemWrite 1711831 13.23% 97.24% # Class of executed instruction +system.cpu1.op_class::IprAccess 357222 2.76% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 12953911 # Class of executed instruction +system.cpu1.op_class::total 12941423 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2765 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 77892 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 26462 38.26% 38.26% # number of times we switched to this ipl +system.cpu1.kern.inst.quiesce 2766 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 77895 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 26463 38.26% 38.26% # number of times we switched to this ipl system.cpu1.kern.ipl_count::22 1970 2.85% 41.11% # number of times we switched to this ipl system.cpu1.kern.ipl_count::30 512 0.74% 41.85% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 40213 58.15% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 69157 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 25618 48.15% 48.15% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_count::31 40215 58.15% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 69160 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 25619 48.15% 48.15% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::22 1970 3.70% 51.85% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::30 512 0.96% 52.81% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 25106 47.19% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 53206 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1910435586500 97.38% 97.38% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 701157000 0.04% 97.41% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 358940000 0.02% 97.43% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 50421293500 2.57% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1961916977000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.968105 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_good::31 25107 47.19% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 53208 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1910451046000 97.38% 97.38% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 701160000 0.04% 97.41% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 358891000 0.02% 97.43% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 50405883500 2.57% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1961916980500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.968106 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.624325 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.769351 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.624319 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.769346 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed @@ -870,7 +875,7 @@ system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # nu system.cpu1.kern.callpal::swpctx 1967 2.75% 3.35% # number of callpals executed system.cpu1.kern.callpal::tbi 3 0.00% 3.35% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 3.36% # number of callpals executed -system.cpu1.kern.callpal::swpipl 62982 88.13% 91.49% # number of callpals executed +system.cpu1.kern.callpal::swpipl 62985 88.13% 91.49% # number of callpals executed system.cpu1.kern.callpal::rdps 2216 3.10% 94.59% # number of callpals executed system.cpu1.kern.callpal::wrkgp 1 0.00% 94.60% # number of callpals executed system.cpu1.kern.callpal::wrusp 3 0.00% 94.60% # number of callpals executed @@ -879,108 +884,108 @@ system.cpu1.kern.callpal::rti 3692 5.17% 99.77% # nu system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 71465 # number of callpals executed +system.cpu1.kern.callpal::total 71468 # number of callpals executed system.cpu1.kern.mode_switch::kernel 1923 # number of protection mode switches -system.cpu1.kern.mode_switch::user 367 # number of protection mode switches +system.cpu1.kern.mode_switch::user 368 # number of protection mode switches system.cpu1.kern.mode_switch::idle 2902 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 803 -system.cpu1.kern.mode_good::user 367 +system.cpu1.kern.mode_good::kernel 804 +system.cpu1.kern.mode_good::user 368 system.cpu1.kern.mode_good::idle 436 -system.cpu1.kern.mode_switch_good::kernel 0.417577 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.418097 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle 0.150241 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.309322 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 17997631500 0.92% 0.92% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1494992000 0.08% 0.99% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1941547962000 99.01% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_switch_good::total 0.309648 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 17982324500 0.92% 0.92% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1495094500 0.08% 0.99% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1941563117500 99.01% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 1968 # number of times the context was actually changed -system.cpu1.dcache.tags.replacements 157269 # number of replacements -system.cpu1.dcache.tags.tagsinuse 486.065602 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 3912422 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 157596 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 24.825643 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1048852145500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.065602 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949347 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.949347 # Average percentage of cache occupancy +system.cpu1.dcache.tags.replacements 157282 # number of replacements +system.cpu1.dcache.tags.tagsinuse 486.069018 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 3911225 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 157609 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 24.816000 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 1048852201500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.069018 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949354 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.949354 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 327 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::3 295 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.638672 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 16561703 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 16561703 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2221454 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2221454 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1590675 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1590675 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 47775 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 47775 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50240 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 50240 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3812129 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3812129 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3812129 # number of overall hits -system.cpu1.dcache.overall_hits::total 3812129 # number of overall hits +system.cpu1.dcache.tags.tag_accesses 16556980 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 16556980 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 2220683 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2220683 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1590246 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1590246 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 47776 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 47776 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50237 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 50237 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3810929 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3810929 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3810929 # number of overall hits +system.cpu1.dcache.overall_hits::total 3810929 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 115097 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 115097 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 57126 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 57126 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8902 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 8902 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5962 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 5962 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 172223 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 172223 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 172223 # number of overall misses -system.cpu1.dcache.overall_misses::total 172223 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1389994499 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1389994499 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1079772299 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1079772299 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 80592000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 80592000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 43791416 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 43791416 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 2469766798 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 2469766798 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 2469766798 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 2469766798 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2336551 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2336551 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1647801 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1647801 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 56677 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 56677 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56202 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 56202 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 3984352 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3984352 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 3984352 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3984352 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049259 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.049259 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034668 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.034668 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.157065 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.157065 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106082 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106082 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043225 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.043225 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043225 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.043225 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12076.722234 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12076.722234 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18901.591202 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18901.591202 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9053.246461 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9053.246461 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7345.088225 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7345.088225 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14340.516644 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14340.516644 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14340.516644 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14340.516644 # average overall miss latency +system.cpu1.dcache.WriteReq_misses::cpu1.data 57138 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 57138 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8903 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 8903 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5967 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 5967 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 172235 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 172235 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 172235 # number of overall misses +system.cpu1.dcache.overall_misses::total 172235 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1388298999 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1388298999 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1079375302 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1079375302 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 80583500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 80583500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 43835417 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 43835417 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 2467674301 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 2467674301 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 2467674301 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 2467674301 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2335780 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2335780 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1647384 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1647384 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 56679 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 56679 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56204 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 56204 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 3983164 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3983164 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 3983164 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 3983164 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049276 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.049276 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034684 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.034684 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.157078 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.157078 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106167 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106167 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043241 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.043241 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043241 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.043241 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12061.991181 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12061.991181 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18890.673492 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18890.673492 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9051.274851 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9051.274851 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7346.307525 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7346.307525 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14327.368427 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14327.368427 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14327.368427 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14327.368427 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -989,62 +994,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 107940 # number of writebacks -system.cpu1.dcache.writebacks::total 107940 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 107942 # number of writebacks +system.cpu1.dcache.writebacks::total 107942 # number of writebacks system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 115097 # number of ReadReq MSHR misses system.cpu1.dcache.ReadReq_mshr_misses::total 115097 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 57126 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 57126 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8902 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8902 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5962 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 5962 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 172223 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 172223 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 172223 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 172223 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1159712501 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1159712501 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 962952701 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 962952701 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 62788000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 62788000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31865584 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31865584 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2122665202 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2122665202 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2122665202 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2122665202 # number of overall MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 57138 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 57138 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8903 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8903 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5967 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 5967 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 172235 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 172235 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 172235 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 172235 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1158014001 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1158014001 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 962534698 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 962534698 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 62777500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 62777500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31899583 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31899583 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2120548699 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2120548699 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2120548699 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2120548699 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 22446500 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 22446500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 726758000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 726758000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 749204500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 749204500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049259 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049259 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034668 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034668 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.157065 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.157065 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106082 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106082 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043225 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.043225 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043225 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.043225 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10075.957679 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10075.957679 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16856.644978 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16856.644978 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7053.246461 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7053.246461 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5344.780946 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5344.780946 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12325.097124 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12325.097124 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12325.097124 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12325.097124 # average overall mshr miss latency +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 726754500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 726754500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 749201000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 749201000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049276 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049276 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034684 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034684 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.157078 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.157078 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106167 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106167 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043241 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.043241 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043241 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.043241 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10061.200561 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10061.200561 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16845.789107 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16845.789107 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7051.274851 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7051.274851 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5346.000168 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5346.000168 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12311.949946 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12311.949946 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12311.949946 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12311.949946 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1052,13 +1057,13 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 318302 # number of replacements -system.cpu1.icache.tags.tagsinuse 446.541764 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 12635057 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 318814 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 39.631437 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1956986830500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.541764 # Average occupied blocks per requestor +system.cpu1.icache.tags.replacements 318148 # number of replacements +system.cpu1.icache.tags.tagsinuse 446.541580 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 12622723 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 318660 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 39.611884 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1956986313500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.541580 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.872152 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.872152 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -1066,44 +1071,44 @@ system.cpu1.icache.tags.age_task_id_blocks_1024::2 72 system.cpu1.icache.tags.age_task_id_blocks_1024::3 439 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 13272765 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 13272765 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 12635057 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 12635057 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 12635057 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 12635057 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 12635057 # number of overall hits -system.cpu1.icache.overall_hits::total 12635057 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 318854 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 318854 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 318854 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 318854 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 318854 # number of overall misses -system.cpu1.icache.overall_misses::total 318854 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4204550742 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4204550742 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4204550742 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4204550742 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4204550742 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4204550742 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 12953911 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 12953911 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 12953911 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 12953911 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 12953911 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 12953911 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024614 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024614 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024614 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024614 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024614 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024614 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13186.445025 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13186.445025 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13186.445025 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13186.445025 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13186.445025 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13186.445025 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 13260123 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 13260123 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 12622723 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 12622723 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 12622723 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 12622723 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 12622723 # number of overall hits +system.cpu1.icache.overall_hits::total 12622723 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 318700 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 318700 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 318700 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 318700 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 318700 # number of overall misses +system.cpu1.icache.overall_misses::total 318700 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4202225742 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4202225742 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4202225742 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4202225742 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4202225742 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4202225742 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 12941423 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 12941423 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 12941423 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 12941423 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 12941423 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 12941423 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024626 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024626 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024626 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024626 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024626 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024626 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13185.521625 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13185.521625 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13185.521625 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13185.521625 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13185.521625 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13185.521625 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1112,30 +1117,30 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 318854 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 318854 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 318854 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 318854 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 318854 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 318854 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3566590258 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3566590258 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3566590258 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3566590258 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3566590258 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3566590258 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024614 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024614 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024614 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024614 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024614 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024614 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11185.653177 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11185.653177 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11185.653177 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11185.653177 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11185.653177 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11185.653177 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 318700 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 318700 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 318700 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 318700 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 318700 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 318700 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3564575258 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3564575258 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3564575258 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3564575258 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3564575258 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3564575258 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024626 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024626 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024626 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024626 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024626 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024626 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11184.735670 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11184.735670 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11184.735670 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11184.735670 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11184.735670 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11184.735670 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1208,7 +1213,7 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 406206788 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 406213784 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) @@ -1217,14 +1222,14 @@ system.iobus.respLayer0.utilization 0.0 # La system.iobus.respLayer1.occupancy 42016500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41696 # number of replacements -system.iocache.tags.tagsinuse 0.577792 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.577776 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41712 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1755504938000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.577792 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.036112 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.036112 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1755504098000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.577776 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.036111 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.036111 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1240,8 +1245,8 @@ system.iocache.overall_misses::tsunami.ide 176 # system.iocache.overall_misses::total 176 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21474383 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21474383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13634244905 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 13634244905 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13634467901 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 13634467901 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::tsunami.ide 21474383 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 21474383 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::tsunami.ide 21474383 # number of overall miss cycles @@ -1264,17 +1269,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122013.539773 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 122013.539773 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328124.877383 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 328124.877383 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328130.244056 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 328130.244056 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency system.iocache.demand_avg_miss_latency::total 122013.539773 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency system.iocache.overall_avg_miss_latency::total 122013.539773 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 206283 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 206274 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23550 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 23554 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.759363 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.757493 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1290,8 +1295,8 @@ system.iocache.overall_mshr_misses::tsunami.ide 176 system.iocache.overall_mshr_misses::total 176 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12321383 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 12321383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11473540905 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11473540905 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11473763901 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11473763901 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::tsunami.ide 12321383 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 12321383 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::tsunami.ide 12321383 # number of overall MSHR miss cycles @@ -1306,187 +1311,187 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 70007.857955 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276124.877383 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276124.877383 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276130.244056 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276130.244056 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 342754 # number of replacements -system.l2c.tags.tagsinuse 65220.433043 # Cycle average of tags in use -system.l2c.tags.total_refs 2449371 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 407927 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.004435 # Average number of references to valid blocks. +system.l2c.tags.replacements 342765 # number of replacements +system.l2c.tags.tagsinuse 65220.427494 # Cycle average of tags in use +system.l2c.tags.total_refs 2449404 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 407938 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.004354 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 8652068750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55272.994922 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4808.176589 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4932.064474 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 162.933205 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 44.263854 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 55273.007246 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4809.132503 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4932.058830 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 161.965185 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 44.263730 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.843399 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.073367 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.073382 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.075257 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002486 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.002471 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.000675 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.995185 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65173 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 764 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5225 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7223 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 767 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 5220 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 7222 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::4 51853 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.994461 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 25998619 # Number of tag accesses -system.l2c.tags.data_accesses 25998619 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 687419 # 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mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002045 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.039472 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.173317 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60793.986161 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52556.207467 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60230.828221 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 58242.320819 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 52950.882923 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10053.381548 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10008.588533 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10036.562896 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10035.675615 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10015.192140 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10025.309392 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56475.322591 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61281.194151 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 56699.748311 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60793.986161 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53743.165348 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60230.828221 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61134.555501 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 54084.877339 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60793.986161 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53743.165348 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60230.828221 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61134.555501 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 54084.877339 # average overall mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.942939 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.766781 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.867973 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.954158 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.975532 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.964856 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.475985 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.119692 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.417881 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018365 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.328008 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002043 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.039486 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.173319 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018365 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.328008 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002043 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.039486 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.173319 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60538.871181 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52550.828390 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59734.254992 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 59817.406143 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 52934.752136 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10053.230223 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10008.575758 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10036.442405 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10037.871508 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10015.176663 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10026.386313 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56413.793892 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61161.826847 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 56635.575673 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60538.871181 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53720.845810 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59734.254992 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61096.974152 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 54054.286512 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60538.871181 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53720.845810 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59734.254992 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61096.974152 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 54054.286512 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1621,96 +1626,96 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 292732 # Transaction distribution -system.membus.trans_dist::ReadResp 292732 # Transaction distribution +system.membus.trans_dist::ReadReq 292731 # Transaction distribution +system.membus.trans_dist::ReadResp 292731 # Transaction distribution system.membus.trans_dist::WriteReq 14079 # Transaction distribution system.membus.trans_dist::WriteResp 14079 # Transaction distribution -system.membus.trans_dist::Writeback 121224 # Transaction distribution +system.membus.trans_dist::Writeback 121235 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16421 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11471 # Transaction distribution -system.membus.trans_dist::UpgradeResp 7051 # Transaction distribution -system.membus.trans_dist::ReadExReq 124094 # Transaction distribution -system.membus.trans_dist::ReadExResp 123249 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16420 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 11480 # Transaction distribution +system.membus.trans_dist::UpgradeResp 7054 # Transaction distribution +system.membus.trans_dist::ReadExReq 124107 # Transaction distribution +system.membus.trans_dist::ReadExResp 123261 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42552 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 932442 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 974994 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 932487 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 975039 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124815 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124815 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1099809 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1099854 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82034 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31235136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31317170 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31236544 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31318578 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36634738 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 22113 # Total snoops (count) -system.membus.snoop_fanout::samples 600297 # Request fanout histogram +system.membus.pkt_size::total 36636146 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 22119 # Total snoops (count) +system.membus.snoop_fanout::samples 600328 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 600297 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 600328 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 600297 # Request fanout histogram -system.membus.reqLayer0.occupancy 40801500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 600328 # Request fanout histogram +system.membus.reqLayer0.occupancy 40794500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1914880000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1915022000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3840416202 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3840524699 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.respLayer2.occupancy 43136500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 2106484 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2106469 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2106481 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2106466 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 14079 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 14079 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 793794 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 793856 # Transaction distribution system.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 16644 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11537 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 28181 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 298092 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 298092 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1400589 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3132441 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 637707 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 458977 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5629714 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44818176 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119962112 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20406592 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16779186 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 201966066 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 99450 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3260906 # Request fanout histogram +system.toL2Bus.trans_dist::UpgradeReq 16639 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11546 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 28185 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 298132 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 298132 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1400829 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3132611 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 637399 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 458996 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5629835 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44825856 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119969536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20396736 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16779122 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 201971250 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 99473 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3261009 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 3.012796 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.112395 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.112394 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 3219178 98.72% 98.72% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 3219281 98.72% 98.72% # Request fanout histogram system.toL2Bus.snoop_fanout::4 41728 1.28% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3260906 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4802513358 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3261009 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4802800383 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3153866996 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3154409746 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5532423832 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 5532665081 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1434969242 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 1434275242 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 787756714 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 787817718 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA |