diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt | 2271 |
1 files changed, 1134 insertions, 1137 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index a1c48ce35..034bdfed2 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,137 +1,140 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.962822 # Number of seconds simulated -sim_ticks 1962822184500 # Number of ticks simulated -final_tick 1962822184500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.962815 # Number of seconds simulated +sim_ticks 1962815218500 # Number of ticks simulated +final_tick 1962815218500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 916137 # Simulator instruction rate (inst/s) -host_op_rate 916137 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 30287148246 # Simulator tick rate (ticks/s) -host_mem_usage 346744 # Number of bytes of host memory used -host_seconds 64.81 # Real time elapsed on the host -sim_insts 59372170 # Number of instructions simulated -sim_ops 59372170 # Number of ops (including micro ops) simulated +host_inst_rate 1506000 # Simulator instruction rate (inst/s) +host_op_rate 1505999 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49787604582 # Simulator tick rate (ticks/s) +host_mem_usage 317424 # Number of bytes of host memory used +host_seconds 39.42 # Real time elapsed on the host +sim_insts 59372159 # Number of instructions simulated +sim_ops 59372159 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 724800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24150336 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2649344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 138496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1080640 # Number of bytes read from this memory -system.physmem.bytes_read::total 28743616 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 724800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 138496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 863296 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7747520 # Number of bytes written to this memory -system.physmem.bytes_written::total 7747520 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11325 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 377349 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41396 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2164 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16885 # Number of read requests responded to by this memory -system.physmem.num_reads::total 449119 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 121055 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121055 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 369264 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12303884 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1349763 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 70560 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 550554 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14644024 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 369264 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 70560 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 439824 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3947133 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3947133 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3947133 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 369264 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12303884 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1349763 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 70560 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 550554 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18591157 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 449119 # Number of read requests accepted -system.physmem.writeReqs 121055 # Number of write requests accepted -system.physmem.readBursts 449119 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 121055 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28736320 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7296 # Total number of bytes read from write queue -system.physmem.bytesWritten 7746176 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28743616 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7747520 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 114 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu0.inst 724992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24166912 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 138560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1080576 # Number of bytes read from this memory +system.physmem.bytes_read::total 26112000 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 724992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 138560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 863552 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5090112 # Number of bytes written to this memory +system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory +system.physmem.bytes_written::total 7749440 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11328 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 377608 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2165 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16884 # Number of read requests responded to by this memory +system.physmem.num_reads::total 408000 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 79533 # Number of write requests responded to by this memory +system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121085 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 369363 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12312372 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 70592 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 550524 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13303341 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 369363 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 70592 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 439956 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2593271 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::tsunami.ide 1354854 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3948125 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2593271 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 369363 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12312372 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1355343 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 70592 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 550524 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17251466 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 408000 # Number of read requests accepted +system.physmem.writeReqs 121085 # Number of write requests accepted +system.physmem.readBursts 408000 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 121085 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26099968 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 12032 # Total number of bytes read from write queue +system.physmem.bytesWritten 7747840 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26112000 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7749440 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 188 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 3360 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 28065 # Per bank write bursts -system.physmem.perBankRdBursts::1 28141 # Per bank write bursts -system.physmem.perBankRdBursts::2 27986 # Per bank write bursts -system.physmem.perBankRdBursts::3 28553 # Per bank write bursts -system.physmem.perBankRdBursts::4 28160 # Per bank write bursts -system.physmem.perBankRdBursts::5 27775 # Per bank write bursts -system.physmem.perBankRdBursts::6 27616 # Per bank write bursts -system.physmem.perBankRdBursts::7 27528 # Per bank write bursts -system.physmem.perBankRdBursts::8 27559 # Per bank write bursts -system.physmem.perBankRdBursts::9 27974 # Per bank write bursts -system.physmem.perBankRdBursts::10 27981 # Per bank write bursts -system.physmem.perBankRdBursts::11 28021 # Per bank write bursts -system.physmem.perBankRdBursts::12 28612 # Per bank write bursts -system.physmem.perBankRdBursts::13 28738 # Per bank write bursts -system.physmem.perBankRdBursts::14 28459 # Per bank write bursts -system.physmem.perBankRdBursts::15 27837 # Per bank write bursts +system.physmem.perBankRdBursts::0 25223 # Per bank write bursts +system.physmem.perBankRdBursts::1 25569 # Per bank write bursts +system.physmem.perBankRdBursts::2 25254 # Per bank write bursts +system.physmem.perBankRdBursts::3 25702 # Per bank write bursts +system.physmem.perBankRdBursts::4 25695 # Per bank write bursts +system.physmem.perBankRdBursts::5 25237 # Per bank write bursts +system.physmem.perBankRdBursts::6 25154 # Per bank write bursts +system.physmem.perBankRdBursts::7 25289 # Per bank write bursts +system.physmem.perBankRdBursts::8 25197 # Per bank write bursts +system.physmem.perBankRdBursts::9 25673 # Per bank write bursts +system.physmem.perBankRdBursts::10 25761 # Per bank write bursts +system.physmem.perBankRdBursts::11 25821 # Per bank write bursts +system.physmem.perBankRdBursts::12 25887 # Per bank write bursts +system.physmem.perBankRdBursts::13 25811 # Per bank write bursts +system.physmem.perBankRdBursts::14 25568 # Per bank write bursts +system.physmem.perBankRdBursts::15 24971 # Per bank write bursts system.physmem.perBankWrBursts::0 7862 # Per bank write bursts -system.physmem.perBankWrBursts::1 7636 # Per bank write bursts +system.physmem.perBankWrBursts::1 7635 # Per bank write bursts system.physmem.perBankWrBursts::2 7481 # Per bank write bursts -system.physmem.perBankWrBursts::3 8065 # Per bank write bursts -system.physmem.perBankWrBursts::4 7619 # Per bank write bursts +system.physmem.perBankWrBursts::3 8078 # Per bank write bursts +system.physmem.perBankWrBursts::4 7635 # Per bank write bursts system.physmem.perBankWrBursts::5 7244 # Per bank write bursts -system.physmem.perBankWrBursts::6 7159 # Per bank write bursts -system.physmem.perBankWrBursts::7 6941 # Per bank write bursts +system.physmem.perBankWrBursts::6 7160 # Per bank write bursts +system.physmem.perBankWrBursts::7 6937 # Per bank write bursts system.physmem.perBankWrBursts::8 6882 # Per bank write bursts system.physmem.perBankWrBursts::9 7297 # Per bank write bursts -system.physmem.perBankWrBursts::10 7427 # Per bank write bursts -system.physmem.perBankWrBursts::11 7400 # Per bank write bursts +system.physmem.perBankWrBursts::10 7429 # Per bank write bursts +system.physmem.perBankWrBursts::11 7398 # Per bank write bursts system.physmem.perBankWrBursts::12 8124 # Per bank write bursts system.physmem.perBankWrBursts::13 8265 # Per bank write bursts -system.physmem.perBankWrBursts::14 8168 # Per bank write bursts +system.physmem.perBankWrBursts::14 8169 # Per bank write bursts system.physmem.perBankWrBursts::15 7464 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 8 # Number of times write queue was full causing retry -system.physmem.totGap 1962815073500 # Total gap between requests +system.physmem.numWrRetry 6 # Number of times write queue was full causing retry +system.physmem.totGap 1962808109000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 449119 # Read request sizes (log2) +system.physmem.readPktSize::6 408000 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 121055 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 407912 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1721 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2712 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1995 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4350 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3947 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3971 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2533 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2190 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2091 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1633 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1613 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1890 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1879 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2087 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1205 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 975 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 896 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 121085 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 407738 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -158,356 +161,357 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1425 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4875 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4927 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4931 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4933 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5467 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 905 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 923 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 937 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 961 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1637 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1890 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1946 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1888 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 14 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 68642 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 531.489409 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 323.678439 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 416.279001 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15609 22.74% 22.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11929 17.38% 40.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5150 7.50% 47.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3087 4.50% 52.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3390 4.94% 57.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1779 2.59% 59.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1473 2.15% 61.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1315 1.92% 63.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24910 36.29% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 68642 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7087 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 63.355581 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 1920.089024 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 7082 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-8191 1 0.01% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-45055 1 0.01% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-61439 1 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::73728-77823 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::122880-126975 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7087 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7087 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.078312 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.846071 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 3.814192 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 5314 74.98% 74.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 115 1.62% 76.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1264 17.84% 94.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 37 0.52% 94.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 12 0.17% 95.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 12 0.17% 95.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 26 0.37% 95.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 96 1.35% 97.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 18 0.25% 97.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 39 0.55% 97.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 16 0.23% 98.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 10 0.14% 98.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 12 0.17% 98.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 8 0.11% 98.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 4 0.06% 98.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 15 0.21% 98.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 3 0.04% 98.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 4 0.06% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 2 0.03% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 1 0.01% 98.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 3 0.04% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38 2 0.03% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 10 0.14% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 6 0.08% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 6 0.08% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 2 0.03% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 2 0.03% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44 2 0.03% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::45 4 0.06% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46 1 0.01% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 10 0.14% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48 2 0.03% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 2 0.03% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::55 1 0.01% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56 9 0.13% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::57 14 0.20% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::58 3 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7087 # Writes before turning the bus around for reads -system.physmem.totQLat 7297703000 # Total ticks spent queuing -system.physmem.totMemAccLat 15716546750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2245025000 # Total ticks spent in databus transfers -system.physmem.avgQLat 16253.06 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 1952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6075 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8896 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8887 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8584 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5640 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 13 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 66023 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 512.666919 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 309.343673 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 413.043592 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15664 23.73% 23.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11865 17.97% 41.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5137 7.78% 49.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3080 4.67% 54.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3330 5.04% 59.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1778 2.69% 61.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1463 2.22% 64.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1306 1.98% 66.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22400 33.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 66023 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5447 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 74.865981 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2190.069327 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 5442 99.91% 99.91% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-8191 1 0.02% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-45055 1 0.02% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::73728-77823 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::122880-126975 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5447 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5447 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.225078 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.080270 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 19.855094 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4780 87.75% 87.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 19 0.35% 88.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 16 0.29% 88.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 235 4.31% 92.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 38 0.70% 93.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 9 0.17% 93.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 13 0.24% 93.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 10 0.18% 94.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 23 0.42% 94.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 3 0.06% 94.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 2 0.04% 94.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.02% 94.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 7 0.13% 94.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.09% 94.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.07% 94.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 29 0.53% 95.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 14 0.26% 95.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 6 0.11% 95.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 6 0.11% 95.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 182 3.34% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.04% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.04% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 10 0.18% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.04% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 5 0.09% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 5 0.09% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 8 0.15% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.04% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 2 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5447 # Writes before turning the bus around for reads +system.physmem.totQLat 2167934250 # Total ticks spent queuing +system.physmem.totMemAccLat 9814409250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2039060000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5316.01 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 35003.06 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 14.64 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24066.01 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.30 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 14.64 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.30 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.95 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.15 # Data bus utilization in percentage -system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.13 # Data bus utilization in percentage +system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.12 # Average write queue length when enqueuing -system.physmem.readRowHits 403892 # Number of row buffer hits during reads -system.physmem.writeRowHits 97505 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.95 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.55 # Row buffer hit rate for writes -system.physmem.avgGap 3442484.35 # Average gap between requests -system.physmem.pageHitRate 87.96 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1840580762750 # Time in different power states -system.physmem.memoryStateTime::REF 65542880000 # Time in different power states +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.06 # Average write queue length when enqueuing +system.physmem.readRowHits 365758 # Number of row buffer hits during reads +system.physmem.writeRowHits 97091 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.69 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.18 # Row buffer hit rate for writes +system.physmem.avgGap 3709816.21 # Average gap between requests +system.physmem.pageHitRate 87.51 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1840831671000 # Time in different power states +system.physmem.memoryStateTime::REF 65542620000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 56696821000 # Time in different power states +system.physmem.memoryStateTime::ACT 56438386500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 18645480 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 292657 # Transaction distribution -system.membus.trans_dist::ReadResp 292657 # Transaction distribution +system.membus.throughput 17291736 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 292660 # Transaction distribution +system.membus.trans_dist::ReadResp 292660 # Transaction distribution system.membus.trans_dist::WriteReq 12414 # Transaction distribution system.membus.trans_dist::WriteResp 12414 # Transaction distribution -system.membus.trans_dist::Writeback 121055 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4555 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1018 # Transaction distribution +system.membus.trans_dist::Writeback 79533 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4556 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1019 # Transaction distribution system.membus.trans_dist::UpgradeResp 3360 # Transaction distribution -system.membus.trans_dist::ReadExReq 164356 # Transaction distribution -system.membus.trans_dist::ReadExResp 164254 # Transaction distribution +system.membus.trans_dist::ReadExReq 122803 # Transaction distribution +system.membus.trans_dist::ReadExResp 122701 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39228 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 904273 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 943501 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124647 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124647 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1068148 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 904540 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 943768 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83295 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83295 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1027063 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68738 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31184320 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 31253058 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5306816 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5306816 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36559874 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36559874 # Total data (bytes) -system.membus.snoop_data_through_bus 37888 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 39221000 # Layer occupancy (ticks) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31201152 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 31269890 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 33930178 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 33930178 # Total data (bytes) +system.membus.snoop_data_through_bus 10304 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 39224500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1574833000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1533573250 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3826410374 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3826483141 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376647250 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 43139750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 342221 # number of replacements -system.l2c.tags.tagsinuse 65256.412579 # Cycle average of tags in use -system.l2c.tags.total_refs 2544259 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 407367 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.245619 # Average number of references to valid blocks. +system.l2c.tags.replacements 342222 # number of replacements +system.l2c.tags.tagsinuse 65256.426750 # Cycle average of tags in use +system.l2c.tags.total_refs 2542307 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 407368 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.240812 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 8652281750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55518.574788 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3744.543964 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4299.514442 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1171.756098 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 522.023286 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.847146 # 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average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10258.478632 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10043.005210 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_mshr_miss_rate::total 0.135701 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.950694 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.870130 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.937443 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.712644 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.792079 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.755319 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.485366 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.157133 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.382340 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.021011 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.434636 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.004670 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.030627 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.168399 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.021011 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.434636 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.004670 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.030627 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.168399 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60278.469280 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52492.993252 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61937.413395 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 52912.555559 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001.767960 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.650716 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56065.515243 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60544.909206 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 56643.410992 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60839.625077 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53504.540544 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61323.243993 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 60715.816579 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 54048.159692 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60839.625077 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53504.540544 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61323.243993 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 60715.816579 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 54048.159692 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56070.797953 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60481.716729 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 56639.797032 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60278.469280 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53506.457848 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61937.413395 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 60638.485413 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 54034.451306 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60278.469280 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53506.457848 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61937.413395 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 60638.485413 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 54034.451306 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -643,101 +647,93 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.tags.replacements 41699 # number of replacements -system.iocache.tags.tagsinuse 0.570023 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.569942 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1756486423000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.570023 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035626 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035626 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1756486320000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.569942 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035621 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035621 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375552 # Number of tag accesses system.iocache.tags.data_accesses 375552 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses system.iocache.ReadReq_misses::total 176 # number of ReadReq misses -system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses -system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41728 # number of demand (read+write) misses -system.iocache.demand_misses::total 41728 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41728 # number of overall misses -system.iocache.overall_misses::total 41728 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21474883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21474883 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 12370994210 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 12370994210 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 12392469093 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 12392469093 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 12392469093 # number of overall miss cycles -system.iocache.overall_miss_latency::total 12392469093 # number of overall miss cycles +system.iocache.demand_misses::tsunami.ide 176 # number of demand (read+write) misses +system.iocache.demand_misses::total 176 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 176 # number of overall misses +system.iocache.overall_misses::total 176 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21474383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21474383 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21474383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21474383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21474383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21474383 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) -system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41728 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41728 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41728 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41728 # number of overall (read+write) accesses +system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::tsunami.ide 176 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 176 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 176 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 176 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122016.380682 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122016.380682 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 297723.195273 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 297723.195273 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 296982.100580 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 296982.100580 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 296982.100580 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 296982.100580 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 362942 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122013.539773 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122013.539773 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 122013.539773 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 122013.539773 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 28216 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.862986 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.fast_writes 41552 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41523 # number of writebacks -system.iocache.writebacks::total 41523 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12321883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12321883 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10208100710 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 10208100710 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 10220422593 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10220422593 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 10220422593 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10220422593 # number of overall MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 176 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 176 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 176 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12321383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12321383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2504351556 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2504351556 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12321383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12321383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12321383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12321383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70010.698864 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70010.698864 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 245670.502262 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 245670.502262 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 244929.605852 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 244929.605852 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 244929.605852 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 244929.605852 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70007.857955 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60270.301213 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60270.301213 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -755,22 +751,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 6067358 # DTB read hits +system.cpu0.dtb.read_hits 6067147 # DTB read hits system.cpu0.dtb.read_misses 7765 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 524069 # DTB read accesses -system.cpu0.dtb.write_hits 4265662 # DTB write hits +system.cpu0.dtb.write_hits 4265547 # DTB write hits system.cpu0.dtb.write_misses 910 # DTB write misses system.cpu0.dtb.write_acv 133 # DTB write access violations system.cpu0.dtb.write_accesses 202595 # DTB write accesses -system.cpu0.dtb.data_hits 10333020 # DTB hits +system.cpu0.dtb.data_hits 10332694 # DTB hits system.cpu0.dtb.data_misses 8675 # DTB misses system.cpu0.dtb.data_acv 343 # DTB access violations system.cpu0.dtb.data_accesses 726664 # DTB accesses -system.cpu0.itb.fetch_hits 3354842 # ITB hits +system.cpu0.itb.fetch_hits 3354719 # ITB hits system.cpu0.itb.fetch_misses 3984 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3358826 # ITB accesses +system.cpu0.itb.fetch_accesses 3358703 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -783,34 +779,34 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3925644369 # number of cpu cycles simulated +system.cpu0.numCycles 3925630437 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 38276564 # Number of instructions committed -system.cpu0.committedOps 38276564 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 35596868 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 153627 # Number of float alu accesses -system.cpu0.num_func_calls 936507 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4464991 # number of instructions that are conditional controls -system.cpu0.num_int_insts 35596868 # number of integer instructions -system.cpu0.num_fp_insts 153627 # number of float instructions -system.cpu0.num_int_register_reads 48919002 # number of times the integer registers were read -system.cpu0.num_int_register_writes 26532177 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 75066 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 75978 # number of times the floating registers were written -system.cpu0.num_mem_refs 10366198 # number of memory refs -system.cpu0.num_load_insts 6090760 # Number of load instructions -system.cpu0.num_store_insts 4275438 # Number of store instructions -system.cpu0.num_idle_cycles 3742234246.498094 # Number of idle cycles -system.cpu0.num_busy_cycles 183410122.501907 # Number of busy cycles -system.cpu0.not_idle_fraction 0.046721 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.953279 # Percentage of idle cycles -system.cpu0.Branches 5694814 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2096369 5.48% 5.48% # Class of executed instruction -system.cpu0.op_class::IntAlu 24995370 65.29% 70.76% # Class of executed instruction -system.cpu0.op_class::IntMult 39322 0.10% 70.86% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 70.86% # Class of executed instruction -system.cpu0.op_class::FloatAdd 12602 0.03% 70.90% # Class of executed instruction +system.cpu0.committedInsts 38276405 # Number of instructions committed +system.cpu0.committedOps 38276405 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 35596815 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 153493 # Number of float alu accesses +system.cpu0.num_func_calls 936479 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4465105 # number of instructions that are conditional controls +system.cpu0.num_int_insts 35596815 # number of integer instructions +system.cpu0.num_fp_insts 153493 # number of float instructions +system.cpu0.num_int_register_reads 48919188 # number of times the integer registers were read +system.cpu0.num_int_register_writes 26532196 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 75000 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 75910 # number of times the floating registers were written +system.cpu0.num_mem_refs 10365856 # number of memory refs +system.cpu0.num_load_insts 6090539 # Number of load instructions +system.cpu0.num_store_insts 4275317 # Number of store instructions +system.cpu0.num_idle_cycles 3742236660.998093 # Number of idle cycles +system.cpu0.num_busy_cycles 183393776.001907 # Number of busy cycles +system.cpu0.not_idle_fraction 0.046717 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.953283 # Percentage of idle cycles +system.cpu0.Branches 5694884 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2096297 5.48% 5.48% # Class of executed instruction +system.cpu0.op_class::IntAlu 24983670 65.26% 70.73% # Class of executed instruction +system.cpu0.op_class::IntMult 39322 0.10% 70.83% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 70.83% # Class of executed instruction +system.cpu0.op_class::FloatAdd 24596 0.06% 70.90% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 70.90% # Class of executed instruction system.cpu0.op_class::FloatCvt 0 0.00% 70.90% # Class of executed instruction system.cpu0.op_class::FloatMult 0 0.00% 70.90% # Class of executed instruction @@ -836,37 +832,37 @@ system.cpu0.op_class::SimdFloatMisc 0 0.00% 70.90% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 70.90% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 70.90% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::MemRead 6233117 16.28% 87.18% # Class of executed instruction -system.cpu0.op_class::MemWrite 4280683 11.18% 98.36% # Class of executed instruction -system.cpu0.op_class::IprAccess 626236 1.64% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 6232893 16.28% 87.18% # Class of executed instruction +system.cpu0.op_class::MemWrite 4280562 11.18% 98.36% # Class of executed instruction +system.cpu0.op_class::IprAccess 626200 1.64% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 38285582 # Class of executed instruction +system.cpu0.op_class::total 38285423 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4866 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 138364 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 44810 38.76% 38.76% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 4863 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 138357 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 44808 38.76% 38.76% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 131 0.11% 38.88% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1975 1.71% 40.58% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 16 0.01% 40.60% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 68668 59.40% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 115600 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 44285 48.84% 48.84% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::31 68665 59.40% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 115595 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 44283 48.84% 48.84% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 131 0.14% 48.98% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1975 2.18% 51.16% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 16 0.02% 51.18% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 44269 48.82% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 90676 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1909704051500 97.29% 97.29% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 94854000 0.00% 97.30% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 764030500 0.04% 97.34% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_good::31 44267 48.82% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 90672 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1909699143000 97.29% 97.29% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 95243500 0.00% 97.30% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 764380500 0.04% 97.34% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::30 12585500 0.00% 97.34% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 52245891000 2.66% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1962821412500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.988284 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_ticks::31 52243094000 2.66% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1962814446500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.988283 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.644682 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.644681 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::total 0.784394 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed @@ -903,10 +899,10 @@ system.cpu0.kern.callpal::wripir 86 0.07% 0.07% # nu system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal::swpctx 2218 1.80% 1.88% # number of callpals executed +system.cpu0.kern.callpal::swpctx 2216 1.80% 1.87% # number of callpals executed system.cpu0.kern.callpal::tbi 51 0.04% 1.92% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.01% 1.92% # number of callpals executed -system.cpu0.kern.callpal::swpipl 109461 88.95% 90.88% # number of callpals executed +system.cpu0.kern.callpal::swpipl 109456 88.95% 90.88% # number of callpals executed system.cpu0.kern.callpal::rdps 6662 5.41% 96.29% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.29% # number of callpals executed system.cpu0.kern.callpal::wrusp 4 0.00% 96.29% # number of callpals executed @@ -915,21 +911,21 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.30% # nu system.cpu0.kern.callpal::rti 4016 3.26% 99.57% # number of callpals executed system.cpu0.kern.callpal::callsys 394 0.32% 99.89% # number of callpals executed system.cpu0.kern.callpal::imb 139 0.11% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 123054 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 5726 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1371 # number of protection mode switches +system.cpu0.kern.callpal::total 123047 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 5724 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1372 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1370 -system.cpu0.kern.mode_good::user 1371 +system.cpu0.kern.mode_good::kernel 1371 +system.cpu0.kern.mode_good::user 1372 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.239260 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.239518 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.386220 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1959031016000 99.81% 99.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3790392000 0.19% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.386556 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1959023925000 99.81% 99.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3790517000 0.19% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 2219 # number of times the context was actually changed +system.cpu0.kern.swap_context 2217 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -961,42 +957,43 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 108070579 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2148343 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2148328 # Transaction distribution +system.toL2Bus.throughput 109416622 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2148133 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2148118 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 12414 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 12414 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 850135 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 4614 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 1062 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 5676 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 363639 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 322090 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1078600 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2181406 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 927231 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1598323 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5785560 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 34514560 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 81611821 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 29671360 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 63815893 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 209613634 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 209603138 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 2520192 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 5075991989 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::Writeback 850078 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 41558 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 4615 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 1065 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 5680 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 322069 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 322069 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1078328 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2181300 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 927173 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1598235 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5785036 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 34505856 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 81606637 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 29669504 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 63812309 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 209594306 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 209584002 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 5180608 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 5075622491 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 738000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2429088500 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2428486244 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4030648808 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4030575545 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 2086694241 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 2086565739 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 2646669064 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 2646502814 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.1 # Layer utilization (%) -system.iobus.throughput 1391043 # Throughput (bytes/s) +system.iobus.throughput 1391048 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7376 # Transaction distribution system.iobus.trans_dist::ReadResp 7376 # Transaction distribution system.iobus.trans_dist::WriteReq 53966 # Transaction distribution @@ -1056,21 +1053,21 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 380139843 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 374413689 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 26814000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 43231750 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42018250 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 538677 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.393435 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 37746273 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 539189 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 70.005644 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 538541 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.393356 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 37746250 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 539053 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 70.023263 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 40276505250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.393435 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.393356 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992956 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.992956 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -1079,44 +1076,44 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 system.cpu0.icache.tags.age_task_id_blocks_1024::2 442 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 38824893 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 38824893 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 37746273 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 37746273 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 37746273 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 37746273 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 37746273 # number of overall hits -system.cpu0.icache.overall_hits::total 37746273 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 539310 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 539310 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 539310 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 539310 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 539310 # number of overall misses -system.cpu0.icache.overall_misses::total 539310 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7764312000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 7764312000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7764312000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 7764312000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7764312000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 7764312000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 38285583 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 38285583 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 38285583 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 38285583 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 38285583 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 38285583 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014087 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014087 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014087 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014087 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014087 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014087 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14396.751405 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14396.751405 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14396.751405 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14396.751405 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14396.751405 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14396.751405 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 38824598 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 38824598 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 37746250 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 37746250 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 37746250 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 37746250 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 37746250 # number of overall hits +system.cpu0.icache.overall_hits::total 37746250 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 539174 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 539174 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 539174 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 539174 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 539174 # number of overall misses +system.cpu0.icache.overall_misses::total 539174 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7756302744 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 7756302744 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 7756302744 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 7756302744 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7756302744 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 7756302744 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 38285424 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 38285424 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 38285424 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 38285424 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 38285424 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 38285424 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014083 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014083 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014083 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014083 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014083 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014083 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14385.528130 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14385.528130 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14385.528130 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14385.528130 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14385.528130 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14385.528130 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1125,119 +1122,119 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 539310 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 539310 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 539310 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 539310 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 539310 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 539310 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6681305000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 6681305000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6681305000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 6681305000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6681305000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 6681305000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014087 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014087 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014087 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014087 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014087 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014087 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12388.616936 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12388.616936 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12388.616936 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12388.616936 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12388.616936 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12388.616936 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 539174 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 539174 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 539174 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 539174 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 539174 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 539174 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6673548256 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 6673548256 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6673548256 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 6673548256 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6673548256 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 6673548256 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014083 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014083 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014083 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014083 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014083 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014083 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12377.355466 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12377.355466 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12377.355466 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12377.355466 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12377.355466 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12377.355466 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 871224 # number of replacements -system.cpu0.dcache.tags.tagsinuse 481.747613 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 9466123 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 871736 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 10.858933 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 871192 # number of replacements +system.cpu0.dcache.tags.tagsinuse 481.742326 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 9465806 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 871704 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 10.858968 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 108210250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 481.747613 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.940913 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.940913 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 481.742326 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.940903 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.940903 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 322 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 42234072 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 42234072 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 5299987 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5299987 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3905819 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3905819 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 124795 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 124795 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 131586 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 131586 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9205806 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 9205806 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9205806 # number of overall hits -system.cpu0.dcache.overall_hits::total 9205806 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 645326 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 645326 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 224198 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 224198 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7833 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 7833 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 495 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 495 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 869524 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 869524 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 869524 # number of overall misses -system.cpu0.dcache.overall_misses::total 869524 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 23374169264 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 23374169264 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9262123232 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 9262123232 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 102899750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 102899750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3567062 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 3567062 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 32636292496 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 32636292496 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 32636292496 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 32636292496 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5945313 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 5945313 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4130017 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4130017 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 132628 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 132628 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 132081 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 132081 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 10075330 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 10075330 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 10075330 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 10075330 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.108544 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.108544 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.054285 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.054285 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059060 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059060 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003748 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003748 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.086302 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.086302 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.086302 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.086302 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 36220.715211 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 36220.715211 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41312.247353 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 41312.247353 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13136.697306 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13136.697306 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7206.185859 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7206.185859 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37533.515459 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 37533.515459 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37533.515459 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 37533.515459 # average overall miss latency +system.cpu0.dcache.tags.tag_accesses 42232679 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 42232679 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 5299779 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5299779 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3905718 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3905718 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 124794 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 124794 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 131579 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 131579 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9205497 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 9205497 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9205497 # number of overall hits +system.cpu0.dcache.overall_hits::total 9205497 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 645318 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 645318 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 224183 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 224183 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7829 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 7829 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 497 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 497 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 869501 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 869501 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 869501 # number of overall misses +system.cpu0.dcache.overall_misses::total 869501 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 23374202500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 23374202500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9262527483 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 9262527483 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 102834500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 102834500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3584562 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 3584562 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 32636729983 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 32636729983 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 32636729983 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 32636729983 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5945097 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 5945097 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4129901 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4129901 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 132623 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 132623 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 132076 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 132076 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10074998 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10074998 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10074998 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10074998 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.108546 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.108546 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.054283 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.054283 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059032 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059032 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003763 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003763 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.086303 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.086303 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.086303 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.086303 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 36221.215742 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 36221.215742 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41316.814758 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 41316.814758 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13135.074722 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13135.074722 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7212.398390 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7212.398390 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37535.011441 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 37535.011441 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37535.011441 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 37535.011441 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1246,62 +1243,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 405192 # number of writebacks -system.cpu0.dcache.writebacks::total 405192 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 645326 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 645326 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 224198 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 224198 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 7833 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7833 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 495 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 495 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 869524 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 869524 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 869524 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 869524 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21958342736 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21958342736 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8764766768 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8764766768 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 87220250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 87220250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 2576938 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2576938 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 30723109504 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 30723109504 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 30723109504 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 30723109504 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1004924500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1004924500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1718153000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1718153000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2723077500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2723077500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.108544 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.108544 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.054285 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.054285 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059060 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059060 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003748 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.003748 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.086302 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.086302 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.086302 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.086302 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 34026.744213 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 34026.744213 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39093.866886 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39093.866886 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11134.973829 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11134.973829 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5205.935354 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5205.935354 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35333.250726 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35333.250726 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35333.250726 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35333.250726 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 405151 # number of writebacks +system.cpu0.dcache.writebacks::total 405151 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 645318 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 645318 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 224183 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 224183 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 7829 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7829 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 497 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 497 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 869501 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 869501 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 869501 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 869501 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21958327500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21958327500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8765186517 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8765186517 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 87163500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 87163500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 2590438 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2590438 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 30723514017 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 30723514017 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 30723514017 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 30723514017 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1004927000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1004927000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1718158000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1718158000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2723085000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2723085000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.108546 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.108546 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.054283 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.054283 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059032 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059032 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003763 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.003763 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.086303 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.086303 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.086303 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.086303 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 34027.142432 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 34027.142432 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39098.354991 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39098.354991 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11133.414229 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11133.414229 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5212.148893 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5212.148893 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35334.650583 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35334.650583 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35334.650583 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35334.650583 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1313,22 +1310,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 3617105 # DTB read hits +system.cpu1.dtb.read_hits 3617054 # DTB read hits system.cpu1.dtb.read_misses 2620 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 205337 # DTB read accesses -system.cpu1.dtb.write_hits 2433899 # DTB write hits +system.cpu1.dtb.write_hits 2433875 # DTB write hits system.cpu1.dtb.write_misses 235 # DTB write misses system.cpu1.dtb.write_acv 24 # DTB write access violations system.cpu1.dtb.write_accesses 89739 # DTB write accesses -system.cpu1.dtb.data_hits 6051004 # DTB hits +system.cpu1.dtb.data_hits 6050929 # DTB hits system.cpu1.dtb.data_misses 2855 # DTB misses system.cpu1.dtb.data_acv 24 # DTB access violations system.cpu1.dtb.data_accesses 295076 # DTB accesses -system.cpu1.itb.fetch_hits 1988116 # ITB hits +system.cpu1.itb.fetch_hits 1988100 # ITB hits system.cpu1.itb.fetch_misses 1064 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1989180 # ITB accesses +system.cpu1.itb.fetch_accesses 1989164 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1341,34 +1338,34 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3923841481 # number of cpu cycles simulated +system.cpu1.numCycles 3923841470 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 21095606 # Number of instructions committed -system.cpu1.committedOps 21095606 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 19410796 # Number of integer alu accesses +system.cpu1.committedInsts 21095754 # Number of instructions committed +system.cpu1.committedOps 21095754 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 19410964 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 175175 # Number of float alu accesses -system.cpu1.num_func_calls 648522 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2286515 # number of instructions that are conditional controls -system.cpu1.num_int_insts 19410796 # number of integer instructions +system.cpu1.num_func_calls 648514 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2286581 # number of instructions that are conditional controls +system.cpu1.num_int_insts 19410964 # number of integer instructions system.cpu1.num_fp_insts 175175 # number of float instructions -system.cpu1.num_int_register_reads 26519930 # number of times the integer registers were read -system.cpu1.num_int_register_writes 14289781 # number of times the integer registers were written +system.cpu1.num_int_register_reads 26520307 # number of times the integer registers were read +system.cpu1.num_int_register_writes 14289908 # number of times the integer registers were written system.cpu1.num_fp_register_reads 90745 # number of times the floating registers were read system.cpu1.num_fp_register_writes 92744 # number of times the floating registers were written -system.cpu1.num_mem_refs 6073244 # number of memory refs -system.cpu1.num_load_insts 3630952 # Number of load instructions -system.cpu1.num_store_insts 2442292 # Number of store instructions -system.cpu1.num_idle_cycles 3837671905.347151 # Number of idle cycles -system.cpu1.num_busy_cycles 86169575.652849 # Number of busy cycles -system.cpu1.not_idle_fraction 0.021961 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.978039 # Percentage of idle cycles -system.cpu1.Branches 3164985 # Number of branches fetched -system.cpu1.op_class::No_OpClass 1250072 5.92% 5.92% # Class of executed instruction -system.cpu1.op_class::IntAlu 13187049 62.50% 68.43% # Class of executed instruction -system.cpu1.op_class::IntMult 30193 0.14% 68.57% # Class of executed instruction +system.cpu1.num_mem_refs 6073169 # number of memory refs +system.cpu1.num_load_insts 3630901 # Number of load instructions +system.cpu1.num_store_insts 2442268 # Number of store instructions +system.cpu1.num_idle_cycles 3837673362.965370 # Number of idle cycles +system.cpu1.num_busy_cycles 86168107.034630 # Number of busy cycles +system.cpu1.not_idle_fraction 0.021960 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.978040 # Percentage of idle cycles +system.cpu1.Branches 3165037 # Number of branches fetched +system.cpu1.op_class::No_OpClass 1250062 5.92% 5.92% # Class of executed instruction +system.cpu1.op_class::IntAlu 13186802 62.50% 68.43% # Class of executed instruction +system.cpu1.op_class::IntMult 30198 0.14% 68.57% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 68.57% # Class of executed instruction -system.cpu1.op_class::FloatAdd 13163 0.06% 68.63% # Class of executed instruction +system.cpu1.op_class::FloatAdd 13644 0.06% 68.63% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 68.63% # Class of executed instruction system.cpu1.op_class::FloatCvt 0 0.00% 68.63% # Class of executed instruction system.cpu1.op_class::FloatMult 0 0.00% 68.63% # Class of executed instruction @@ -1394,34 +1391,34 @@ system.cpu1.op_class::SimdFloatMisc 0 0.00% 68.64% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 68.64% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.64% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::MemRead 3726131 17.66% 86.30% # Class of executed instruction -system.cpu1.op_class::MemWrite 2443312 11.58% 97.88% # Class of executed instruction -system.cpu1.op_class::IprAccess 446806 2.12% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 3726078 17.66% 86.30% # Class of executed instruction +system.cpu1.op_class::MemWrite 2443288 11.58% 97.88% # Class of executed instruction +system.cpu1.op_class::IprAccess 446802 2.12% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 21098485 # Class of executed instruction +system.cpu1.op_class::total 21098633 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 3863 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 100735 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 37219 40.29% 40.29% # number of times we switched to this ipl +system.cpu1.kern.inst.hwrei 100733 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 37218 40.29% 40.29% # number of times we switched to this ipl system.cpu1.kern.ipl_count::22 1970 2.13% 42.42% # number of times we switched to this ipl system.cpu1.kern.ipl_count::30 86 0.09% 42.51% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 53109 57.49% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 92384 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 36367 48.68% 48.68% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_count::31 53108 57.49% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 92382 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 36366 48.68% 48.68% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::22 1970 2.64% 51.32% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::30 86 0.12% 51.43% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 36281 48.57% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 74704 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1906656399000 97.18% 97.18% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 706249000 0.04% 97.22% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_good::31 36280 48.57% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 74702 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1906657223000 97.18% 97.18% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 706239500 0.04% 97.22% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::30 59367000 0.00% 97.22% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 54498695500 2.78% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1961920710500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 54497875500 2.78% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1961920705000 # number of cycles we spent at this ipl system.cpu1.kern.ipl_used::0 0.977108 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.683142 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.808625 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.683136 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.808621 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed @@ -1443,7 +1440,7 @@ system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # nu system.cpu1.kern.callpal::swpctx 2020 2.13% 2.15% # number of callpals executed system.cpu1.kern.callpal::tbi 3 0.00% 2.16% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 2.16% # number of callpals executed -system.cpu1.kern.callpal::swpipl 87061 91.90% 94.06% # number of callpals executed +system.cpu1.kern.callpal::swpipl 87059 91.90% 94.06% # number of callpals executed system.cpu1.kern.callpal::rdps 2187 2.31% 96.37% # number of callpals executed system.cpu1.kern.callpal::wrkgp 1 0.00% 96.37% # number of callpals executed system.cpu1.kern.callpal::wrusp 3 0.00% 96.38% # number of callpals executed @@ -1452,72 +1449,72 @@ system.cpu1.kern.callpal::rti 3266 3.45% 99.83% # nu system.cpu1.kern.callpal::callsys 121 0.13% 99.95% # number of callpals executed system.cpu1.kern.callpal::imb 42 0.04% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 94734 # number of callpals executed +system.cpu1.kern.callpal::total 94732 # number of callpals executed system.cpu1.kern.mode_switch::kernel 2415 # number of protection mode switches -system.cpu1.kern.mode_switch::user 366 # number of protection mode switches +system.cpu1.kern.mode_switch::user 367 # number of protection mode switches system.cpu1.kern.mode_switch::idle 2037 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 414 -system.cpu1.kern.mode_good::user 366 +system.cpu1.kern.mode_good::kernel 415 +system.cpu1.kern.mode_good::user 367 system.cpu1.kern.mode_good::idle 48 -system.cpu1.kern.mode_switch_good::kernel 0.171429 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.171843 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle 0.023564 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.171856 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 65780447000 3.35% 3.35% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1486717000 0.08% 3.43% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1893764152500 96.57% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_switch_good::total 0.172235 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 65779284000 3.35% 3.35% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1486343500 0.08% 3.43% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1893759051500 96.57% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 2021 # number of times the context was actually changed -system.cpu1.icache.tags.replacements 463064 # number of replacements -system.cpu1.icache.tags.tagsinuse 500.061225 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 20634869 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 463576 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 44.512376 # Average number of references to valid blocks. +system.cpu1.icache.tags.replacements 463035 # number of replacements +system.cpu1.icache.tags.tagsinuse 500.061178 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 20635046 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 463547 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 44.515542 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 97712638250 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 500.061225 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_blocks::cpu1.inst 500.061178 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.976682 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.976682 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 108 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 404 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 21562101 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 21562101 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 20634869 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 20634869 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 20634869 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 20634869 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 20634869 # number of overall hits -system.cpu1.icache.overall_hits::total 20634869 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 463616 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 463616 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 463616 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 463616 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 463616 # number of overall misses -system.cpu1.icache.overall_misses::total 463616 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6201828741 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6201828741 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6201828741 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6201828741 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6201828741 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6201828741 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 21098485 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 21098485 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 21098485 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 21098485 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 21098485 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 21098485 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.021974 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.021974 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.021974 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.021974 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.021974 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.021974 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13377.080905 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13377.080905 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13377.080905 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13377.080905 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13377.080905 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13377.080905 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 21562220 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 21562220 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 20635046 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 20635046 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 20635046 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 20635046 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 20635046 # number of overall hits +system.cpu1.icache.overall_hits::total 20635046 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 463587 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 463587 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 463587 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 463587 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 463587 # number of overall misses +system.cpu1.icache.overall_misses::total 463587 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6202855739 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 6202855739 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 6202855739 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6202855739 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6202855739 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6202855739 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 21098633 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 21098633 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 21098633 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 21098633 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 21098633 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 21098633 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.021972 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.021972 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.021972 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.021972 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.021972 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.021972 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13380.133047 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13380.133047 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13380.133047 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13380.133047 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13380.133047 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13380.133047 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1526,118 +1523,118 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 463616 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 463616 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 463616 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 463616 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 463616 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 463616 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5273752259 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5273752259 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5273752259 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5273752259 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5273752259 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5273752259 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.021974 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.021974 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.021974 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.021974 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.021974 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.021974 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11375.259394 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11375.259394 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11375.259394 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11375.259394 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11375.259394 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11375.259394 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 463587 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 463587 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 463587 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 463587 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 463587 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 463587 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5274833261 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5274833261 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5274833261 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5274833261 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5274833261 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5274833261 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.021972 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.021972 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.021972 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.021972 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.021972 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.021972 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11378.302802 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11378.302802 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11378.302802 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11378.302802 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11378.302802 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11378.302802 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 581734 # number of replacements -system.cpu1.dcache.tags.tagsinuse 492.027113 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 5462976 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 582077 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 9.385315 # Average number of references to valid blocks. +system.cpu1.dcache.tags.replacements 581700 # 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Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.669922 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 24828652 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 24828652 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 3080166 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3080166 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 2260006 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 2260006 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 60928 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 60928 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71558 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 71558 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 5340172 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 5340172 # 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number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 8279020734 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 8279020734 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3553376 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3553376 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 2362509 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 2362509 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 72600 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 72600 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 72125 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 72125 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 5915885 # 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number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2338814234 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2338814234 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 149892750 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 149892750 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4181580 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4181580 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 8277022984 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8277022984 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8277022984 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8277022984 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3553327 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3553327 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 2362487 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 2362487 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 72598 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 72598 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 72123 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 72123 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 5915814 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 5915814 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 5915814 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 5915814 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.133165 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.133165 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.043387 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_miss_rate::total 0.043387 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.160771 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.160771 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.007861 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.007861 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.097316 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.097316 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.097316 # 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average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14380.465152 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14380.465152 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14380.465152 # average overall miss latency +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.160762 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.160762 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.007875 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.007875 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.097312 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.097312 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.097312 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.097312 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12549.629843 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12549.629843 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22817.477234 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 22817.477234 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12843.179676 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12843.179676 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7361.936620 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7361.936620 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14377.844222 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14377.844222 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14377.844222 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14377.844222 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1646,62 +1643,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 444943 # number of writebacks -system.cpu1.dcache.writebacks::total 444943 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 473210 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 473210 # 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number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 7120750266 # number of overall MSHR miss cycles +system.cpu1.dcache.writebacks::writebacks 444927 # number of writebacks +system.cpu1.dcache.writebacks::total 444927 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 473178 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 473178 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 102501 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 102501 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11671 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11671 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 568 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 568 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 575679 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 575679 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 575679 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 575679 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 4991497250 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 4991497250 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2127317766 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2127317766 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 126550250 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 126550250 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3045420 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3045420 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7118815016 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 7118815016 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7118815016 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 7118815016 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 479658500 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 479658500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 907861000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 907861000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1387519500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1387519500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.133172 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.133172 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 907862000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 907862000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1387520500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1387520500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.133165 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.133165 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.043387 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.043387 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.160771 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.160771 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.007861 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.007861 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.097316 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.097316 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.097316 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.097316 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10549.537203 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10549.537203 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 20766.258217 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 20766.258217 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10843.150274 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10843.150274 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5342.010582 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5342.010582 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12368.576471 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12368.576471 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12368.576471 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12368.576471 # average overall mshr miss latency +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.160762 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.160762 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.007875 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.007875 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.097312 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.097312 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.097312 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.097312 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10548.878540 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10548.878540 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 20754.117189 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 20754.117189 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10843.136835 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10843.136835 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5361.654930 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5361.654930 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12365.945285 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12365.945285 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12365.945285 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12365.945285 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency |