diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt | 1782 |
1 files changed, 0 insertions, 1782 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt deleted file mode 100644 index 5f20e9468..000000000 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ /dev/null @@ -1,1782 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 1.966742 # Number of seconds simulated -sim_ticks 1966742176000 # Number of ticks simulated -final_tick 1966742176000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1742915 # Simulator instruction rate (inst/s) -host_op_rate 1742915 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56229643103 # Simulator tick rate (ticks/s) -host_mem_usage 335876 # Number of bytes of host memory used -host_seconds 34.98 # Real time elapsed on the host -sim_insts 60961842 # Number of instructions simulated -sim_ops 60961842 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.inst 796800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24828736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 62272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 430784 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26119552 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 796800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 62272 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 859072 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7774400 # Number of bytes written to this memory -system.physmem.bytes_written::total 7774400 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12450 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 387949 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 973 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6731 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 408118 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 121475 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121475 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 405137 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12624296 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 31663 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 219034 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 488 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13280618 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 405137 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 31663 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 436800 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3952933 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3952933 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3952933 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 405137 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12624296 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 31663 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 219034 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 488 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17233551 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 408118 # Number of read requests accepted -system.physmem.writeReqs 121475 # Number of write requests accepted -system.physmem.readBursts 408118 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 121475 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26112384 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7168 # Total number of bytes read from write queue -system.physmem.bytesWritten 7772672 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26119552 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7774400 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 112 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25299 # Per bank write bursts -system.physmem.perBankRdBursts::1 25599 # Per bank write bursts -system.physmem.perBankRdBursts::2 25910 # Per bank write bursts -system.physmem.perBankRdBursts::3 25657 # Per bank write bursts -system.physmem.perBankRdBursts::4 25586 # Per bank write bursts -system.physmem.perBankRdBursts::5 25177 # Per bank write bursts -system.physmem.perBankRdBursts::6 26012 # Per bank write bursts -system.physmem.perBankRdBursts::7 25110 # Per bank write bursts -system.physmem.perBankRdBursts::8 25002 # Per bank write bursts -system.physmem.perBankRdBursts::9 25326 # Per bank write bursts -system.physmem.perBankRdBursts::10 25349 # Per bank write bursts -system.physmem.perBankRdBursts::11 25350 # Per bank write bursts -system.physmem.perBankRdBursts::12 25737 # Per bank write bursts -system.physmem.perBankRdBursts::13 25386 # Per bank write bursts -system.physmem.perBankRdBursts::14 25673 # Per bank write bursts -system.physmem.perBankRdBursts::15 25833 # Per bank write bursts -system.physmem.perBankWrBursts::0 7888 # Per bank write bursts -system.physmem.perBankWrBursts::1 7973 # Per bank write bursts -system.physmem.perBankWrBursts::2 7891 # Per bank write bursts -system.physmem.perBankWrBursts::3 7697 # Per bank write bursts -system.physmem.perBankWrBursts::4 7528 # Per bank write bursts -system.physmem.perBankWrBursts::5 7375 # Per bank write bursts -system.physmem.perBankWrBursts::6 8079 # Per bank write bursts -system.physmem.perBankWrBursts::7 7030 # Per bank write bursts -system.physmem.perBankWrBursts::8 7056 # Per bank write bursts -system.physmem.perBankWrBursts::9 7058 # Per bank write bursts -system.physmem.perBankWrBursts::10 7244 # Per bank write bursts -system.physmem.perBankWrBursts::11 7671 # Per bank write bursts -system.physmem.perBankWrBursts::12 7657 # Per bank write bursts -system.physmem.perBankWrBursts::13 7545 # Per bank write bursts -system.physmem.perBankWrBursts::14 7813 # Per bank write bursts -system.physmem.perBankWrBursts::15 7943 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 71 # Number of times write queue was full causing retry -system.physmem.totGap 1966734882500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 408118 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 121475 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 407913 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 80 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5743 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6550 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8420 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6966 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5774 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 397 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 156 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65997 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 513.433277 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 309.806046 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 413.661980 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15519 23.51% 23.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 12333 18.69% 42.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4691 7.11% 49.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3281 4.97% 54.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3296 4.99% 59.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1531 2.32% 61.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1650 2.50% 64.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1071 1.62% 65.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22625 34.28% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65997 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5403 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 75.512863 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2871.806103 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5400 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5403 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5403 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.477883 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.790649 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 24.259878 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4886 90.43% 90.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 27 0.50% 90.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 174 3.22% 94.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 7 0.13% 94.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 5 0.09% 94.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 18 0.33% 94.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 10 0.19% 94.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 2 0.04% 94.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 26 0.48% 95.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 6 0.11% 95.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 152 2.81% 98.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 23 0.43% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 4 0.07% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 3 0.06% 98.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 4 0.07% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 5 0.09% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 2 0.04% 99.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 1 0.02% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 1 0.02% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 5 0.09% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 7 0.13% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 10 0.19% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 7 0.13% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 3 0.06% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 1 0.02% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 6 0.11% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 4 0.07% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 2 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-343 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5403 # Writes before turning the bus around for reads -system.physmem.totQLat 6253232750 # Total ticks spent queuing -system.physmem.totMemAccLat 13903345250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2040030000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15326.33 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 34076.33 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.28 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.28 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.95 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.13 # Data bus utilization in percentage -system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.81 # Average write queue length when enqueuing -system.physmem.readRowHits 365871 # Number of row buffer hits during reads -system.physmem.writeRowHits 97586 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.67 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.33 # Row buffer hit rate for writes -system.physmem.avgGap 3713672.35 # Average gap between requests -system.physmem.pageHitRate 87.53 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 236455380 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 125679015 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1459059000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 320826420 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5647926960.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5154923820 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 376838880 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 13418648160 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 6443555040 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 458974810065 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 492161345970 # Total energy per rank (pJ) -system.physmem_0.averagePower 250.241923 # Core power per rank (mW) -system.physmem_0.totalIdleTime 1954449369000 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 631981750 # Time in different power states -system.physmem_0.memoryStateTime::REF 2402382000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 1908243357500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 16780134250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9257305750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 29427014750 # Time in different power states -system.physmem_1.actEnergy 234763200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 124779600 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1454103840 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 313132140 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5778230640.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5151828720 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 364649760 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 13829543490 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 6726228480 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 458595076560 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 492575015880 # Total energy per rank (pJ) -system.physmem_1.averagePower 250.452256 # Core power per rank (mW) -system.physmem_1.totalIdleTime 1954420956750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 598934250 # Time in different power states -system.physmem_1.memoryStateTime::REF 2457676000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 1906644575500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 17516296750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9196775500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 30327918000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dtb.fetch_hits 0 # ITB hits -system.cpu0.dtb.fetch_misses 0 # ITB misses -system.cpu0.dtb.fetch_acv 0 # ITB acv -system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7479524 # DTB read hits -system.cpu0.dtb.read_misses 7764 # DTB read misses -system.cpu0.dtb.read_acv 210 # DTB read access violations -system.cpu0.dtb.read_accesses 524068 # DTB read accesses -system.cpu0.dtb.write_hits 5079926 # DTB write hits -system.cpu0.dtb.write_misses 909 # DTB write misses -system.cpu0.dtb.write_acv 133 # DTB write access violations -system.cpu0.dtb.write_accesses 202594 # DTB write accesses -system.cpu0.dtb.data_hits 12559450 # DTB hits -system.cpu0.dtb.data_misses 8673 # DTB misses -system.cpu0.dtb.data_acv 343 # DTB access violations -system.cpu0.dtb.data_accesses 726662 # DTB accesses -system.cpu0.itb.fetch_hits 3638587 # ITB hits -system.cpu0.itb.fetch_misses 3984 # ITB misses -system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3642571 # ITB accesses -system.cpu0.itb.read_hits 0 # DTB read hits -system.cpu0.itb.read_misses 0 # DTB read misses -system.cpu0.itb.read_acv 0 # DTB read access violations -system.cpu0.itb.read_accesses 0 # DTB read accesses -system.cpu0.itb.write_hits 0 # DTB write hits -system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.write_acv 0 # DTB write access violations -system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.data_hits 0 # DTB hits -system.cpu0.itb.data_misses 0 # DTB misses -system.cpu0.itb.data_acv 0 # DTB access violations -system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numPwrStateTransitions 13586 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 6793 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 272328046.518475 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 432907003.390448 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 6793 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 169000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 6793 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 116817756000 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 1849924420000 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 3933484352 # number of cpu cycles simulated -system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6793 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 163848 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 56217 40.17% 40.17% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.26% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1975 1.41% 41.67% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 433 0.31% 41.98% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 81195 58.02% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 139951 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 55705 49.07% 49.07% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1975 1.74% 50.93% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 433 0.38% 51.31% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 55272 48.69% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 113516 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1903162232500 96.77% 96.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 93267000 0.00% 96.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 789745000 0.04% 96.81% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 321096500 0.02% 96.83% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 62375109000 3.17% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1966741450000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.990892 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.680732 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.811112 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 525 0.35% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3063 2.07% 2.43% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.46% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.46% # number of callpals executed -system.cpu0.kern.callpal::swpipl 132999 89.79% 92.25% # number of callpals executed -system.cpu0.kern.callpal::rdps 6513 4.40% 96.65% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.65% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 96.65% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.66% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.66% # number of callpals executed -system.cpu0.kern.callpal::rti 4412 2.98% 99.64% # number of callpals executed -system.cpu0.kern.callpal::callsys 394 0.27% 99.91% # number of callpals executed -system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 148123 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6987 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1370 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1369 -system.cpu0.kern.mode_good::user 1370 -system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.195935 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.327749 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1962822047500 99.80% 99.80% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3919400500 0.20% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3064 # number of times the context was actually changed -system.cpu0.committedInsts 47693300 # Number of instructions committed -system.cpu0.committedOps 47693300 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 44245928 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 210005 # Number of float alu accesses -system.cpu0.num_func_calls 1191022 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5607802 # number of instructions that are conditional controls -system.cpu0.num_int_insts 44245928 # number of integer instructions -system.cpu0.num_fp_insts 210005 # number of float instructions -system.cpu0.num_int_register_reads 60860766 # number of times the integer registers were read -system.cpu0.num_int_register_writes 32957591 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 102620 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 104398 # number of times the floating registers were written -system.cpu0.num_mem_refs 12600240 # number of memory refs -system.cpu0.num_load_insts 7507148 # Number of load instructions -system.cpu0.num_store_insts 5093092 # Number of store instructions -system.cpu0.num_idle_cycles 3699848839.998118 # Number of idle cycles -system.cpu0.num_busy_cycles 233635512.001881 # Number of busy cycles -system.cpu0.not_idle_fraction 0.059397 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.940603 # Percentage of idle cycles -system.cpu0.Branches 7183589 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2715591 5.69% 5.69% # Class of executed instruction -system.cpu0.op_class::IntAlu 31389831 65.80% 71.50% # Class of executed instruction -system.cpu0.op_class::IntMult 52060 0.11% 71.61% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.61% # Class of executed instruction -system.cpu0.op_class::FloatAdd 26674 0.06% 71.66% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::FloatMultAcc 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1883 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::FloatMisc 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::MemRead 7588720 15.91% 87.57% # Class of executed instruction -system.cpu0.op_class::MemWrite 5010315 10.50% 98.08% # Class of executed instruction -system.cpu0.op_class::FloatMemRead 92556 0.19% 98.27% # Class of executed instruction -system.cpu0.op_class::FloatMemWrite 88892 0.19% 98.46% # Class of executed instruction -system.cpu0.op_class::IprAccess 735794 1.54% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 47702316 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 1183155 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.237754 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11370167 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1183667 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.605883 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 121324500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.237754 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986792 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986792 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51474763 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51474763 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 6401125 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6401125 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4669512 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4669512 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138994 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 138994 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 146310 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 146310 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11070637 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11070637 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11070637 # number of overall hits -system.cpu0.dcache.overall_hits::total 11070637 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 938392 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 938392 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 255335 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 255335 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13590 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13590 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5728 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5728 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1193727 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1193727 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1193727 # number of overall misses -system.cpu0.dcache.overall_misses::total 1193727 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 31214419000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 31214419000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 12662507500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 12662507500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150368000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 150368000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 31952500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 31952500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 43876926500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 43876926500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 43876926500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 43876926500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7339517 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7339517 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4924847 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4924847 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 152584 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 152584 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 152038 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 152038 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12264364 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12264364 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12264364 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12264364 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127855 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.127855 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051846 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051846 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.089066 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.089066 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037675 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037675 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097333 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.097333 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097333 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097333 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 33263.730935 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 33263.730935 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 49591.742221 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 49591.742221 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11064.606328 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11064.606328 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5578.299581 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5578.299581 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36756.248707 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 36756.248707 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36756.248707 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 36756.248707 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 681263 # number of writebacks -system.cpu0.dcache.writebacks::total 681263 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 938392 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 938392 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 255335 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 255335 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13590 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13590 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5728 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 5728 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1193727 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1193727 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1193727 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1193727 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7073 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7073 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10752 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10752 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17825 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17825 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 30276027000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 30276027000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 12407172500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12407172500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 136778000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136778000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 26224500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 26224500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 42683199500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 42683199500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 42683199500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 42683199500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1572134500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1572134500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1572134500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1572134500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127855 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127855 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051846 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051846 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.089066 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.089066 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037675 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037675 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097333 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097333 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097333 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097333 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32263.730935 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32263.730935 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 48591.742221 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48591.742221 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10064.606328 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10064.606328 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4578.299581 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4578.299581 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35756.248707 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35756.248707 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35756.248707 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35756.248707 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222272.656581 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222272.656581 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 88198.288920 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 88198.288920 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 692168 # number of replacements -system.cpu0.icache.tags.tagsinuse 507.922544 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 47009511 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 692680 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.866130 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 44813247500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 507.922544 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992036 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.992036 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 435 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 48395123 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 48395123 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 47009511 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 47009511 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 47009511 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 47009511 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 47009511 # number of overall hits -system.cpu0.icache.overall_hits::total 47009511 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 692806 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 692806 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 692806 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 692806 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 692806 # number of overall misses -system.cpu0.icache.overall_misses::total 692806 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10342349000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10342349000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10342349000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10342349000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10342349000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10342349000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47702317 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47702317 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47702317 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47702317 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47702317 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47702317 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014524 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014524 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014524 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014524 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014524 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014524 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14928.203566 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14928.203566 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14928.203566 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14928.203566 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14928.203566 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14928.203566 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 692168 # number of writebacks -system.cpu0.icache.writebacks::total 692168 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 692806 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 692806 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 692806 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 692806 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 692806 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 692806 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9649543000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9649543000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9649543000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9649543000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9649543000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9649543000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014524 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014524 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014524 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13928.203566 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13928.203566 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13928.203566 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13928.203566 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13928.203566 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13928.203566 # average overall mshr miss latency -system.cpu1.dtb.fetch_hits 0 # ITB hits -system.cpu1.dtb.fetch_misses 0 # ITB misses -system.cpu1.dtb.fetch_acv 0 # ITB acv -system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2442461 # DTB read hits -system.cpu1.dtb.read_misses 2621 # DTB read misses -system.cpu1.dtb.read_acv 0 # DTB read access violations -system.cpu1.dtb.read_accesses 205338 # DTB read accesses -system.cpu1.dtb.write_hits 1749247 # DTB write hits -system.cpu1.dtb.write_misses 236 # DTB write misses -system.cpu1.dtb.write_acv 24 # DTB write access violations -system.cpu1.dtb.write_accesses 89740 # DTB write accesses -system.cpu1.dtb.data_hits 4191708 # DTB hits -system.cpu1.dtb.data_misses 2857 # DTB misses -system.cpu1.dtb.data_acv 24 # DTB access violations -system.cpu1.dtb.data_accesses 295078 # DTB accesses -system.cpu1.itb.fetch_hits 1826964 # ITB hits -system.cpu1.itb.fetch_misses 1064 # ITB misses -system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1828028 # ITB accesses -system.cpu1.itb.read_hits 0 # DTB read hits -system.cpu1.itb.read_misses 0 # DTB read misses -system.cpu1.itb.read_acv 0 # DTB read access violations -system.cpu1.itb.read_accesses 0 # DTB read accesses -system.cpu1.itb.write_hits 0 # DTB write hits -system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.write_acv 0 # DTB write access violations -system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.data_hits 0 # DTB hits -system.cpu1.itb.data_misses 0 # DTB misses -system.cpu1.itb.data_acv 0 # DTB access violations -system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numPwrStateTransitions 5609 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2805 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 692201198.395722 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 417085998.942743 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 2805 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 61500 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 974672500 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2805 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 25117814500 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 1941624361500 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 3931646343 # number of cpu cycles simulated -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2805 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 79704 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 27198 38.42% 38.42% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1969 2.78% 41.20% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 525 0.74% 41.94% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 41099 58.06% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 70791 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 26333 48.20% 48.20% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1969 3.60% 51.80% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 525 0.96% 52.76% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 25808 47.24% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 54635 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1909855455500 97.15% 97.15% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 731138500 0.04% 97.19% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 371933000 0.02% 97.21% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 54864614500 2.79% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1965823141500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.968196 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.627947 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.771779 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 433 0.59% 0.59% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed -system.cpu1.kern.callpal::swpctx 2016 2.75% 3.35% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 3.35% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.36% # number of callpals executed -system.cpu1.kern.callpal::swpipl 64571 88.14% 91.50% # number of callpals executed -system.cpu1.kern.callpal::rdps 2334 3.19% 94.68% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.68% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.00% 94.69% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.69% # number of callpals executed -system.cpu1.kern.callpal::rti 3725 5.08% 99.78% # number of callpals executed -system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed -system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 73263 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1964 # number of protection mode switches -system.cpu1.kern.mode_switch::user 367 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2923 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 816 -system.cpu1.kern.mode_good::user 367 -system.cpu1.kern.mode_good::idle 449 -system.cpu1.kern.mode_switch_good::kernel 0.415479 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.153609 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.310620 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 18379231500 0.94% 0.94% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1492112000 0.08% 1.01% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1945079443000 98.99% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 2017 # number of times the context was actually changed -system.cpu1.committedInsts 13268542 # Number of instructions committed -system.cpu1.committedOps 13268542 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 12224320 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 175144 # Number of float alu accesses -system.cpu1.num_func_calls 423403 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1315333 # number of instructions that are conditional controls -system.cpu1.num_int_insts 12224320 # number of integer instructions -system.cpu1.num_fp_insts 175144 # number of float instructions -system.cpu1.num_int_register_reads 16795598 # number of times the integer registers were read -system.cpu1.num_int_register_writes 8988647 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 90944 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 92918 # number of times the floating registers were written -system.cpu1.num_mem_refs 4214775 # number of memory refs -system.cpu1.num_load_insts 2456291 # Number of load instructions -system.cpu1.num_store_insts 1758484 # Number of store instructions -system.cpu1.num_idle_cycles 3881434187.727123 # Number of idle cycles -system.cpu1.num_busy_cycles 50212155.272877 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012771 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987229 # Percentage of idle cycles -system.cpu1.Branches 1898911 # Number of branches fetched -system.cpu1.op_class::No_OpClass 719210 5.42% 5.42% # Class of executed instruction -system.cpu1.op_class::IntAlu 7860972 59.23% 64.65% # Class of executed instruction -system.cpu1.op_class::IntMult 22603 0.17% 64.82% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.82% # Class of executed instruction -system.cpu1.op_class::FloatAdd 13252 0.10% 64.92% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.92% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.92% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.92% # Class of executed instruction -system.cpu1.op_class::FloatMultAcc 0 0.00% 64.92% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1759 0.01% 64.93% # Class of executed instruction -system.cpu1.op_class::FloatMisc 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::MemRead 2447819 18.44% 83.38% # Class of executed instruction -system.cpu1.op_class::MemWrite 1681290 12.67% 96.05% # Class of executed instruction -system.cpu1.op_class::FloatMemRead 81935 0.62% 96.67% # Class of executed instruction -system.cpu1.op_class::FloatMemWrite 78198 0.59% 97.25% # Class of executed instruction -system.cpu1.op_class::IprAccess 364385 2.75% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 13271423 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 162127 # number of replacements -system.cpu1.dcache.tags.tagsinuse 484.320008 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 4015090 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 162456 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 24.714938 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 72636345500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 484.320008 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.945938 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.945938 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 329 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 297 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.642578 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 16996743 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 16996743 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 2273788 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2273788 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1634135 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1634135 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 51915 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 51915 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 52085 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 52085 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3907923 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3907923 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3907923 # number of overall hits -system.cpu1.dcache.overall_hits::total 3907923 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 118690 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 118690 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 58791 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 58791 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9152 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 9152 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6117 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 6117 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 177481 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 177481 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 177481 # number of overall misses -system.cpu1.dcache.overall_misses::total 177481 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1467443500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1467443500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1300528500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1300528500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 84062000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 84062000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 34151000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 34151000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 2767972000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 2767972000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 2767972000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 2767972000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2392478 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2392478 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1692926 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1692926 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 61067 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 61067 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 58202 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 58202 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4085404 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4085404 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4085404 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4085404 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049610 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.049610 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034727 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.034727 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.149868 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.149868 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105099 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105099 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043443 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.043443 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043443 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.043443 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12363.665852 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12363.665852 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22121.217533 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 22121.217533 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9185.096154 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9185.096154 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5582.965506 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5582.965506 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15595.877869 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15595.877869 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15595.877869 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15595.877869 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 111642 # number of writebacks -system.cpu1.dcache.writebacks::total 111642 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118690 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 118690 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 58791 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 58791 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9152 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9152 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6117 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 6117 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 177481 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 177481 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 177481 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 177481 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 125 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 125 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3371 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3371 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3496 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3496 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1348753500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1348753500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1241737500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1241737500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74910000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74910000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 28034000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 28034000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2590491000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2590491000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2590491000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2590491000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 26291000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 26291000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 26291000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 26291000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049610 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049610 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034727 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034727 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.149868 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.149868 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105099 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105099 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043443 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.043443 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043443 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.043443 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11363.665852 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11363.665852 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21121.217533 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21121.217533 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8185.096154 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8185.096154 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4582.965506 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4582.965506 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14595.877869 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14595.877869 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14595.877869 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14595.877869 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 210328 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210328 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 7520.308924 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 7520.308924 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 326560 # number of replacements -system.cpu1.icache.tags.tagsinuse 445.783409 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 12944312 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 327071 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 39.576459 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1960887860500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.783409 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.870671 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.870671 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 434 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 13598534 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 13598534 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 12944312 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 12944312 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 12944312 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 12944312 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 12944312 # number of overall hits -system.cpu1.icache.overall_hits::total 12944312 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 327111 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 327111 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 327111 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 327111 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 327111 # number of overall misses -system.cpu1.icache.overall_misses::total 327111 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4448984500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4448984500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4448984500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4448984500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4448984500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4448984500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13271423 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13271423 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13271423 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13271423 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13271423 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13271423 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024648 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024648 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024648 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024648 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024648 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024648 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13600.840388 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13600.840388 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13600.840388 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13600.840388 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13600.840388 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13600.840388 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 326560 # number of writebacks -system.cpu1.icache.writebacks::total 326560 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 327111 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 327111 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 327111 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 327111 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 327111 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 327111 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4121873500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4121873500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4121873500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4121873500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4121873500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4121873500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024648 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024648 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024648 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024648 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024648 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024648 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12600.840388 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12600.840388 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12600.840388 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12600.840388 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12600.840388 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12600.840388 # average overall mshr miss latency -system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. -system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_txs 395 # Number of DMA write transactions. -system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. -system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. -system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 7376 # Transaction distribution -system.iobus.trans_dist::ReadResp 7376 # Transaction distribution -system.iobus.trans_dist::WriteReq 55675 # Transaction distribution -system.iobus.trans_dist::WriteResp 55675 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14036 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 42642 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83460 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 126102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 56144 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 82394 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2744042 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 15108500 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 758500 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) -system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 174000 # Layer occupancy (ticks) -system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 15840500 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 2459000 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6051000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216236013 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28519000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41956000 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 41698 # number of replacements -system.iocache.tags.tagsinuse 0.568425 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1760410358000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.568425 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035527 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035527 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375570 # Number of tag accesses -system.iocache.tags.data_accesses 375570 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses -system.iocache.ReadReq_misses::total 178 # number of ReadReq misses -system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 41730 # number of demand (read+write) misses -system.iocache.demand_misses::total 41730 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41730 # number of overall misses -system.iocache.overall_misses::total 41730 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 22412883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 22412883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4955951130 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4955951130 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4978364013 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4978364013 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4978364013 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4978364013 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41730 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41730 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses -system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125915.073034 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125915.073034 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 119271.061080 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 119271.061080 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 119299.401222 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 119299.401222 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 119299.401222 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 119299.401222 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 1665 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 166.500000 # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 41520 # number of writebacks -system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41730 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41730 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41730 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13512883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13512883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2875898127 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2875898127 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2889411010 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2889411010 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2889411010 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2889411010 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75915.073034 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 75915.073034 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 69212.026545 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69212.026545 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69240.618500 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 69240.618500 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69240.618500 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 69240.618500 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 342924 # number of replacements -system.l2c.tags.tagsinuse 65389.954347 # Cycle average of tags in use -system.l2c.tags.total_refs 3989934 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 408445 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 9.768596 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 7750508000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 285.827021 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4794.067634 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 59305.224879 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 165.844219 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 838.990595 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.004361 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.073152 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.904926 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002531 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.012802 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.997772 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65521 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 697 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1597 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6182 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 57022 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.999771 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 35598107 # Number of tag accesses -system.l2c.tags.data_accesses 35598107 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 792905 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 792905 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 747283 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 747283 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 3151 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 2387 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 5538 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 946 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 957 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 1903 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 128511 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 43286 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 171797 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 680335 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 326126 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1006461 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 663262 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 108452 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 771714 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 680335 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 791773 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 326126 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 151738 # number of demand (read+write) hits -system.l2c.demand_hits::total 1949972 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 680335 # number of overall hits -system.l2c.overall_hits::cpu0.data 791773 # number of overall hits -system.l2c.overall_hits::cpu1.inst 326126 # number of overall hits -system.l2c.overall_hits::cpu1.data 151738 # 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number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1019895 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 934779 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 108791 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 1043570 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 692785 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1180106 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 327110 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 158496 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2358497 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 692785 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1180106 # 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number of overall MSHR misses -system.l2c.overall_mshr_misses::total 408514 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7073 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 125 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 7198 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 10752 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3371 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 14123 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 17825 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3496 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 21321 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 250000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 18500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 268500 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 9455084500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 595276000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 10050360500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1157029500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 89768000 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::total 1246797500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 19230420000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 38376500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 19268796500 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1157029500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 28685504500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 89768000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 633652500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 30565954500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1157029500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 28685504500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 89768000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 633652500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 30565954500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1483681000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 24728000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1508409000 # number of ReadReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1483681000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 24728000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 1508409000 # number of overall MSHR uncacheable cycles -system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.001584 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.000419 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.001082 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.476164 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.129142 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.417700 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.017971 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.002975 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013161 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.290461 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.003116 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260506 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.017971 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.329066 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002975 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.042638 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.173209 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.017971 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.329066 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002975 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.042638 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.173209 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 50000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18500 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44750 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 80939.978256 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92736.563328 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 81554.432588 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 92934.096386 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 92258.992806 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 92885.159800 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 70825.841476 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 113205.014749 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 70878.687614 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 92934.096386 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 73868.315338 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 92258.992806 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 93763.317550 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 74822.293728 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 92934.096386 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 73868.315338 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 92258.992806 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 93763.317550 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 74822.293728 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209766.859890 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 197824 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209559.460961 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 83235.960729 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 7073.226545 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 70747.572816 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 856478 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 407046 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 512 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 7198 # Transaction distribution -system.membus.trans_dist::ReadResp 292655 # Transaction distribution -system.membus.trans_dist::WriteReq 14123 # Transaction distribution -system.membus.trans_dist::WriteResp 14123 # Transaction distribution -system.membus.trans_dist::WritebackDirty 121475 # Transaction distribution -system.membus.trans_dist::CleanEvict 262336 # Transaction distribution -system.membus.trans_dist::UpgradeReq 11690 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 9942 # Transaction distribution -system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 123955 # Transaction distribution -system.membus.trans_dist::ReadExResp 123087 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 285457 # Transaction distribution -system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::InvalidateResp 148 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42642 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1181082 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1223724 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83443 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 83443 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1307167 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82394 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31235712 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31318106 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33976346 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 22923 # Total snoops (count) -system.membus.snoopTraffic 27264 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 493917 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001373 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.037025 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 493239 99.86% 99.86% # Request fanout histogram -system.membus.snoop_fanout::1 678 0.14% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 493917 # Request fanout histogram -system.membus.reqLayer0.occupancy 40493500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1322925099 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2182236750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1074598 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 4789722 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2388089 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 374620 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 991 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 930 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 61 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 7198 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2107102 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14123 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14123 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 872860 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1018728 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 815346 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 17080 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11845 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 28925 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 297046 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 297046 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1019917 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1079990 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 246 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 4 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2077759 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3616208 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 980781 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 523727 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7198475 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 88636992 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119193988 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 41834880 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17315286 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 266981146 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 403271 # Total snoops (count) -system.toL2Bus.snoopTraffic 7578112 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 2790369 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.143087 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.350419 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2391353 85.70% 85.70% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 398767 14.29% 99.99% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 248 0.01% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 1 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2790369 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4224217497 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 304383 # Layer occupancy (ticks) -system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1039374668 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1817986111 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 491891046 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 276353266 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states - ----------- End Simulation Statistics ---------- |