1 files changed, 8 insertions, 12 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
index 586901b21..191ca5cbb 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
@@ -94,7 +94,7 @@ dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -103,7 +103,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -114,7 +114,6 @@ size=32768
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -135,7 +134,7 @@ eventq_index=0
 size=64
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -144,7 +143,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -155,7 +154,6 @@ size=32768
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -185,7 +183,7 @@ eventq_index=0
 size=48
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -194,7 +192,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -205,7 +203,6 @@ size=4194304
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
@@ -320,7 +317,7 @@ master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_
 slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:134217727
 assoc=8
@@ -329,7 +326,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -340,7 +337,6 @@ size=1024
 system=system
 tags=system.iocache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[29]
 mem_side=system.membus.slave[2]