diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt | 1582 |
1 files changed, 786 insertions, 796 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 5922aa080..2decdfb20 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.922397 # Number of seconds simulated -sim_ticks 1922397182500 # Number of ticks simulated -final_tick 1922397182500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.941266 # Number of seconds simulated +sim_ticks 1941266487500 # Number of ticks simulated +final_tick 1941266487500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1085217 # Simulator instruction rate (inst/s) -host_op_rate 1085217 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37124537063 # Simulator tick rate (ticks/s) -host_mem_usage 372212 # Number of bytes of host memory used -host_seconds 51.78 # Real time elapsed on the host -sim_insts 56195121 # Number of instructions simulated -sim_ops 56195121 # Number of ops (including micro ops) simulated +host_inst_rate 1056307 # Simulator instruction rate (inst/s) +host_op_rate 1056307 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36524098946 # Simulator tick rate (ticks/s) +host_mem_usage 374096 # Number of bytes of host memory used +host_seconds 53.15 # Real time elapsed on the host +sim_insts 56143021 # Number of instructions simulated +sim_ops 56143021 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 848768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24858048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 848832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24855488 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25707776 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 848768 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 848768 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7409088 # Number of bytes written to this memory -system.physmem.bytes_written::total 7409088 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13262 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388407 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25705280 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 848832 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 848832 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7407552 # Number of bytes written to this memory +system.physmem.bytes_written::total 7407552 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13263 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388367 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 401684 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115767 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115767 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 441515 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12930756 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 499 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13372770 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 441515 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 441515 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3854088 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3854088 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3854088 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 441515 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12930756 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17226858 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 401684 # Number of read requests accepted -system.physmem.writeReqs 115767 # Number of write requests accepted -system.physmem.readBursts 401684 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 115767 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25700352 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7424 # Total number of bytes read from write queue -system.physmem.bytesWritten 7407168 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25707776 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7409088 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 116 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 401645 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115743 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115743 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 437257 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12803749 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 495 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13241500 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 437257 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 437257 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3815835 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3815835 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3815835 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 437257 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12803749 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 495 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17057335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 401645 # Number of read requests accepted +system.physmem.writeReqs 115743 # Number of write requests accepted +system.physmem.readBursts 401645 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115743 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25697728 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7552 # Total number of bytes read from write queue +system.physmem.bytesWritten 7406016 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25705280 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7407552 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 118 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 41682 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25233 # Per bank write bursts -system.physmem.perBankRdBursts::1 25641 # Per bank write bursts -system.physmem.perBankRdBursts::2 25574 # Per bank write bursts -system.physmem.perBankRdBursts::3 25503 # Per bank write bursts -system.physmem.perBankRdBursts::4 24973 # Per bank write bursts -system.physmem.perBankRdBursts::5 24969 # Per bank write bursts -system.physmem.perBankRdBursts::6 24206 # Per bank write bursts -system.physmem.perBankRdBursts::7 24501 # Per bank write bursts -system.physmem.perBankRdBursts::8 25169 # Per bank write bursts -system.physmem.perBankRdBursts::9 24770 # Per bank write bursts -system.physmem.perBankRdBursts::10 25259 # Per bank write bursts -system.physmem.perBankRdBursts::11 24898 # Per bank write bursts -system.physmem.perBankRdBursts::12 24500 # Per bank write bursts -system.physmem.perBankRdBursts::13 25360 # Per bank write bursts -system.physmem.perBankRdBursts::14 25653 # Per bank write bursts -system.physmem.perBankRdBursts::15 25359 # Per bank write bursts -system.physmem.perBankWrBursts::0 7624 # Per bank write bursts -system.physmem.perBankWrBursts::1 7642 # Per bank write bursts -system.physmem.perBankWrBursts::2 7864 # Per bank write bursts -system.physmem.perBankWrBursts::3 7542 # Per bank write bursts -system.physmem.perBankWrBursts::4 7123 # Per bank write bursts -system.physmem.perBankWrBursts::5 6988 # Per bank write bursts -system.physmem.perBankWrBursts::6 6319 # Per bank write bursts -system.physmem.perBankWrBursts::7 6328 # Per bank write bursts -system.physmem.perBankWrBursts::8 7314 # Per bank write bursts -system.physmem.perBankWrBursts::9 6525 # Per bank write bursts -system.physmem.perBankWrBursts::10 7109 # Per bank write bursts -system.physmem.perBankWrBursts::11 6927 # Per bank write bursts -system.physmem.perBankWrBursts::12 7069 # Per bank write bursts -system.physmem.perBankWrBursts::13 7821 # Per bank write bursts -system.physmem.perBankWrBursts::14 7867 # Per bank write bursts -system.physmem.perBankWrBursts::15 7675 # Per bank write bursts +system.physmem.perBankRdBursts::0 25168 # Per bank write bursts +system.physmem.perBankRdBursts::1 25510 # Per bank write bursts +system.physmem.perBankRdBursts::2 25518 # Per bank write bursts +system.physmem.perBankRdBursts::3 25527 # Per bank write bursts +system.physmem.perBankRdBursts::4 25065 # Per bank write bursts +system.physmem.perBankRdBursts::5 24960 # Per bank write bursts +system.physmem.perBankRdBursts::6 24241 # Per bank write bursts +system.physmem.perBankRdBursts::7 24604 # Per bank write bursts +system.physmem.perBankRdBursts::8 25078 # Per bank write bursts +system.physmem.perBankRdBursts::9 24653 # Per bank write bursts +system.physmem.perBankRdBursts::10 25359 # Per bank write bursts +system.physmem.perBankRdBursts::11 24824 # Per bank write bursts +system.physmem.perBankRdBursts::12 24407 # Per bank write bursts +system.physmem.perBankRdBursts::13 25357 # Per bank write bursts +system.physmem.perBankRdBursts::14 25770 # Per bank write bursts +system.physmem.perBankRdBursts::15 25486 # Per bank write bursts +system.physmem.perBankWrBursts::0 7561 # Per bank write bursts +system.physmem.perBankWrBursts::1 7519 # Per bank write bursts +system.physmem.perBankWrBursts::2 7810 # Per bank write bursts +system.physmem.perBankWrBursts::3 7560 # Per bank write bursts +system.physmem.perBankWrBursts::4 7221 # Per bank write bursts +system.physmem.perBankWrBursts::5 6978 # Per bank write bursts +system.physmem.perBankWrBursts::6 6351 # Per bank write bursts +system.physmem.perBankWrBursts::7 6424 # Per bank write bursts +system.physmem.perBankWrBursts::8 7248 # Per bank write bursts +system.physmem.perBankWrBursts::9 6410 # Per bank write bursts +system.physmem.perBankWrBursts::10 7207 # Per bank write bursts +system.physmem.perBankWrBursts::11 6855 # Per bank write bursts +system.physmem.perBankWrBursts::12 6980 # Per bank write bursts +system.physmem.perBankWrBursts::13 7819 # Per bank write bursts +system.physmem.perBankWrBursts::14 7982 # Per bank write bursts +system.physmem.perBankWrBursts::15 7794 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 15 # Number of times write queue was full causing retry -system.physmem.totGap 1922385313500 # Total gap between requests +system.physmem.numWrRetry 23 # Number of times write queue was full causing retry +system.physmem.totGap 1941254508500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 401684 # Read request sizes (log2) +system.physmem.readPktSize::6 401645 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 115767 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 401554 # What read queue length does an incoming req see +system.physmem.writePktSize::6 115743 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 401513 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see @@ -148,195 +148,179 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5951 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7083 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6732 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 39 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64336 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 514.603333 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 307.690032 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 416.700723 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15764 24.50% 24.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11265 17.51% 42.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5118 7.96% 49.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3016 4.69% 54.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2317 3.60% 58.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1789 2.78% 61.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1464 2.28% 63.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1374 2.14% 65.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22229 34.55% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64336 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5099 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 78.750735 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2955.508201 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5096 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1824 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5414 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8014 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6616 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5981 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 87 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64921 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 509.908104 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 310.461658 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 406.215984 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15228 23.46% 23.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11644 17.94% 41.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4997 7.70% 49.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2980 4.59% 53.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2446 3.77% 57.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4228 6.51% 63.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1452 2.24% 66.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2063 3.18% 69.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19883 30.63% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64921 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5102 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 78.697570 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2954.645683 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5099 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5099 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5099 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.697980 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.062005 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 23.025558 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4477 87.80% 87.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 19 0.37% 88.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 190 3.73% 91.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 14 0.27% 92.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 27 0.53% 92.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 53 1.04% 93.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 14 0.27% 94.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 3 0.06% 94.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 6 0.12% 94.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 3 0.06% 94.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.06% 94.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 3 0.06% 94.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 8 0.16% 94.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 3 0.06% 94.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 2 0.04% 94.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 10 0.20% 94.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 4 0.08% 94.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 16 0.31% 95.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 21 0.41% 95.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 18 0.35% 95.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 148 2.90% 98.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 12 0.24% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.02% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.02% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 3 0.06% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.02% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.04% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 5 0.10% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 2 0.04% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 4 0.08% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 4 0.08% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 5 0.10% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.02% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 3 0.06% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 2 0.04% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 5 0.10% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5099 # Writes before turning the bus around for reads -system.physmem.totQLat 2147063750 # Total ticks spent queuing -system.physmem.totMemAccLat 9676463750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2007840000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5346.70 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5102 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5102 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.681105 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.154688 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.203626 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4492 88.04% 88.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 201 3.94% 91.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 29 0.57% 92.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 48 0.94% 93.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 38 0.74% 94.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 6 0.12% 94.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 11 0.22% 94.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 38 0.74% 95.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 34 0.67% 95.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 1 0.02% 96.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 159 3.12% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 2 0.04% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 2 0.04% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 5 0.10% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 1 0.02% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 2 0.04% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 3 0.06% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 3 0.06% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 4 0.08% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 8 0.16% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 4 0.08% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 3 0.06% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 2 0.04% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 4 0.08% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5102 # Writes before turning the bus around for reads +system.physmem.totQLat 2705942000 # Total ticks spent queuing +system.physmem.totMemAccLat 10234573250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2007635000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6739.13 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24096.70 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.37 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.85 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.37 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.85 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 25489.13 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.82 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.24 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.82 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.13 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.55 # Average write queue length when enqueuing -system.physmem.readRowHits 359411 # Number of row buffer hits during reads -system.physmem.writeRowHits 93558 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.50 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.82 # Row buffer hit rate for writes -system.physmem.avgGap 3715106.00 # Average gap between requests -system.physmem.pageHitRate 87.56 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 236030760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 128786625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1564680000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 372146400 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 125561429760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 64059295815 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1097244171000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1289166540360 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.604667 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1825128497250 # Time in different power states -system.physmem_0.memoryStateTime::REF 64192960000 # Time in different power states +system.physmem.avgWrQLen 24.77 # Average write queue length when enqueuing +system.physmem.readRowHits 358859 # Number of row buffer hits during reads +system.physmem.writeRowHits 93466 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.37 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.75 # Row buffer hit rate for writes +system.physmem.avgGap 3752028.47 # Average gap between requests +system.physmem.pageHitRate 87.44 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 239349600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 130597500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1564625400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 372107520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 126793670640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 71640444015 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1101913691250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1302654485925 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.035450 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1832853481750 # Time in different power states +system.physmem_0.memoryStateTime::REF 64822940000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 33072782750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 43583902000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 250349400 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 136599375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1567550400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 377829360 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 125561429760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 65774789190 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1095739352250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1289407899735 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.730219 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1822618194250 # Time in different power states -system.physmem_1.memoryStateTime::REF 64192960000 # Time in different power states +system.physmem_1.actEnergy 251453160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 137201625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1567285200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 377751600 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 126793670640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 72584952255 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1101085183500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1302797497980 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.109115 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1831469435000 # Time in different power states +system.physmem_1.memoryStateTime::REF 64822940000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 35583085750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 44967962500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9066440 # DTB read hits -system.cpu.dtb.read_misses 10312 # DTB read misses +system.cpu.dtb.read_hits 9058452 # DTB read hits +system.cpu.dtb.read_misses 10327 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728817 # DTB read accesses -system.cpu.dtb.write_hits 6357400 # DTB write hits -system.cpu.dtb.write_misses 1140 # DTB write misses +system.cpu.dtb.read_accesses 728858 # DTB read accesses +system.cpu.dtb.write_hits 6353129 # DTB write hits +system.cpu.dtb.write_misses 1143 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291929 # DTB write accesses -system.cpu.dtb.data_hits 15423840 # DTB hits -system.cpu.dtb.data_misses 11452 # DTB misses +system.cpu.dtb.write_accesses 291932 # DTB write accesses +system.cpu.dtb.data_hits 15411581 # DTB hits +system.cpu.dtb.data_misses 11470 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020746 # DTB accesses -system.cpu.itb.fetch_hits 4973902 # ITB hits -system.cpu.itb.fetch_misses 4997 # ITB misses +system.cpu.dtb.data_accesses 1020790 # DTB accesses +system.cpu.itb.fetch_hits 4975133 # ITB hits +system.cpu.itb.fetch_misses 5010 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4978899 # ITB accesses +system.cpu.itb.fetch_accesses 4980143 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -349,37 +333,37 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3844794365 # number of cpu cycles simulated +system.cpu.numCycles 3882532975 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56195121 # Number of instructions committed -system.cpu.committedOps 56195121 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52066883 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324259 # Number of float alu accesses -system.cpu.num_func_calls 1483708 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6469750 # number of instructions that are conditional controls -system.cpu.num_int_insts 52066883 # number of integer instructions -system.cpu.num_fp_insts 324259 # number of float instructions -system.cpu.num_int_register_reads 71341331 # number of times the integer registers were read -system.cpu.num_int_register_writes 38530727 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163543 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166418 # number of times the floating registers were written -system.cpu.num_mem_refs 15476411 # number of memory refs -system.cpu.num_load_insts 9103258 # Number of load instructions -system.cpu.num_store_insts 6373153 # Number of store instructions -system.cpu.num_idle_cycles 3587818415.000134 # Number of idle cycles -system.cpu.num_busy_cycles 256975949.999866 # Number of busy cycles -system.cpu.not_idle_fraction 0.066837 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.933163 # Percentage of idle cycles -system.cpu.Branches 8423975 # Number of branches fetched -system.cpu.op_class::No_OpClass 3201032 5.70% 5.70% # Class of executed instruction -system.cpu.op_class::IntAlu 36240615 64.48% 70.17% # Class of executed instruction -system.cpu.op_class::IntMult 61007 0.11% 70.28% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 70.28% # Class of executed instruction -system.cpu.op_class::FloatAdd 38081 0.07% 70.35% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 70.35% # Class of executed instruction +system.cpu.committedInsts 56143021 # Number of instructions committed +system.cpu.committedOps 56143021 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52016582 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses +system.cpu.num_func_calls 1482534 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6465507 # number of instructions that are conditional controls +system.cpu.num_int_insts 52016582 # number of integer instructions +system.cpu.num_fp_insts 324393 # number of float instructions +system.cpu.num_int_register_reads 71267420 # number of times the integer registers were read +system.cpu.num_int_register_writes 38489507 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written +system.cpu.num_mem_refs 15464199 # number of memory refs +system.cpu.num_load_insts 9095305 # Number of load instructions +system.cpu.num_store_insts 6368894 # Number of store instructions +system.cpu.num_idle_cycles 3584401371.998154 # Number of idle cycles +system.cpu.num_busy_cycles 298131603.001846 # Number of busy cycles +system.cpu.not_idle_fraction 0.076788 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.923212 # Percentage of idle cycles +system.cpu.Branches 8418668 # Number of branches fetched +system.cpu.op_class::No_OpClass 3199011 5.70% 5.70% # Class of executed instruction +system.cpu.op_class::IntAlu 36202225 64.47% 70.17% # Class of executed instruction +system.cpu.op_class::IntMult 61032 0.11% 70.27% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction +system.cpu.op_class::FloatAdd 38085 0.07% 70.34% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::FloatDiv 3636 0.01% 70.35% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 70.35% # Class of executed instruction @@ -402,34 +386,34 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 70.35% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::MemRead 9330336 16.60% 86.95% # Class of executed instruction -system.cpu.op_class::MemWrite 6379227 11.35% 98.30% # Class of executed instruction -system.cpu.op_class::IprAccess 953006 1.70% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 9322424 16.60% 86.95% # Class of executed instruction +system.cpu.op_class::MemWrite 6374975 11.35% 98.30% # Class of executed instruction +system.cpu.op_class::IprAccess 953470 1.70% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 56206940 # Class of executed instruction +system.cpu.op_class::total 56154858 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211964 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74896 40.89% 40.89% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106217 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183176 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73529 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.inst.quiesce 6377 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 212043 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74906 40.88% 40.88% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 131 0.07% 40.95% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1935 1.06% 42.01% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 106248 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183220 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73539 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73529 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149121 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1858096797000 96.66% 96.66% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 92317000 0.00% 96.66% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 743733500 0.04% 96.70% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 63463601000 3.30% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1922396448500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1935 1.30% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73539 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149144 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1860736112500 95.85% 95.85% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 92522000 0.00% 95.86% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 746030500 0.04% 95.89% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 79691088500 4.11% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1941265753500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981750 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692253 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814086 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692145 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814016 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -465,113 +449,113 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4174 2.16% 2.17% # number of callpals executed +system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175955 91.22% 93.41% # number of callpals executed -system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 175993 91.21% 93.41% # number of callpals executed +system.cpu.kern.callpal::rdps 6835 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed +system.cpu.kern.callpal::whami 2 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal::rti 5160 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192899 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5904 # number of protection mode switches -system.cpu.kern.mode_switch::user 1741 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2093 # number of protection mode switches +system.cpu.kern.callpal::total 192944 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5907 # number of protection mode switches +system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches system.cpu.kern.mode_good::kernel 1910 -system.cpu.kern.mode_good::user 1741 -system.cpu.kern.mode_good::idle 169 -system.cpu.kern.mode_switch_good::kernel 0.323509 # fraction of useful protection mode switches +system.cpu.kern.mode_good::user 1740 +system.cpu.kern.mode_good::idle 170 +system.cpu.kern.mode_switch_good::kernel 0.323345 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080745 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392278 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46413360000 2.41% 2.41% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5233781000 0.27% 2.69% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1870749305500 97.31% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4175 # number of times the context was actually changed -system.cpu.dcache.tags.replacements 1390740 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.978175 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14051600 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1391252 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 10.099968 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 112405500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.978175 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999957 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999957 # Average percentage of cache occupancy +system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392117 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 48524962500 2.50% 2.50% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5595783500 0.29% 2.79% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1887145005500 97.21% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4177 # number of times the context was actually changed +system.cpu.dcache.tags.replacements 1390004 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.973850 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 14040102 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1390516 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.097045 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 143374500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.973850 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999949 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999949 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63162665 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63162665 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7816092 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7816092 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5853262 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5853262 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183004 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183004 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199225 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199225 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13669354 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13669354 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13669354 # number of overall hits -system.cpu.dcache.overall_hits::total 13669354 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1069466 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1069466 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304560 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304560 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17244 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17244 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1374026 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1374026 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1374026 # number of overall misses -system.cpu.dcache.overall_misses::total 1374026 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 30729736500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 30729736500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11677039000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11677039000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228891000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 228891000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 42406775500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 42406775500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 42406775500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 42406775500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 8885558 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 8885558 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6157822 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6157822 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200248 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200248 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199225 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199225 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15043380 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15043380 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15043380 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15043380 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120360 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120360 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049459 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049459 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086113 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086113 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091338 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091338 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091338 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091338 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28733.719913 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28733.719913 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38340.684923 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38340.684923 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13273.660404 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13273.660404 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30863.153608 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30863.153608 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30863.153608 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30863.153608 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63112993 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63112993 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7808536 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7808536 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5849272 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5849272 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183025 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183025 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199252 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199252 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13657808 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13657808 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13657808 # number of overall hits +system.cpu.dcache.overall_hits::total 13657808 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1069028 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1069028 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304257 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304257 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17249 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17249 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1373285 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1373285 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1373285 # number of overall misses +system.cpu.dcache.overall_misses::total 1373285 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 44750637500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 44750637500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 17613913000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 17613913000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232507000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 232507000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 62364550500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 62364550500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 62364550500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 62364550500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8877564 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8877564 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6153529 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6153529 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200274 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200274 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199252 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199252 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15031093 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15031093 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15031093 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15031093 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120419 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120419 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049444 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049444 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086127 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086127 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091363 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091363 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091363 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091363 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41861.052751 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41861.052751 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57891.562068 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 57891.562068 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13479.448084 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13479.448084 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45412.678723 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45412.678723 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45412.678723 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45412.678723 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -580,120 +564,120 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 835293 # number of writebacks -system.cpu.dcache.writebacks::total 835293 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069466 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069466 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304560 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304560 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17244 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17244 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1374026 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1374026 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1374026 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1374026 # 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number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2049565500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3499676000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3499676000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120360 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120360 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049459 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049459 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086113 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086113 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091338 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091338 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091338 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091338 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27733.719913 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27733.719913 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37340.684923 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37340.684923 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12273.660404 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12273.660404 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29863.153608 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29863.153608 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29863.153608 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29863.153608 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209251.154401 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209251.154401 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212390.207254 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212390.207254 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 211078.166466 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 211078.166466 # average overall mshr uncacheable latency +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9653 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 9653 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16583 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 16583 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43681609500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 43681609500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17309656000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 17309656000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 215258000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 215258000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 60991265500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 60991265500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 60991265500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 60991265500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1450109500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1450109500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2050243500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2050243500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3500353000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3500353000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120419 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120419 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049444 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049444 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086127 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086127 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091363 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091363 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091363 # 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average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44412.678723 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209251.010101 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209251.010101 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212394.436963 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212394.436963 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 211080.805644 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 211080.805644 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 928306 # number of replacements -system.cpu.icache.tags.tagsinuse 508.094938 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 55277964 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 928817 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 59.514376 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 41861098500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 508.094938 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.992373 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.992373 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 928672 # number of replacements +system.cpu.icache.tags.tagsinuse 506.358595 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 55225516 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 929183 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 59.434488 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 58555927500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 506.358595 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.988982 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.988982 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 57135918 # Number of tag accesses -system.cpu.icache.tags.data_accesses 57135918 # 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average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127432.712889 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130998.944432 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130998.944432 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123975.202144 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123975.202144 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130998.944432 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 125013.975311 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 125211.424805 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130998.944432 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 125013.975311 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 125211.424805 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -845,125 +829,131 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 74255 # number of writebacks -system.cpu.l2cache.writebacks::total 74255 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 74231 # number of writebacks +system.cpu.l2cache.writebacks::total 74231 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 280 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 280 # number of CleanEvict MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116823 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116823 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 13262 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 13262 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 271974 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 271974 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 13262 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 388797 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 402059 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 13262 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 388797 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 402059 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116798 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116798 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 13263 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 13263 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 271959 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 271959 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 13263 # 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number of overall MSHR uncacheable misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 364500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 364500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7775812500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7775812500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 929982000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 929982000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16967384500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16967384500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 929982000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 24743197000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25673179000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 929982000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 24743197000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25673179000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1363485500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1363485500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1938590500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1938590500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3302076000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3302076000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9653 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9653 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16583 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16583 # number of overall MSHR uncacheable misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 922500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 922500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13715906000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13715906000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1604809000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1604809000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30996582000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30996582000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1604809000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44712488000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 46317297000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1604809000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44712488000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 46317297000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1363484500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1363484500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1939234000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1939234000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3302718500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3302718500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383601 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383601 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014276 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014276 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250273 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250273 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014276 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279458 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173286 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014276 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279458 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173286 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 28038.461538 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 28038.461538 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66560.630184 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66560.630184 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70123.812396 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70123.812396 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62386.053446 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62386.053446 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70123.812396 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63640.401032 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63854.257708 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70123.812396 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63640.401032 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63854.257708 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196751.154401 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196751.154401 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200890.207254 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200890.207254 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199160.193004 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199160.193004 # average overall mshr uncacheable latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383901 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383901 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014272 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014272 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250359 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250359 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014272 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279577 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.173296 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014272 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279577 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.173296 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70961.538462 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70961.538462 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117432.712889 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117432.712889 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120998.944432 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120998.944432 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113975.202144 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113975.202144 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120998.944432 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 115013.975311 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115211.424805 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120998.944432 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 115013.975311 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115211.424805 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196751.010101 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196751.010101 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200894.436963 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200894.436963 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199162.907797 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199162.907797 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 4638553 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2318842 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1502 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1135 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1135 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2022774 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 951075 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1744381 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2022707 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9653 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9653 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 950299 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1744757 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304543 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304543 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 928977 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1086883 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304240 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304240 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 929343 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1086450 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2786015 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4205333 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6991348 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59453248 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142553556 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 202006804 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 419801 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5075497 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.082676 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.275393 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2787117 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4203130 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6990247 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59476672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142457836 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 201934508 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 419768 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5074727 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000845 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.029056 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4655873 91.73% 91.73% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 419624 8.27% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5070439 99.92% 99.92% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4288 0.08% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5075497 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3168054500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5074727 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3166927500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 293383 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1393465500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1394014500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2098643000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2097540500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -979,9 +969,9 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51202 # Transaction distribution -system.iobus.trans_dist::WriteResp 51202 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5156 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51205 # Transaction distribution +system.iobus.trans_dist::WriteResp 51205 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5162 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -993,11 +983,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33160 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33166 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116610 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116616 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20648 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1009,11 +999,11 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 44564 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 44588 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2706172 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 4767000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2706196 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 4773000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1035,23 +1025,23 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 216066756 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 215085744 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23513000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.342844 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.339381 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1756461860000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.342844 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.083928 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.083928 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1774103808000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.339381 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.083711 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.083711 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1065,14 +1055,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21632883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21632883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4907244873 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4907244873 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21632883 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21632883 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21632883 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21632883 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21913883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21913883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5427871861 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5427871861 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21913883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21913883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21913883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21913883 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1089,14 +1079,14 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125045.566474 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125045.566474 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118098.885084 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118098.885084 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 125045.566474 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125045.566474 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 125045.566474 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125045.566474 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126669.843931 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126669.843931 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130628.414059 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130628.414059 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 126669.843931 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126669.843931 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 126669.843931 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126669.843931 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1115,14 +1105,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 173 system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12982883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12982883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2829644873 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2829644873 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12982883 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12982883 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12982883 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12982883 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13263883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13263883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3350271861 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3350271861 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 13263883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 13263883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 13263883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 13263883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1131,59 +1121,59 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75045.566474 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 75045.566474 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68098.885084 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68098.885084 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75045.566474 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75045.566474 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75045.566474 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75045.566474 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76669.843931 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76669.843931 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80628.414059 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80628.414059 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76669.843931 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76669.843931 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76669.843931 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76669.843931 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 292339 # Transaction distribution -system.membus.trans_dist::WriteReq 9650 # Transaction distribution -system.membus.trans_dist::WriteResp 9650 # Transaction distribution -system.membus.trans_dist::Writeback 115767 # Transaction distribution -system.membus.trans_dist::CleanEvict 261512 # Transaction distribution +system.membus.trans_dist::ReadResp 292325 # Transaction distribution +system.membus.trans_dist::WriteReq 9653 # Transaction distribution +system.membus.trans_dist::WriteResp 9653 # Transaction distribution +system.membus.trans_dist::Writeback 115743 # Transaction distribution +system.membus.trans_dist::CleanEvict 261495 # Transaction distribution system.membus.trans_dist::UpgradeReq 132 # Transaction distribution system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 116704 # Transaction distribution -system.membus.trans_dist::ReadExResp 116704 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 285409 # Transaction distribution +system.membus.trans_dist::ReadExReq 116679 # Transaction distribution +system.membus.trans_dist::ReadExResp 116679 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 285395 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139625 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172785 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33166 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139506 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172672 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1297602 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30459136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30503700 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1297489 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44588 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30455104 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30499692 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33161428 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33157420 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 431 # Total snoops (count) -system.membus.snoop_fanout::samples 837831 # Request fanout histogram +system.membus.snoop_fanout::samples 837762 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 837831 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 837762 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 837831 # Request fanout histogram -system.membus.reqLayer0.occupancy 30056000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 837762 # Request fanout histogram +system.membus.reqLayer0.occupancy 30061000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1285352189 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1285186893 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2143948368 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2143459620 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 72076390 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 69854947 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA |