diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt')
-rw-r--r-- | tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt | 282 |
1 files changed, 141 insertions, 141 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index dfbac48e1..e3ca77030 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.910582 # Nu sim_ticks 1910582068000 # Number of ticks simulated final_tick 1910582068000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 942466 # Simulator instruction rate (inst/s) -host_op_rate 942466 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32082735017 # Simulator tick rate (ticks/s) -host_mem_usage 321492 # Number of bytes of host memory used -host_seconds 59.55 # Real time elapsed on the host +host_inst_rate 951839 # Simulator instruction rate (inst/s) +host_op_rate 951839 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32401800424 # Simulator tick rate (ticks/s) +host_mem_usage 374212 # Number of bytes of host memory used +host_seconds 58.97 # Real time elapsed on the host sim_insts 56125446 # Number of instructions simulated sim_ops 56125446 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory @@ -548,142 +548,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 11647.123628 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11647.123628 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 11647.123628 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1389800 # number of replacements -system.cpu.dcache.tagsinuse 511.980808 # Cycle average of tags in use -system.cpu.dcache.total_refs 14036386 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1390312 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 10.095853 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 93442000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.980808 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999963 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999963 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7806239 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7806239 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5847887 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5847887 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183020 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183020 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199223 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199223 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13654126 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13654126 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13654126 # number of overall hits -system.cpu.dcache.overall_hits::total 13654126 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1068876 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1068876 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304232 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304232 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17223 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17223 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1373108 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1373108 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1373108 # number of overall misses -system.cpu.dcache.overall_misses::total 1373108 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 22711107000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 22711107000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8598536500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8598536500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 227697000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 227697000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31309643500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31309643500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 31309643500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31309643500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 8875115 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 8875115 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6152119 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6152119 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200243 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200243 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199223 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199223 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15027234 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15027234 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15027234 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15027234 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120435 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120435 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049452 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049452 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086010 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086010 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091375 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091375 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091375 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091375 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21247.653610 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21247.653610 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28263.090339 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28263.090339 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13220.519073 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13220.519073 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22802.025405 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22802.025405 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22802.025405 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22802.025405 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 834403 # number of writebacks -system.cpu.dcache.writebacks::total 834403 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1068876 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1068876 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304232 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304232 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17223 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17223 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1373108 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1373108 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1373108 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1373108 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 20573355000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 20573355000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7990072500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7990072500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 193251000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 193251000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28563427500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28563427500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28563427500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28563427500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424236000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424236000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2010997500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2010997500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435233500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435233500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120435 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120435 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049452 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049452 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086010 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086010 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091375 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091375 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091375 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091375 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19247.653610 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19247.653610 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26263.090339 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26263.090339 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11220.519073 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11220.519073 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20802.025405 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20802.025405 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20802.025405 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20802.025405 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 336061 # number of replacements system.cpu.l2cache.tagsinuse 65323.847661 # Cycle average of tags in use system.cpu.l2cache.total_refs 2445310 # Total number of references to valid blocks. @@ -854,5 +718,141 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 1389800 # number of replacements +system.cpu.dcache.tagsinuse 511.980808 # Cycle average of tags in use +system.cpu.dcache.total_refs 14036386 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1390312 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 10.095853 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 93442000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.980808 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999963 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999963 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 7806239 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7806239 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5847887 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5847887 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183020 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183020 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199223 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199223 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13654126 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13654126 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13654126 # number of overall hits +system.cpu.dcache.overall_hits::total 13654126 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1068876 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1068876 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304232 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304232 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17223 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17223 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1373108 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1373108 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1373108 # number of overall misses +system.cpu.dcache.overall_misses::total 1373108 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 22711107000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 22711107000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8598536500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8598536500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 227697000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 227697000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 31309643500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31309643500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31309643500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31309643500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8875115 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8875115 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6152119 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6152119 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200243 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200243 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199223 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199223 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15027234 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15027234 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15027234 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15027234 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120435 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120435 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049452 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049452 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086010 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086010 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091375 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091375 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091375 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091375 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21247.653610 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21247.653610 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28263.090339 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28263.090339 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13220.519073 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13220.519073 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22802.025405 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22802.025405 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22802.025405 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22802.025405 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 834403 # number of writebacks +system.cpu.dcache.writebacks::total 834403 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1068876 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1068876 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304232 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304232 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17223 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17223 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1373108 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1373108 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1373108 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1373108 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 20573355000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 20573355000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7990072500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7990072500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 193251000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 193251000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28563427500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28563427500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28563427500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28563427500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424236000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424236000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2010997500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2010997500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435233500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435233500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120435 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120435 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049452 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049452 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086010 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086010 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091375 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091375 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091375 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091375 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19247.653610 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19247.653610 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26263.090339 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26263.090339 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11220.519073 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11220.519073 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20802.025405 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20802.025405 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20802.025405 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20802.025405 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |