diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt | 1711 |
1 files changed, 867 insertions, 844 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 9ceba3cc3..23c45cb03 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.941276 # Number of seconds simulated -sim_ticks 1941275996000 # Number of ticks simulated -final_tick 1941275996000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.922415 # Number of seconds simulated +sim_ticks 1922415409000 # Number of ticks simulated +final_tick 1922415409000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 780683 # Simulator instruction rate (inst/s) -host_op_rate 780683 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 26974878622 # Simulator tick rate (ticks/s) -host_mem_usage 326192 # Number of bytes of host memory used -host_seconds 71.97 # Real time elapsed on the host -sim_insts 56182685 # Number of instructions simulated -sim_ops 56182685 # Number of ops (including micro ops) simulated +host_inst_rate 933149 # Simulator instruction rate (inst/s) +host_op_rate 933149 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 31931169584 # Simulator tick rate (ticks/s) +host_mem_usage 334404 # Number of bytes of host memory used +host_seconds 60.21 # Real time elapsed on the host +sim_insts 56180200 # Number of instructions simulated +sim_ops 56180200 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 844800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24856512 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 844608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24856576 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25702272 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 844800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 844800 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7410752 # Number of bytes written to this memory -system.physmem.bytes_written::total 7410752 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13200 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388383 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25702144 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 844608 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 844608 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7408512 # Number of bytes written to this memory +system.physmem.bytes_written::total 7408512 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13197 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388384 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 401598 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115793 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115793 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 435178 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12804213 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 495 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13239886 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 435178 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 435178 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3817464 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3817464 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3817464 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 435178 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12804213 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 495 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17057350 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 401598 # Number of read requests accepted -system.physmem.writeReqs 115793 # Number of write requests accepted -system.physmem.readBursts 401598 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 115793 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25694784 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7488 # Total number of bytes read from write queue -system.physmem.bytesWritten 7408704 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25702272 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7410752 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 117 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 401596 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115758 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115758 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 439347 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12929867 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 499 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13369714 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 439347 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 439347 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3853752 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3853752 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3853752 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 439347 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12929867 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 499 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17223466 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 401596 # Number of read requests accepted +system.physmem.writeReqs 115758 # Number of write requests accepted +system.physmem.readBursts 401596 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115758 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25695616 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6528 # Total number of bytes read from write queue +system.physmem.bytesWritten 7407424 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25702144 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7408512 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 102 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25225 # Per bank write bursts -system.physmem.perBankRdBursts::1 25628 # Per bank write bursts -system.physmem.perBankRdBursts::2 25541 # Per bank write bursts -system.physmem.perBankRdBursts::3 25494 # Per bank write bursts -system.physmem.perBankRdBursts::4 25069 # Per bank write bursts -system.physmem.perBankRdBursts::5 24955 # Per bank write bursts -system.physmem.perBankRdBursts::6 24242 # Per bank write bursts -system.physmem.perBankRdBursts::7 24604 # Per bank write bursts -system.physmem.perBankRdBursts::8 25085 # Per bank write bursts -system.physmem.perBankRdBursts::9 24651 # Per bank write bursts -system.physmem.perBankRdBursts::10 25269 # Per bank write bursts -system.physmem.perBankRdBursts::11 24875 # Per bank write bursts -system.physmem.perBankRdBursts::12 24508 # Per bank write bursts -system.physmem.perBankRdBursts::13 25360 # Per bank write bursts -system.physmem.perBankRdBursts::14 25616 # Per bank write bursts -system.physmem.perBankRdBursts::15 25359 # Per bank write bursts -system.physmem.perBankWrBursts::0 7625 # Per bank write bursts -system.physmem.perBankWrBursts::1 7638 # Per bank write bursts -system.physmem.perBankWrBursts::2 7842 # Per bank write bursts -system.physmem.perBankWrBursts::3 7532 # Per bank write bursts -system.physmem.perBankWrBursts::4 7224 # Per bank write bursts -system.physmem.perBankWrBursts::5 6973 # Per bank write bursts -system.physmem.perBankWrBursts::6 6356 # Per bank write bursts -system.physmem.perBankWrBursts::7 6427 # Per bank write bursts -system.physmem.perBankWrBursts::8 7248 # Per bank write bursts -system.physmem.perBankWrBursts::9 6409 # Per bank write bursts -system.physmem.perBankWrBursts::10 7117 # Per bank write bursts +system.physmem.perBankRdBursts::0 25227 # Per bank write bursts +system.physmem.perBankRdBursts::1 25633 # Per bank write bursts +system.physmem.perBankRdBursts::2 25570 # Per bank write bursts +system.physmem.perBankRdBursts::3 25510 # Per bank write bursts +system.physmem.perBankRdBursts::4 24963 # Per bank write bursts +system.physmem.perBankRdBursts::5 24975 # Per bank write bursts +system.physmem.perBankRdBursts::6 24200 # Per bank write bursts +system.physmem.perBankRdBursts::7 24494 # Per bank write bursts +system.physmem.perBankRdBursts::8 25179 # Per bank write bursts +system.physmem.perBankRdBursts::9 24767 # Per bank write bursts +system.physmem.perBankRdBursts::10 25265 # Per bank write bursts +system.physmem.perBankRdBursts::11 24877 # Per bank write bursts +system.physmem.perBankRdBursts::12 24504 # Per bank write bursts +system.physmem.perBankRdBursts::13 25368 # Per bank write bursts +system.physmem.perBankRdBursts::14 25615 # Per bank write bursts +system.physmem.perBankRdBursts::15 25347 # Per bank write bursts +system.physmem.perBankWrBursts::0 7623 # Per bank write bursts +system.physmem.perBankWrBursts::1 7643 # Per bank write bursts +system.physmem.perBankWrBursts::2 7871 # Per bank write bursts +system.physmem.perBankWrBursts::3 7543 # Per bank write bursts +system.physmem.perBankWrBursts::4 7113 # Per bank write bursts +system.physmem.perBankWrBursts::5 6990 # Per bank write bursts +system.physmem.perBankWrBursts::6 6317 # Per bank write bursts +system.physmem.perBankWrBursts::7 6320 # Per bank write bursts +system.physmem.perBankWrBursts::8 7316 # Per bank write bursts +system.physmem.perBankWrBursts::9 6519 # Per bank write bursts +system.physmem.perBankWrBursts::10 7114 # Per bank write bursts system.physmem.perBankWrBursts::11 6905 # Per bank write bursts -system.physmem.perBankWrBursts::12 7093 # Per bank write bursts -system.physmem.perBankWrBursts::13 7822 # Per bank write bursts -system.physmem.perBankWrBursts::14 7863 # Per bank write bursts -system.physmem.perBankWrBursts::15 7687 # Per bank write bursts +system.physmem.perBankWrBursts::12 7090 # Per bank write bursts +system.physmem.perBankWrBursts::13 7827 # Per bank write bursts +system.physmem.perBankWrBursts::14 7864 # Per bank write bursts +system.physmem.perBankWrBursts::15 7686 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 8 # Number of times write queue was full causing retry -system.physmem.totGap 1941264122500 # Total gap between requests +system.physmem.numWrRetry 12 # Number of times write queue was full causing retry +system.physmem.totGap 1922403535500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 401598 # Read request sizes (log2) +system.physmem.readPktSize::6 401596 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 115793 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 401467 # What read queue length does an incoming req see +system.physmem.writePktSize::6 115758 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 401480 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see @@ -149,179 +149,197 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5632 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 5708 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5891 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5694 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8397 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7394 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5808 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6441 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6948 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7511 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6031 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5597 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5364 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 168 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 30 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64912 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 509.974858 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 310.437414 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 406.111966 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15297 23.57% 23.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11509 17.73% 41.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4968 7.65% 48.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3096 4.77% 53.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2466 3.80% 57.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4203 6.47% 63.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1427 2.20% 66.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2060 3.17% 69.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19886 30.64% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64912 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5094 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 78.810561 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2956.623385 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5091 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::46 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 29 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 63567 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 520.758255 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 315.623593 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 415.134860 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14658 23.06% 23.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11541 18.16% 41.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4861 7.65% 48.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3298 5.19% 54.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2285 3.59% 57.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1919 3.02% 60.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1565 2.46% 63.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1066 1.68% 64.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22374 35.20% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63567 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5112 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 78.539124 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2951.473216 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5109 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5094 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5094 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.724971 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.335038 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.028996 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4499 88.32% 88.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 29 0.57% 88.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 21 0.41% 89.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 41 0.80% 90.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 209 4.10% 94.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 11 0.22% 94.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 11 0.22% 94.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 30 0.59% 95.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 184 3.61% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 6 0.12% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 5 0.10% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 4 0.08% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 1 0.02% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 8 0.16% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 5 0.10% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 1 0.02% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 4 0.08% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 6 0.12% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 5 0.10% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 1 0.02% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 2 0.04% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 6 0.12% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 4 0.08% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5094 # Writes before turning the bus around for reads -system.physmem.totQLat 2720435750 # Total ticks spent queuing -system.physmem.totMemAccLat 10248204500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2007405000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6776.00 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5112 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5112 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.641041 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.167929 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.759533 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4475 87.54% 87.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 34 0.67% 88.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 11 0.22% 88.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 14 0.27% 88.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 223 4.36% 93.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 16 0.31% 93.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 14 0.27% 93.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 12 0.23% 93.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 3 0.06% 93.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 7 0.14% 94.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.10% 94.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.04% 94.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 12 0.23% 94.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 2 0.04% 94.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.06% 94.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 1 0.02% 94.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 33 0.65% 95.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 3 0.06% 95.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 18 0.35% 95.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 95.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 174 3.40% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.08% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 4 0.08% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.04% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.04% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 2 0.04% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.02% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 4 0.08% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.02% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 9 0.18% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 2 0.04% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 2 0.04% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 3 0.06% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 5 0.10% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-251 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5112 # Writes before turning the bus around for reads +system.physmem.totQLat 2082530750 # Total ticks spent queuing +system.physmem.totMemAccLat 9610543250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2007470000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5186.95 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25526.00 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.24 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.82 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.24 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.82 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 23936.95 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.37 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.85 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.37 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.85 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.13 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.10 # Average write queue length when enqueuing -system.physmem.readRowHits 358846 # Number of row buffer hits during reads -system.physmem.writeRowHits 93484 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.38 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.73 # Row buffer hit rate for writes -system.physmem.avgGap 3752025.30 # Average gap between requests -system.physmem.pageHitRate 87.44 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 240264360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 131096625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1565912400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 373358160 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 126794687760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 71567881875 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1101986685750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1302659886930 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.032849 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1832974732500 # Time in different power states -system.physmem_0.memoryStateTime::REF 64823460000 # Time in different power states +system.physmem.avgWrQLen 24.01 # Average write queue length when enqueuing +system.physmem.readRowHits 359878 # Number of row buffer hits during reads +system.physmem.writeRowHits 93790 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.63 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.02 # Row buffer hit rate for writes +system.physmem.avgGap 3715837.77 # Average gap between requests +system.physmem.pageHitRate 87.71 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 235297440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 128386500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1564461600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 372081600 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 125562446880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 64706229855 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1096686028500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1289254932375 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.645215 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1824198256500 # Time in different power states +system.physmem_0.memoryStateTime::REF 64193480000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 43477703750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 34018076000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 250470360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 136665375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1565639400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 376773120 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 126794687760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 72629135235 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1101055761750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1302809133000 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.109730 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1831423337250 # Time in different power states -system.physmem_1.memoryStateTime::REF 64823460000 # Time in different power states +system.physmem_1.actEnergy 245269080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 133827375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1567191600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 377920080 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 125562446880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 65408106195 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1096070355750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1289365116960 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.702526 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1823171088500 # Time in different power states +system.physmem_1.memoryStateTime::REF 64193480000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 45029099000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 35045257750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9064642 # DTB read hits -system.cpu.dtb.read_misses 10324 # DTB read misses +system.cpu.dtb.read_hits 9064160 # DTB read hits +system.cpu.dtb.read_misses 10312 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728853 # DTB read accesses -system.cpu.dtb.write_hits 6356200 # DTB write hits -system.cpu.dtb.write_misses 1142 # DTB write misses +system.cpu.dtb.read_accesses 728817 # DTB read accesses +system.cpu.dtb.write_hits 6356116 # DTB write hits +system.cpu.dtb.write_misses 1140 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 15420842 # DTB hits -system.cpu.dtb.data_misses 11466 # DTB misses +system.cpu.dtb.write_accesses 291929 # DTB write accesses +system.cpu.dtb.data_hits 15420276 # DTB hits +system.cpu.dtb.data_misses 11452 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020784 # DTB accesses -system.cpu.itb.fetch_hits 4975134 # ITB hits -system.cpu.itb.fetch_misses 5010 # ITB misses +system.cpu.dtb.data_accesses 1020746 # DTB accesses +system.cpu.itb.fetch_hits 4973965 # ITB hits +system.cpu.itb.fetch_misses 4997 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4980144 # ITB accesses +system.cpu.itb.fetch_accesses 4978962 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -334,43 +352,43 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numPwrStateTransitions 12750 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 6375 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 281084850.117804 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 439246512.061173 # Distribution of time spent in the clock gated state +system.cpu.numPwrStateTransitions 12754 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 6377 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 281224726.046887 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 439034613.415905 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::underflows 1 0.02% 0.02% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 6374 99.98% 100.00% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 6376 99.98% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 6375 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 149360076499 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 1791915919501 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 3882551992 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::total 6377 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 129045330999 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 1793370078001 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 3844830818 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 212050 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74912 40.88% 40.88% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6377 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211971 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74899 40.89% 40.89% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1935 1.06% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106253 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183231 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73545 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 106221 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183183 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73532 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1935 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73545 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149156 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1860509959000 95.84% 95.84% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 94068000 0.00% 95.84% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 770529000 0.04% 95.88% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 79900706000 4.12% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1941275262000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981752 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73532 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149127 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1857710123500 96.63% 96.63% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 93945500 0.00% 96.64% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 769790000 0.04% 96.68% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 63840816000 3.32% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1922414675000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692169 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814033 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692255 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814088 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -406,58 +424,58 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed +system.cpu.kern.callpal::swpctx 4174 2.16% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 176004 91.22% 93.41% # number of callpals executed -system.cpu.kern.callpal::rdps 6835 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 175962 91.22% 93.41% # number of callpals executed +system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5160 2.67% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192955 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5908 # number of protection mode switches -system.cpu.kern.mode_switch::user 1739 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1909 -system.cpu.kern.mode_good::user 1739 -system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.323121 # fraction of useful protection mode switches +system.cpu.kern.callpal::total 192906 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5901 # number of protection mode switches +system.cpu.kern.mode_switch::user 1741 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1910 +system.cpu.kern.mode_good::user 1741 +system.cpu.kern.mode_good::idle 169 +system.cpu.kern.mode_switch_good::kernel 0.323674 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081184 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.391952 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 48613391500 2.50% 2.50% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5603093000 0.29% 2.79% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1887058775500 97.21% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4177 # number of times the context was actually changed -system.cpu.committedInsts 56182685 # Number of instructions committed -system.cpu.committedOps 56182685 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52054580 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses -system.cpu.num_func_calls 1483390 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6468674 # number of instructions that are conditional controls -system.cpu.num_int_insts 52054580 # number of integer instructions -system.cpu.num_fp_insts 324393 # number of float instructions -system.cpu.num_int_register_reads 71322431 # number of times the integer registers were read -system.cpu.num_int_register_writes 38520860 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written -system.cpu.num_mem_refs 15473452 # number of memory refs -system.cpu.num_load_insts 9101488 # Number of load instructions -system.cpu.num_store_insts 6371964 # Number of store instructions -system.cpu.num_idle_cycles 3583831839.000154 # Number of idle cycles -system.cpu.num_busy_cycles 298720152.999846 # Number of busy cycles -system.cpu.not_idle_fraction 0.076939 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.923061 # Percentage of idle cycles -system.cpu.Branches 8422715 # Number of branches fetched -system.cpu.op_class::No_OpClass 3200634 5.70% 5.70% # Class of executed instruction -system.cpu.op_class::IntAlu 36230987 64.47% 70.17% # Class of executed instruction -system.cpu.op_class::IntMult 61043 0.11% 70.28% # Class of executed instruction +system.cpu.kern.mode_switch_good::idle 0.080630 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392278 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 46528757000 2.42% 2.42% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5244548000 0.27% 2.69% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1870641368000 97.31% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4175 # number of times the context was actually changed +system.cpu.committedInsts 56180200 # Number of instructions committed +system.cpu.committedOps 56180200 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52052716 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324259 # Number of float alu accesses +system.cpu.num_func_calls 1483318 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6468478 # number of instructions that are conditional controls +system.cpu.num_int_insts 52052716 # number of integer instructions +system.cpu.num_fp_insts 324259 # number of float instructions +system.cpu.num_int_register_reads 71320481 # number of times the integer registers were read +system.cpu.num_int_register_writes 38519316 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163543 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166418 # number of times the floating registers were written +system.cpu.num_mem_refs 15472847 # number of memory refs +system.cpu.num_load_insts 9100978 # Number of load instructions +system.cpu.num_store_insts 6371869 # Number of store instructions +system.cpu.num_idle_cycles 3586740156.000134 # Number of idle cycles +system.cpu.num_busy_cycles 258090661.999866 # Number of busy cycles +system.cpu.not_idle_fraction 0.067127 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.932873 # Percentage of idle cycles +system.cpu.Branches 8422318 # Number of branches fetched +system.cpu.op_class::No_OpClass 3200272 5.70% 5.70% # Class of executed instruction +system.cpu.op_class::IntAlu 36230015 64.48% 70.17% # Class of executed instruction +system.cpu.op_class::IntMult 60990 0.11% 70.28% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 70.28% # Class of executed instruction -system.cpu.op_class::FloatAdd 38085 0.07% 70.35% # Class of executed instruction +system.cpu.op_class::FloatAdd 38081 0.07% 70.35% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 70.35% # Class of executed instruction @@ -483,483 +501,482 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 70.35% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::MemRead 9328618 16.60% 86.95% # Class of executed instruction -system.cpu.op_class::MemWrite 6378045 11.35% 98.30% # Class of executed instruction -system.cpu.op_class::IprAccess 953470 1.70% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 9328048 16.60% 86.95% # Class of executed instruction +system.cpu.op_class::MemWrite 6377943 11.35% 98.30% # Class of executed instruction +system.cpu.op_class::IprAccess 953034 1.70% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 56194518 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1390398 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.973391 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14048965 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1390910 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 10.100556 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 145150500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.973391 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999948 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999948 # Average percentage of cache occupancy +system.cpu.op_class::total 56192019 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 1390892 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.977567 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 14047886 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1391404 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.096195 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 114940500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.977567 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999956 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999956 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63150415 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63150415 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 7814386 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7814386 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5852266 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5852266 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183036 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183036 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199260 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199260 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13666652 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13666652 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13666652 # number of overall hits -system.cpu.dcache.overall_hits::total 13666652 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1069356 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1069356 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304326 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304326 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17246 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17246 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1373682 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1373682 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1373682 # number of overall misses -system.cpu.dcache.overall_misses::total 1373682 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 44772600000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 44772600000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 17635207000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 17635207000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232797500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 232797500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 62407807000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 62407807000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 62407807000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 62407807000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 8883742 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 8883742 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6156592 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6156592 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200282 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200282 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199260 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199260 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15040334 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15040334 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15040334 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15040334 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120372 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120372 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049431 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049431 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086109 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086109 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091333 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091333 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091333 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091333 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41868.750912 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41868.750912 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57948.407300 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 57948.407300 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13498.637365 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13498.637365 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45431.043720 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45431.043720 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45431.043720 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45431.043720 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63148569 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63148569 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 7813455 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7813455 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5852226 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5852226 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 182968 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 182968 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199220 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199220 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13665681 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13665681 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13665681 # number of overall hits +system.cpu.dcache.overall_hits::total 13665681 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1069828 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1069828 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304319 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304319 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17275 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17275 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1374147 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1374147 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1374147 # number of overall misses +system.cpu.dcache.overall_misses::total 1374147 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 30980928500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 30980928500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11763694500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11763694500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 230325000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 230325000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 42744623000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 42744623000 # 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number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15039828 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15039828 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15039828 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120432 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120432 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049430 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049430 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086270 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086270 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091367 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091367 # 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average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37655.800328 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37655.800328 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12332.850941 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12332.850941 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30106.295760 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 30106.295760 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30106.295760 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 30106.295760 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221343.578644 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221343.578644 # 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number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13686093000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13686093000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13686093000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56194519 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56194519 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56194519 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56194519 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 56194519 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56194519 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016543 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016543 # 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Number of tag accesses +system.cpu.icache.tags.data_accesses 57120725 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 55263315 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55263315 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55263315 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55263315 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55263315 # number of overall hits +system.cpu.icache.overall_hits::total 55263315 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 928705 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 928705 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 928705 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 928705 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 928705 # 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Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 5475.418237 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.840345 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.071505 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.083548 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.995397 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 722 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5220 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3221 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55822 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 37812907 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 37812907 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 834943 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 834943 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 928709 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 928709 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187489 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187489 # 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average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13023.634523 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13023.634523 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 336391 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65395.484463 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4235202 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 401913 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 10.537609 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 7260348000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 235.775942 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4738.507265 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 60421.201256 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.003598 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072304 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.921954 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.997856 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 518 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 384 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4753 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59867 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 37502484 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 37502484 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 835265 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 835265 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 927811 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 927811 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 12 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 12 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 187491 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187491 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 915488 # 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number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13197 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 13197 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 271975 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 271975 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 13197 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 388786 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 401983 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 13197 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 388786 # number of overall misses +system.cpu.l2cache.overall_misses::total 401983 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 246500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 246500 # 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average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130816.060606 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 125061.104810 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 125250.077738 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130816.060606 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 125061.104810 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 125250.077738 # average overall miss latency +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304302 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304302 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 928685 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 928685 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1087103 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1087103 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 928685 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1391405 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2320090 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 928685 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1391405 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2320090 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.294118 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.294118 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383865 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383865 # 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number of overall MSHR uncacheable cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383886 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383886 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014200 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014200 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250295 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250295 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014200 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279523 # 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average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113988.346184 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113988.346184 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120816.060606 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 115061.104810 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115250.077738 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120816.060606 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 115061.104810 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115250.077738 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 207838.961039 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 207838.961039 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86855.454381 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 86855.454381 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4639859 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319495 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1502 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1136 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1136 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9650 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9650 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16580 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16580 # number of overall MSHR uncacheable misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 196500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 196500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7862462500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7862462500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 944176500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 944176500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17200833000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17200833000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 944176500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25063295500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26007472000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 944176500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25063295500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26007472000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1447255500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1447255500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1447255500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1447255500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.294118 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.294118 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383865 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383865 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014210 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014210 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250183 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250183 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014210 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279420 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.173262 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014210 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279420 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.173262 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 39300 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 39300 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67309.264538 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67309.264538 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71544.782905 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71544.782905 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63244.169501 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63244.169501 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71544.782905 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64465.529880 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64697.939963 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71544.782905 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64465.529880 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64697.939963 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208839.177489 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208839.177489 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87289.234017 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87289.234017 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4639053 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319092 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1505 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 884 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 884 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2023291 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9653 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9653 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 950744 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 928931 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 817740 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2022895 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 909511 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 928034 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 817772 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304309 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304309 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 929602 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1086775 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2788115 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4205577 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6993692 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118944832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142509292 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 261454124 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 419988 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 7422592 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2756924 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001015 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.031847 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 304302 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304302 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 928705 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1087263 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 219 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2785424 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4207053 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6992477 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118830016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142561492 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 261391508 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 336947 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 4763072 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2673477 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000954 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.030869 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2754125 99.90% 99.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2799 0.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2670927 99.90% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2550 0.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2756924 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4096921500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2673477 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4095940500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 293383 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1394403000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1393057500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2098131500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2098871000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -973,12 +990,12 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51205 # Transaction distribution -system.iobus.trans_dist::WriteResp 51205 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5162 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51202 # Transaction distribution +system.iobus.trans_dist::WriteResp 51202 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5156 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -987,11 +1004,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 1812 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33166 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33160 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116616 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20648 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116610 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20624 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1000,13 +1017,13 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 44588 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 44564 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2706196 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 5341000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2706172 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 5337500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 759000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 758500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1014,36 +1031,36 @@ system.iobus.reqLayer6.occupancy 10000 # La system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 174000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 15817500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 15814000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 1891500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6038000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6041500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 82000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 215662167 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216133054 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23513000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.339384 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.342865 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1774106669000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.339384 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.083712 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.083712 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1756469369000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.342865 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.083929 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.083929 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375525 # Number of tag accesses system.iocache.tags.data_accesses 375525 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -1052,14 +1069,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21742883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21742883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5244723284 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5244723284 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 5266466167 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5266466167 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 5266466167 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5266466167 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21758883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21758883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4857806171 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4857806171 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4879565054 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4879565054 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4879565054 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4879565054 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1076,19 +1093,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125681.404624 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125681.404624 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126220.718233 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 126220.718233 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 126218.482133 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126218.482133 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 126218.482133 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126218.482133 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 29 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125773.890173 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125773.890173 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116909.081897 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 116909.081897 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 116945.837124 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 116945.837124 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 116945.837124 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 116945.837124 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 14.500000 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks @@ -1100,14 +1117,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13092883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13092883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165324984 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3165324984 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3178417867 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3178417867 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3178417867 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3178417867 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13108883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13108883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2777800981 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2777800981 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2790909864 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2790909864 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2790909864 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2790909864 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1116,65 +1133,71 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75681.404624 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 75681.404624 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76177.439931 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76177.439931 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76175.383271 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76175.383271 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76175.383271 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76175.383271 # average overall mshr miss latency -system.membus.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75773.890173 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 75773.890173 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66851.198041 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66851.198041 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66888.193265 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 66888.193265 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66888.193265 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 66888.193265 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 821076 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 378187 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 407 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 292274 # Transaction distribution -system.membus.trans_dist::WriteReq 9653 # Transaction distribution -system.membus.trans_dist::WriteResp 9653 # Transaction distribution -system.membus.trans_dist::WritebackDirty 115793 # Transaction distribution -system.membus.trans_dist::CleanEvict 261560 # Transaction distribution -system.membus.trans_dist::UpgradeReq 150 # Transaction distribution +system.membus.trans_dist::ReadResp 292275 # Transaction distribution +system.membus.trans_dist::WriteReq 9650 # Transaction distribution +system.membus.trans_dist::WriteResp 9650 # Transaction distribution +system.membus.trans_dist::WritebackDirty 115758 # Transaction distribution +system.membus.trans_dist::CleanEvict 261593 # Transaction distribution +system.membus.trans_dist::UpgradeReq 136 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 116683 # Transaction distribution -system.membus.trans_dist::ReadExResp 116683 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 285344 # Transaction distribution +system.membus.trans_dist::ReadExReq 116680 # Transaction distribution +system.membus.trans_dist::ReadExResp 116680 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 285345 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33166 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139255 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172421 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139235 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172395 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1255846 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44588 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30455296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30499884 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1255820 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30452928 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30497492 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33157612 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33155220 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 431 # Total snoops (count) system.membus.snoopTraffic 27456 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 837673 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::samples 460293 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001416 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.037610 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 837673 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 459641 99.86% 99.86% # Request fanout histogram +system.membus.snoop_fanout::1 652 0.14% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 837673 # Request fanout histogram -system.membus.reqLayer0.occupancy 30123000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 460293 # Request fanout histogram +system.membus.reqLayer0.occupancy 30118500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1287200717 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1286935040 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2143013000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2142767250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.membus.respLayer2.occupancy 887117 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1206,28 +1229,28 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- |