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Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt')
-rw-r--r--tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt1300
1 files changed, 660 insertions, 640 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
index 7916cb036..a960683a9 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
@@ -1,76 +1,76 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.919439 # Number of seconds simulated
-sim_ticks 1919438772000 # Number of ticks simulated
-final_tick 1919438772000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 1919439025000 # Number of ticks simulated
+final_tick 1919439025000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1398299 # Simulator instruction rate (inst/s)
-host_op_rate 1398299 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 47840414078 # Simulator tick rate (ticks/s)
-host_mem_usage 314348 # Number of bytes of host memory used
-host_seconds 40.12 # Real time elapsed on the host
-sim_insts 56102112 # Number of instructions simulated
-sim_ops 56102112 # Number of ops (including micro ops) simulated
+host_inst_rate 1426339 # Simulator instruction rate (inst/s)
+host_op_rate 1426339 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 48799693433 # Simulator tick rate (ticks/s)
+host_mem_usage 367228 # Number of bytes of host memory used
+host_seconds 39.33 # Real time elapsed on the host
+sim_insts 56102180 # Number of instructions simulated
+sim_ops 56102180 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 850816 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 24875968 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 24875904 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 25727744 # Number of bytes read from this memory
+system.physmem.bytes_read::total 25727680 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 850816 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 850816 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4747712 # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks 4747520 # Number of bytes written to this memory
system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7407040 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7406848 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 13294 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 388687 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 388686 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 401996 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 74183 # Number of write requests responded to by this memory
+system.physmem.num_reads::total 401995 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 74180 # Number of write requests responded to by this memory
system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 115735 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 115732 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 443263 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 12960022 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 12959987 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 500 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 13403785 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 13403750 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 443263 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 443263 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2473490 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::tsunami.ide 1385472 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 3858961 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2473490 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2473389 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::tsunami.ide 1385471 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 3858861 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2473389 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 443263 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 12960022 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 12959987 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1385972 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 17262746 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 401996 # Number of read requests accepted
-system.physmem.writeReqs 115735 # Number of write requests accepted
-system.physmem.readBursts 401996 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 115735 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 25716224 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 11520 # Total number of bytes read from write queue
-system.physmem.bytesWritten 7405312 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 25727744 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 7407040 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 180 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total 17262610 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 401995 # Number of read requests accepted
+system.physmem.writeReqs 115732 # Number of write requests accepted
+system.physmem.readBursts 401995 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 115732 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 25715968 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 11712 # Total number of bytes read from write queue
+system.physmem.bytesWritten 7405120 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 25727680 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 7406848 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 183 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 132 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 25161 # Per bank write bursts
-system.physmem.perBankRdBursts::1 25541 # Per bank write bursts
+system.physmem.perBankRdBursts::1 25539 # Per bank write bursts
system.physmem.perBankRdBursts::2 25618 # Per bank write bursts
-system.physmem.perBankRdBursts::3 25537 # Per bank write bursts
-system.physmem.perBankRdBursts::4 24981 # Per bank write bursts
-system.physmem.perBankRdBursts::5 24976 # Per bank write bursts
+system.physmem.perBankRdBursts::3 25536 # Per bank write bursts
+system.physmem.perBankRdBursts::4 24982 # Per bank write bursts
+system.physmem.perBankRdBursts::5 24977 # Per bank write bursts
system.physmem.perBankRdBursts::6 24228 # Per bank write bursts
system.physmem.perBankRdBursts::7 24506 # Per bank write bursts
-system.physmem.perBankRdBursts::8 25159 # Per bank write bursts
-system.physmem.perBankRdBursts::9 24820 # Per bank write bursts
+system.physmem.perBankRdBursts::8 25158 # Per bank write bursts
+system.physmem.perBankRdBursts::9 24823 # Per bank write bursts
system.physmem.perBankRdBursts::10 25363 # Per bank write bursts
-system.physmem.perBankRdBursts::11 24840 # Per bank write bursts
-system.physmem.perBankRdBursts::12 24420 # Per bank write bursts
+system.physmem.perBankRdBursts::11 24839 # Per bank write bursts
+system.physmem.perBankRdBursts::12 24418 # Per bank write bursts
system.physmem.perBankRdBursts::13 25388 # Per bank write bursts
system.physmem.perBankRdBursts::14 25795 # Per bank write bursts
-system.physmem.perBankRdBursts::15 25483 # Per bank write bursts
+system.physmem.perBankRdBursts::15 25481 # Per bank write bursts
system.physmem.perBankWrBursts::0 7550 # Per bank write bursts
system.physmem.perBankWrBursts::1 7529 # Per bank write bursts
system.physmem.perBankWrBursts::2 7880 # Per bank write bursts
@@ -78,9 +78,9 @@ system.physmem.perBankWrBursts::3 7553 # Pe
system.physmem.perBankWrBursts::4 7115 # Per bank write bursts
system.physmem.perBankWrBursts::5 6983 # Per bank write bursts
system.physmem.perBankWrBursts::6 6321 # Per bank write bursts
-system.physmem.perBankWrBursts::7 6319 # Per bank write bursts
+system.physmem.perBankWrBursts::7 6315 # Per bank write bursts
system.physmem.perBankWrBursts::8 7293 # Per bank write bursts
-system.physmem.perBankWrBursts::9 6554 # Per bank write bursts
+system.physmem.perBankWrBursts::9 6555 # Per bank write bursts
system.physmem.perBankWrBursts::10 7205 # Per bank write bursts
system.physmem.perBankWrBursts::11 6861 # Per bank write bursts
system.physmem.perBankWrBursts::12 6964 # Per bank write bursts
@@ -88,23 +88,23 @@ system.physmem.perBankWrBursts::13 7821 # Pe
system.physmem.perBankWrBursts::14 7980 # Per bank write bursts
system.physmem.perBankWrBursts::15 7780 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 11 # Number of times write queue was full causing retry
-system.physmem.totGap 1919426851000 # Total gap between requests
+system.physmem.numWrRetry 12 # Number of times write queue was full causing retry
+system.physmem.totGap 1919427104000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 401996 # Read request sizes (log2)
+system.physmem.readPktSize::6 401995 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 115735 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 401802 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 115732 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 401798 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
@@ -151,124 +151,123 @@ system.physmem.wrQLenPdf::11 1 # Wh
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 1859 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 2606 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 5607 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 5735 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 5978 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 6706 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 6976 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 8149 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 8460 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 8432 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 8109 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 8281 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 6824 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 6355 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 5592 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 5334 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 5330 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 5306 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 213 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 190 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 175 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 156 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 153 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 129 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 122 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 128 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 172 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 155 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 1803 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 2465 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 5530 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 5623 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 5839 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 6566 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 6884 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 8073 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 8473 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 8504 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 8199 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 8343 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 6888 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 6495 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 5617 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 5359 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 5332 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 5312 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 203 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 203 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 198 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 198 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 202 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 177 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 167 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 165 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 180 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 160 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 170 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 198 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 218 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 205 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 182 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 176 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 146 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 120 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 111 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 104 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 111 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 122 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 116 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 111 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 111 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 94 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 70 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 30 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 24 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 63869 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 518.585480 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 313.979775 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 413.923527 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 14875 23.29% 23.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 11515 18.03% 41.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 4721 7.39% 48.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3142 4.92% 53.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 3018 4.73% 58.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1863 2.92% 61.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1301 2.04% 63.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1404 2.20% 65.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 22030 34.49% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 63869 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 5101 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 78.768477 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 2955.016496 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191 5098 99.94% 99.94% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::44 189 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 216 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 208 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 201 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 197 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 176 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 132 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 127 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 105 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 93 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 101 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 109 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 112 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 113 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 91 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 72 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 62 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 35 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 27 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 63991 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 517.589786 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 312.394273 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 414.375602 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 15074 23.56% 23.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 11584 18.10% 41.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 4587 7.17% 48.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 3091 4.83% 53.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 3045 4.76% 58.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1807 2.82% 61.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1323 2.07% 63.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1474 2.30% 65.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 22006 34.39% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 63991 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 5109 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 78.644353 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 2952.702952 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191 5106 99.94% 99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 5101 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 5101 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 22.683395 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 19.235797 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 21.276820 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 4452 87.28% 87.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 22 0.43% 87.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 15 0.29% 88.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 224 4.39% 92.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 41 0.80% 93.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 6 0.12% 93.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 9 0.18% 93.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 7 0.14% 93.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 19 0.37% 94.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 2 0.04% 94.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 4 0.08% 94.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 2 0.04% 94.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 11 0.22% 94.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 3 0.06% 94.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 7 0.14% 94.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 30 0.59% 95.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87 13 0.25% 95.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91 3 0.06% 95.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95 1 0.02% 95.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 166 3.25% 98.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103 10 0.20% 98.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 2 0.04% 98.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123 6 0.12% 99.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 4 0.08% 99.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135 2 0.04% 99.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139 6 0.12% 99.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143 9 0.18% 99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147 9 0.18% 99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151 1 0.02% 99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155 3 0.06% 99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159 2 0.04% 99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163 3 0.06% 99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167 1 0.02% 99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171 1 0.02% 99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::220-223 1 0.02% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-227 4 0.08% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 5101 # Writes before turning the bus around for reads
-system.physmem.totQLat 2117396500 # Total ticks spent queuing
-system.physmem.totMemAccLat 9651446500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 2009080000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 5269.57 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 5109 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 5109 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 22.647289 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 19.199358 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 21.195525 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 4460 87.30% 87.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 21 0.41% 87.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 12 0.23% 87.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 224 4.38% 92.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 41 0.80% 93.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 20 0.39% 93.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 7 0.14% 93.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 6 0.12% 93.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 14 0.27% 94.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 4 0.08% 94.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 3 0.06% 94.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 1 0.02% 94.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 9 0.18% 94.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 5 0.10% 94.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 4 0.08% 94.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 25 0.49% 95.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87 9 0.18% 95.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95 15 0.29% 95.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 168 3.29% 98.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103 2 0.04% 98.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111 1 0.02% 98.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 2 0.04% 98.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119 1 0.02% 98.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123 2 0.04% 98.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 8 0.16% 99.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135 5 0.10% 99.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139 5 0.10% 99.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 9 0.18% 99.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147 13 0.25% 99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151 1 0.02% 99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155 1 0.02% 99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159 2 0.04% 99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163 5 0.10% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175 1 0.02% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227 3 0.06% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 5109 # Writes before turning the bus around for reads
+system.physmem.totQLat 2129492750 # Total ticks spent queuing
+system.physmem.totMemAccLat 9663467750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2009060000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 5299.72 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 24019.57 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 24049.72 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 13.40 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 3.86 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 13.40 # Average system read bandwidth in MiByte/s
@@ -278,100 +277,113 @@ system.physmem.busUtil 0.13 # Da
system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 23.42 # Average write queue length when enqueuing
-system.physmem.readRowHits 360116 # Number of row buffer hits during reads
-system.physmem.writeRowHits 93539 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 89.62 # Row buffer hit rate for reads
+system.physmem.avgWrQLen 24.48 # Average write queue length when enqueuing
+system.physmem.readRowHits 359991 # Number of row buffer hits during reads
+system.physmem.writeRowHits 93535 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 89.59 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 80.82 # Row buffer hit rate for writes
-system.physmem.avgGap 3707382.50 # Average gap between requests
-system.physmem.pageHitRate 87.65 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 1800046548500 # Time in different power states
+system.physmem.avgGap 3707411.64 # Average gap between requests
+system.physmem.pageHitRate 87.63 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 1800186005000 # Time in different power states
system.physmem.memoryStateTime::REF 64094160000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 55294756500 # Time in different power states
+system.physmem.memoryStateTime::ACT 55155300000 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 17291227 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 292357 # Transaction distribution
system.membus.trans_dist::ReadResp 292357 # Transaction distribution
system.membus.trans_dist::WriteReq 9649 # Transaction distribution
system.membus.trans_dist::WriteResp 9649 # Transaction distribution
-system.membus.trans_dist::Writeback 74183 # Transaction distribution
+system.membus.trans_dist::Writeback 74180 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
system.membus.trans_dist::UpgradeReq 132 # Transaction distribution
system.membus.trans_dist::UpgradeResp 132 # Transaction distribution
-system.membus.trans_dist::ReadExReq 116727 # Transaction distribution
-system.membus.trans_dist::ReadExResp 116727 # Transaction distribution
+system.membus.trans_dist::ReadExReq 116726 # Transaction distribution
+system.membus.trans_dist::ReadExResp 116726 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33158 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878409 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911567 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878404 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911562 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83292 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 83292 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 994859 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30474496 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30519052 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 33179340 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 33179340 # Total data (bytes)
-system.membus.snoop_data_through_bus 10112 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 32375500 # Layer occupancy (ticks)
+system.membus.pkt_count::total 994854 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30474240 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30518796 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 33179084 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 158 # Total snoops (count)
+system.membus.snoop_fanout::samples 518029 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 518029 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 518029 # Request fanout histogram
+system.membus.reqLayer0.occupancy 30371000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 1450892000 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 1451093000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer1.occupancy 3751806368 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 3752017868 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer2.occupancy 43113000 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 43114250 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 41685 # number of replacements
-system.iocache.tags.tagsinuse 1.344805 # Cycle average of tags in use
+system.iocache.tags.tagsinuse 1.344808 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 1753524887000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide 1.344805 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide 0.084050 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.084050 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 1753524972000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide 1.344808 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide 0.084051 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.084051 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 375525 # Number of tag accesses
-system.iocache.tags.data_accesses 375525 # Number of data accesses
+system.iocache.tags.tag_accesses 375557 # Number of tag accesses
+system.iocache.tags.data_accesses 375557 # Number of data accesses
system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
+system.iocache.WriteInvalidateReq_misses::tsunami.ide 4 # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total 4 # number of WriteInvalidateReq misses
system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses
system.iocache.demand_misses::total 173 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
system.iocache.overall_misses::total 173 # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::tsunami.ide 24523133 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 24523133 # number of ReadReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide 24523133 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 24523133 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide 24523133 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 24523133 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41556 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total 41556 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 0.000096 # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total 0.000096 # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 141752.213873 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 141752.213873 # average ReadReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 141752.213873 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 141752.213873 # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 141752.213873 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 141752.213873 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -388,30 +400,30 @@ system.iocache.demand_mshr_misses::tsunami.ide 173
system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2506570306 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2506570306 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 15526633 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 15526633 # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2512178304 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2512178304 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide 15526633 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 15526633 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide 15526633 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 15526633 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.999904 # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.999904 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60323.698161 # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60323.698161 # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 89749.323699 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 89749.323699 # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60458.661533 # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60458.661533 # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 89749.323699 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 89749.323699 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 89749.323699 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 89749.323699 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
@@ -430,22 +442,22 @@ system.cpu.dtb.fetch_hits 0 # IT
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 9052614 # DTB read hits
-system.cpu.dtb.read_misses 10356 # DTB read misses
+system.cpu.dtb.read_hits 9052455 # DTB read hits
+system.cpu.dtb.read_misses 10357 # DTB read misses
system.cpu.dtb.read_acv 210 # DTB read access violations
-system.cpu.dtb.read_accesses 728915 # DTB read accesses
-system.cpu.dtb.write_hits 6349217 # DTB write hits
-system.cpu.dtb.write_misses 1144 # DTB write misses
+system.cpu.dtb.read_accesses 728916 # DTB read accesses
+system.cpu.dtb.write_hits 6349129 # DTB write hits
+system.cpu.dtb.write_misses 1143 # DTB write misses
system.cpu.dtb.write_acv 157 # DTB write access violations
-system.cpu.dtb.write_accesses 291933 # DTB write accesses
-system.cpu.dtb.data_hits 15401831 # DTB hits
+system.cpu.dtb.write_accesses 291932 # DTB write accesses
+system.cpu.dtb.data_hits 15401584 # DTB hits
system.cpu.dtb.data_misses 11500 # DTB misses
system.cpu.dtb.data_acv 367 # DTB access violations
system.cpu.dtb.data_accesses 1020848 # DTB accesses
-system.cpu.itb.fetch_hits 4974960 # ITB hits
+system.cpu.itb.fetch_hits 4974880 # ITB hits
system.cpu.itb.fetch_misses 5010 # ITB misses
system.cpu.itb.fetch_acv 184 # ITB acv
-system.cpu.itb.fetch_accesses 4979970 # ITB accesses
+system.cpu.itb.fetch_accesses 4979890 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -458,34 +470,34 @@ system.cpu.itb.data_hits 0 # DT
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.numCycles 3838877544 # number of cpu cycles simulated
+system.cpu.numCycles 3838878050 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 56102112 # Number of instructions committed
-system.cpu.committedOps 56102112 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 51977185 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses
-system.cpu.num_func_calls 1481236 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 6460933 # number of instructions that are conditional controls
-system.cpu.num_int_insts 51977185 # number of integer instructions
-system.cpu.num_fp_insts 324460 # number of float instructions
-system.cpu.num_int_register_reads 71206533 # number of times the integer registers were read
-system.cpu.num_int_register_writes 38459103 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written
-system.cpu.num_mem_refs 15454487 # number of memory refs
-system.cpu.num_load_insts 9089505 # Number of load instructions
-system.cpu.num_store_insts 6364982 # Number of store instructions
-system.cpu.num_idle_cycles 3587234430.998131 # Number of idle cycles
-system.cpu.num_busy_cycles 251643113.001869 # Number of busy cycles
-system.cpu.not_idle_fraction 0.065551 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.934449 # Percentage of idle cycles
-system.cpu.Branches 8412678 # Number of branches fetched
-system.cpu.op_class::No_OpClass 3197715 5.70% 5.70% # Class of executed instruction
-system.cpu.op_class::IntAlu 36172357 64.46% 70.16% # Class of executed instruction
-system.cpu.op_class::IntMult 61004 0.11% 70.27% # Class of executed instruction
+system.cpu.committedInsts 56102180 # Number of instructions committed
+system.cpu.committedOps 56102180 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 51977296 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 324326 # Number of float alu accesses
+system.cpu.num_func_calls 1481232 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 6461044 # number of instructions that are conditional controls
+system.cpu.num_int_insts 51977296 # number of integer instructions
+system.cpu.num_fp_insts 324326 # number of float instructions
+system.cpu.num_int_register_reads 71206831 # number of times the integer registers were read
+system.cpu.num_int_register_writes 38459262 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 163576 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 166452 # number of times the floating registers were written
+system.cpu.num_mem_refs 15454224 # number of memory refs
+system.cpu.num_load_insts 9089337 # Number of load instructions
+system.cpu.num_store_insts 6364887 # Number of store instructions
+system.cpu.num_idle_cycles 3587231475.998131 # Number of idle cycles
+system.cpu.num_busy_cycles 251646574.001869 # Number of busy cycles
+system.cpu.not_idle_fraction 0.065552 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.934448 # Percentage of idle cycles
+system.cpu.Branches 8412776 # Number of branches fetched
+system.cpu.op_class::No_OpClass 3197684 5.70% 5.70% # Class of executed instruction
+system.cpu.op_class::IntAlu 36172751 64.46% 70.16% # Class of executed instruction
+system.cpu.op_class::IntMult 60997 0.11% 70.27% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction
-system.cpu.op_class::FloatAdd 38087 0.07% 70.34% # Class of executed instruction
+system.cpu.op_class::FloatAdd 38083 0.07% 70.34% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 70.34% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 70.34% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction
@@ -511,14 +523,14 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 70.34% # Cl
system.cpu.op_class::SimdFloatMult 0 0.00% 70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.34% # Class of executed instruction
-system.cpu.op_class::MemRead 9316582 16.60% 86.95% # Class of executed instruction
-system.cpu.op_class::MemWrite 6371054 11.35% 98.30% # Class of executed instruction
-system.cpu.op_class::IprAccess 953544 1.70% 100.00% # Class of executed instruction
+system.cpu.op_class::MemRead 9316413 16.60% 86.95% # Class of executed instruction
+system.cpu.op_class::MemWrite 6370959 11.35% 98.30% # Class of executed instruction
+system.cpu.op_class::IprAccess 953524 1.70% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 56113979 # Class of executed instruction
+system.cpu.op_class::total 56114047 # Class of executed instruction
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei 212019 # number of hwrei instructions executed
+system.cpu.kern.inst.quiesce 6380 # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei 212017 # number of hwrei instructions executed
system.cpu.kern.ipl_count::0 74895 40.89% 40.89% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22 1931 1.05% 42.01% # number of times we switched to this ipl
@@ -529,11 +541,11 @@ system.cpu.kern.ipl_good::21 131 0.09% 49.40% # nu
system.cpu.kern.ipl_good::22 1931 1.29% 50.69% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31 73528 49.31% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total 149118 # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0 1857248521000 96.76% 96.76% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21 91287500 0.00% 96.76% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22 737179000 0.04% 96.80% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31 61361050500 3.20% 100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total 1919438038000 # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::0 1857251860000 96.76% 96.76% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21 91366000 0.00% 96.76% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22 736784000 0.04% 96.80% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31 61358281000 3.20% 100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total 1919438291000 # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
@@ -574,8 +586,8 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
-system.cpu.kern.callpal::swpctx 4177 2.17% 2.17% # number of callpals executed
-system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
+system.cpu.kern.callpal::swpctx 4175 2.16% 2.17% # number of callpals executed
+system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed
system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
system.cpu.kern.callpal::swpipl 175949 91.22% 93.41% # number of callpals executed
system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed
@@ -586,21 +598,21 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu
system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
-system.cpu.kern.callpal::total 192894 # number of callpals executed
-system.cpu.kern.mode_switch::kernel 5902 # number of protection mode switches
+system.cpu.kern.callpal::total 192892 # number of callpals executed
+system.cpu.kern.mode_switch::kernel 5903 # number of protection mode switches
system.cpu.kern.mode_switch::user 1742 # number of protection mode switches
-system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
-system.cpu.kern.mode_good::kernel 1912
+system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches
+system.cpu.kern.mode_good::kernel 1911
system.cpu.kern.mode_good::user 1742
-system.cpu.kern.mode_good::idle 170
-system.cpu.kern.mode_switch_good::kernel 0.323958 # fraction of useful protection mode switches
+system.cpu.kern.mode_good::idle 169
+system.cpu.kern.mode_switch_good::kernel 0.323734 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total 0.392567 # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel 46116573000 2.40% 2.40% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user 5192895500 0.27% 2.67% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle 1868128567500 97.33% 100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context 4178 # number of times the context was actually changed
+system.cpu.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total 0.392443 # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel 46142250000 2.40% 2.40% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user 5192719000 0.27% 2.67% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle 1868103320000 97.33% 100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context 4176 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
@@ -632,11 +644,11 @@ system.tsunami.ethernet.totalRxOrn 0 # to
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.iobus.throughput 1409873 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
-system.iobus.trans_dist::WriteReq 51201 # Transaction distribution
+system.iobus.trans_dist::WriteReq 51197 # Transaction distribution
system.iobus.trans_dist::WriteResp 51201 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateReq 4 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5154 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
@@ -653,23 +665,22 @@ system.iobus.pkt_count_system.bridge.master::total 33158
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 116608 # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20616 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total 44556 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total 2706164 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus 2706164 # Total data (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20616 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 44556 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2706164 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks)
@@ -692,21 +703,21 @@ system.iobus.reqLayer27.occupancy 76000 # La
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer29.occupancy 374407689 # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy 374412187 # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 23509000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 42014000 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 42016750 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu.icache.tags.replacements 927724 # number of replacements
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@@ -898,66 +909,66 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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@@ -965,11 +976,11 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf
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system.cpu.dcache.tags.tagsinuse 511.978881 # Cycle average of tags in use
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system.cpu.dcache.tags.warmup_cycle 107775250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.978881 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy
@@ -979,72 +990,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 187
system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id
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-system.cpu.dcache.WriteReq_miss_latency::total 10906246382 # number of WriteReq miss cycles
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-system.cpu.dcache.LoadLockedReq_miss_latency::total 228174000 # number of LoadLockedReq miss cycles
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-system.cpu.dcache.ReadReq_accesses::total 8871761 # number of ReadReq accesses(hits+misses)
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-system.cpu.dcache.WriteReq_accesses::total 6149649 # number of WriteReq accesses(hits+misses)
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-system.cpu.dcache.StoreCondReq_accesses::total 199227 # number of StoreCondReq accesses(hits+misses)
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-system.cpu.dcache.demand_miss_rate::total 0.091429 # miss rate for demand accesses
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-system.cpu.dcache.overall_miss_rate::total 0.091429 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27121.578377 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 27121.578377 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35851.398495 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 35851.398495 # average WriteReq miss latency
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-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13255.141164 # average LoadLockedReq miss latency
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-system.cpu.dcache.demand_avg_miss_latency::total 29055.226541 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 29055.226541 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 29055.226541 # average overall miss latency
+system.cpu.dcache.tags.tag_accesses 63073026 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 63073026 # Number of data accesses
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+system.cpu.dcache.ReadReq_hits::total 7802461 # number of ReadReq hits
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+system.cpu.dcache.LoadLockedReq_accesses::total 200245 # number of LoadLockedReq accesses(hits+misses)
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+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085970 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085970 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.091427 # miss rate for demand accesses
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+system.cpu.dcache.overall_miss_rate::total 0.091427 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27119.413703 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 27119.413703 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35903.935596 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 35903.935596 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13259.991287 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13259.991287 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 29065.256879 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 29065.256879 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 29065.256879 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 29065.256879 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1053,54 +1064,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 834526 # number of writebacks
-system.cpu.dcache.writebacks::total 834526 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069193 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1069193 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304207 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 304207 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17214 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 17214 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1373400 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1373400 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1373400 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1373400 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26734131250 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 26734131250 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10245126618 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 10245126618 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 193732000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 193732000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36979257868 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 36979257868 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36979257868 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 36979257868 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424236000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424236000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011219500 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011219500 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435455500 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435455500 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120516 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120516 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049467 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049467 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085963 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085963 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091429 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.091429 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091429 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.091429 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25004.027570 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25004.027570 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33678.142245 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33678.142245 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11254.327873 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11254.327873 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26925.337023 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26925.337023 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26925.337023 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26925.337023 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 834448 # number of writebacks
+system.cpu.dcache.writebacks::total 834448 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069134 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1069134 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304206 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 304206 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17215 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 17215 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1373340 # number of demand (read+write) MSHR misses
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+system.cpu.dcache.overall_mshr_misses::total 1373340 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26730348750 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 26730348750 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10261067368 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 10261067368 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 193828250 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 193828250 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36991416118 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 36991416118 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36991416118 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 36991416118 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424273000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424273000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2009178000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2009178000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3433451000 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 3433451000 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120512 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120512 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049468 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049468 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085970 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085970 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091427 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.091427 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091427 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.091427 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25001.869504 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25001.869504 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33730.654123 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33730.654123 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11259.265176 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11259.265176 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26935.366419 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26935.366419 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26935.366419 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26935.366419 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
@@ -1108,32 +1119,41 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 106562255 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 2021905 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 2021888 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq 2021774 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2021757 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 9649 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 9649 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 834526 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41563 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 834448 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41564 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 304190 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 304190 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1856770 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3649068 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 5505838 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59416000 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142462412 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 201878412 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 201868428 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 2671296 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 2424407500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.trans_dist::ReadExReq 304189 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 304189 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1856624 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3648872 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 5505496 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59411328 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142453644 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 201864972 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 41913 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 3195062 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1.013063 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.113544 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 3153325 98.69% 98.69% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 41737 1.31% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 3195062 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 2424224500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1395179500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 1395050000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 2186860632 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 2186768132 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
---------- End Simulation Statistics ----------