diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt | 1044 |
1 files changed, 516 insertions, 528 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index bc2bfd41e..04e45bbeb 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -4,13 +4,13 @@ sim_seconds 1.941276 # Nu sim_ticks 1941275996000 # Number of ticks simulated final_tick 1941275996000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 450874 # Simulator instruction rate (inst/s) -host_op_rate 450874 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15578984909 # Simulator tick rate (ticks/s) -host_mem_usage 311244 # Number of bytes of host memory used -host_seconds 124.61 # Real time elapsed on the host -sim_insts 56182743 # Number of instructions simulated -sim_ops 56182743 # Number of ops (including micro ops) simulated +host_inst_rate 1255554 # Simulator instruction rate (inst/s) +host_op_rate 1255553 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43383023327 # Simulator tick rate (ticks/s) +host_mem_usage 332188 # Number of bytes of host memory used +host_seconds 44.75 # Real time elapsed on the host +sim_insts 56182685 # Number of instructions simulated +sim_ops 56182685 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 844800 # Number of bytes read from this memory @@ -51,7 +51,7 @@ system.physmem.bytesReadSys 25702272 # To system.physmem.bytesWrittenSys 7410752 # Total written bytes from the system interface side system.physmem.servicedByWrQ 117 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 303100 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 25225 # Per bank write bursts system.physmem.perBankRdBursts::1 25628 # Per bank write bursts system.physmem.perBankRdBursts::2 25541 # Per bank write bursts @@ -85,7 +85,7 @@ system.physmem.perBankWrBursts::13 7822 # Pe system.physmem.perBankWrBursts::14 7863 # Per bank write bursts system.physmem.perBankWrBursts::15 7687 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 16 # Number of times write queue was full causing retry +system.physmem.numWrRetry 8 # Number of times write queue was full causing retry system.physmem.totGap 1941264122500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) @@ -148,123 +148,112 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5822 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7624 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6622 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5554 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 51 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64945 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 509.715729 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 310.174215 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 406.042967 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15358 23.65% 23.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11454 17.64% 41.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4958 7.63% 48.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3153 4.85% 53.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2453 3.78% 57.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4205 6.47% 64.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1430 2.20% 66.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2063 3.18% 69.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19871 30.60% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64945 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5113 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 78.517700 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2951.127633 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5110 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6714 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5907 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6941 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 34 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64912 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 509.974858 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 310.431433 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 406.117715 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15298 23.57% 23.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11509 17.73% 41.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4967 7.65% 48.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3096 4.77% 53.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2467 3.80% 57.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4201 6.47% 63.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1427 2.20% 66.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2061 3.18% 69.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19886 30.64% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64912 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5093 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 78.826036 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2956.913485 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5090 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5113 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5113 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.640524 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.158069 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.669047 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4483 87.68% 87.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 26 0.51% 88.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 11 0.22% 88.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 181 3.54% 91.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 5 0.10% 92.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 20 0.39% 92.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 39 0.76% 93.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 6 0.12% 93.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 12 0.23% 93.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 31 0.61% 94.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.06% 94.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 3 0.06% 94.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 9 0.18% 94.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 1 0.02% 94.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 22 0.43% 94.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 27 0.53% 95.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 2 0.04% 95.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 26 0.51% 95.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.06% 96.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 161 3.15% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 5 0.10% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.04% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 3 0.06% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.02% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 4 0.08% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 4 0.08% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 11 0.22% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 5 0.10% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5113 # Writes before turning the bus around for reads -system.physmem.totQLat 2718840250 # Total ticks spent queuing -system.physmem.totMemAccLat 10246609000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.rdPerTurnAround::total 5093 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5093 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.729433 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.333640 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.082746 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4499 88.34% 88.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 29 0.57% 88.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 20 0.39% 89.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 41 0.81% 90.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 209 4.10% 94.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 11 0.22% 94.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 11 0.22% 94.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 30 0.59% 95.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 184 3.61% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 6 0.12% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 5 0.10% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 4 0.08% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 1 0.02% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 8 0.16% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 5 0.10% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 1 0.02% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 4 0.08% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 5 0.10% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 5 0.10% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 1 0.02% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 2 0.04% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 7 0.14% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 4 0.08% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5093 # Writes before turning the bus around for reads +system.physmem.totQLat 2720413750 # Total ticks spent queuing +system.physmem.totMemAccLat 10248182500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2007405000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6772.03 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6775.95 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25522.03 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25525.95 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.24 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.82 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.24 # Average system read bandwidth in MiByte/s @@ -274,55 +263,55 @@ system.physmem.busUtil 0.13 # Da system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.09 # Average write queue length when enqueuing -system.physmem.readRowHits 358828 # Number of row buffer hits during reads -system.physmem.writeRowHits 93469 # Number of row buffer hits during writes +system.physmem.avgWrQLen 22.10 # Average write queue length when enqueuing +system.physmem.readRowHits 358846 # Number of row buffer hits during reads +system.physmem.writeRowHits 93484 # Number of row buffer hits during writes system.physmem.readRowHitRate 89.38 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.72 # Row buffer hit rate for writes +system.physmem.writeRowHitRate 80.73 # Row buffer hit rate for writes system.physmem.avgGap 3752025.30 # Average gap between requests system.physmem.pageHitRate 87.44 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 240377760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 131158500 # Energy for precharge commands per rank (pJ) +system.physmem_0.actEnergy 240264360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 131096625 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 1565912400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 373358160 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 126794687760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 71534855790 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1102015656000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1302656006370 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.030850 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1833021874000 # Time in different power states +system.physmem_0.actBackEnergy 71567841690 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1101986721000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1302659881995 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.032847 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1832974788000 # Time in different power states system.physmem_0.memoryStateTime::REF 64823460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 43430562250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 43477648250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 250606440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 136739625 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 250470360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 136665375 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1565639400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 376773120 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 126794687760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 72705843270 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1100988474000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1302818763615 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.114691 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1831312114000 # Time in different power states +system.physmem_1.actBackEnergy 72629101890 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1101055791000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1302809128905 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.109728 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1831423384000 # Time in different power states system.physmem_1.memoryStateTime::REF 64823460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 45140322250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 45029052250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9064657 # DTB read hits +system.cpu.dtb.read_hits 9064642 # DTB read hits system.cpu.dtb.read_misses 10324 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations system.cpu.dtb.read_accesses 728853 # DTB read accesses -system.cpu.dtb.write_hits 6356207 # DTB write hits +system.cpu.dtb.write_hits 6356200 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 15420864 # DTB hits +system.cpu.dtb.data_hits 15420842 # DTB hits system.cpu.dtb.data_misses 11466 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations system.cpu.dtb.data_accesses 1020784 # DTB accesses @@ -358,10 +347,10 @@ system.cpu.kern.ipl_good::21 131 0.09% 49.40% # nu system.cpu.kern.ipl_good::22 1935 1.30% 50.69% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73545 49.31% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 149156 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1860509805500 95.84% 95.84% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 94040000 0.00% 95.84% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 770515500 0.04% 95.88% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 79900901000 4.12% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1860509936500 95.84% 95.84% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 94066500 0.00% 95.84% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 770529000 0.04% 95.88% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 79900730000 4.12% 100.00% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::total 1941275262000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981752 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl @@ -426,32 +415,32 @@ system.cpu.kern.mode_switch_good::kernel 0.323121 # fr system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081184 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.391952 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 48611852500 2.50% 2.50% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5602941000 0.29% 2.79% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1887060466500 97.21% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::kernel 48613441500 2.50% 2.50% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5603081000 0.29% 2.79% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1887058737500 97.21% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed -system.cpu.committedInsts 56182743 # Number of instructions committed -system.cpu.committedOps 56182743 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52054633 # Number of integer alu accesses +system.cpu.committedInsts 56182685 # Number of instructions committed +system.cpu.committedOps 56182685 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52054580 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses -system.cpu.num_func_calls 1483394 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6468678 # number of instructions that are conditional controls -system.cpu.num_int_insts 52054633 # number of integer instructions +system.cpu.num_func_calls 1483390 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6468674 # number of instructions that are conditional controls +system.cpu.num_int_insts 52054580 # number of integer instructions system.cpu.num_fp_insts 324393 # number of float instructions -system.cpu.num_int_register_reads 71322499 # number of times the integer registers were read -system.cpu.num_int_register_writes 38520900 # number of times the integer registers were written +system.cpu.num_int_register_reads 71322431 # number of times the integer registers were read +system.cpu.num_int_register_writes 38520860 # number of times the integer registers were written system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written -system.cpu.num_mem_refs 15473474 # number of memory refs -system.cpu.num_load_insts 9101503 # Number of load instructions -system.cpu.num_store_insts 6371971 # Number of store instructions -system.cpu.num_idle_cycles 3583834697.998154 # Number of idle cycles -system.cpu.num_busy_cycles 298717294.001846 # Number of busy cycles -system.cpu.not_idle_fraction 0.076938 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.923062 # Percentage of idle cycles -system.cpu.Branches 8422724 # Number of branches fetched -system.cpu.op_class::No_OpClass 3200638 5.70% 5.70% # Class of executed instruction -system.cpu.op_class::IntAlu 36231019 64.47% 70.17% # Class of executed instruction +system.cpu.num_mem_refs 15473452 # number of memory refs +system.cpu.num_load_insts 9101488 # Number of load instructions +system.cpu.num_store_insts 6371964 # Number of store instructions +system.cpu.num_idle_cycles 3583831790.000154 # Number of idle cycles +system.cpu.num_busy_cycles 298720201.999846 # Number of busy cycles +system.cpu.not_idle_fraction 0.076939 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.923061 # Percentage of idle cycles +system.cpu.Branches 8422715 # Number of branches fetched +system.cpu.op_class::No_OpClass 3200634 5.70% 5.70% # Class of executed instruction +system.cpu.op_class::IntAlu 36230987 64.47% 70.17% # Class of executed instruction system.cpu.op_class::IntMult 61043 0.11% 70.28% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 70.28% # Class of executed instruction system.cpu.op_class::FloatAdd 38085 0.07% 70.35% # Class of executed instruction @@ -480,16 +469,16 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 70.35% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::MemRead 9328633 16.60% 86.95% # Class of executed instruction -system.cpu.op_class::MemWrite 6378052 11.35% 98.30% # Class of executed instruction +system.cpu.op_class::MemRead 9328618 16.60% 86.95% # Class of executed instruction +system.cpu.op_class::MemWrite 6378045 11.35% 98.30% # Class of executed instruction system.cpu.op_class::IprAccess 953470 1.70% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 56194576 # Class of executed instruction -system.cpu.dcache.tags.replacements 1390387 # number of replacements +system.cpu.op_class::total 56194518 # Class of executed instruction +system.cpu.dcache.tags.replacements 1390402 # number of replacements system.cpu.dcache.tags.tagsinuse 511.973391 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14048998 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1390899 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 10.100660 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 14048961 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1390914 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.100525 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 145150500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.973391 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999948 # Average percentage of cache occupancy @@ -499,72 +488,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 system.cpu.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63150492 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63150492 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7814415 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7814415 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5852271 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5852271 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183035 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183035 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 63150419 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63150419 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7814383 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7814383 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5852265 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5852265 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183036 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183036 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 199260 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 199260 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13666686 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13666686 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13666686 # number of overall hits -system.cpu.dcache.overall_hits::total 13666686 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1069342 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1069342 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304328 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304328 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17247 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17247 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1373670 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1373670 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1373670 # number of overall misses -system.cpu.dcache.overall_misses::total 1373670 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 44771016500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 44771016500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 17634519000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 17634519000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232810500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 232810500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 62405535500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 62405535500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 62405535500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 62405535500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 8883757 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 8883757 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6156599 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6156599 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 13666648 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13666648 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13666648 # number of overall hits +system.cpu.dcache.overall_hits::total 13666648 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1069359 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1069359 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304327 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304327 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17246 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17246 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1373686 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1373686 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1373686 # number of overall misses +system.cpu.dcache.overall_misses::total 1373686 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 44772641000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 44772641000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 17635172000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 17635172000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232797500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 232797500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 62407813000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 62407813000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 62407813000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 62407813000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8883742 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8883742 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6156592 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6156592 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200282 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 200282 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 199260 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 199260 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15040356 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15040356 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15040356 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15040356 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120370 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120370 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 15040334 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15040334 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15040334 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15040334 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120373 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120373 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049431 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.049431 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086114 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086114 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091332 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091332 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091332 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091332 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41867.818247 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41867.818247 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57945.765753 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 57945.765753 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13498.608454 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13498.608454 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45429.786994 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45429.786994 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45429.786994 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45429.786994 # average overall miss latency +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086109 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086109 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091333 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091333 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091333 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091333 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41868.671793 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41868.671793 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57948.101877 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 57948.101877 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13498.637365 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13498.637365 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45430.915799 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45430.915799 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45430.915799 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45430.915799 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -573,74 +562,74 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 834936 # number of writebacks -system.cpu.dcache.writebacks::total 834936 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069342 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069342 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304328 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304328 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17247 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17247 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1373670 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1373670 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1373670 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1373670 # number of overall MSHR misses +system.cpu.dcache.writebacks::writebacks 834944 # number of writebacks +system.cpu.dcache.writebacks::total 834944 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069359 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1069359 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304327 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304327 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17246 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17246 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1373686 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1373686 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1373686 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1373686 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9653 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 9653 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16583 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 16583 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43701674500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 43701674500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17330191000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 17330191000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 215563500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 215563500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61031865500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 61031865500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61031865500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 61031865500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43703282000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 43703282000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17330845000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 17330845000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 215551500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 215551500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61034127000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 61034127000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61034127000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 61034127000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1526978500 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1526978500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2172467000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2172467000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3699445500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3699445500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120370 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120370 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2172486500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2172486500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3699465000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3699465000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120373 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120373 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049431 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049431 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086114 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086114 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091332 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091332 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091332 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091332 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40867.818247 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40867.818247 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56945.765753 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56945.765753 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12498.608454 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12498.608454 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44429.786994 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 44429.786994 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44429.786994 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44429.786994 # average overall mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086109 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086109 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091333 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091333 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091333 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091333 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40868.671793 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40868.671793 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56948.101877 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56948.101877 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12498.637365 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12498.637365 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44430.915799 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 44430.915799 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44430.915799 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44430.915799 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220343.217893 # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220343.217893 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 225056.148348 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 225056.148348 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 223086.624857 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 223086.624857 # average overall mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 225058.168445 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 225058.168445 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 223087.800760 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 223087.800760 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 928920 # number of replacements -system.cpu.icache.tags.tagsinuse 506.355618 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 55264986 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 929431 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 59.461096 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 928931 # number of replacements +system.cpu.icache.tags.tagsinuse 506.355616 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 55264917 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 929442 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 59.460318 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 58592056500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 506.355618 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 506.355616 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.988976 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.988976 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id @@ -649,44 +638,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 1 system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 57124168 # Number of tag accesses -system.cpu.icache.tags.data_accesses 57124168 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 55264986 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55264986 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55264986 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55264986 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55264986 # number of overall hits -system.cpu.icache.overall_hits::total 55264986 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 929591 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 929591 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 929591 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 929591 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 929591 # number of overall misses -system.cpu.icache.overall_misses::total 929591 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13686841500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13686841500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13686841500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13686841500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13686841500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13686841500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56194577 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56194577 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56194577 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56194577 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 56194577 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56194577 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016542 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016542 # 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Number of tag accesses +system.cpu.icache.tags.data_accesses 57124121 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 55264917 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55264917 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55264917 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55264917 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55264917 # number of overall hits +system.cpu.icache.overall_hits::total 55264917 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 929602 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 929602 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 929602 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 929602 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 929602 # number of overall misses +system.cpu.icache.overall_misses::total 929602 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13686117000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13686117000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13686117000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13686117000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13686117000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13686117000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 56194519 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56194519 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 56194519 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 56194519 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 56194519 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 56194519 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016543 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016543 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016543 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016543 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016543 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016543 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14722.555459 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14722.555459 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14722.555459 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14722.555459 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14722.555459 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14722.555459 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -695,44 +684,44 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 928920 # number of writebacks -system.cpu.icache.writebacks::total 928920 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929591 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 929591 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 929591 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 929591 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 929591 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 929591 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12757250500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12757250500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12757250500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12757250500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12757250500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12757250500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016542 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.016542 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.016542 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13723.509049 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13723.509049 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13723.509049 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13723.509049 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13723.509049 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13723.509049 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 928931 # number of writebacks +system.cpu.icache.writebacks::total 928931 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929602 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 929602 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 929602 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 929602 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 929602 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 929602 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12756515000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12756515000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12756515000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12756515000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12756515000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12756515000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016543 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.016543 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.016543 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13722.555459 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13722.555459 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13722.555459 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13722.555459 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13722.555459 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13722.555459 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 336393 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65234.360010 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3930350 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 65234.360001 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3930403 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 401556 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 9.787800 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 9.787932 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 10619817000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 55072.826279 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4686.115262 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 5475.418469 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 55072.820493 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4686.121272 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 5475.418237 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.840345 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.071504 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.071505 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.083548 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.995397 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id @@ -742,26 +731,26 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5220 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3221 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55822 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 37812565 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 37812565 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 834936 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 834936 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 928699 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 928699 # number of WritebackClean hits +system.cpu.l2cache.tags.tag_accesses 37812972 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 37812972 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 834944 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 834944 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 928709 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 928709 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187491 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187491 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 916371 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 916371 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 814618 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 814618 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 916371 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1002109 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1918480 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 916371 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1002109 # number of overall hits -system.cpu.l2cache.overall_hits::total 1918480 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 187490 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187490 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 916382 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 916382 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 814634 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 814634 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 916382 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1002124 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1918506 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 916382 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1002124 # number of overall hits +system.cpu.l2cache.overall_hits::total 1918506 # number of overall hits system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 116820 # number of ReadExReq misses @@ -776,66 +765,66 @@ system.cpu.l2cache.demand_misses::total 401991 # nu system.cpu.l2cache.overall_misses::cpu.inst 13200 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 388791 # number of overall misses system.cpu.l2cache.overall_misses::total 401991 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 320500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 320500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14900653000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 14900653000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1727668500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 1727668500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33719834000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 33719834000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1727668500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 48620487000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 50348155500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1727668500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 48620487000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 50348155500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 834936 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 834936 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 928699 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 928699 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 315000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 315000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14901349500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 14901349500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1726796000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 1726796000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33721236500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 33721236500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1726796000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 48622586000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 50349382000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1726796000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 48622586000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 50349382000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 834944 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 834944 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 928709 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 928709 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304311 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304311 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 929571 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 929571 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1086589 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1086589 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 929571 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1390900 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2320471 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 929571 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1390900 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2320471 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304310 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304310 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 929582 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 929582 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1086605 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1086605 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 929582 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1390915 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2320497 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 929582 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1390915 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2320497 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383884 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383884 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383885 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383885 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014200 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014200 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.250298 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.250298 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.250294 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.250294 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014200 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.279525 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.173237 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.279522 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.173235 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014200 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.279525 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.173237 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 24653.846154 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 24653.846154 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127552.242767 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127552.242767 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130883.977273 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130883.977273 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123983.196738 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123983.196738 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130883.977273 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 125055.587707 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 125246.971947 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130883.977273 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 125055.587707 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 125246.971947 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.279522 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.173235 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 24230.769231 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 24230.769231 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127558.204931 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127558.204931 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130817.878788 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130817.878788 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123988.353538 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123988.353538 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130817.878788 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 125060.986494 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 125250.023010 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130817.878788 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 125060.986494 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 125250.023010 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -866,106 +855,106 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9653 system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9653 # number of WriteReq MSHR uncacheable system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16583 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16583 # number of overall MSHR uncacheable misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 924500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 924500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13732453000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13732453000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1595668500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1595668500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31000124000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31000124000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1595668500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44732577000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 46328245500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1595668500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44732577000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 46328245500 # number of overall MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 893500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 893500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13733149500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13733149500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1594796000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1594796000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31001526500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31001526500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1594796000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44734676000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 46329472000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1594796000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44734676000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 46329472000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1440322500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1440322500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2061377000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2061377000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3501699500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3501699500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2061396500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2061396500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3501719000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3501719000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383884 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383884 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383885 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383885 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014200 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014200 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250298 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250298 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250294 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250294 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014200 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279525 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173237 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279522 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.173235 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014200 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279525 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173237 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71115.384615 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71115.384615 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117552.242767 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117552.242767 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120883.977273 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120883.977273 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113983.196738 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113983.196738 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120883.977273 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 115055.587707 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115246.971947 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120883.977273 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 115055.587707 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115246.971947 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279522 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.173235 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68730.769231 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68730.769231 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117558.204931 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117558.204931 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120817.878788 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120817.878788 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113988.353538 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113988.353538 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120817.878788 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 115060.986494 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115250.023010 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120817.878788 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 115060.986494 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115250.023010 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 207838.744589 # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 207838.744589 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213547.808971 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213547.808971 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211162.003256 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211162.003256 # average overall mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213549.829069 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213549.829069 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211163.179159 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211163.179159 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 4639815 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319473 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1501 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 4639867 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319499 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1502 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 1136 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1136 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2023267 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2023294 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9653 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9653 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 950745 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 928699 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 816471 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 928931 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 817743 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304311 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304311 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 929591 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1086762 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304310 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304310 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 929602 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1086778 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2787861 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4204279 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6992140 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118929280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142508140 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 261437420 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 419996 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2756910 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2788115 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4205589 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6993704 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118944832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142509612 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 261454444 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 419988 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2756928 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.001015 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.031841 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.031847 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2754112 99.90% 99.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2798 0.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2754129 99.90% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2799 0.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2756910 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4096881500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2756928 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4096926500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 293383 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1394386500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1394403000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2098115000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2098137500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1019,15 +1008,15 @@ system.iobus.reqLayer6.occupancy 10000 # La system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 174000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 15817000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 15817500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 1891500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6032000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6038000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 215014002 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 215662167 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23513000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) @@ -1038,7 +1027,7 @@ system.iocache.tags.tagsinuse 1.339384 # Cy system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1774106672000 # Cycle when the warmup percentage was hit. +system.iocache.tags.warmup_cycle 1774106669000 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::tsunami.ide 1.339384 # Average occupied blocks per requestor system.iocache.tags.occ_percent::tsunami.ide 0.083712 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.083712 # Average percentage of cache occupancy @@ -1057,8 +1046,8 @@ system.iocache.overall_misses::tsunami.ide 173 # system.iocache.overall_misses::total 173 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21742883 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21742883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5428926119 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5428926119 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5244713284 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5244713284 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::tsunami.ide 21742883 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 21742883 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::tsunami.ide 21742883 # number of overall miss cycles @@ -1081,17 +1070,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125681.404624 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 125681.404624 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130653.786075 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130653.786075 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126220.477570 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 126220.477570 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 125681.404624 # average overall miss latency system.iocache.demand_avg_miss_latency::total 125681.404624 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 125681.404624 # average overall miss latency system.iocache.overall_avg_miss_latency::total 125681.404624 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 32 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 29 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 14.500000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1107,8 +1096,8 @@ system.iocache.overall_mshr_misses::tsunami.ide 173 system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13092883 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 13092883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3351326119 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3351326119 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165314984 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3165314984 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::tsunami.ide 13092883 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 13092883 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::tsunami.ide 13092883 # number of overall MSHR miss cycles @@ -1123,8 +1112,8 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75681.404624 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 75681.404624 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80653.786075 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80653.786075 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76177.199268 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76177.199268 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75681.404624 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 75681.404624 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75681.404624 # average overall mshr miss latency @@ -1135,20 +1124,19 @@ system.membus.trans_dist::ReadResp 292274 # Tr system.membus.trans_dist::WriteReq 9653 # Transaction distribution system.membus.trans_dist::WriteResp 9653 # Transaction distribution system.membus.trans_dist::WritebackDirty 115793 # Transaction distribution -system.membus.trans_dist::CleanEvict 261400 # Transaction distribution +system.membus.trans_dist::CleanEvict 261560 # Transaction distribution system.membus.trans_dist::UpgradeReq 150 # Transaction distribution -system.membus.trans_dist::UpgradeResp 150 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2 # Transaction distribution system.membus.trans_dist::ReadExReq 116683 # Transaction distribution system.membus.trans_dist::ReadExResp 116683 # Transaction distribution system.membus.trans_dist::ReadSharedReq 285344 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33166 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139403 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172569 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1297386 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139255 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172421 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1255846 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44588 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30455296 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30499884 # Cumulative packet size per connected master and slave (bytes) @@ -1156,24 +1144,24 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 33157612 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 431 # Total snoops (count) -system.membus.snoop_fanout::samples 837681 # Request fanout histogram +system.membus.snoop_fanout::samples 837673 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 837681 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 837673 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 837681 # Request fanout histogram -system.membus.reqLayer0.occupancy 30116000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 837673 # Request fanout histogram +system.membus.reqLayer0.occupancy 30122500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1287207146 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1287200967 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2143289352 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2143013000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 69814679 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 887117 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA |