diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha/linux')
4 files changed, 2294 insertions, 2290 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index a85398f56..59ee1a74c 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -4,52 +4,52 @@ sim_seconds 1.869358 # Nu sim_ticks 1869358498000 # Number of ticks simulated final_tick 1869358498000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2452265 # Simulator instruction rate (inst/s) -host_op_rate 2452264 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 70524991939 # Simulator tick rate (ticks/s) -host_mem_usage 374768 # Number of bytes of host memory used -host_seconds 26.51 # Real time elapsed on the host +host_inst_rate 2397277 # Simulator instruction rate (inst/s) +host_op_rate 2397276 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68943602925 # Simulator tick rate (ticks/s) +host_mem_usage 377676 # Number of bytes of host memory used +host_seconds 27.11 # Real time elapsed on the host sim_insts 65000470 # Number of instructions simulated sim_ops 65000470 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 763584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 763776 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 66536960 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 106240 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 766208 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 68173952 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 763584 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 68174144 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 763776 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 106240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 869824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 870016 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 7835712 # Number of bytes written to this memory system.physmem.bytes_written::total 7835712 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11931 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 11934 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 1039640 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 1660 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 11972 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1065218 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1065221 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 122433 # Number of write requests responded to by this memory system.physmem.num_writes::total 122433 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 408474 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 408577 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.data 35593472 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 56832 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.data 409878 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 514 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36469170 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 408474 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 36469272 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 408577 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 56832 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 465306 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 465409 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 4191658 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 4191658 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 4191658 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 408474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 408577 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.data 35593472 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 56832 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 409878 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40660828 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 40660931 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses @@ -737,20 +737,20 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 999684 # number of replacements +system.l2c.tags.replacements 999687 # number of replacements system.l2c.tags.tagsinuse 65320.982503 # Cycle average of tags in use -system.l2c.tags.total_refs 4588619 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1064734 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.309639 # Average number of references to valid blocks. +system.l2c.tags.total_refs 4249853 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1064737 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.991458 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55911.037805 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4939.570238 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4176.759225 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 55911.121944 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4939.470586 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4176.774738 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.inst 179.034361 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.data 114.580874 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.853135 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.075372 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.063732 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::writebacks 0.853136 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.075370 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.063733 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.inst 0.002732 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.001748 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.996719 # Average percentage of cache occupancy @@ -761,8 +761,8 @@ system.l2c.tags.age_task_id_blocks_1024::2 6123 # system.l2c.tags.age_task_id_blocks_1024::3 5943 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::4 48945 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.992584 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 49101323 # Number of tag accesses -system.l2c.tags.data_accesses 49101323 # Number of data accesses +system.l2c.tags.tag_accesses 46365678 # Number of tag accesses +system.l2c.tags.data_accesses 46365678 # Number of data accesses system.l2c.Writeback_hits::writebacks 777520 # number of Writeback hits system.l2c.Writeback_hits::total 777520 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 116 # number of UpgradeReq hits @@ -774,22 +774,22 @@ system.l2c.SCUpgradeReq_hits::total 50 # nu system.l2c.ReadExReq_hits::cpu0.data 111476 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu1.data 56603 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 168079 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 606993 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 606990 # number of ReadCleanReq hits system.l2c.ReadCleanReq_hits::cpu1.inst 379552 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 986545 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 986542 # number of ReadCleanReq hits system.l2c.ReadSharedReq_hits::cpu0.data 626685 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.data 129013 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::total 755698 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 606993 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 606990 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 738161 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 379552 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 185616 # number of demand (read+write) hits -system.l2c.demand_hits::total 1910322 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 606993 # number of overall hits +system.l2c.demand_hits::total 1910319 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 606990 # number of overall hits system.l2c.overall_hits::cpu0.data 738161 # number of overall hits system.l2c.overall_hits::cpu1.inst 379552 # number of overall hits system.l2c.overall_hits::cpu1.data 185616 # number of overall hits -system.l2c.overall_hits::total 1910322 # number of overall hits +system.l2c.overall_hits::total 1910319 # number of overall hits system.l2c.UpgradeReq_misses::cpu0.data 3006 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 2174 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 5180 # number of UpgradeReq misses @@ -799,22 +799,22 @@ system.l2c.SCUpgradeReq_misses::total 2285 # nu system.l2c.ReadExReq_misses::cpu0.data 113873 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 11069 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 124942 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 11931 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 11934 # number of ReadCleanReq misses system.l2c.ReadCleanReq_misses::cpu1.inst 1660 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 13591 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 13594 # number of ReadCleanReq misses system.l2c.ReadSharedReq_misses::cpu0.data 926611 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.data 1033 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::total 927644 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.inst 11931 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 11934 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 1040484 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 1660 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 12102 # number of demand (read+write) misses -system.l2c.demand_misses::total 1066177 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 11931 # number of overall misses +system.l2c.demand_misses::total 1066180 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 11934 # number of overall misses system.l2c.overall_misses::cpu0.data 1040484 # number of overall misses system.l2c.overall_misses::cpu1.inst 1660 # number of overall misses system.l2c.overall_misses::cpu1.data 12102 # number of overall misses -system.l2c.overall_misses::total 1066177 # number of overall misses +system.l2c.overall_misses::total 1066180 # number of overall misses system.l2c.Writeback_accesses::writebacks 777520 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 777520 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 3122 # number of UpgradeReq accesses(hits+misses) @@ -851,22 +851,22 @@ system.l2c.SCUpgradeReq_miss_rate::total 0.978587 # mi system.l2c.ReadExReq_miss_rate::cpu0.data 0.505318 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.163568 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 0.426393 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.019277 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.019282 # miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004355 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.013589 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.013592 # miss rate for ReadCleanReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596545 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.007943 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::total 0.551073 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.019277 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.019282 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.584987 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.004355 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.061208 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.358198 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.019277 # miss rate for overall accesses +system.l2c.demand_miss_rate::total 0.358199 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.019282 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.584987 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.004355 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.061208 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.358198 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.358199 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -879,49 +879,55 @@ system.l2c.writebacks::writebacks 80913 # nu system.l2c.writebacks::total 80913 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 7449 # Transaction distribution -system.membus.trans_dist::ReadResp 948863 # Transaction distribution +system.membus.trans_dist::ReadResp 948866 # Transaction distribution system.membus.trans_dist::WriteReq 14588 # Transaction distribution system.membus.trans_dist::WriteResp 14588 # Transaction distribution system.membus.trans_dist::Writeback 122433 # Transaction distribution -system.membus.trans_dist::CleanEvict 922490 # Transaction distribution +system.membus.trans_dist::CleanEvict 917961 # Transaction distribution system.membus.trans_dist::UpgradeReq 19616 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 14180 # Transaction distribution system.membus.trans_dist::UpgradeResp 8160 # Transaction distribution system.membus.trans_dist::ReadExReq 126472 # Transaction distribution system.membus.trans_dist::ReadExResp 124247 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 941414 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 941417 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 44074 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3178369 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3222443 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125161 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 125161 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3347604 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3174012 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3218086 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124995 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124995 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3343081 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 86162 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73369280 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 73455442 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73369472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 73455634 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2668736 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2668736 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 76124178 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 76124370 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2210194 # Request fanout histogram +system.membus.snoop_fanout::samples 2205834 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2210194 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2205834 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2210194 # Request fanout histogram +system.membus.snoop_fanout::total 2205834 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 6035921 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 3018741 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 376832 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1611 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1521 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 90 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 7449 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 2732182 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 14588 # Transaction distribution system.toL2Bus.trans_dist::Writeback 777520 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2204578 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1862622 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 19614 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 14230 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 33844 # Transaction distribution @@ -929,30 +935,30 @@ system.toL2Bus.trans_dist::ReadExReq 295246 # Tr system.toL2Bus.trans_dist::ReadExResp 295246 # Transaction distribution system.toL2Bus.trans_dist::ReadCleanReq 1000157 # Transaction distribution system.toL2Bus.trans_dist::ReadSharedReq 1724576 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1856188 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5450155 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1143095 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 684380 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 9133818 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1705094 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5410979 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1014431 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 661358 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8791862 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39612480 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155758075 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24397568 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23357975 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 243126098 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 41895 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 6099689 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.006841 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.082430 # Request fanout histogram +system.toL2Bus.snoops 1083281 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 7141075 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.106201 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.308342 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 6057958 99.32% 99.32% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 41731 0.68% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 6383226 89.39% 89.39% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 757309 10.60% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 538 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 6099689 # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 7141075 # Request fanout histogram system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 60a4f6e98..34e6d6348 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.829332 # Nu sim_ticks 1829332273500 # Number of ticks simulated final_tick 1829332273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2495393 # Simulator instruction rate (inst/s) -host_op_rate 2495392 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 76033049021 # Simulator tick rate (ticks/s) -host_mem_usage 371696 # Number of bytes of host memory used -host_seconds 24.06 # Real time elapsed on the host +host_inst_rate 2390951 # Simulator instruction rate (inst/s) +host_op_rate 2390950 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 72850763127 # Simulator tick rate (ticks/s) +host_mem_usage 374092 # Number of bytes of host memory used +host_seconds 25.11 # Real time elapsed on the host sim_insts 60038341 # Number of instructions simulated sim_ops 60038341 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -338,9 +338,9 @@ system.cpu.icache.cache_copies 0 # nu system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 992219 # number of replacements system.cpu.l2cache.tags.tagsinuse 65424.374112 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4561879 # Total number of references to valid blocks. +system.cpu.l2cache.tags.total_refs 4560066 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1057382 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.314315 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.312600 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 56252.896873 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 4923.444270 # Average occupied blocks per requestor @@ -356,8 +356,8 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4024 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3053 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54045 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 48768396 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 48768396 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 48753828 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 48753828 # Number of data accesses system.cpu.l2cache.Writeback_hits::writebacks 833493 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 833493 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits @@ -429,36 +429,42 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 74334 # number of writebacks system.cpu.l2cache.writebacks::total 74334 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 5925822 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2962455 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1834 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1449 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1449 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 7184 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 2666303 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 833493 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2128840 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2127019 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 304354 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 304354 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 920232 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 1738887 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2760069 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6163286 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8923355 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2759817 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6161717 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8921534 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58894848 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184157102 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 243051950 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 41883 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5984570 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.006972 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.083208 # Request fanout histogram +system.cpu.toL2Bus.snoops 1075788 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 7018475 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000744 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.027269 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5942844 99.30% 99.30% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41726 0.70% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 7013252 99.93% 99.93% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5223 0.07% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5984570 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 7018475 # Request fanout histogram system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -561,7 +567,7 @@ system.membus.trans_dist::ReadResp 948374 # Tr system.membus.trans_dist::WriteReq 9838 # Transaction distribution system.membus.trans_dist::WriteResp 9838 # Transaction distribution system.membus.trans_dist::Writeback 115846 # Transaction distribution -system.membus.trans_dist::CleanEvict 918371 # Transaction distribution +system.membus.trans_dist::CleanEvict 917156 # Transaction distribution system.membus.trans_dist::UpgradeReq 132 # Transaction distribution system.membus.trans_dist::UpgradeResp 132 # Transaction distribution system.membus.trans_dist::ReadExReq 116946 # Transaction distribution @@ -570,11 +576,11 @@ system.membus.trans_dist::ReadSharedReq 941190 # Tr system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3108719 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3142763 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125138 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 125138 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3267901 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3107665 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3141709 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124977 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124977 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3266686 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72466944 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72513070 # Cumulative packet size per connected master and slave (bytes) @@ -582,17 +588,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2667904 system.membus.pkt_size_system.iocache.mem_side::total 2667904 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 75180974 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2151059 # Request fanout histogram +system.membus.snoop_fanout::samples 2150005 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2151059 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2150005 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2151059 # Request fanout histogram +system.membus.snoop_fanout::total 2150005 # Request fanout histogram system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 67605a567..69fe46592 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,118 +1,118 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.962608 # Number of seconds simulated -sim_ticks 1962608482500 # Number of ticks simulated -final_tick 1962608482500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.982585 # Number of seconds simulated +sim_ticks 1982585357000 # Number of ticks simulated +final_tick 1982585357000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1019388 # Simulator instruction rate (inst/s) -host_op_rate 1019388 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32859851956 # Simulator tick rate (ticks/s) -host_mem_usage 375280 # Number of bytes of host memory used -host_seconds 59.73 # Real time elapsed on the host -sim_insts 60884587 # Number of instructions simulated -sim_ops 60884587 # Number of ops (including micro ops) simulated +host_inst_rate 1043358 # Simulator instruction rate (inst/s) +host_op_rate 1043358 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 33918612914 # Simulator tick rate (ticks/s) +host_mem_usage 377952 # Number of bytes of host memory used +host_seconds 58.45 # Real time elapsed on the host +sim_insts 60985541 # Number of instructions simulated +sim_ops 60985541 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 831936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24730240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 31616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 435904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 804544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24689088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 59456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 522432 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26030656 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 831936 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 31616 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 863552 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7705152 # Number of bytes written to this memory -system.physmem.bytes_written::total 7705152 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12999 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 386410 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 494 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6811 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26076480 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 804544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 59456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 864000 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7738240 # Number of bytes written to this memory +system.physmem.bytes_written::total 7738240 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12571 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 385767 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 929 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8163 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 406729 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120393 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120393 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 423893 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12600700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 16109 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 222104 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13263295 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 423893 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 16109 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 440002 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3925975 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3925975 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3925975 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 423893 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12600700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 16109 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 222104 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 489 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17189270 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 406729 # Number of read requests accepted -system.physmem.writeReqs 120393 # Number of write requests accepted -system.physmem.readBursts 406729 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 120393 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26023296 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue -system.physmem.bytesWritten 7703744 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26030656 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7705152 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 407445 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120910 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120910 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 405805 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12452976 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 29989 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 263510 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 484 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13152765 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 405805 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 29989 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 435795 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3903106 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3903106 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3903106 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 405805 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12452976 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 29989 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 263510 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17055871 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 407445 # Number of read requests accepted +system.physmem.writeReqs 120910 # Number of write requests accepted +system.physmem.readBursts 407445 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 120910 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26068672 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7808 # Total number of bytes read from write queue +system.physmem.bytesWritten 7736640 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26076480 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7738240 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 122 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 48492 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25025 # Per bank write bursts -system.physmem.perBankRdBursts::1 25421 # Per bank write bursts -system.physmem.perBankRdBursts::2 25447 # Per bank write bursts -system.physmem.perBankRdBursts::3 24899 # Per bank write bursts -system.physmem.perBankRdBursts::4 25181 # Per bank write bursts -system.physmem.perBankRdBursts::5 25235 # Per bank write bursts -system.physmem.perBankRdBursts::6 25799 # Per bank write bursts -system.physmem.perBankRdBursts::7 25539 # Per bank write bursts -system.physmem.perBankRdBursts::8 25681 # Per bank write bursts -system.physmem.perBankRdBursts::9 25348 # Per bank write bursts -system.physmem.perBankRdBursts::10 25259 # Per bank write bursts -system.physmem.perBankRdBursts::11 25592 # Per bank write bursts -system.physmem.perBankRdBursts::12 25653 # Per bank write bursts -system.physmem.perBankRdBursts::13 25554 # Per bank write bursts -system.physmem.perBankRdBursts::14 25887 # Per bank write bursts -system.physmem.perBankRdBursts::15 25094 # Per bank write bursts -system.physmem.perBankWrBursts::0 7701 # Per bank write bursts -system.physmem.perBankWrBursts::1 7641 # Per bank write bursts -system.physmem.perBankWrBursts::2 7454 # Per bank write bursts -system.physmem.perBankWrBursts::3 6926 # Per bank write bursts -system.physmem.perBankWrBursts::4 7165 # Per bank write bursts -system.physmem.perBankWrBursts::5 7117 # Per bank write bursts -system.physmem.perBankWrBursts::6 7626 # Per bank write bursts -system.physmem.perBankWrBursts::7 7252 # Per bank write bursts -system.physmem.perBankWrBursts::8 7527 # Per bank write bursts -system.physmem.perBankWrBursts::9 7238 # Per bank write bursts -system.physmem.perBankWrBursts::10 7225 # Per bank write bursts -system.physmem.perBankWrBursts::11 7418 # Per bank write bursts -system.physmem.perBankWrBursts::12 7843 # Per bank write bursts -system.physmem.perBankWrBursts::13 8207 # Per bank write bursts -system.physmem.perBankWrBursts::14 8447 # Per bank write bursts -system.physmem.perBankWrBursts::15 7584 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 48696 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25232 # Per bank write bursts +system.physmem.perBankRdBursts::1 25377 # Per bank write bursts +system.physmem.perBankRdBursts::2 25433 # Per bank write bursts +system.physmem.perBankRdBursts::3 24853 # Per bank write bursts +system.physmem.perBankRdBursts::4 25156 # Per bank write bursts +system.physmem.perBankRdBursts::5 25421 # Per bank write bursts +system.physmem.perBankRdBursts::6 25501 # Per bank write bursts +system.physmem.perBankRdBursts::7 25341 # Per bank write bursts +system.physmem.perBankRdBursts::8 25248 # Per bank write bursts +system.physmem.perBankRdBursts::9 25578 # Per bank write bursts +system.physmem.perBankRdBursts::10 25745 # Per bank write bursts +system.physmem.perBankRdBursts::11 25922 # Per bank write bursts +system.physmem.perBankRdBursts::12 25991 # Per bank write bursts +system.physmem.perBankRdBursts::13 25558 # Per bank write bursts +system.physmem.perBankRdBursts::14 25312 # Per bank write bursts +system.physmem.perBankRdBursts::15 25655 # Per bank write bursts +system.physmem.perBankWrBursts::0 7850 # Per bank write bursts +system.physmem.perBankWrBursts::1 7774 # Per bank write bursts +system.physmem.perBankWrBursts::2 7467 # Per bank write bursts +system.physmem.perBankWrBursts::3 6887 # Per bank write bursts +system.physmem.perBankWrBursts::4 7102 # Per bank write bursts +system.physmem.perBankWrBursts::5 7345 # Per bank write bursts +system.physmem.perBankWrBursts::6 7434 # Per bank write bursts +system.physmem.perBankWrBursts::7 7145 # Per bank write bursts +system.physmem.perBankWrBursts::8 7156 # Per bank write bursts +system.physmem.perBankWrBursts::9 7306 # Per bank write bursts +system.physmem.perBankWrBursts::10 7741 # Per bank write bursts +system.physmem.perBankWrBursts::11 8153 # Per bank write bursts +system.physmem.perBankWrBursts::12 8257 # Per bank write bursts +system.physmem.perBankWrBursts::13 7909 # Per bank write bursts +system.physmem.perBankWrBursts::14 7539 # Per bank write bursts +system.physmem.perBankWrBursts::15 7820 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 20 # Number of times write queue was full causing retry -system.physmem.totGap 1962561950500 # Total gap between requests +system.physmem.numWrRetry 21 # Number of times write queue was full causing retry +system.physmem.totGap 1982577992500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 406729 # Read request sizes (log2) +system.physmem.readPktSize::6 407445 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 120393 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 406538 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 63 # What read queue length does an incoming req see +system.physmem.writePktSize::6 120910 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 407244 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see @@ -158,181 +158,177 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6416 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6086 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8835 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7633 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6911 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5875 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 58 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 67016 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 503.268473 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 299.027850 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 415.161234 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16754 25.00% 25.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 12205 18.21% 43.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5432 8.11% 51.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3034 4.53% 55.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2418 3.61% 59.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1895 2.83% 62.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1494 2.23% 64.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1474 2.20% 66.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22310 33.29% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 67016 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5361 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 75.845178 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2883.640505 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5358 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5781 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6708 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7869 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7617 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5590 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 70 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 67564 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 500.345036 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 302.441164 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 405.330516 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16348 24.20% 24.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 12278 18.17% 42.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5298 7.84% 50.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3150 4.66% 54.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2433 3.60% 58.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4298 6.36% 64.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1531 2.27% 67.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2195 3.25% 70.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20033 29.65% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 67564 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5409 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 75.303198 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2854.593157 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5406 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5361 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5361 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.453087 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.909523 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 23.339442 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4763 88.85% 88.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 210 3.92% 92.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 83 1.55% 94.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 15 0.28% 94.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 3 0.06% 94.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 2 0.04% 94.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 8 0.15% 94.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 9 0.17% 95.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 7 0.13% 95.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 35 0.65% 95.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 171 3.19% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 7 0.13% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 4 0.07% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 1 0.02% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 3 0.06% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 3 0.06% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 1 0.02% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 3 0.06% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 3 0.06% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 4 0.07% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 2 0.04% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 4 0.07% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.02% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 6 0.11% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 10 0.19% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5361 # Writes before turning the bus around for reads -system.physmem.totQLat 2204423500 # Total ticks spent queuing -system.physmem.totMemAccLat 9828436000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2033070000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5421.42 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5409 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5409 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.348863 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.981514 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.757339 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4806 88.85% 88.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 190 3.51% 92.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 24 0.44% 92.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 50 0.92% 93.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 37 0.68% 94.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 6 0.11% 94.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 18 0.33% 94.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 42 0.78% 95.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 29 0.54% 96.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 3 0.06% 96.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 162 3.00% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 1 0.02% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 4 0.07% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 3 0.06% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 2 0.04% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 2 0.04% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 4 0.07% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 6 0.11% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 10 0.18% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 2 0.04% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 2 0.04% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 4 0.07% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::312-319 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5409 # Writes before turning the bus around for reads +system.physmem.totQLat 2792890500 # Total ticks spent queuing +system.physmem.totMemAccLat 10430196750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2036615000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6856.70 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24171.42 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.26 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.93 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.26 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.93 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 25606.70 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.15 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.90 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.15 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.90 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.13 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.74 # Average write queue length when enqueuing -system.physmem.readRowHits 363741 # Number of row buffer hits during reads -system.physmem.writeRowHits 96228 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.46 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.93 # Row buffer hit rate for writes -system.physmem.avgGap 3723164.56 # Average gap between requests -system.physmem.pageHitRate 87.28 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 249797520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 136298250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1579858800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 381555360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 128187633600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 65826808245 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1119818638500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1316180590275 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.630269 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1862676833500 # Time in different power states -system.physmem_0.memoryStateTime::REF 65535600000 # Time in different power states +system.physmem.avgWrQLen 25.01 # Average write queue length when enqueuing +system.physmem.readRowHits 363877 # Number of row buffer hits during reads +system.physmem.writeRowHits 96767 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.33 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.03 # Row buffer hit rate for writes +system.physmem.avgGap 3752359.67 # Average gap between requests +system.physmem.pageHitRate 87.20 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 243303480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 132754875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1578049200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 382345920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 129492598560 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 72929786580 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1125575674500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1330334513115 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.011108 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1872213779250 # Time in different power states +system.physmem_0.memoryStateTime::REF 66202760000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 34390001500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 44165427000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 256843440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 140142750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1591730400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 398448720 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 128187633600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 66351904785 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1119358027500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1316284731195 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.683332 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1861912025250 # Time in different power states -system.physmem_1.memoryStateTime::REF 65535600000 # Time in different power states +system.physmem_1.actEnergy 267480360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 145946625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1599070200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 400988880 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 129492598560 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 74043413820 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1124598800250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1330548298695 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.118945 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1870589115500 # Time in different power states +system.physmem_1.memoryStateTime::REF 66202760000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 35154809750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 45790077000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7500026 # DTB read hits -system.cpu0.dtb.read_misses 7443 # DTB read misses +system.cpu0.dtb.read_hits 7416955 # DTB read hits +system.cpu0.dtb.read_misses 7442 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations -system.cpu0.dtb.read_accesses 490673 # DTB read accesses -system.cpu0.dtb.write_hits 5074087 # DTB write hits -system.cpu0.dtb.write_misses 813 # DTB write misses +system.cpu0.dtb.read_accesses 490672 # DTB read accesses +system.cpu0.dtb.write_hits 5004564 # DTB write hits +system.cpu0.dtb.write_misses 812 # DTB write misses system.cpu0.dtb.write_acv 134 # DTB write access violations -system.cpu0.dtb.write_accesses 187452 # DTB write accesses -system.cpu0.dtb.data_hits 12574113 # DTB hits -system.cpu0.dtb.data_misses 8256 # DTB misses +system.cpu0.dtb.write_accesses 187451 # DTB write accesses +system.cpu0.dtb.data_hits 12421519 # DTB hits +system.cpu0.dtb.data_misses 8254 # DTB misses system.cpu0.dtb.data_acv 344 # DTB access violations -system.cpu0.dtb.data_accesses 678125 # DTB accesses -system.cpu0.itb.fetch_hits 3504450 # ITB hits +system.cpu0.dtb.data_accesses 678123 # DTB accesses +system.cpu0.itb.fetch_hits 3482641 # ITB hits system.cpu0.itb.fetch_misses 3871 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3508321 # ITB accesses +system.cpu0.itb.fetch_accesses 3486512 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -345,91 +341,91 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3923838721 # number of cpu cycles simulated +system.cpu0.numCycles 3964851833 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 47783493 # Number of instructions committed -system.cpu0.committedOps 47783493 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 44315744 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 211234 # Number of float alu accesses -system.cpu0.num_func_calls 1203861 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5612503 # number of instructions that are conditional controls -system.cpu0.num_int_insts 44315744 # number of integer instructions -system.cpu0.num_fp_insts 211234 # number of float instructions -system.cpu0.num_int_register_reads 60912860 # number of times the integer registers were read -system.cpu0.num_int_register_writes 33024751 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 102598 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 104462 # number of times the floating registers were written -system.cpu0.num_mem_refs 12614351 # number of memory refs -system.cpu0.num_load_insts 7527207 # Number of load instructions -system.cpu0.num_store_insts 5087144 # Number of store instructions -system.cpu0.num_idle_cycles 3699336863.028799 # Number of idle cycles -system.cpu0.num_busy_cycles 224501857.971201 # Number of busy cycles -system.cpu0.not_idle_fraction 0.057215 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.942785 # Percentage of idle cycles -system.cpu0.Branches 7204257 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2730537 5.71% 5.71% # Class of executed instruction -system.cpu0.op_class::IntAlu 31447784 65.80% 71.51% # Class of executed instruction -system.cpu0.op_class::IntMult 52772 0.11% 71.63% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.63% # Class of executed instruction -system.cpu0.op_class::FloatAdd 25731 0.05% 71.68% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1656 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::MemRead 7703007 16.12% 87.80% # Class of executed instruction -system.cpu0.op_class::MemWrite 5093240 10.66% 98.46% # Class of executed instruction -system.cpu0.op_class::IprAccess 737366 1.54% 100.00% # Class of executed instruction +system.cpu0.committedInsts 47325532 # Number of instructions committed +system.cpu0.committedOps 47325532 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 43895499 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 207106 # Number of float alu accesses +system.cpu0.num_func_calls 1185742 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5567031 # number of instructions that are conditional controls +system.cpu0.num_int_insts 43895499 # number of integer instructions +system.cpu0.num_fp_insts 207106 # number of float instructions +system.cpu0.num_int_register_reads 60349527 # number of times the integer registers were read +system.cpu0.num_int_register_writes 32725613 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 100583 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 102386 # number of times the floating registers were written +system.cpu0.num_mem_refs 12461430 # number of memory refs +system.cpu0.num_load_insts 7443904 # Number of load instructions +system.cpu0.num_store_insts 5017526 # Number of store instructions +system.cpu0.num_idle_cycles 3700363584.987226 # Number of idle cycles +system.cpu0.num_busy_cycles 264488248.012774 # Number of busy cycles +system.cpu0.not_idle_fraction 0.066708 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.933292 # Percentage of idle cycles +system.cpu0.Branches 7135463 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2703242 5.71% 5.71% # Class of executed instruction +system.cpu0.op_class::IntAlu 31183402 65.88% 71.59% # Class of executed instruction +system.cpu0.op_class::IntMult 51823 0.11% 71.70% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::FloatAdd 25571 0.05% 71.75% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 71.75% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 71.75% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 71.75% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1656 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::MemRead 7617030 16.09% 87.85% # Class of executed instruction +system.cpu0.op_class::MemWrite 5023630 10.61% 98.46% # Class of executed instruction +system.cpu0.op_class::IprAccess 727776 1.54% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 47792093 # Class of executed instruction +system.cpu0.op_class::total 47334130 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6802 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 165261 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 56971 40.19% 40.19% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.29% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1973 1.39% 41.68% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 419 0.30% 41.97% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 82246 58.03% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 141740 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 56429 49.08% 49.08% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 419 0.36% 51.28% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 56010 48.72% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 114962 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1900835958000 96.89% 96.89% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 91198500 0.00% 96.89% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 757506500 0.04% 96.93% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 303704500 0.02% 96.95% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 59930963000 3.05% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1961919330500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.990486 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6807 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 162813 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 55930 40.12% 40.12% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 133 0.10% 40.21% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1978 1.42% 41.63% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 435 0.31% 41.94% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 80947 58.06% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 139423 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 55420 49.07% 49.07% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 133 0.12% 49.18% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1978 1.75% 50.93% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 435 0.39% 51.32% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 54986 48.68% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 112952 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1904955657000 96.09% 96.09% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 92166000 0.00% 96.10% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 765642500 0.04% 96.14% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 319863500 0.02% 96.15% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 76292557500 3.85% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1982425886500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.990881 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.681006 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.811077 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.679284 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810139 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed @@ -461,124 +457,124 @@ system.cpu0.kern.syscall::144 2 0.90% 99.10% # nu system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 222 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 500 0.33% 0.33% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.33% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3072 2.05% 2.38% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed -system.cpu0.kern.callpal::swpipl 134879 89.87% 92.29% # number of callpals executed -system.cpu0.kern.callpal::rdps 6699 4.46% 96.76% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.76% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.76% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.77% # number of callpals executed -system.cpu0.kern.callpal::rti 4337 2.89% 99.66% # number of callpals executed -system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed +system.cpu0.kern.callpal::wripir 523 0.35% 0.35% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3026 2.05% 2.41% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed +system.cpu0.kern.callpal::swpipl 132550 89.80% 92.24% # number of callpals executed +system.cpu0.kern.callpal::rdps 6593 4.47% 96.71% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.71% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.71% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.72% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.72% # number of callpals executed +system.cpu0.kern.callpal::rti 4327 2.93% 99.65% # number of callpals executed +system.cpu0.kern.callpal::callsys 381 0.26% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 150081 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6891 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1282 # number of protection mode switches +system.cpu0.kern.callpal::total 147613 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6866 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1281 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1282 -system.cpu0.kern.mode_good::user 1282 +system.cpu0.kern.mode_good::kernel 1281 +system.cpu0.kern.mode_good::user 1281 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.186040 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.186572 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.313716 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1958152340000 99.82% 99.82% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3531530500 0.18% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.314472 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1977675856500 99.80% 99.80% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3900112000 0.20% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3073 # number of times the context was actually changed -system.cpu0.dcache.tags.replacements 1181794 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.240594 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11382177 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1182212 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.627865 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 112405500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.240594 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986798 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986798 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 418 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 372 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.816406 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51530574 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51530574 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6418852 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6418852 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4665452 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4665452 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140662 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 140662 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148383 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 148383 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11084304 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11084304 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11084304 # number of overall hits -system.cpu0.dcache.overall_hits::total 11084304 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 939259 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 939259 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 251797 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 251797 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13671 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13671 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5399 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5399 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1191056 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1191056 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1191056 # number of overall misses -system.cpu0.dcache.overall_misses::total 1191056 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 28901225000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 28901225000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10875412500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 10875412500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150368000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 150368000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 47710000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 47710000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 39776637500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 39776637500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 39776637500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 39776637500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7358111 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7358111 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4917249 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4917249 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154333 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 154333 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153782 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 153782 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12275360 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12275360 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12275360 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12275360 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127649 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.127649 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051207 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051207 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088581 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088581 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035108 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035108 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097028 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.097028 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097028 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097028 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30770.240157 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 30770.240157 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43191.191714 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 43191.191714 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10999.049082 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10999.049082 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8836.821634 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8836.821634 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33396.110258 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33396.110258 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33396.110258 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33396.110258 # average overall miss latency +system.cpu0.kern.swap_context 3027 # number of times the context was actually changed +system.cpu0.dcache.tags.replacements 1172695 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.333942 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11237582 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1173114 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.579275 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 143226500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.333942 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986980 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986980 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 419 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 371 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.818359 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 50910847 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 50910847 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6343242 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6343242 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4601243 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4601243 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138155 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 138155 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145460 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 145460 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10944485 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10944485 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10944485 # number of overall hits +system.cpu0.dcache.overall_hits::total 10944485 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 934191 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 934191 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 249028 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 249028 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13578 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13578 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5734 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 5734 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1183219 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1183219 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1183219 # number of overall misses +system.cpu0.dcache.overall_misses::total 1183219 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 42879044000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 42879044000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 16797420000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 16797420000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 151036000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 151036000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 96889000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 96889000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 59676464000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 59676464000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 59676464000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 59676464000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7277433 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7277433 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4850271 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4850271 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 151733 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 151733 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 151194 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 151194 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12127704 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12127704 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12127704 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12127704 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.128368 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.128368 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051343 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051343 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.089486 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.089486 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037925 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037925 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097563 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.097563 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097563 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.097563 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 45899.654353 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 45899.654353 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 67451.933116 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 67451.933116 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11123.582265 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11123.582265 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 16897.279386 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16897.279386 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50435.687730 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 50435.687730 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50435.687730 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 50435.687730 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -587,126 +583,126 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 679941 # number of writebacks -system.cpu0.dcache.writebacks::total 679941 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 939259 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 939259 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251797 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 251797 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13671 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13671 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5399 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 5399 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1191056 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1191056 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1191056 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1191056 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7110 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7110 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10829 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10829 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17939 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17939 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27961966000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27961966000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10623615500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10623615500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 136697000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136697000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 42311000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 42311000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38585581500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 38585581500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38585581500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 38585581500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1492228000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1492228000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2319869500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2319869500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3812097500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3812097500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127649 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127649 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051207 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051207 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088581 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088581 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035108 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035108 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097028 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097028 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097028 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097028 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29770.240157 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29770.240157 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42191.191714 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42191.191714 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9999.049082 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9999.049082 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7836.821634 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7836.821634 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32396.110258 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32396.110258 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32396.110258 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32396.110258 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209877.355837 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209877.355837 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 214227.490996 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 214227.490996 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 212503.344668 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 212503.344668 # average overall mshr uncacheable latency +system.cpu0.dcache.writebacks::writebacks 672708 # number of writebacks +system.cpu0.dcache.writebacks::total 672708 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 934191 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 934191 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249028 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 249028 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13578 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13578 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5734 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5734 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1183219 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1183219 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1183219 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1183219 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7086 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7086 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10784 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10784 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17870 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17870 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 41944853000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 41944853000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 16548392000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 16548392000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 137458000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137458000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 91155000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 91155000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 58493245000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 58493245000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 58493245000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 58493245000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1488672000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1488672000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2316060500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2316060500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3804732500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3804732500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128368 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128368 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051343 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051343 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.089486 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.089486 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037925 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037925 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097563 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097563 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097563 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097563 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 44899.654353 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 44899.654353 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 66451.933116 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 66451.933116 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10123.582265 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10123.582265 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 15897.279386 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15897.279386 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 49435.687730 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 49435.687730 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 49435.687730 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 49435.687730 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210086.367485 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210086.367485 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 214768.221439 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 214768.221439 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 212911.723559 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 212911.723559 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 700401 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.179347 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 47091062 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 700913 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.185317 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 42246954500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.179347 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992538 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.992538 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 686863 # number of replacements +system.cpu0.icache.tags.tagsinuse 506.493433 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 46646633 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 687375 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.861987 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 58997592500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 506.493433 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.989245 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.989245 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 355 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 157 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 417 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 48493124 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 48493124 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 47091062 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 47091062 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 47091062 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 47091062 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 47091062 # number of overall hits -system.cpu0.icache.overall_hits::total 47091062 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 701031 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 701031 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 701031 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 701031 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 701031 # number of overall misses -system.cpu0.icache.overall_misses::total 701031 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10017639000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10017639000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10017639000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10017639000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10017639000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10017639000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47792093 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47792093 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47792093 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47792093 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47792093 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47792093 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014668 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014668 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014668 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014668 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014668 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014668 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14289.865926 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14289.865926 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14289.865926 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14289.865926 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14289.865926 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14289.865926 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 48021627 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 48021627 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 46646633 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 46646633 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 46646633 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 46646633 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 46646633 # number of overall hits +system.cpu0.icache.overall_hits::total 46646633 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 687497 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 687497 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 687497 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 687497 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 687497 # number of overall misses +system.cpu0.icache.overall_misses::total 687497 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10629492500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10629492500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10629492500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10629492500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10629492500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10629492500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47334130 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47334130 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47334130 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47334130 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47334130 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47334130 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014524 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014524 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014524 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014524 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014524 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014524 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15461.147467 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 15461.147467 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15461.147467 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 15461.147467 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15461.147467 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 15461.147467 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -715,51 +711,51 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 701031 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 701031 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 701031 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 701031 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 701031 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 701031 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9316608000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9316608000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9316608000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9316608000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9316608000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9316608000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014668 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014668 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014668 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014668 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014668 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014668 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13289.865926 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13289.865926 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13289.865926 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13289.865926 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13289.865926 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13289.865926 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 687497 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 687497 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 687497 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 687497 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 687497 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 687497 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9941995500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9941995500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9941995500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9941995500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9941995500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9941995500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014524 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014524 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014524 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14461.147467 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14461.147467 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14461.147467 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 14461.147467 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14461.147467 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 14461.147467 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2409623 # DTB read hits -system.cpu1.dtb.read_misses 2992 # DTB read misses +system.cpu1.dtb.read_hits 2508569 # DTB read hits +system.cpu1.dtb.read_misses 2993 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations -system.cpu1.dtb.read_accesses 239363 # DTB read accesses -system.cpu1.dtb.write_hits 1749165 # DTB write hits -system.cpu1.dtb.write_misses 341 # DTB write misses +system.cpu1.dtb.read_accesses 239364 # DTB read accesses +system.cpu1.dtb.write_hits 1828737 # DTB write hits +system.cpu1.dtb.write_misses 342 # DTB write misses system.cpu1.dtb.write_acv 29 # DTB write access violations -system.cpu1.dtb.write_accesses 105247 # DTB write accesses -system.cpu1.dtb.data_hits 4158788 # DTB hits -system.cpu1.dtb.data_misses 3333 # DTB misses +system.cpu1.dtb.write_accesses 105248 # DTB write accesses +system.cpu1.dtb.data_hits 4337306 # DTB hits +system.cpu1.dtb.data_misses 3335 # DTB misses system.cpu1.dtb.data_acv 29 # DTB access violations -system.cpu1.dtb.data_accesses 344610 # DTB accesses -system.cpu1.itb.fetch_hits 1960477 # ITB hits +system.cpu1.dtb.data_accesses 344612 # DTB accesses +system.cpu1.itb.fetch_hits 1989876 # ITB hits system.cpu1.itb.fetch_misses 1216 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1961693 # ITB accesses +system.cpu1.itb.fetch_accesses 1991092 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -772,87 +768,87 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3925216965 # number of cpu cycles simulated +system.cpu1.numCycles 3965170714 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 13101094 # Number of instructions committed -system.cpu1.committedOps 13101094 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 12083765 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 172106 # Number of float alu accesses -system.cpu1.num_func_calls 409417 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1299945 # number of instructions that are conditional controls -system.cpu1.num_int_insts 12083765 # number of integer instructions -system.cpu1.num_fp_insts 172106 # number of float instructions -system.cpu1.num_int_register_reads 16637487 # number of times the integer registers were read -system.cpu1.num_int_register_writes 8868500 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 90075 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 91936 # number of times the floating registers were written -system.cpu1.num_mem_refs 4182249 # number of memory refs -system.cpu1.num_load_insts 2423870 # Number of load instructions -system.cpu1.num_store_insts 1758379 # Number of store instructions -system.cpu1.num_idle_cycles 3876316507.998025 # Number of idle cycles -system.cpu1.num_busy_cycles 48900457.001975 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012458 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987542 # Percentage of idle cycles -system.cpu1.Branches 1864071 # Number of branches fetched -system.cpu1.op_class::No_OpClass 700818 5.35% 5.35% # Class of executed instruction -system.cpu1.op_class::IntAlu 7749061 59.13% 64.48% # Class of executed instruction -system.cpu1.op_class::IntMult 21359 0.16% 64.64% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.64% # Class of executed instruction -system.cpu1.op_class::FloatAdd 14141 0.11% 64.75% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.75% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.75% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.75% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1986 0.02% 64.77% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::MemRead 2495218 19.04% 83.81% # Class of executed instruction -system.cpu1.op_class::MemWrite 1759360 13.43% 97.23% # Class of executed instruction -system.cpu1.op_class::IprAccess 362513 2.77% 100.00% # Class of executed instruction +system.cpu1.committedInsts 13660009 # Number of instructions committed +system.cpu1.committedOps 13660009 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 12598388 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 178445 # Number of float alu accesses +system.cpu1.num_func_calls 429702 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1355296 # number of instructions that are conditional controls +system.cpu1.num_int_insts 12598388 # number of integer instructions +system.cpu1.num_fp_insts 178445 # number of float instructions +system.cpu1.num_int_register_reads 17340989 # number of times the integer registers were read +system.cpu1.num_int_register_writes 9240436 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 93179 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 95134 # number of times the floating registers were written +system.cpu1.num_mem_refs 4361445 # number of memory refs +system.cpu1.num_load_insts 2523214 # Number of load instructions +system.cpu1.num_store_insts 1838231 # Number of store instructions +system.cpu1.num_idle_cycles 3912374881.998026 # Number of idle cycles +system.cpu1.num_busy_cycles 52795832.001973 # Number of busy cycles +system.cpu1.not_idle_fraction 0.013315 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.986685 # Percentage of idle cycles +system.cpu1.Branches 1945174 # Number of branches fetched +system.cpu1.op_class::No_OpClass 733210 5.37% 5.37% # Class of executed instruction +system.cpu1.op_class::IntAlu 8079835 59.13% 64.50% # Class of executed instruction +system.cpu1.op_class::IntMult 22791 0.17% 64.67% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.67% # Class of executed instruction +system.cpu1.op_class::FloatAdd 14367 0.11% 64.77% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1986 0.01% 64.79% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::MemRead 2597857 19.01% 83.80% # Class of executed instruction +system.cpu1.op_class::MemWrite 1839254 13.46% 97.26% # Class of executed instruction +system.cpu1.op_class::IprAccess 374073 2.74% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 13104456 # Class of executed instruction +system.cpu1.op_class::total 13663373 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2738 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 78185 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 26382 38.32% 38.32% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1969 2.86% 41.18% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 500 0.73% 41.90% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 40003 58.10% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 68854 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 25547 48.14% 48.14% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1969 3.71% 51.85% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 500 0.94% 52.80% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 25048 47.20% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 53064 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1909718189500 97.31% 97.31% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 702775500 0.04% 97.34% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 343141500 0.02% 97.36% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 51843654000 2.64% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1962607760500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.968350 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2868 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 81018 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 27534 38.52% 38.52% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1971 2.76% 41.28% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 523 0.73% 42.01% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 41447 57.99% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 71475 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 26667 48.22% 48.22% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1971 3.56% 51.78% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 523 0.95% 52.73% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 26144 47.27% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 55305 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1912303307000 96.46% 96.46% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 705769500 0.04% 96.49% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 367699000 0.02% 96.51% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 69207844500 3.49% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1982584620000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.968512 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.626153 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.770674 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.630781 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.773767 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed @@ -868,124 +864,124 @@ system.cpu1.kern.syscall::74 10 9.62% 97.12% # nu system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 104 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 419 0.59% 0.59% # number of callpals executed +system.cpu1.kern.callpal::wripir 435 0.59% 0.59% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1985 2.79% 3.38% # number of callpals executed +system.cpu1.kern.callpal::swpctx 2064 2.79% 3.38% # number of callpals executed system.cpu1.kern.callpal::tbi 3 0.00% 3.39% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 3.40% # number of callpals executed -system.cpu1.kern.callpal::swpipl 62619 88.03% 91.42% # number of callpals executed -system.cpu1.kern.callpal::rdps 2146 3.02% 94.44% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.44% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 94.45% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.45% # number of callpals executed -system.cpu1.kern.callpal::rti 3766 5.29% 99.75% # number of callpals executed -system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed +system.cpu1.kern.callpal::swpipl 65156 88.12% 91.51% # number of callpals executed +system.cpu1.kern.callpal::rdps 2261 3.06% 94.57% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.57% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 94.58% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.58% # number of callpals executed +system.cpu1.kern.callpal::rti 3824 5.17% 99.76% # number of callpals executed +system.cpu1.kern.callpal::callsys 136 0.18% 99.94% # number of callpals executed system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 71137 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2053 # number of protection mode switches -system.cpu1.kern.mode_switch::user 465 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2874 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 889 -system.cpu1.kern.mode_good::user 465 -system.cpu1.kern.mode_good::idle 424 -system.cpu1.kern.mode_switch_good::kernel 0.433025 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 73942 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2112 # number of protection mode switches +system.cpu1.kern.mode_switch::user 464 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2921 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 911 +system.cpu1.kern.mode_good::user 464 +system.cpu1.kern.mode_good::idle 447 +system.cpu1.kern.mode_switch_good::kernel 0.431345 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.147530 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.329748 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 17552018500 0.89% 0.89% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1707542500 0.09% 0.98% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1943348197500 99.02% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1986 # number of times the context was actually changed -system.cpu1.dcache.tags.replacements 165381 # number of replacements -system.cpu1.dcache.tags.tagsinuse 485.645767 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 3991235 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 165893 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 24.059092 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1050804836500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.645767 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.948527 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.948527 # Average percentage of cache occupancy +system.cpu1.kern.mode_switch_good::idle 0.153030 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.331454 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 19415818500 0.98% 0.98% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1728972000 0.09% 1.07% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1961439827500 98.93% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 2065 # number of times the context was actually changed +system.cpu1.dcache.tags.replacements 173710 # number of replacements +system.cpu1.dcache.tags.tagsinuse 481.751289 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 4161033 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 174222 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 23.883511 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 90304766500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.751289 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.940920 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.940920 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 16867850 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 16867850 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2245744 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2245744 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1632527 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1632527 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48591 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 48591 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50409 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 50409 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3878271 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3878271 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3878271 # number of overall hits -system.cpu1.dcache.overall_hits::total 3878271 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 117597 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 117597 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 62279 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 62279 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8857 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 8857 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5813 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 5813 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 179876 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 179876 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 179876 # number of overall misses -system.cpu1.dcache.overall_misses::total 179876 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1425631000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1425631000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1255840500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1255840500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 80743500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 80743500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49386500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 49386500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 2681471500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 2681471500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 2681471500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 2681471500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2363341 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2363341 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1694806 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1694806 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57448 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 57448 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56222 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 56222 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4058147 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4058147 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4058147 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4058147 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049759 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.049759 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036747 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.036747 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.154174 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.154174 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103394 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103394 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044325 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.044325 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044325 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.044325 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12123.021846 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12123.021846 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20164.750558 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 20164.750558 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9116.348651 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9116.348651 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8495.871323 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8495.871323 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14907.333385 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14907.333385 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14907.333385 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14907.333385 # average overall miss latency +system.cpu1.dcache.tags.tag_accesses 17592927 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 17592927 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 2337017 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2337017 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1705874 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1705874 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 50407 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 50407 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 53062 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 53062 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 4042891 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 4042891 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 4042891 # number of overall hits +system.cpu1.dcache.overall_hits::total 4042891 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 123430 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 123430 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 65652 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 65652 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9249 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 9249 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6101 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 6101 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 189082 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 189082 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 189082 # number of overall misses +system.cpu1.dcache.overall_misses::total 189082 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1554368000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1554368000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1876323500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1876323500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 84244000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 84244000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 98989500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 98989500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 3430691500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 3430691500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 3430691500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 3430691500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2460447 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2460447 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1771526 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1771526 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 59656 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 59656 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 59163 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 59163 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4231973 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4231973 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4231973 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4231973 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050166 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.050166 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.037060 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.037060 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.155039 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.155039 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103122 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103122 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044679 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.044679 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044679 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.044679 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12593.113506 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12593.113506 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 28579.837629 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 28579.837629 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9108.444156 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9108.444156 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 16225.127028 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 16225.127028 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18143.934907 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18143.934907 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18143.934907 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18143.934907 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -994,128 +990,128 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 113645 # number of writebacks -system.cpu1.dcache.writebacks::total 113645 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 117597 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 117597 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62279 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 62279 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8857 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8857 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5813 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 5813 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 179876 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 179876 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 179876 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 179876 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 89 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 89 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3214 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3214 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3303 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3303 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1308034000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1308034000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1193561500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1193561500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 71886500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 71886500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 43573500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 43573500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2501595500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2501595500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2501595500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2501595500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19086500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19086500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 723672500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 723672500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742759000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742759000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049759 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049759 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036747 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036747 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.154174 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.154174 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103394 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103394 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044325 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.044325 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044325 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.044325 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11123.021846 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11123.021846 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19164.750558 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19164.750558 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8116.348651 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8116.348651 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7495.871323 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7495.871323 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13907.333385 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13907.333385 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13907.333385 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13907.333385 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 214455.056180 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 214455.056180 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 225162.570006 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 225162.570006 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 224874.053890 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 224874.053890 # average overall mshr uncacheable latency +system.cpu1.dcache.writebacks::writebacks 119711 # number of writebacks +system.cpu1.dcache.writebacks::total 119711 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 123430 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 123430 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 65652 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 65652 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9249 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9249 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6101 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 6101 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 189082 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 189082 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 189082 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 189082 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 118 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 118 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3347 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3347 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3465 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3465 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1430938000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1430938000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1810671500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1810671500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74995000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74995000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 92888500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 92888500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3241609500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3241609500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3241609500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3241609500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 23714500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 23714500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 747400000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 747400000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 771114500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 771114500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050166 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050166 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.037060 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.037060 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155039 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155039 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103122 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103122 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044679 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.044679 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044679 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.044679 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11593.113506 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11593.113506 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27579.837629 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27579.837629 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8108.444156 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8108.444156 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15225.127028 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 15225.127028 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17143.934907 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17143.934907 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17143.934907 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17143.934907 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 200970.338983 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 200970.338983 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 223304.451748 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 223304.451748 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 222543.867244 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 222543.867244 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 313887 # number of replacements -system.cpu1.icache.tags.tagsinuse 445.952187 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 12790016 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 314399 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 40.680842 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1961762459500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.952187 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.871000 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.871000 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 331160 # number of replacements +system.cpu1.icache.tags.tagsinuse 442.919388 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 13331662 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 331672 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 40.195319 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1976558526500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 442.919388 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.865077 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.865077 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 406 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 31 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 13418898 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 13418898 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 12790016 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 12790016 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 12790016 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 12790016 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 12790016 # number of overall hits -system.cpu1.icache.overall_hits::total 12790016 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 314441 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 314441 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 314441 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 314441 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 314441 # number of overall misses -system.cpu1.icache.overall_misses::total 314441 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4125234500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4125234500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4125234500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4125234500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4125234500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4125234500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13104457 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13104457 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13104457 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13104457 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13104457 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13104457 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023995 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.023995 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023995 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.023995 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023995 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.023995 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13119.264027 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13119.264027 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13119.264027 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13119.264027 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13119.264027 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13119.264027 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 13995086 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 13995086 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 13331662 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 13331662 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 13331662 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 13331662 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 13331662 # number of overall hits +system.cpu1.icache.overall_hits::total 13331662 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 331712 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 331712 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 331712 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 331712 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 331712 # number of overall misses +system.cpu1.icache.overall_misses::total 331712 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4531331500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4531331500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4531331500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4531331500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4531331500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4531331500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 13663374 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13663374 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 13663374 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 13663374 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 13663374 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 13663374 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024277 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024277 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024277 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024277 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024277 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024277 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13660.438875 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13660.438875 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13660.438875 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13660.438875 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13660.438875 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13660.438875 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1124,30 +1120,30 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 314441 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 314441 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 314441 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 314441 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 314441 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 314441 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3810793500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3810793500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3810793500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3810793500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3810793500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3810793500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023995 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023995 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023995 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.023995 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023995 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.023995 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12119.264027 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12119.264027 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12119.264027 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12119.264027 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12119.264027 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12119.264027 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 331712 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 331712 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 331712 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 331712 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 331712 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 331712 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4199619500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4199619500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4199619500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4199619500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4199619500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4199619500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024277 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024277 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024277 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024277 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024277 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024277 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12660.438875 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12660.438875 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12660.438875 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12660.438875 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12660.438875 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12660.438875 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1161,45 +1157,45 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 7373 # Transaction distribution -system.iobus.trans_dist::ReadResp 7373 # Transaction distribution -system.iobus.trans_dist::WriteReq 55595 # Transaction distribution -system.iobus.trans_dist::WriteResp 55595 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13874 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 7379 # Transaction distribution +system.iobus.trans_dist::ReadResp 7379 # Transaction distribution +system.iobus.trans_dist::WriteReq 55683 # Transaction distribution +system.iobus.trans_dist::WriteResp 55683 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14064 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2476 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 42484 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 125936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55496 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 42670 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 126124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 56256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9884 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 81762 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2743378 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 13229000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 82499 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2744123 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 13414000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1209,9 +1205,9 @@ system.iobus.reqLayer22.occupancy 155000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 2453000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 2454000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 5167000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) @@ -1219,52 +1215,52 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 216079499 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 215099489 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28441000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 28539000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41948000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41950000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41694 # number of replacements -system.iocache.tags.tagsinuse 0.567878 # Cycle average of tags in use +system.iocache.tags.replacements 41695 # number of replacements +system.iocache.tags.tagsinuse 0.566806 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1756483227000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.567878 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035492 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035492 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1775098751000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.566806 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035425 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035425 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375534 # Number of tag accesses -system.iocache.tags.data_accesses 375534 # Number of data accesses -system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses -system.iocache.ReadReq_misses::total 174 # number of ReadReq misses +system.iocache.tags.tag_accesses 375543 # Number of tag accesses +system.iocache.tags.data_accesses 375543 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses +system.iocache.ReadReq_misses::total 175 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses -system.iocache.demand_misses::total 174 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 174 # number of overall misses -system.iocache.overall_misses::total 174 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21744883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21744883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4908047616 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4908047616 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21744883 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21744883 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21744883 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21744883 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses +system.iocache.demand_misses::total 175 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 175 # number of overall misses +system.iocache.overall_misses::total 175 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 22127883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22127883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5428057606 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5428057606 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 22127883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 22127883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 22127883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 22127883 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 174 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 174 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses @@ -1273,40 +1269,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 124970.591954 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124970.591954 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118118.204082 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118118.204082 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 124970.591954 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124970.591954 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 124970.591954 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124970.591954 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126445.045714 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126445.045714 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130632.884241 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130632.884241 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 126445.045714 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126445.045714 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 126445.045714 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126445.045714 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 55 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 18.333333 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # 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number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13377883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3350457606 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3350457606 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 13377883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 13377883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 13377883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 13377883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1315,195 +1311,195 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 74970.591954 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 74970.591954 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68118.204082 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68118.204082 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 74970.591954 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 74970.591954 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 74970.591954 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 74970.591954 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76445.045714 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76445.045714 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80632.884241 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80632.884241 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76445.045714 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76445.045714 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76445.045714 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76445.045714 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 341250 # number of replacements -system.l2c.tags.tagsinuse 65213.641245 # Cycle average of tags in use -system.l2c.tags.total_refs 3683713 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 406253 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 9.067534 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 9107201000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55129.108381 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4852.505635 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5029.950253 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 158.753057 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 43.323918 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.841203 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.074043 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.076751 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002422 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000661 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995081 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65003 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 185 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 1120 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 4999 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6097 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52602 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.991867 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 35905885 # Number of tag accesses -system.l2c.tags.data_accesses 35905885 # Number of data accesses -system.l2c.Writeback_hits::writebacks 793586 # number of Writeback hits -system.l2c.Writeback_hits::total 793586 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 173 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 535 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 708 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 43 # number of SCUpgradeReq hits +system.l2c.tags.replacements 341926 # number of replacements +system.l2c.tags.tagsinuse 65167.982973 # Cycle average of tags in use +system.l2c.tags.total_refs 3685196 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 406932 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 9.056049 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 12918028000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 54774.174056 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4860.572445 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5374.369214 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 120.511186 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 38.356073 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.835788 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.074166 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.082006 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.001839 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000585 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.994385 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65006 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 516 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 5383 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6300 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52705 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.991913 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 35906123 # Number of tag accesses +system.l2c.tags.data_accesses 35906123 # Number of data accesses +system.l2c.Writeback_hits::writebacks 792419 # number of Writeback hits +system.l2c.Writeback_hits::total 792419 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 186 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 557 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 743 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 39 # 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number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 155607 # number of demand (read+write) hits -system.l2c.demand_hits::total 1949434 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 688011 # number of overall hits -system.l2c.overall_hits::cpu0.data 791881 # number of overall hits -system.l2c.overall_hits::cpu1.inst 313935 # number of overall hits -system.l2c.overall_hits::cpu1.data 155607 # number of overall hits -system.l2c.overall_hits::total 1949434 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 2935 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1733 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 4668 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 882 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 893 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1775 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 115542 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 63888.278357 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197377.355837 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 201955.056180 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197433.949160 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 202727.398652 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 213662.103298 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 205230.007833 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 200606.945761 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 213346.654556 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 202587.891912 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941009 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.764482 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.865350 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.959544 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.974816 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.967136 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.480915 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.139213 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.415606 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.018286 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.002801 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013246 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.291677 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.002954 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260159 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018286 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.330343 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002801 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.048080 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.172987 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018286 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.330343 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002801 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.048080 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.172987 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 71556.285811 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 71793.694690 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71646.178010 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71034.054054 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71513.455328 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71274.271845 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 117140.858485 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121861.139369 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 117443.057297 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 121383.939225 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122768.030140 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 121479.185185 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 113999.243205 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 119537.091988 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114006.107541 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121383.939225 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 114933.737808 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122768.030140 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121765.638337 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 115287.456732 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121383.939225 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 114933.737808 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122768.030140 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121765.638337 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 115287.456732 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197585.944115 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 188466.101695 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197436.563021 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 203268.082344 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 211804.152973 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 205289.894558 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 201014.941242 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 211009.379509 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 202638.129834 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 7199 # Transaction distribution -system.membus.trans_dist::ReadResp 292720 # Transaction distribution -system.membus.trans_dist::WriteReq 14043 # Transaction distribution -system.membus.trans_dist::WriteResp 14043 # Transaction distribution -system.membus.trans_dist::Writeback 120393 # Transaction distribution -system.membus.trans_dist::CleanEvict 261901 # Transaction distribution -system.membus.trans_dist::UpgradeReq 15996 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11145 # Transaction distribution -system.membus.trans_dist::UpgradeResp 6943 # Transaction distribution -system.membus.trans_dist::ReadExReq 122456 # Transaction distribution -system.membus.trans_dist::ReadExResp 121630 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 285521 # Transaction distribution +system.membus.trans_dist::ReadReq 7204 # Transaction distribution +system.membus.trans_dist::ReadResp 292756 # Transaction distribution +system.membus.trans_dist::WriteReq 14131 # Transaction distribution +system.membus.trans_dist::WriteResp 14131 # Transaction distribution +system.membus.trans_dist::Writeback 120910 # Transaction distribution +system.membus.trans_dist::CleanEvict 262059 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16821 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 11772 # Transaction distribution +system.membus.trans_dist::UpgradeResp 7147 # Transaction distribution +system.membus.trans_dist::ReadExReq 123180 # Transaction distribution +system.membus.trans_dist::ReadExResp 122316 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 285552 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42484 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1189359 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1231843 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124826 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124826 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1356669 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 81762 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31077568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31159330 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42670 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1193160 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1235830 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124827 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124827 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1360657 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82499 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31156480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31238979 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33817570 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 21449 # Total snoops (count) -system.membus.snoop_fanout::samples 880387 # Request fanout histogram +system.membus.pkt_size::total 33897219 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 22736 # Total snoops (count) +system.membus.snoop_fanout::samples 883364 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 880387 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 883364 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 880387 # Request fanout histogram -system.membus.reqLayer0.occupancy 40402000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 883364 # Request fanout histogram +system.membus.reqLayer0.occupancy 40609000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1321574195 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1325313892 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2188968059 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2193032106 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 72063409 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 69837727 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 7199 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2102214 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14043 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14043 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 913999 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1505100 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 16204 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11212 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 27416 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 297872 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 297872 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1015472 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1079558 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 4790600 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2395468 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 361643 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1240 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1180 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 60 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 7204 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2107021 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 14131 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 14131 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 913350 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1503335 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 17046 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11835 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 28881 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 297634 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 297634 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1019209 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1080623 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1960114 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3569990 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 818944 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 514014 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6863062 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44864640 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119041472 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20124160 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17694178 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 201724450 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 480853 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 5227539 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.081241 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.273205 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1918193 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3544327 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 867106 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 539630 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6869256 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43998144 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118001405 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 21229504 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 18604166 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 201833219 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 484490 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 5237304 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.138719 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.345885 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 4802849 91.88% 91.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 424690 8.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4511205 86.14% 86.14% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 725687 13.86% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 408 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 4 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5227539 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3202032998 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 5237304 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3205453497 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 238500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 297883 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1051547997 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1031366757 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1814279465 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1802104925 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 471668486 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 498533066 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 279553995 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 293884764 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 5922aa080..2decdfb20 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.922397 # Number of seconds simulated -sim_ticks 1922397182500 # Number of ticks simulated -final_tick 1922397182500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.941266 # Number of seconds simulated +sim_ticks 1941266487500 # Number of ticks simulated +final_tick 1941266487500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1085217 # Simulator instruction rate (inst/s) -host_op_rate 1085217 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37124537063 # Simulator tick rate (ticks/s) -host_mem_usage 372212 # Number of bytes of host memory used -host_seconds 51.78 # Real time elapsed on the host -sim_insts 56195121 # Number of instructions simulated -sim_ops 56195121 # Number of ops (including micro ops) simulated +host_inst_rate 1056307 # Simulator instruction rate (inst/s) +host_op_rate 1056307 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36524098946 # Simulator tick rate (ticks/s) +host_mem_usage 374096 # Number of bytes of host memory used +host_seconds 53.15 # Real time elapsed on the host +sim_insts 56143021 # Number of instructions simulated +sim_ops 56143021 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 848768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24858048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 848832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24855488 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25707776 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 848768 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 848768 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7409088 # Number of bytes written to this memory -system.physmem.bytes_written::total 7409088 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13262 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388407 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25705280 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 848832 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 848832 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7407552 # Number of bytes written to this memory +system.physmem.bytes_written::total 7407552 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13263 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388367 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 401684 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115767 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115767 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 441515 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12930756 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 499 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13372770 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 441515 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 441515 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3854088 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3854088 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3854088 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 441515 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12930756 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17226858 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 401684 # Number of read requests accepted -system.physmem.writeReqs 115767 # Number of write requests accepted -system.physmem.readBursts 401684 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 115767 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25700352 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7424 # Total number of bytes read from write queue -system.physmem.bytesWritten 7407168 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25707776 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7409088 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 116 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 401645 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115743 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115743 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 437257 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12803749 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 495 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13241500 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 437257 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 437257 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3815835 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3815835 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3815835 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 437257 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12803749 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 495 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17057335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 401645 # Number of read requests accepted +system.physmem.writeReqs 115743 # Number of write requests accepted +system.physmem.readBursts 401645 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115743 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25697728 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7552 # Total number of bytes read from write queue +system.physmem.bytesWritten 7406016 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25705280 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7407552 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 118 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 41682 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25233 # Per bank write bursts -system.physmem.perBankRdBursts::1 25641 # Per bank write bursts -system.physmem.perBankRdBursts::2 25574 # Per bank write bursts -system.physmem.perBankRdBursts::3 25503 # Per bank write bursts -system.physmem.perBankRdBursts::4 24973 # Per bank write bursts -system.physmem.perBankRdBursts::5 24969 # Per bank write bursts -system.physmem.perBankRdBursts::6 24206 # Per bank write bursts -system.physmem.perBankRdBursts::7 24501 # Per bank write bursts -system.physmem.perBankRdBursts::8 25169 # Per bank write bursts -system.physmem.perBankRdBursts::9 24770 # Per bank write bursts -system.physmem.perBankRdBursts::10 25259 # Per bank write bursts -system.physmem.perBankRdBursts::11 24898 # Per bank write bursts -system.physmem.perBankRdBursts::12 24500 # Per bank write bursts -system.physmem.perBankRdBursts::13 25360 # Per bank write bursts -system.physmem.perBankRdBursts::14 25653 # Per bank write bursts -system.physmem.perBankRdBursts::15 25359 # Per bank write bursts -system.physmem.perBankWrBursts::0 7624 # Per bank write bursts -system.physmem.perBankWrBursts::1 7642 # Per bank write bursts -system.physmem.perBankWrBursts::2 7864 # Per bank write bursts -system.physmem.perBankWrBursts::3 7542 # Per bank write bursts -system.physmem.perBankWrBursts::4 7123 # Per bank write bursts -system.physmem.perBankWrBursts::5 6988 # Per bank write bursts -system.physmem.perBankWrBursts::6 6319 # Per bank write bursts -system.physmem.perBankWrBursts::7 6328 # Per bank write bursts -system.physmem.perBankWrBursts::8 7314 # Per bank write bursts -system.physmem.perBankWrBursts::9 6525 # Per bank write bursts -system.physmem.perBankWrBursts::10 7109 # Per bank write bursts -system.physmem.perBankWrBursts::11 6927 # Per bank write bursts -system.physmem.perBankWrBursts::12 7069 # Per bank write bursts -system.physmem.perBankWrBursts::13 7821 # Per bank write bursts -system.physmem.perBankWrBursts::14 7867 # Per bank write bursts -system.physmem.perBankWrBursts::15 7675 # Per bank write bursts +system.physmem.perBankRdBursts::0 25168 # Per bank write bursts +system.physmem.perBankRdBursts::1 25510 # Per bank write bursts +system.physmem.perBankRdBursts::2 25518 # Per bank write bursts +system.physmem.perBankRdBursts::3 25527 # Per bank write bursts +system.physmem.perBankRdBursts::4 25065 # Per bank write bursts +system.physmem.perBankRdBursts::5 24960 # Per bank write bursts +system.physmem.perBankRdBursts::6 24241 # Per bank write bursts +system.physmem.perBankRdBursts::7 24604 # Per bank write bursts +system.physmem.perBankRdBursts::8 25078 # Per bank write bursts +system.physmem.perBankRdBursts::9 24653 # Per bank write bursts +system.physmem.perBankRdBursts::10 25359 # Per bank write bursts +system.physmem.perBankRdBursts::11 24824 # Per bank write bursts +system.physmem.perBankRdBursts::12 24407 # Per bank write bursts +system.physmem.perBankRdBursts::13 25357 # Per bank write bursts +system.physmem.perBankRdBursts::14 25770 # Per bank write bursts +system.physmem.perBankRdBursts::15 25486 # Per bank write bursts +system.physmem.perBankWrBursts::0 7561 # Per bank write bursts +system.physmem.perBankWrBursts::1 7519 # Per bank write bursts +system.physmem.perBankWrBursts::2 7810 # Per bank write bursts +system.physmem.perBankWrBursts::3 7560 # Per bank write bursts +system.physmem.perBankWrBursts::4 7221 # Per bank write bursts +system.physmem.perBankWrBursts::5 6978 # Per bank write bursts +system.physmem.perBankWrBursts::6 6351 # Per bank write bursts +system.physmem.perBankWrBursts::7 6424 # Per bank write bursts +system.physmem.perBankWrBursts::8 7248 # Per bank write bursts +system.physmem.perBankWrBursts::9 6410 # Per bank write bursts +system.physmem.perBankWrBursts::10 7207 # Per bank write bursts +system.physmem.perBankWrBursts::11 6855 # Per bank write bursts +system.physmem.perBankWrBursts::12 6980 # Per bank write bursts +system.physmem.perBankWrBursts::13 7819 # Per bank write bursts +system.physmem.perBankWrBursts::14 7982 # Per bank write bursts +system.physmem.perBankWrBursts::15 7794 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 15 # Number of times write queue was full causing retry -system.physmem.totGap 1922385313500 # Total gap between requests +system.physmem.numWrRetry 23 # Number of times write queue was full causing retry +system.physmem.totGap 1941254508500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 401684 # Read request sizes (log2) +system.physmem.readPktSize::6 401645 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 115767 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 401554 # What read queue length does an incoming req see +system.physmem.writePktSize::6 115743 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 401513 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see @@ -148,195 +148,179 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5951 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7083 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6732 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 39 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64336 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 514.603333 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 307.690032 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 416.700723 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15764 24.50% 24.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11265 17.51% 42.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5118 7.96% 49.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3016 4.69% 54.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2317 3.60% 58.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1789 2.78% 61.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1464 2.28% 63.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1374 2.14% 65.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22229 34.55% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64336 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5099 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 78.750735 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2955.508201 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5096 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1824 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5414 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8014 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6616 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5981 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 87 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64921 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 509.908104 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 310.461658 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 406.215984 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15228 23.46% 23.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11644 17.94% 41.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4997 7.70% 49.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2980 4.59% 53.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2446 3.77% 57.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4228 6.51% 63.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1452 2.24% 66.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2063 3.18% 69.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19883 30.63% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64921 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5102 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 78.697570 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2954.645683 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5099 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5099 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5099 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.697980 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.062005 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 23.025558 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4477 87.80% 87.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 19 0.37% 88.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 190 3.73% 91.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 14 0.27% 92.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 27 0.53% 92.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 53 1.04% 93.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 14 0.27% 94.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 3 0.06% 94.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 6 0.12% 94.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 3 0.06% 94.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.06% 94.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 3 0.06% 94.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 8 0.16% 94.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 3 0.06% 94.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 2 0.04% 94.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 10 0.20% 94.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 4 0.08% 94.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 16 0.31% 95.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 21 0.41% 95.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 18 0.35% 95.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 148 2.90% 98.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 12 0.24% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.02% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.02% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 3 0.06% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.02% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.04% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 5 0.10% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 2 0.04% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 4 0.08% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 4 0.08% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 5 0.10% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.02% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 3 0.06% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 2 0.04% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 5 0.10% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5099 # Writes before turning the bus around for reads -system.physmem.totQLat 2147063750 # Total ticks spent queuing -system.physmem.totMemAccLat 9676463750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2007840000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5346.70 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5102 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5102 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.681105 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.154688 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.203626 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4492 88.04% 88.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 201 3.94% 91.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 29 0.57% 92.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 48 0.94% 93.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 38 0.74% 94.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 6 0.12% 94.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 11 0.22% 94.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 38 0.74% 95.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 34 0.67% 95.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 1 0.02% 96.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 159 3.12% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 2 0.04% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 2 0.04% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 5 0.10% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 1 0.02% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 2 0.04% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 3 0.06% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 3 0.06% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 4 0.08% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 8 0.16% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 4 0.08% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 3 0.06% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 2 0.04% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 4 0.08% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5102 # Writes before turning the bus around for reads +system.physmem.totQLat 2705942000 # Total ticks spent queuing +system.physmem.totMemAccLat 10234573250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2007635000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6739.13 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24096.70 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.37 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.85 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.37 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.85 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 25489.13 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.82 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.24 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.82 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.13 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.55 # Average write queue length when enqueuing -system.physmem.readRowHits 359411 # Number of row buffer hits during reads -system.physmem.writeRowHits 93558 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.50 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.82 # Row buffer hit rate for writes -system.physmem.avgGap 3715106.00 # Average gap between requests -system.physmem.pageHitRate 87.56 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 236030760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 128786625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1564680000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 372146400 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 125561429760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 64059295815 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1097244171000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1289166540360 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.604667 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1825128497250 # Time in different power states -system.physmem_0.memoryStateTime::REF 64192960000 # Time in different power states +system.physmem.avgWrQLen 24.77 # Average write queue length when enqueuing +system.physmem.readRowHits 358859 # Number of row buffer hits during reads +system.physmem.writeRowHits 93466 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.37 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.75 # Row buffer hit rate for writes +system.physmem.avgGap 3752028.47 # Average gap between requests +system.physmem.pageHitRate 87.44 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 239349600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 130597500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1564625400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 372107520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 126793670640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 71640444015 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1101913691250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1302654485925 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.035450 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1832853481750 # Time in different power states +system.physmem_0.memoryStateTime::REF 64822940000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 33072782750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 43583902000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 250349400 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 136599375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1567550400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 377829360 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 125561429760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 65774789190 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1095739352250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1289407899735 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.730219 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1822618194250 # Time in different power states -system.physmem_1.memoryStateTime::REF 64192960000 # Time in different power states +system.physmem_1.actEnergy 251453160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 137201625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1567285200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 377751600 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 126793670640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 72584952255 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1101085183500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1302797497980 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.109115 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1831469435000 # Time in different power states +system.physmem_1.memoryStateTime::REF 64822940000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 35583085750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 44967962500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9066440 # DTB read hits -system.cpu.dtb.read_misses 10312 # DTB read misses +system.cpu.dtb.read_hits 9058452 # DTB read hits +system.cpu.dtb.read_misses 10327 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728817 # DTB read accesses -system.cpu.dtb.write_hits 6357400 # DTB write hits -system.cpu.dtb.write_misses 1140 # DTB write misses +system.cpu.dtb.read_accesses 728858 # DTB read accesses +system.cpu.dtb.write_hits 6353129 # DTB write hits +system.cpu.dtb.write_misses 1143 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291929 # DTB write accesses -system.cpu.dtb.data_hits 15423840 # DTB hits -system.cpu.dtb.data_misses 11452 # DTB misses +system.cpu.dtb.write_accesses 291932 # DTB write accesses +system.cpu.dtb.data_hits 15411581 # DTB hits +system.cpu.dtb.data_misses 11470 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020746 # DTB accesses -system.cpu.itb.fetch_hits 4973902 # ITB hits -system.cpu.itb.fetch_misses 4997 # ITB misses +system.cpu.dtb.data_accesses 1020790 # DTB accesses +system.cpu.itb.fetch_hits 4975133 # ITB hits +system.cpu.itb.fetch_misses 5010 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4978899 # ITB accesses +system.cpu.itb.fetch_accesses 4980143 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -349,37 +333,37 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3844794365 # number of cpu cycles simulated +system.cpu.numCycles 3882532975 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56195121 # Number of instructions committed -system.cpu.committedOps 56195121 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52066883 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324259 # Number of float alu accesses -system.cpu.num_func_calls 1483708 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6469750 # number of instructions that are conditional controls -system.cpu.num_int_insts 52066883 # number of integer instructions -system.cpu.num_fp_insts 324259 # number of float instructions -system.cpu.num_int_register_reads 71341331 # number of times the integer registers were read -system.cpu.num_int_register_writes 38530727 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163543 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166418 # number of times the floating registers were written -system.cpu.num_mem_refs 15476411 # number of memory refs -system.cpu.num_load_insts 9103258 # Number of load instructions -system.cpu.num_store_insts 6373153 # Number of store instructions -system.cpu.num_idle_cycles 3587818415.000134 # Number of idle cycles -system.cpu.num_busy_cycles 256975949.999866 # Number of busy cycles -system.cpu.not_idle_fraction 0.066837 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.933163 # Percentage of idle cycles -system.cpu.Branches 8423975 # Number of branches fetched -system.cpu.op_class::No_OpClass 3201032 5.70% 5.70% # Class of executed instruction -system.cpu.op_class::IntAlu 36240615 64.48% 70.17% # Class of executed instruction -system.cpu.op_class::IntMult 61007 0.11% 70.28% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 70.28% # Class of executed instruction -system.cpu.op_class::FloatAdd 38081 0.07% 70.35% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 70.35% # Class of executed instruction +system.cpu.committedInsts 56143021 # Number of instructions committed +system.cpu.committedOps 56143021 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52016582 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses +system.cpu.num_func_calls 1482534 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6465507 # number of instructions that are conditional controls +system.cpu.num_int_insts 52016582 # number of integer instructions +system.cpu.num_fp_insts 324393 # number of float instructions +system.cpu.num_int_register_reads 71267420 # number of times the integer registers were read +system.cpu.num_int_register_writes 38489507 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written +system.cpu.num_mem_refs 15464199 # number of memory refs +system.cpu.num_load_insts 9095305 # Number of load instructions +system.cpu.num_store_insts 6368894 # Number of store instructions +system.cpu.num_idle_cycles 3584401371.998154 # Number of idle cycles +system.cpu.num_busy_cycles 298131603.001846 # Number of busy cycles +system.cpu.not_idle_fraction 0.076788 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.923212 # Percentage of idle cycles +system.cpu.Branches 8418668 # Number of branches fetched +system.cpu.op_class::No_OpClass 3199011 5.70% 5.70% # Class of executed instruction +system.cpu.op_class::IntAlu 36202225 64.47% 70.17% # Class of executed instruction +system.cpu.op_class::IntMult 61032 0.11% 70.27% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction +system.cpu.op_class::FloatAdd 38085 0.07% 70.34% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::FloatDiv 3636 0.01% 70.35% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 70.35% # Class of executed instruction @@ -402,34 +386,34 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 70.35% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::MemRead 9330336 16.60% 86.95% # Class of executed instruction -system.cpu.op_class::MemWrite 6379227 11.35% 98.30% # Class of executed instruction -system.cpu.op_class::IprAccess 953006 1.70% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 9322424 16.60% 86.95% # Class of executed instruction +system.cpu.op_class::MemWrite 6374975 11.35% 98.30% # Class of executed instruction +system.cpu.op_class::IprAccess 953470 1.70% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 56206940 # Class of executed instruction +system.cpu.op_class::total 56154858 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211964 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74896 40.89% 40.89% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106217 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183176 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73529 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.inst.quiesce 6377 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 212043 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74906 40.88% 40.88% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 131 0.07% 40.95% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1935 1.06% 42.01% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 106248 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183220 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73539 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73529 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149121 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1858096797000 96.66% 96.66% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 92317000 0.00% 96.66% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 743733500 0.04% 96.70% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 63463601000 3.30% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1922396448500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1935 1.30% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73539 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149144 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1860736112500 95.85% 95.85% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 92522000 0.00% 95.86% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 746030500 0.04% 95.89% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 79691088500 4.11% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1941265753500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981750 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692253 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814086 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692145 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814016 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -465,113 +449,113 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4174 2.16% 2.17% # number of callpals executed +system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175955 91.22% 93.41% # number of callpals executed -system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 175993 91.21% 93.41% # number of callpals executed +system.cpu.kern.callpal::rdps 6835 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed +system.cpu.kern.callpal::whami 2 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal::rti 5160 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192899 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5904 # number of protection mode switches -system.cpu.kern.mode_switch::user 1741 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2093 # number of protection mode switches +system.cpu.kern.callpal::total 192944 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5907 # number of protection mode switches +system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches system.cpu.kern.mode_good::kernel 1910 -system.cpu.kern.mode_good::user 1741 -system.cpu.kern.mode_good::idle 169 -system.cpu.kern.mode_switch_good::kernel 0.323509 # fraction of useful protection mode switches +system.cpu.kern.mode_good::user 1740 +system.cpu.kern.mode_good::idle 170 +system.cpu.kern.mode_switch_good::kernel 0.323345 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080745 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392278 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46413360000 2.41% 2.41% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5233781000 0.27% 2.69% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1870749305500 97.31% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4175 # number of times the context was actually changed -system.cpu.dcache.tags.replacements 1390740 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.978175 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14051600 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1391252 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 10.099968 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 112405500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.978175 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999957 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999957 # Average percentage of cache occupancy +system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392117 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 48524962500 2.50% 2.50% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5595783500 0.29% 2.79% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1887145005500 97.21% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4177 # number of times the context was actually changed +system.cpu.dcache.tags.replacements 1390004 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.973850 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 14040102 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1390516 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.097045 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 143374500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.973850 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999949 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999949 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63162665 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63162665 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7816092 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7816092 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5853262 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5853262 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183004 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183004 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199225 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199225 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13669354 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13669354 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13669354 # number of overall hits -system.cpu.dcache.overall_hits::total 13669354 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1069466 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1069466 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304560 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304560 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17244 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17244 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1374026 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1374026 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1374026 # number of overall misses -system.cpu.dcache.overall_misses::total 1374026 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 30729736500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 30729736500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11677039000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11677039000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228891000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 228891000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 42406775500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 42406775500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 42406775500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 42406775500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 8885558 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 8885558 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6157822 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6157822 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200248 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200248 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199225 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199225 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15043380 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15043380 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15043380 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15043380 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120360 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120360 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049459 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049459 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086113 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086113 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091338 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091338 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091338 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091338 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28733.719913 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28733.719913 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38340.684923 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38340.684923 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13273.660404 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13273.660404 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30863.153608 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30863.153608 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30863.153608 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30863.153608 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63112993 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63112993 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7808536 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7808536 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5849272 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5849272 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183025 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183025 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199252 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199252 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13657808 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13657808 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13657808 # number of overall hits +system.cpu.dcache.overall_hits::total 13657808 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1069028 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1069028 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304257 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304257 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17249 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17249 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1373285 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1373285 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1373285 # number of overall misses +system.cpu.dcache.overall_misses::total 1373285 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 44750637500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 44750637500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 17613913000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 17613913000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232507000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 232507000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 62364550500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 62364550500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 62364550500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 62364550500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8877564 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8877564 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6153529 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6153529 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200274 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200274 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199252 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199252 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15031093 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15031093 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15031093 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15031093 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120419 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120419 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049444 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049444 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086127 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086127 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091363 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091363 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091363 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091363 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41861.052751 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41861.052751 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57891.562068 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 57891.562068 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13479.448084 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13479.448084 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45412.678723 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45412.678723 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45412.678723 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45412.678723 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -580,120 +564,120 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 835293 # number of writebacks -system.cpu.dcache.writebacks::total 835293 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069466 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069466 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304560 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304560 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17244 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17244 # 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average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12273.660404 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29863.153608 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29863.153608 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29863.153608 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29863.153608 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209251.154401 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209251.154401 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212390.207254 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212390.207254 # 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Cycle average of tags in use +system.cpu.icache.tags.total_refs 55225516 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 929183 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 59.434488 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 58555927500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 506.358595 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.988982 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.988982 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # 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number of ReadReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9650 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9650 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16580 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16580 # number of overall MSHR uncacheable misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 364500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 364500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7775812500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7775812500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 929982000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 929982000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16967384500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16967384500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 929982000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 24743197000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25673179000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 929982000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 24743197000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25673179000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1363485500 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 46317297000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1604809000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44712488000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 46317297000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1363484500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1363484500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1939234000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1939234000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3302718500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3302718500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383601 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383601 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014276 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014276 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250273 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250273 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014276 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279458 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173286 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014276 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279458 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173286 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 28038.461538 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 28038.461538 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66560.630184 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66560.630184 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70123.812396 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70123.812396 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62386.053446 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62386.053446 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70123.812396 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63640.401032 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63854.257708 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70123.812396 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63640.401032 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63854.257708 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196751.154401 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196751.154401 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200890.207254 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200890.207254 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199160.193004 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199160.193004 # average overall mshr uncacheable latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383901 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383901 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014272 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014272 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250359 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250359 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014272 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279577 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.173296 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014272 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279577 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.173296 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70961.538462 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70961.538462 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117432.712889 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117432.712889 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120998.944432 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120998.944432 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113975.202144 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113975.202144 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120998.944432 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 115013.975311 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115211.424805 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120998.944432 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 115013.975311 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115211.424805 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196751.010101 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196751.010101 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200894.436963 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200894.436963 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199162.907797 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199162.907797 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 4638553 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2318842 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1502 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1135 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1135 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2022774 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 951075 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1744381 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2022707 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9653 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9653 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 950299 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1744757 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304543 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304543 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 928977 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1086883 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304240 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304240 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 929343 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1086450 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2786015 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4205333 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6991348 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59453248 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142553556 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 202006804 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 419801 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5075497 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.082676 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.275393 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2787117 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4203130 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6990247 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59476672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142457836 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 201934508 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 419768 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5074727 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000845 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.029056 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4655873 91.73% 91.73% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 419624 8.27% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5070439 99.92% 99.92% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4288 0.08% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5075497 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3168054500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5074727 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3166927500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 293383 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1393465500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1394014500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2098643000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2097540500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -979,9 +969,9 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51202 # Transaction distribution -system.iobus.trans_dist::WriteResp 51202 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5156 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51205 # Transaction distribution +system.iobus.trans_dist::WriteResp 51205 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5162 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -993,11 +983,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33160 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33166 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116610 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116616 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20648 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1009,11 +999,11 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 44564 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 44588 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2706172 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 4767000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2706196 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 4773000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1035,23 +1025,23 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 216066756 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 215085744 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23513000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.342844 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.339381 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1756461860000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.342844 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.083928 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.083928 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1774103808000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.339381 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.083711 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.083711 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1065,14 +1055,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21632883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21632883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4907244873 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4907244873 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21632883 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21632883 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21632883 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21632883 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21913883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21913883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5427871861 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5427871861 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21913883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21913883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21913883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21913883 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1089,14 +1079,14 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125045.566474 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125045.566474 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118098.885084 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118098.885084 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 125045.566474 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125045.566474 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 125045.566474 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125045.566474 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126669.843931 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126669.843931 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130628.414059 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130628.414059 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 126669.843931 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126669.843931 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 126669.843931 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126669.843931 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1115,14 +1105,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 173 system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12982883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12982883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2829644873 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2829644873 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12982883 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12982883 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12982883 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12982883 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13263883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13263883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3350271861 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3350271861 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 13263883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 13263883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 13263883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 13263883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1131,59 +1121,59 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75045.566474 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 75045.566474 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68098.885084 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68098.885084 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75045.566474 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75045.566474 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75045.566474 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75045.566474 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76669.843931 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76669.843931 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80628.414059 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80628.414059 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76669.843931 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76669.843931 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76669.843931 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76669.843931 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 292339 # Transaction distribution -system.membus.trans_dist::WriteReq 9650 # Transaction distribution -system.membus.trans_dist::WriteResp 9650 # Transaction distribution -system.membus.trans_dist::Writeback 115767 # Transaction distribution -system.membus.trans_dist::CleanEvict 261512 # Transaction distribution +system.membus.trans_dist::ReadResp 292325 # Transaction distribution +system.membus.trans_dist::WriteReq 9653 # Transaction distribution +system.membus.trans_dist::WriteResp 9653 # Transaction distribution +system.membus.trans_dist::Writeback 115743 # Transaction distribution +system.membus.trans_dist::CleanEvict 261495 # Transaction distribution system.membus.trans_dist::UpgradeReq 132 # Transaction distribution system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 116704 # Transaction distribution -system.membus.trans_dist::ReadExResp 116704 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 285409 # Transaction distribution +system.membus.trans_dist::ReadExReq 116679 # Transaction distribution +system.membus.trans_dist::ReadExResp 116679 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 285395 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139625 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172785 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33166 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139506 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172672 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1297602 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30459136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30503700 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1297489 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44588 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30455104 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30499692 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33161428 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33157420 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 431 # Total snoops (count) -system.membus.snoop_fanout::samples 837831 # Request fanout histogram +system.membus.snoop_fanout::samples 837762 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 837831 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 837762 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 837831 # Request fanout histogram -system.membus.reqLayer0.occupancy 30056000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 837762 # Request fanout histogram +system.membus.reqLayer0.occupancy 30061000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1285352189 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1285186893 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2143948368 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2143459620 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 72076390 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 69854947 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA |