diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha/linux')
4 files changed, 2337 insertions, 2363 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index f73eb8157..41f61bd3d 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -1,76 +1,76 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.869358 # Number of seconds simulated -sim_ticks 1869358498000 # Number of ticks simulated -final_tick 1869358498000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1869357988000 # Number of ticks simulated +final_tick 1869357988000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1016587 # Simulator instruction rate (inst/s) -host_op_rate 1016586 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 29236138105 # Simulator tick rate (ticks/s) -host_mem_usage 314344 # Number of bytes of host memory used -host_seconds 63.94 # Real time elapsed on the host -sim_insts 65000470 # Number of instructions simulated -sim_ops 65000470 # Number of ops (including micro ops) simulated +host_inst_rate 1993950 # Simulator instruction rate (inst/s) +host_op_rate 1993950 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57344769220 # Simulator tick rate (ticks/s) +host_mem_usage 333724 # Number of bytes of host memory used +host_seconds 32.60 # Real time elapsed on the host +sim_insts 64999904 # Number of instructions simulated +sim_ops 64999904 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 758272 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 66535616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 105984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 106112 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 766336 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 68167168 # Number of bytes read from this memory +system.physmem.bytes_read::total 68167296 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 758272 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 105984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 864256 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7836224 # Number of bytes written to this memory -system.physmem.bytes_written::total 7836224 # Number of bytes written to this memory +system.physmem.bytes_inst_read::cpu1.inst 106112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 864384 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7836352 # Number of bytes written to this memory +system.physmem.bytes_written::total 7836352 # Number of bytes written to this memory system.physmem.num_reads::cpu0.inst 11848 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 1039619 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1656 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1658 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 11974 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1065112 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122441 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122441 # Number of write requests responded to by this memory +system.physmem.num_reads::total 1065114 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122443 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122443 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.inst 405632 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 35592753 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 56695 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 35592763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 56764 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.data 409946 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 514 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36465540 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 36465619 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 405632 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 56695 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 462328 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4191932 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4191932 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4191932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 56764 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 462396 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4192002 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4192002 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4192002 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 405632 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 35592753 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 56695 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 35592763 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 56764 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 409946 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40657473 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 40657621 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7758839 # DTB read hits +system.cpu0.dtb.read_hits 7758808 # DTB read hits system.cpu0.dtb.read_misses 7155 # DTB read misses system.cpu0.dtb.read_acv 152 # DTB read access violations system.cpu0.dtb.read_accesses 531148 # DTB read accesses -system.cpu0.dtb.write_hits 4740268 # DTB write hits +system.cpu0.dtb.write_hits 4740251 # DTB write hits system.cpu0.dtb.write_misses 732 # DTB write misses system.cpu0.dtb.write_acv 102 # DTB write access violations system.cpu0.dtb.write_accesses 201714 # DTB write accesses -system.cpu0.dtb.data_hits 12499107 # DTB hits +system.cpu0.dtb.data_hits 12499059 # DTB hits system.cpu0.dtb.data_misses 7887 # DTB misses system.cpu0.dtb.data_acv 254 # DTB access violations system.cpu0.dtb.data_accesses 732862 # DTB accesses -system.cpu0.itb.fetch_hits 3525737 # ITB hits +system.cpu0.itb.fetch_hits 3525726 # ITB hits system.cpu0.itb.fetch_misses 3572 # ITB misses system.cpu0.itb.fetch_acv 127 # ITB acv -system.cpu0.itb.fetch_accesses 3529309 # ITB accesses +system.cpu0.itb.fetch_accesses 3529298 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -83,36 +83,36 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3738723791 # number of cpu cycles simulated +system.cpu0.numCycles 3738722771 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 150436 # number of hwrei instructions executed +system.cpu0.kern.inst.hwrei 150435 # number of hwrei instructions executed system.cpu0.kern.ipl_count::0 51398 40.00% 40.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 243 0.19% 40.18% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 243 0.19% 40.19% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1907 1.48% 41.67% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 514 0.40% 42.07% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 74447 57.93% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 128509 # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 74446 57.93% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 128508 # number of times we switched to this ipl system.cpu0.kern.ipl_good::0 51050 48.97% 48.97% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 243 0.23% 49.20% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1907 1.83% 51.03% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 514 0.49% 51.52% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 50536 48.48% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 104250 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1853222948500 99.14% 99.14% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1853222721000 99.14% 99.14% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.14% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::22 82001000 0.00% 99.14% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::30 57621500 0.00% 99.15% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 15975609500 0.85% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1869358290500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 15975327000 0.85% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1869357780500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.993229 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.678818 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.811227 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.678828 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.811234 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 6 2.63% 2.63% # number of syscalls executed system.cpu0.kern.syscall::3 20 8.77% 11.40% # number of syscalls executed system.cpu0.kern.syscall::4 2 0.88% 12.28% # number of syscalls executed @@ -152,7 +152,7 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.46% # nu system.cpu0.kern.callpal::swpctx 2743 2.02% 2.47% # number of callpals executed system.cpu0.kern.callpal::tbi 39 0.03% 2.50% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.01% 2.51% # number of callpals executed -system.cpu0.kern.callpal::swpipl 121669 89.51% 92.02% # number of callpals executed +system.cpu0.kern.callpal::swpipl 121668 89.51% 92.02% # number of callpals executed system.cpu0.kern.callpal::rdps 6149 4.52% 96.54% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.54% # number of callpals executed system.cpu0.kern.callpal::wrusp 3 0.00% 96.54% # number of callpals executed @@ -161,44 +161,44 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.55% # nu system.cpu0.kern.callpal::rti 4175 3.07% 99.62% # number of callpals executed system.cpu0.kern.callpal::callsys 369 0.27% 99.89% # number of callpals executed system.cpu0.kern.callpal::imb 146 0.11% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 135930 # number of callpals executed +system.cpu0.kern.callpal::total 135929 # number of callpals executed system.cpu0.kern.mode_switch::kernel 6593 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1174 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1173 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1173 -system.cpu0.kern.mode_good::user 1174 +system.cpu0.kern.mode_good::kernel 1172 +system.cpu0.kern.mode_good::user 1173 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.177916 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.177764 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.302176 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1868349657500 99.95% 99.95% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1008632000 0.05% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.301957 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1868349152500 99.95% 99.95% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1008627000 0.05% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 2744 # number of times the context was actually changed -system.cpu0.committedInsts 49478313 # Number of instructions committed -system.cpu0.committedOps 49478313 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 46202260 # Number of integer alu accesses +system.cpu0.committedInsts 49477745 # Number of instructions committed +system.cpu0.committedOps 49477745 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 46201705 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 197598 # Number of float alu accesses -system.cpu0.num_func_calls 1124639 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 6043708 # number of instructions that are conditional controls -system.cpu0.num_int_insts 46202260 # number of integer instructions +system.cpu0.num_func_calls 1124633 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 6043603 # number of instructions that are conditional controls +system.cpu0.num_int_insts 46201705 # number of integer instructions system.cpu0.num_fp_insts 197598 # number of float instructions -system.cpu0.num_int_register_reads 64004164 # number of times the integer registers were read -system.cpu0.num_int_register_writes 34834852 # number of times the integer registers were written +system.cpu0.num_int_register_reads 64003225 # number of times the integer registers were read +system.cpu0.num_int_register_writes 34834421 # number of times the integer registers were written system.cpu0.num_fp_register_reads 97440 # number of times the floating registers were read system.cpu0.num_fp_register_writes 98967 # number of times the floating registers were written -system.cpu0.num_mem_refs 12536155 # number of memory refs -system.cpu0.num_load_insts 7783785 # Number of load instructions -system.cpu0.num_store_insts 4752370 # Number of store instructions -system.cpu0.num_idle_cycles 3689240240.665401 # Number of idle cycles -system.cpu0.num_busy_cycles 49483550.334599 # Number of busy cycles +system.cpu0.num_mem_refs 12536107 # number of memory refs +system.cpu0.num_load_insts 7783754 # Number of load instructions +system.cpu0.num_store_insts 4752353 # Number of store instructions +system.cpu0.num_idle_cycles 3689239788.666409 # Number of idle cycles +system.cpu0.num_busy_cycles 49482982.333591 # Number of busy cycles system.cpu0.not_idle_fraction 0.013235 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.986765 # Percentage of idle cycles -system.cpu0.Branches 7530941 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2589824 5.23% 5.23% # Class of executed instruction -system.cpu0.op_class::IntAlu 33436514 67.57% 72.80% # Class of executed instruction -system.cpu0.op_class::IntMult 50547 0.10% 72.90% # Class of executed instruction +system.cpu0.Branches 7530826 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2589816 5.23% 5.23% # Class of executed instruction +system.cpu0.op_class::IntAlu 33436017 67.57% 72.80% # Class of executed instruction +system.cpu0.op_class::IntMult 50540 0.10% 72.90% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 72.90% # Class of executed instruction system.cpu0.op_class::FloatAdd 27840 0.06% 72.96% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 72.96% # Class of executed instruction @@ -226,18 +226,18 @@ system.cpu0.op_class::SimdFloatMisc 0 0.00% 72.96% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 72.96% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.96% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::MemRead 7945621 16.06% 89.02% # Class of executed instruction -system.cpu0.op_class::MemWrite 4758309 9.62% 98.63% # Class of executed instruction -system.cpu0.op_class::IprAccess 675566 1.37% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 7945590 16.06% 89.02% # Class of executed instruction +system.cpu0.op_class::MemWrite 4758292 9.62% 98.63% # Class of executed instruction +system.cpu0.op_class::IprAccess 675558 1.37% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 49486454 # Class of executed instruction -system.cpu0.dcache.tags.replacements 1781373 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.187448 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10705809 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1781885 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 6.008137 # Average number of references to valid blocks. +system.cpu0.op_class::total 49485886 # Class of executed instruction +system.cpu0.dcache.tags.replacements 1781371 # number of replacements +system.cpu0.dcache.tags.tagsinuse 506.187328 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10705763 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1781883 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 6.008118 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.187448 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.187328 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988647 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.988647 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -245,56 +245,56 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 446 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51822236 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51822236 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6068914 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6068914 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4360098 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4360098 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 127591 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 127591 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 132845 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 132845 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10429012 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10429012 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10429012 # number of overall hits -system.cpu0.dcache.overall_hits::total 10429012 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1560067 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1560067 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 236542 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 236542 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 12627 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 12627 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6925 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 6925 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1796609 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1796609 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1796609 # number of overall misses -system.cpu0.dcache.overall_misses::total 1796609 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7628981 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7628981 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4596640 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4596640 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.tags.tag_accesses 51822042 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 51822042 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6068881 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6068881 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4360085 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4360085 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 127592 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 127592 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 132849 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 132849 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10428966 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10428966 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10428966 # number of overall hits +system.cpu0.dcache.overall_hits::total 10428966 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1560069 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1560069 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 236538 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 236538 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 12626 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 12626 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6921 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 6921 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1796607 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1796607 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1796607 # number of overall misses +system.cpu0.dcache.overall_misses::total 1796607 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7628950 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7628950 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4596623 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4596623 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 140218 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 140218 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 139770 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 139770 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12225621 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12225621 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12225621 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12225621 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.204492 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.204492 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051460 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051460 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.090053 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.090053 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049546 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.049546 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.146954 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.146954 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.146954 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.146954 # miss rate for overall accesses +system.cpu0.dcache.demand_accesses::cpu0.data 12225573 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12225573 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12225573 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12225573 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.204493 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.204493 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051459 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051459 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.090046 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.090046 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049517 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.049517 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.146955 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.146955 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.146955 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.146955 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -303,16 +303,16 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 632988 # number of writebacks -system.cpu0.dcache.writebacks::total 632988 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 633127 # number of writebacks +system.cpu0.dcache.writebacks::total 633127 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 618298 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.240646 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 48867509 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 618810 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 78.970135 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 618292 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.240644 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 48866947 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 618804 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 78.969992 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 9786048500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.240646 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.240644 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998517 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.998517 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -320,26 +320,26 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 system.cpu0.icache.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 333 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 50105399 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 50105399 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 48867509 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 48867509 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 48867509 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 48867509 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 48867509 # number of overall hits -system.cpu0.icache.overall_hits::total 48867509 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 618945 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 618945 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 618945 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 618945 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 618945 # number of overall misses -system.cpu0.icache.overall_misses::total 618945 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 49486454 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 49486454 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 49486454 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 49486454 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 49486454 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 49486454 # number of overall (read+write) accesses +system.cpu0.icache.tags.tag_accesses 50104825 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 50104825 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 48866947 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 48866947 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 48866947 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 48866947 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 48866947 # number of overall hits +system.cpu0.icache.overall_hits::total 48866947 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 618939 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 618939 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 618939 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 618939 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 618939 # number of overall misses +system.cpu0.icache.overall_misses::total 618939 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 49485886 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 49485886 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 49485886 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 49485886 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 49485886 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 49485886 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012507 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.012507 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012507 # miss rate for demand accesses @@ -354,14 +354,14 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 618298 # number of writebacks -system.cpu0.icache.writebacks::total 618298 # number of writebacks +system.cpu0.icache.writebacks::writebacks 618292 # number of writebacks +system.cpu0.icache.writebacks::total 618292 # number of writebacks system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2831558 # DTB read hits +system.cpu1.dtb.read_hits 2831559 # DTB read hits system.cpu1.dtb.read_misses 3191 # DTB read misses system.cpu1.dtb.read_acv 58 # DTB read access violations system.cpu1.dtb.read_accesses 198160 # DTB read accesses @@ -369,7 +369,7 @@ system.cpu1.dtb.write_hits 2101673 # DT system.cpu1.dtb.write_misses 412 # DTB write misses system.cpu1.dtb.write_acv 55 # DTB write access violations system.cpu1.dtb.write_accesses 90619 # DTB write accesses -system.cpu1.dtb.data_hits 4933231 # DTB hits +system.cpu1.dtb.data_hits 4933232 # DTB hits system.cpu1.dtb.data_misses 3603 # DTB misses system.cpu1.dtb.data_acv 113 # DTB access violations system.cpu1.dtb.data_accesses 288779 # DTB accesses @@ -389,7 +389,7 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3738297607 # number of cpu cycles simulated +system.cpu1.numCycles 3738296587 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed @@ -405,11 +405,11 @@ system.cpu1.kern.ipl_good::22 1906 2.99% 51.49% # nu system.cpu1.kern.ipl_good::30 616 0.97% 52.46% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::31 30319 47.54% 100.00% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::total 63776 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1856124001500 99.30% 99.30% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::0 1856123490500 99.30% 99.30% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::22 81958000 0.00% 99.31% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::30 70736500 0.00% 99.31% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 12870742500 0.69% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1869147438500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 12870743500 0.69% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1869146928500 # number of cycles we spent at this ipl system.cpu1.kern.ipl_used::0 0.967808 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl @@ -461,32 +461,32 @@ system.cpu1.kern.mode_switch_good::kernel 0.434066 # f system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle 0.177356 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::total 0.358625 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 5986367000 0.32% 0.32% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::kernel 5986368000 0.32% 0.32% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::user 456602000 0.02% 0.34% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1862102855500 99.66% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1862102404500 99.66% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 2507 # number of times the context was actually changed -system.cpu1.committedInsts 15522157 # Number of instructions committed -system.cpu1.committedOps 15522157 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 14295542 # Number of integer alu accesses +system.cpu1.committedInsts 15522159 # Number of instructions committed +system.cpu1.committedOps 15522159 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 14295544 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 198941 # Number of float alu accesses system.cpu1.num_func_calls 493140 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1540067 # number of instructions that are conditional controls -system.cpu1.num_int_insts 14295542 # number of integer instructions +system.cpu1.num_conditional_control_insts 1540068 # number of instructions that are conditional controls +system.cpu1.num_int_insts 14295544 # number of integer instructions system.cpu1.num_fp_insts 198941 # number of float instructions -system.cpu1.num_int_register_reads 19514287 # number of times the integer registers were read -system.cpu1.num_int_register_writes 10457599 # number of times the integer registers were written +system.cpu1.num_int_register_reads 19514289 # number of times the integer registers were read +system.cpu1.num_int_register_writes 10457600 # number of times the integer registers were written system.cpu1.num_fp_register_reads 101734 # number of times the floating registers were read system.cpu1.num_fp_register_writes 104129 # number of times the floating registers were written -system.cpu1.num_mem_refs 4961785 # number of memory refs -system.cpu1.num_load_insts 2849089 # Number of load instructions +system.cpu1.num_mem_refs 4961786 # number of memory refs +system.cpu1.num_load_insts 2849090 # Number of load instructions system.cpu1.num_store_insts 2112696 # Number of store instructions -system.cpu1.num_idle_cycles 3722774671.474094 # Number of idle cycles -system.cpu1.num_busy_cycles 15522935.525906 # Number of busy cycles +system.cpu1.num_idle_cycles 3722773649.474793 # Number of idle cycles +system.cpu1.num_busy_cycles 15522937.525207 # Number of busy cycles system.cpu1.not_idle_fraction 0.004152 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.995848 # Percentage of idle cycles -system.cpu1.Branches 2214162 # Number of branches fetched +system.cpu1.Branches 2214163 # Number of branches fetched system.cpu1.op_class::No_OpClass 856043 5.51% 5.51% # Class of executed instruction -system.cpu1.op_class::IntAlu 9156765 58.98% 64.49% # Class of executed instruction +system.cpu1.op_class::IntAlu 9156766 58.98% 64.49% # Class of executed instruction system.cpu1.op_class::IntMult 25065 0.16% 64.65% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 64.65% # Class of executed instruction system.cpu1.op_class::FloatAdd 12426 0.08% 64.73% # Class of executed instruction @@ -515,68 +515,68 @@ system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.74% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 64.74% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.74% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::MemRead 2937015 18.92% 83.66% # Class of executed instruction +system.cpu1.op_class::MemRead 2937016 18.92% 83.66% # Class of executed instruction system.cpu1.op_class::MemWrite 2113897 13.62% 97.27% # Class of executed instruction system.cpu1.op_class::IprAccess 423253 2.73% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 15525873 # Class of executed instruction -system.cpu1.dcache.tags.replacements 201756 # number of replacements -system.cpu1.dcache.tags.tagsinuse 497.613037 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 4718402 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 202064 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 23.351027 # Average number of references to valid blocks. +system.cpu1.op_class::total 15525875 # Class of executed instruction +system.cpu1.dcache.tags.replacements 201757 # number of replacements +system.cpu1.dcache.tags.tagsinuse 497.601960 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 4718401 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 202065 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 23.350907 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 15869420000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 497.613037 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.971900 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.971900 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 497.601960 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.971879 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.971879 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.601562 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 20020602 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 20020602 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2632689 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2632689 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1954642 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1954642 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 61099 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 61099 # number of LoadLockedReq hits +system.cpu1.dcache.tags.tag_accesses 20020608 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 20020608 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 2632688 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2632688 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1954643 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1954643 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 61098 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 61098 # number of LoadLockedReq hits system.cpu1.dcache.StoreCondReq_hits::cpu1.data 64210 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 64210 # number of StoreCondReq hits system.cpu1.dcache.demand_hits::cpu1.data 4587331 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::total 4587331 # number of demand (read+write) hits system.cpu1.dcache.overall_hits::cpu1.data 4587331 # number of overall hits system.cpu1.dcache.overall_hits::total 4587331 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 140883 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 140883 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 78318 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 78318 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10999 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 10999 # number of LoadLockedReq misses +system.cpu1.dcache.ReadReq_misses::cpu1.data 140885 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 140885 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 78317 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 78317 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11000 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 11000 # number of LoadLockedReq misses system.cpu1.dcache.StoreCondReq_misses::cpu1.data 7305 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 7305 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 219201 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 219201 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 219201 # number of overall misses -system.cpu1.dcache.overall_misses::total 219201 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2773572 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2773572 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.demand_misses::cpu1.data 219202 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 219202 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 219202 # number of overall misses +system.cpu1.dcache.overall_misses::total 219202 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2773573 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2773573 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 2032960 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::total 2032960 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 72098 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 72098 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 71515 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 71515 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4806532 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4806532 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4806532 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4806532 # number of overall (read+write) accesses +system.cpu1.dcache.demand_accesses::cpu1.data 4806533 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4806533 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4806533 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4806533 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050795 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.050795 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.038524 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_miss_rate::total 0.038524 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.152556 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.152556 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.152570 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.152570 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.102146 # miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::total 0.102146 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.045605 # miss rate for demand accesses @@ -591,48 +591,48 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 144531 # number of writebacks -system.cpu1.dcache.writebacks::total 144531 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 144536 # number of writebacks +system.cpu1.dcache.writebacks::total 144536 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 380671 # number of replacements -system.cpu1.icache.tags.tagsinuse 453.133725 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 15144661 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 381183 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 39.730683 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1859779767500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 453.133725 # Average occupied blocks per requestor +system.cpu1.icache.tags.replacements 380647 # number of replacements +system.cpu1.icache.tags.tagsinuse 453.133719 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 15144687 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 381159 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 39.733253 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1859777157500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 453.133719 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.885027 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.885027 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 509 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 15907085 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 15907085 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 15144661 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 15144661 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 15144661 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 15144661 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 15144661 # number of overall hits -system.cpu1.icache.overall_hits::total 15144661 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 381212 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 381212 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 381212 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 381212 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 381212 # number of overall misses -system.cpu1.icache.overall_misses::total 381212 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 15525873 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 15525873 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 15525873 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 15525873 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 15525873 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 15525873 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024553 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024553 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024553 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024553 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024553 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024553 # miss rate for overall accesses +system.cpu1.icache.tags.tag_accesses 15907063 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 15907063 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 15144687 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 15144687 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 15144687 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 15144687 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 15144687 # number of overall hits +system.cpu1.icache.overall_hits::total 15144687 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 381188 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 381188 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 381188 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 381188 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 381188 # number of overall misses +system.cpu1.icache.overall_misses::total 381188 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 15525875 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 15525875 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 15525875 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 15525875 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 15525875 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 15525875 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024552 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024552 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024552 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024552 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024552 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024552 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -641,8 +641,8 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 380671 # number of writebacks -system.cpu1.icache.writebacks::total 380671 # number of writebacks +system.cpu1.icache.writebacks::writebacks 380647 # number of writebacks +system.cpu1.icache.writebacks::total 380647 # number of writebacks system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -687,12 +687,12 @@ system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 26616 system.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2747818 # Cumulative packet size per connected master and slave (bytes) system.iocache.tags.replacements 41699 # number of replacements -system.iocache.tags.tagsinuse 0.434101 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.434096 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 1685787163517 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.434101 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::tsunami.ide 0.434096 # Average occupied blocks per requestor system.iocache.tags.occ_percent::tsunami.ide 0.027131 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.027131 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -735,140 +735,140 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 999918 # number of replacements -system.l2c.tags.tagsinuse 65320.982415 # Cycle average of tags in use -system.l2c.tags.total_refs 4249962 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1064968 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.990695 # Average number of references to valid blocks. +system.l2c.tags.replacements 999922 # number of replacements +system.l2c.tags.tagsinuse 65337.856722 # Cycle average of tags in use +system.l2c.tags.total_refs 4259784 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1064972 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.999902 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55992.770808 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4860.291584 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4178.146657 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 175.172078 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 114.601288 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.854382 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 55997.404251 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4860.296117 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4190.275222 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 175.171528 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 114.709605 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.854453 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.074162 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.063753 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.063939 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.inst 0.002673 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.001749 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996719 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.001750 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.996977 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65050 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 768 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 3271 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 6123 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5943 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 48945 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 6047 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5933 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 49031 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.992584 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 46365909 # Number of tag accesses -system.l2c.tags.data_accesses 46365909 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 777519 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 777519 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 719211 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 719211 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 116 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 577 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 693 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 37 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 13 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 50 # number of SCUpgradeReq hits +system.l2c.tags.tag_accesses 46377222 # Number of tag accesses +system.l2c.tags.data_accesses 46377222 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 777663 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 777663 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 721478 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 721478 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 130 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 604 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 734 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 44 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 28 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 72 # number of SCUpgradeReq hits system.l2c.ReadExReq_hits::cpu0.data 111475 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 56603 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 168078 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 607076 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 379556 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 986632 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 626681 # number of ReadSharedReq hits +system.l2c.ReadExReq_hits::cpu1.data 56605 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 168080 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 607070 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 379530 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 986600 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 626719 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.data 129011 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 755692 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 607076 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 738156 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 379556 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 185614 # number of demand (read+write) hits -system.l2c.demand_hits::total 1910402 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 607076 # number of overall hits -system.l2c.overall_hits::cpu0.data 738156 # number of overall hits -system.l2c.overall_hits::cpu1.inst 379556 # number of overall hits -system.l2c.overall_hits::cpu1.data 185614 # number of overall hits -system.l2c.overall_hits::total 1910402 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 3006 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 2174 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 5180 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 1175 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1110 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2285 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 113874 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 11069 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 124943 # number of ReadExReq misses +system.l2c.ReadSharedReq_hits::total 755730 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.inst 607070 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 738194 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 379530 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 185616 # number of demand (read+write) hits +system.l2c.demand_hits::total 1910410 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 607070 # number of overall hits +system.l2c.overall_hits::cpu0.data 738194 # number of overall hits +system.l2c.overall_hits::cpu1.inst 379530 # number of overall hits +system.l2c.overall_hits::cpu1.data 185616 # number of overall hits +system.l2c.overall_hits::total 1910410 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 2989 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 2147 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 5136 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 1165 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1095 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 2260 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 113871 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 11066 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 124937 # number of ReadExReq misses system.l2c.ReadCleanReq_misses::cpu0.inst 11848 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 1656 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 13504 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 1658 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 13506 # number of ReadCleanReq misses system.l2c.ReadSharedReq_misses::cpu0.data 926615 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.data 1035 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::total 927650 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0.inst 11848 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 1040489 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1656 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 12104 # number of demand (read+write) misses -system.l2c.demand_misses::total 1066097 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 1040486 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1658 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 12101 # number of demand (read+write) misses +system.l2c.demand_misses::total 1066093 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.inst 11848 # number of overall misses -system.l2c.overall_misses::cpu0.data 1040489 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1656 # number of overall misses -system.l2c.overall_misses::cpu1.data 12104 # number of overall misses -system.l2c.overall_misses::total 1066097 # number of overall misses -system.l2c.WritebackDirty_accesses::writebacks 777519 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 777519 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 719211 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 719211 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 3122 # number of UpgradeReq accesses(hits+misses) +system.l2c.overall_misses::cpu0.data 1040486 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1658 # number of overall misses +system.l2c.overall_misses::cpu1.data 12101 # number of overall misses +system.l2c.overall_misses::total 1066093 # number of overall misses +system.l2c.WritebackDirty_accesses::writebacks 777663 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 777663 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 721478 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 721478 # number of WritebackClean accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 3119 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 2751 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 5873 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 1212 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 5870 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 1209 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 1123 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2335 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 225349 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 67672 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 293021 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 618924 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 381212 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1000136 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 1553296 # number of ReadSharedReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2332 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 225346 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 67671 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 293017 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 618918 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 381188 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1000106 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 1553334 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu1.data 130046 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 1683342 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 618924 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1778645 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 381212 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 197718 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2976499 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 618924 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1778645 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 381212 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 197718 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2976499 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.962844 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.790258 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.882002 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.969472 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.988424 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.978587 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.505323 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.163568 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.426396 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_accesses::total 1683380 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 618918 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1778680 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 381188 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 197717 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2976503 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 618918 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1778680 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 381188 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 197717 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2976503 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.958320 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.780443 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.874957 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.963606 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.975067 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.969125 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.505316 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.163526 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.426381 # miss rate for ReadExReq accesses system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.019143 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004344 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.013502 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596548 # miss rate for ReadSharedReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004350 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.013505 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596533 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.007959 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.551076 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.551064 # miss rate for ReadSharedReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.019143 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.584990 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.004344 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.061219 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.358171 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.584976 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.004350 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.061204 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.358170 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.019143 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.584990 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.004344 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.061219 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.358171 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.584976 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.004350 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.061204 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.358170 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -877,91 +877,91 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 80921 # number of writebacks -system.l2c.writebacks::total 80921 # number of writebacks +system.l2c.writebacks::writebacks 80923 # number of writebacks +system.l2c.writebacks::total 80923 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 7449 # Transaction distribution -system.membus.trans_dist::ReadResp 948782 # Transaction distribution +system.membus.trans_dist::ReadResp 948784 # Transaction distribution system.membus.trans_dist::WriteReq 14588 # Transaction distribution system.membus.trans_dist::WriteResp 14588 # Transaction distribution -system.membus.trans_dist::WritebackDirty 122441 # Transaction distribution -system.membus.trans_dist::CleanEvict 917844 # Transaction distribution -system.membus.trans_dist::UpgradeReq 19642 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 14180 # Transaction distribution -system.membus.trans_dist::UpgradeResp 8186 # Transaction distribution -system.membus.trans_dist::ReadExReq 126447 # Transaction distribution +system.membus.trans_dist::WritebackDirty 122443 # Transaction distribution +system.membus.trans_dist::CleanEvict 918012 # Transaction distribution +system.membus.trans_dist::UpgradeReq 19594 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 14154 # Transaction distribution +system.membus.trans_dist::UpgradeResp 8111 # Transaction distribution +system.membus.trans_dist::ReadExReq 125245 # Transaction distribution system.membus.trans_dist::ReadExResp 124222 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 941333 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 941335 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 44074 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3173737 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3217811 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124995 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124995 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3342806 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3172394 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3216468 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125161 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 125161 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3341629 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 86162 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73363008 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 73449170 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73363264 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 73449426 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2668736 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2668736 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 76117906 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 76118162 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2205642 # Request fanout histogram +system.membus.snoop_fanout::samples 2204372 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2205642 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2204372 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2205642 # Request fanout histogram -system.toL2Bus.snoop_filter.tot_requests 6035921 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 3018741 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 376832 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_fanout::total 2204372 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 6035855 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 3018704 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 374458 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 1611 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 1521 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 90 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 7449 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2732182 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2732156 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 14588 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 777519 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 719211 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1143412 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 19614 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 14230 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 33844 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 295246 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 295246 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1000157 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1724576 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1705094 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5410979 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1014431 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 661358 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8791862 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 69513536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155758011 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 40526016 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23357975 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 289155538 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1083512 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 7141306 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.106198 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.308338 # Request fanout histogram +system.toL2Bus.trans_dist::WritebackDirty 777663 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 998939 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1205465 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 19613 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 14226 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 33839 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 295242 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 295242 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1000127 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1724580 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1856170 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5450139 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1143023 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 684385 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 9133717 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 79182784 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155766779 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 48757440 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23358423 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 307065426 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1083516 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 7141244 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.105534 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.307488 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 6383457 89.39% 89.39% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 757309 10.60% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 6388144 89.45% 89.45% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 752560 10.54% 99.99% # Request fanout histogram system.toL2Bus.snoop_fanout::2 538 0.01% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 7141306 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 7141244 # Request fanout histogram system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index be6733354..25be00c51 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -1,51 +1,51 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.829332 # Number of seconds simulated -sim_ticks 1829332273500 # Number of ticks simulated -final_tick 1829332273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1829331993500 # Number of ticks simulated +final_tick 1829331993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 996309 # Simulator instruction rate (inst/s) -host_op_rate 996308 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 30356892493 # Simulator tick rate (ticks/s) -host_mem_usage 311076 # Number of bytes of host memory used -host_seconds 60.26 # Real time elapsed on the host -sim_insts 60038341 # Number of instructions simulated -sim_ops 60038341 # Number of ops (including micro ops) simulated +host_inst_rate 1828258 # Simulator instruction rate (inst/s) +host_op_rate 1828257 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55705727715 # Simulator tick rate (ticks/s) +host_mem_usage 331420 # Number of bytes of host memory used +host_seconds 32.84 # Real time elapsed on the host +sim_insts 60038469 # Number of instructions simulated +sim_ops 60038469 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 850496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 66835456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 66835072 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 67686912 # Number of bytes read from this memory +system.physmem.bytes_read::total 67686528 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 850496 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 850496 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7416128 # Number of bytes written to this memory -system.physmem.bytes_written::total 7416128 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 7415744 # Number of bytes written to this memory +system.physmem.bytes_written::total 7415744 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 13289 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1044304 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1044298 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1057608 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115877 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115877 # Number of write requests responded to by this memory +system.physmem.num_reads::total 1057602 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115871 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115871 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 464922 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 36535438 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 36535234 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 37000884 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 37000680 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 464922 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 464922 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4054008 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4054008 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4054008 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 4053799 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4053799 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4053799 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 464922 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 36535438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 36535234 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 525 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 41054893 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 41054479 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9710422 # DTB read hits +system.cpu.dtb.read_hits 9710423 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations system.cpu.dtb.read_accesses 728856 # DTB read accesses @@ -53,14 +53,14 @@ system.cpu.dtb.write_hits 6352496 # DT system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 16062918 # DTB hits +system.cpu.dtb.data_hits 16062919 # DTB hits system.cpu.dtb.data_misses 11471 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations system.cpu.dtb.data_accesses 1020787 # DTB accesses -system.cpu.itb.fetch_hits 4974648 # ITB hits +system.cpu.itb.fetch_hits 4974637 # ITB hits system.cpu.itb.fetch_misses 5006 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979654 # ITB accesses +system.cpu.itb.fetch_accesses 4979643 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -73,32 +73,32 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3658670905 # number of cpu cycles simulated +system.cpu.numCycles 3658670345 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed +system.cpu.kern.inst.hwrei 211318 # number of hwrei instructions executed system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105623 57.86% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182562 # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105622 57.86% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182561 # number of times we switched to this ipl system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1811929473000 99.05% 99.05% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1811929127500 99.05% 99.05% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 17302245000 0.95% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1829332066000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 17302310500 0.95% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1829331786000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.695521 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.816353 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.695527 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.816357 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -137,7 +137,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175249 91.19% 93.40% # number of callpals executed +system.cpu.kern.callpal::swpipl 175248 91.19% 93.40% # number of callpals executed system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed @@ -146,43 +146,43 @@ system.cpu.kern.callpal::whami 2 0.00% 96.93% # nu system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192180 # number of callpals executed +system.cpu.kern.callpal::total 192179 # number of callpals executed system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches -system.cpu.kern.mode_switch::user 1738 # number of protection mode switches +system.cpu.kern.mode_switch::user 1737 # number of protection mode switches system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1909 -system.cpu.kern.mode_good::user 1738 +system.cpu.kern.mode_good::kernel 1908 +system.cpu.kern.mode_good::user 1737 system.cpu.kern.mode_good::idle 171 -system.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.320726 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.390229 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 26833319500 1.47% 1.47% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1801033671500 98.45% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 0.390064 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 26833316500 1.47% 1.47% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 1465069000 0.08% 1.55% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1801033399500 98.45% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed -system.cpu.committedInsts 60038341 # Number of instructions committed -system.cpu.committedOps 60038341 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 55913563 # Number of integer alu accesses +system.cpu.committedInsts 60038469 # Number of instructions committed +system.cpu.committedOps 60038469 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 55913692 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses system.cpu.num_func_calls 1484182 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7110761 # number of instructions that are conditional controls -system.cpu.num_int_insts 55913563 # number of integer instructions +system.cpu.num_conditional_control_insts 7110791 # number of instructions that are conditional controls +system.cpu.num_int_insts 55913692 # number of integer instructions system.cpu.num_fp_insts 324460 # number of float instructions -system.cpu.num_int_register_reads 76954014 # number of times the integer registers were read -system.cpu.num_int_register_writes 41740254 # number of times the integer registers were written +system.cpu.num_int_register_reads 76954245 # number of times the integer registers were read +system.cpu.num_int_register_writes 41740352 # number of times the integer registers were written system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written -system.cpu.num_mem_refs 16115702 # number of memory refs -system.cpu.num_load_insts 9747508 # Number of load instructions +system.cpu.num_mem_refs 16115703 # number of memory refs +system.cpu.num_load_insts 9747509 # Number of load instructions system.cpu.num_store_insts 6368194 # Number of store instructions -system.cpu.num_idle_cycles 3598621691.055137 # Number of idle cycles -system.cpu.num_busy_cycles 60049213.944863 # Number of busy cycles +system.cpu.num_idle_cycles 3598621002.088897 # Number of idle cycles +system.cpu.num_busy_cycles 60049342.911103 # Number of busy cycles system.cpu.not_idle_fraction 0.016413 # Percentage of non-idle cycles system.cpu.idle_fraction 0.983587 # Percentage of idle cycles -system.cpu.Branches 9064400 # Number of branches fetched -system.cpu.op_class::No_OpClass 3199098 5.33% 5.33% # Class of executed instruction -system.cpu.op_class::IntAlu 39448273 65.69% 71.02% # Class of executed instruction +system.cpu.Branches 9064428 # Number of branches fetched +system.cpu.op_class::No_OpClass 3199100 5.33% 5.33% # Class of executed instruction +system.cpu.op_class::IntAlu 39448406 65.69% 71.02% # Class of executed instruction system.cpu.op_class::IntMult 60677 0.10% 71.12% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction system.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction @@ -211,16 +211,16 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::MemRead 9975076 16.61% 87.80% # Class of executed instruction +system.cpu.op_class::MemRead 9975077 16.61% 87.80% # Class of executed instruction system.cpu.op_class::MemWrite 6374115 10.61% 98.42% # Class of executed instruction -system.cpu.op_class::IprAccess 951217 1.58% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 951209 1.58% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 60050179 # Class of executed instruction -system.cpu.dcache.tags.replacements 2042728 # number of replacements +system.cpu.op_class::total 60050307 # Class of executed instruction +system.cpu.dcache.tags.replacements 2042707 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14038398 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2043240 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 6.870655 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 14038420 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2043219 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 6.870737 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy @@ -230,52 +230,52 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 443 system.cpu.dcache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 66369797 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 66369797 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7807758 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7807758 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5848202 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5848202 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183140 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183140 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 66369780 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 66369780 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7807771 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7807771 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5848210 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5848210 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13655960 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13655960 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13655960 # number of overall hits -system.cpu.dcache.overall_hits::total 13655960 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1721724 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1721724 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304370 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304370 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17163 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17163 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2026094 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2026094 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2026094 # number of overall misses -system.cpu.dcache.overall_misses::total 2026094 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 9529482 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9529482 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 13655981 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13655981 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13655981 # number of overall hits +system.cpu.dcache.overall_hits::total 13655981 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1721712 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1721712 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304362 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2026074 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2026074 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2026074 # number of overall misses +system.cpu.dcache.overall_misses::total 2026074 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 9529483 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9529483 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6152572 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6152572 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15682054 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15682054 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15682054 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15682054 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180673 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.180673 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049470 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049470 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085685 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085685 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.129198 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.129198 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.129198 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.129198 # miss rate for overall accesses +system.cpu.dcache.demand_accesses::cpu.data 15682055 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15682055 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15682055 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15682055 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -284,16 +284,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 833492 # number of writebacks -system.cpu.dcache.writebacks::total 833492 # number of writebacks +system.cpu.dcache.writebacks::writebacks 833475 # number of writebacks +system.cpu.dcache.writebacks::total 833475 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 919605 # number of replacements -system.cpu.icache.tags.tagsinuse 511.215260 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 59129947 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 920117 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 64.263509 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 919603 # number of replacements +system.cpu.icache.tags.tagsinuse 511.215257 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 59130077 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 920115 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 64.263790 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 9686452000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.215260 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 511.215257 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -301,26 +301,26 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 63 system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 332 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 60970411 # Number of tag accesses -system.cpu.icache.tags.data_accesses 60970411 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 59129947 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 59129947 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 59129947 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 59129947 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 59129947 # number of overall hits -system.cpu.icache.overall_hits::total 59129947 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 920232 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 920232 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 920232 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 920232 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 920232 # number of overall misses -system.cpu.icache.overall_misses::total 920232 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 60050179 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 60050179 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 60050179 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 60050179 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 60050179 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 60050179 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 60970537 # Number of tag accesses +system.cpu.icache.tags.data_accesses 60970537 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 59130077 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 59130077 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 59130077 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 59130077 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 59130077 # number of overall hits +system.cpu.icache.overall_hits::total 59130077 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 920230 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 920230 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 920230 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 920230 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 920230 # number of overall misses +system.cpu.icache.overall_misses::total 920230 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 60050307 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 60050307 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 60050307 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 60050307 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 60050307 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 60050307 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses @@ -335,18 +335,18 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 919605 # number of writebacks -system.cpu.icache.writebacks::total 919605 # number of writebacks +system.cpu.icache.writebacks::writebacks 919603 # number of writebacks +system.cpu.icache.writebacks::total 919603 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 992425 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65424.374115 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4560164 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1057588 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.311853 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 992419 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65424.374401 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4560132 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1057582 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.311847 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 56331.555575 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4843.320500 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4249.498040 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 56331.541205 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4843.327000 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 4249.506195 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.859551 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073903 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.064842 # Average percentage of cache occupancy @@ -355,75 +355,75 @@ system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 781 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3260 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4024 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3053 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54045 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3046 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54052 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 48754034 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 48754034 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 833492 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 833492 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 919353 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 919353 # number of WritebackClean hits +system.cpu.l2cache.tags.tag_accesses 48753652 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 48753652 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 833475 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 833475 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 919351 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 919351 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187288 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187288 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 906925 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 906925 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 811243 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 811243 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 906925 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 998531 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1905456 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 906925 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 998531 # number of overall hits -system.cpu.l2cache.overall_hits::total 1905456 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 187286 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187286 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 906923 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 906923 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 811230 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 811230 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 906923 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 998516 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1905439 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 906923 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 998516 # number of overall hits +system.cpu.l2cache.overall_hits::total 1905439 # number of overall hits system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 117066 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 117066 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 117060 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 117060 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13289 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 13289 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 927644 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 927644 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 13289 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1044710 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1057999 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1044704 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1057993 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 13289 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1044710 # number of overall misses -system.cpu.l2cache.overall_misses::total 1057999 # number of overall misses -system.cpu.l2cache.WritebackDirty_accesses::writebacks 833492 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 833492 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 919353 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 919353 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 1044704 # number of overall misses +system.cpu.l2cache.overall_misses::total 1057993 # number of overall misses +system.cpu.l2cache.WritebackDirty_accesses::writebacks 833475 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 833475 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 919351 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 919351 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304354 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304354 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 920214 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 920214 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1738887 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1738887 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 920214 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2043241 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2963455 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 920214 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2043241 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2963455 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304346 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 920212 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 920212 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1738874 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1738874 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 920212 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2043220 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2963432 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 920212 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2043220 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2963432 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384638 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.384638 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384628 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.384628 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014441 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014441 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.533470 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.533470 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.533474 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.533474 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014441 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.511300 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.357015 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.511303 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.357016 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014441 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.511300 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.357015 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.511303 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.357016 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -432,46 +432,46 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 74365 # number of writebacks -system.cpu.l2cache.writebacks::total 74365 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 74359 # number of writebacks +system.cpu.l2cache.writebacks::total 74359 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5925822 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2962455 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5925776 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2962432 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1834 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 1449 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1449 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 7184 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2666303 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2666288 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 833492 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 919353 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1207667 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 833475 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 919603 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1209232 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304354 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304354 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 920232 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1738887 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2759817 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6161717 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8921534 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 117733440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184157038 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 301890478 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1075994 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 7018681 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 304346 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304346 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 920230 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1738874 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2760063 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6163223 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8923286 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 117749312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184154606 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 301903918 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1075988 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 7018629 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.000744 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.027269 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 7013458 99.93% 99.93% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 7013406 99.93% 99.93% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 5223 0.07% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 7018681 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 7018629 # Request fanout histogram system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -515,12 +515,12 @@ system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 26616 system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2707742 # Cumulative packet size per connected master and slave (bytes) system.iocache.tags.replacements 41686 # number of replacements -system.iocache.tags.tagsinuse 1.225572 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.225569 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 1685780587017 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.225572 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::tsunami.ide 1.225569 # Average occupied blocks per requestor system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -567,39 +567,39 @@ system.membus.trans_dist::ReadReq 7184 # Tr system.membus.trans_dist::ReadResp 948291 # Transaction distribution system.membus.trans_dist::WriteReq 9838 # Transaction distribution system.membus.trans_dist::WriteResp 9838 # Transaction distribution -system.membus.trans_dist::WritebackDirty 115877 # Transaction distribution -system.membus.trans_dist::CleanEvict 917027 # Transaction distribution +system.membus.trans_dist::WritebackDirty 115871 # Transaction distribution +system.membus.trans_dist::CleanEvict 917188 # Transaction distribution system.membus.trans_dist::UpgradeReq 147 # Transaction distribution system.membus.trans_dist::UpgradeResp 147 # Transaction distribution -system.membus.trans_dist::ReadExReq 116931 # Transaction distribution -system.membus.trans_dist::ReadExResp 116931 # Transaction distribution +system.membus.trans_dist::ReadExReq 116925 # Transaction distribution +system.membus.trans_dist::ReadExResp 116925 # Transaction distribution system.membus.trans_dist::ReadSharedReq 941107 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3107401 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3141445 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124977 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124977 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3266422 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3107383 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3141427 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125138 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 125138 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3266565 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72462656 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72508782 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72461888 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72508014 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2667904 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2667904 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 75176686 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 75175918 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2149824 # Request fanout histogram +system.membus.snoop_fanout::samples 2149812 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2149824 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2149812 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2149824 # Request fanout histogram +system.membus.snoop_fanout::total 2149812 # Request fanout histogram system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index a1e8c67e3..965d378dd 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,118 +1,118 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.982594 # Number of seconds simulated -sim_ticks 1982594146000 # Number of ticks simulated -final_tick 1982594146000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.982593 # Number of seconds simulated +sim_ticks 1982593132000 # Number of ticks simulated +final_tick 1982593132000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 452083 # Simulator instruction rate (inst/s) -host_op_rate 452083 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 14696000274 # Simulator tick rate (ticks/s) -host_mem_usage 314492 # Number of bytes of host memory used -host_seconds 134.91 # Real time elapsed on the host -sim_insts 60989111 # Number of instructions simulated -sim_ops 60989111 # Number of ops (including micro ops) simulated +host_inst_rate 1109655 # Simulator instruction rate (inst/s) +host_op_rate 1109654 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36063876778 # Simulator tick rate (ticks/s) +host_mem_usage 333984 # Number of bytes of host memory used +host_seconds 54.97 # Real time elapsed on the host +sim_insts 61002651 # Number of instructions simulated +sim_ops 61002651 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 800320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24686528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 60096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 523456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 800256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24686464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 59392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 523264 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26071360 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 800320 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 60096 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 860416 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7740160 # Number of bytes written to this memory -system.physmem.bytes_written::total 7740160 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12505 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 385727 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 939 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8179 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26070336 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 800256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 59392 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 859648 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7739904 # Number of bytes written to this memory +system.physmem.bytes_written::total 7739904 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12504 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 385726 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 928 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8176 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 407365 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120940 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120940 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 403673 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12451630 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 30312 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 264026 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 407349 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120936 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120936 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 403641 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12451604 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 29957 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 263929 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 484 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13150125 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 403673 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 30312 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 433985 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3904057 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3904057 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3904057 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 403673 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12451630 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 30312 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 264026 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13149615 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 403641 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 29957 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 433598 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3903930 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3903930 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3903930 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 403641 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12451604 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 29957 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 263929 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 484 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17054181 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 407365 # Number of read requests accepted -system.physmem.writeReqs 120940 # Number of write requests accepted -system.physmem.readBursts 407365 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 120940 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26063552 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7808 # Total number of bytes read from write queue -system.physmem.bytesWritten 7739008 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26071360 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7740160 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 122 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 17053544 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 407349 # Number of read requests accepted +system.physmem.writeReqs 120936 # Number of write requests accepted +system.physmem.readBursts 407349 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 120936 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26062656 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue +system.physmem.bytesWritten 7738112 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26070336 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7739904 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 310700 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 25226 # Per bank write bursts system.physmem.perBankRdBursts::1 25379 # Per bank write bursts -system.physmem.perBankRdBursts::2 25426 # Per bank write bursts -system.physmem.perBankRdBursts::3 24856 # Per bank write bursts +system.physmem.perBankRdBursts::2 25428 # Per bank write bursts +system.physmem.perBankRdBursts::3 24855 # Per bank write bursts system.physmem.perBankRdBursts::4 25157 # Per bank write bursts system.physmem.perBankRdBursts::5 25423 # Per bank write bursts -system.physmem.perBankRdBursts::6 25497 # Per bank write bursts -system.physmem.perBankRdBursts::7 25344 # Per bank write bursts +system.physmem.perBankRdBursts::6 25496 # Per bank write bursts +system.physmem.perBankRdBursts::7 25345 # Per bank write bursts system.physmem.perBankRdBursts::8 25239 # Per bank write bursts system.physmem.perBankRdBursts::9 25589 # Per bank write bursts -system.physmem.perBankRdBursts::10 25746 # Per bank write bursts -system.physmem.perBankRdBursts::11 25918 # Per bank write bursts +system.physmem.perBankRdBursts::10 25733 # Per bank write bursts +system.physmem.perBankRdBursts::11 25919 # Per bank write bursts system.physmem.perBankRdBursts::12 25947 # Per bank write bursts system.physmem.perBankRdBursts::13 25572 # Per bank write bursts system.physmem.perBankRdBursts::14 25277 # Per bank write bursts -system.physmem.perBankRdBursts::15 25647 # Per bank write bursts -system.physmem.perBankWrBursts::0 7851 # Per bank write bursts +system.physmem.perBankRdBursts::15 25644 # Per bank write bursts +system.physmem.perBankWrBursts::0 7850 # Per bank write bursts system.physmem.perBankWrBursts::1 7778 # Per bank write bursts system.physmem.perBankWrBursts::2 7471 # Per bank write bursts -system.physmem.perBankWrBursts::3 6887 # Per bank write bursts +system.physmem.perBankWrBursts::3 6886 # Per bank write bursts system.physmem.perBankWrBursts::4 7104 # Per bank write bursts system.physmem.perBankWrBursts::5 7345 # Per bank write bursts -system.physmem.perBankWrBursts::6 7441 # Per bank write bursts -system.physmem.perBankWrBursts::7 7150 # Per bank write bursts +system.physmem.perBankWrBursts::6 7430 # Per bank write bursts +system.physmem.perBankWrBursts::7 7151 # Per bank write bursts system.physmem.perBankWrBursts::8 7161 # Per bank write bursts system.physmem.perBankWrBursts::9 7315 # Per bank write bursts system.physmem.perBankWrBursts::10 7729 # Per bank write bursts -system.physmem.perBankWrBursts::11 8151 # Per bank write bursts +system.physmem.perBankWrBursts::11 8152 # Per bank write bursts system.physmem.perBankWrBursts::12 8256 # Per bank write bursts system.physmem.perBankWrBursts::13 7924 # Per bank write bursts system.physmem.perBankWrBursts::14 7541 # Per bank write bursts -system.physmem.perBankWrBursts::15 7818 # Per bank write bursts +system.physmem.perBankWrBursts::15 7815 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 19 # Number of times write queue was full causing retry -system.physmem.totGap 1982586778500 # Total gap between requests +system.physmem.numWrRetry 11 # Number of times write queue was full causing retry +system.physmem.totGap 1982585764500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 407365 # Read request sizes (log2) +system.physmem.readPktSize::6 407349 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 120940 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 407167 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 63 # What read queue length does an incoming req see +system.physmem.writePktSize::6 120936 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 407149 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 67 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see @@ -158,125 +158,112 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1876 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5780 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6579 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8718 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5622 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1879 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7458 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8528 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7538 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 66 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 76 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 67594 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 500.082256 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 302.770491 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 404.772373 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16306 24.12% 24.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 12315 18.22% 42.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5219 7.72% 50.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3345 4.95% 55.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2482 3.67% 58.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4236 6.27% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1519 2.25% 67.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2145 3.17% 70.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20027 29.63% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 67594 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5426 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 75.053815 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2863.944316 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5423 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::63 30 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 67582 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 500.144536 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 302.732498 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 404.890859 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16271 24.08% 24.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 12393 18.34% 42.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5170 7.65% 50.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3294 4.87% 54.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2518 3.73% 58.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4277 6.33% 64.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1487 2.20% 67.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2102 3.11% 70.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20070 29.70% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 67582 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5413 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 75.229078 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2867.379606 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5410 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5426 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5426 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.285662 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.994987 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.002081 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4792 88.32% 88.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 23 0.42% 88.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 16 0.29% 89.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 184 3.39% 92.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 1 0.02% 92.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 19 0.35% 92.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 45 0.83% 93.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 3 0.06% 93.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 7 0.13% 93.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 30 0.55% 94.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 7 0.13% 94.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 4 0.07% 94.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 5 0.09% 94.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 4 0.07% 94.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 20 0.37% 95.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 26 0.48% 95.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 28 0.52% 96.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.02% 96.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 4 0.07% 96.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.02% 96.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 168 3.10% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.02% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.04% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 1 0.02% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.02% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.04% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.04% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 5 0.09% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 5 0.09% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 10 0.18% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 3 0.06% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5426 # Writes before turning the bus around for reads -system.physmem.totQLat 2787487250 # Total ticks spent queuing -system.physmem.totMemAccLat 10423293500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2036215000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6844.78 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5413 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5413 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.336597 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.167195 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 20.176387 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4808 88.82% 88.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 29 0.54% 89.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 21 0.39% 89.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 46 0.85% 90.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 212 3.92% 94.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 15 0.28% 94.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 14 0.26% 95.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 26 0.48% 95.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 189 3.49% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 5 0.09% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 5 0.09% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 4 0.07% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 5 0.09% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 2 0.04% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 4 0.07% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 1 0.02% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 1 0.02% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 8 0.15% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 1 0.02% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 2 0.04% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 3 0.06% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 8 0.15% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 2 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 2 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5413 # Writes before turning the bus around for reads +system.physmem.totQLat 2790032750 # Total ticks spent queuing +system.physmem.totMemAccLat 10425576500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2036145000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6851.26 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25594.78 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25601.26 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.15 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.90 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.15 # Average system read bandwidth in MiByte/s @@ -286,62 +273,62 @@ system.physmem.busUtil 0.13 # Da system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.89 # Average write queue length when enqueuing -system.physmem.readRowHits 363847 # Number of row buffer hits during reads -system.physmem.writeRowHits 96724 # Number of row buffer hits during writes +system.physmem.avgWrQLen 24.37 # Average write queue length when enqueuing +system.physmem.readRowHits 363813 # Number of row buffer hits during reads +system.physmem.writeRowHits 96742 # Number of row buffer hits during writes system.physmem.readRowHitRate 89.34 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.98 # Row buffer hit rate for writes -system.physmem.avgGap 3752731.43 # Average gap between requests +system.physmem.writeRowHitRate 79.99 # Row buffer hit rate for writes +system.physmem.avgGap 3752871.58 # Average gap between requests system.physmem.pageHitRate 87.20 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 243930960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 133097250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1578002400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 382494960 # Energy for write commands per rank (pJ) +system.physmem_0.actEnergy 244006560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 133138500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1578010200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 382417200 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 129493107120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 72912858435 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1125595195500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1330338686625 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.010578 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1872246434250 # Time in different power states +system.physmem_0.actBackEnergy 72939489120 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1125571835250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1330342003950 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.012251 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1872206783000 # Time in different power states system.physmem_0.memoryStateTime::REF 66203020000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 44140298250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 44179949500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 267079680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 145728000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1598493000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 401079600 # Energy for write commands per rank (pJ) +system.physmem_1.actEnergy 266913360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 145637250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1598376000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 401066640 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 129493107120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 73974222945 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1124664165750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1330543876095 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.114078 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1870697169250 # Time in different power states +system.physmem_1.actBackEnergy 73838725110 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1124783023500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1330526848980 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.105490 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1870895185000 # Time in different power states system.physmem_1.memoryStateTime::REF 66203020000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 45689549500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 45491533750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7416215 # DTB read hits +system.cpu0.dtb.read_hits 7416541 # DTB read hits system.cpu0.dtb.read_misses 7442 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 490672 # DTB read accesses -system.cpu0.dtb.write_hits 5004240 # DTB write hits +system.cpu0.dtb.write_hits 5004457 # DTB write hits system.cpu0.dtb.write_misses 812 # DTB write misses system.cpu0.dtb.write_acv 134 # DTB write access violations system.cpu0.dtb.write_accesses 187451 # DTB write accesses -system.cpu0.dtb.data_hits 12420455 # DTB hits +system.cpu0.dtb.data_hits 12420998 # DTB hits system.cpu0.dtb.data_misses 8254 # DTB misses system.cpu0.dtb.data_acv 344 # DTB access violations system.cpu0.dtb.data_accesses 678123 # DTB accesses -system.cpu0.itb.fetch_hits 3482237 # ITB hits +system.cpu0.itb.fetch_hits 3482402 # ITB hits system.cpu0.itb.fetch_misses 3871 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3486108 # ITB accesses +system.cpu0.itb.fetch_accesses 3486273 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -354,36 +341,36 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3964851893 # number of cpu cycles simulated +system.cpu0.numCycles 3964851877 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6804 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 162792 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6803 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 162801 # number of hwrei instructions executed system.cpu0.kern.ipl_count::0 55926 40.12% 40.12% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.21% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 133 0.10% 40.21% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1977 1.42% 41.63% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 435 0.31% 41.94% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 80934 58.06% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 139403 # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 80941 58.06% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 139412 # number of times we switched to this ipl system.cpu0.kern.ipl_good::0 55417 49.07% 49.07% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.12% 49.18% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 133 0.12% 49.18% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1977 1.75% 50.93% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 435 0.39% 51.32% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 54982 48.68% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 112942 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1904792162000 96.08% 96.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 93245000 0.00% 96.09% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 790775500 0.04% 96.13% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 326471500 0.02% 96.14% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 76423262500 3.86% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1982425916500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_good::31 54983 48.68% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 112945 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1904793300500 96.08% 96.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 93813000 0.00% 96.09% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 790638500 0.04% 96.13% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 326474000 0.02% 96.15% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 76421682500 3.85% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1982425908500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.990899 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.679344 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810183 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.679297 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810153 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed @@ -422,54 +409,54 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # nu system.cpu0.kern.callpal::swpctx 3024 2.05% 2.41% # number of callpals executed system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed -system.cpu0.kern.callpal::swpipl 132535 89.80% 92.24% # number of callpals executed +system.cpu0.kern.callpal::swpipl 132542 89.80% 92.24% # number of callpals executed system.cpu0.kern.callpal::rdps 6593 4.47% 96.71% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.71% # number of callpals executed system.cpu0.kern.callpal::wrusp 3 0.00% 96.71% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.01% 96.72% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 96.72% # number of callpals executed -system.cpu0.kern.callpal::rti 4324 2.93% 99.65% # number of callpals executed +system.cpu0.kern.callpal::rti 4325 2.93% 99.65% # number of callpals executed system.cpu0.kern.callpal::callsys 381 0.26% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 147594 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6862 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1281 # number of protection mode switches +system.cpu0.kern.callpal::total 147602 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6863 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1282 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1281 -system.cpu0.kern.mode_good::user 1281 +system.cpu0.kern.mode_good::kernel 1282 +system.cpu0.kern.mode_good::user 1282 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.186680 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.186799 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.314626 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1977686351500 99.80% 99.80% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3896829000 0.20% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.314794 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1977682087000 99.80% 99.80% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3901070000 0.20% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 3025 # number of times the context was actually changed -system.cpu0.committedInsts 47311851 # Number of instructions committed -system.cpu0.committedOps 47311851 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 43882265 # Number of integer alu accesses +system.cpu0.committedInsts 47316172 # Number of instructions committed +system.cpu0.committedOps 47316172 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 43886449 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 206939 # Number of float alu accesses -system.cpu0.num_func_calls 1185568 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5564719 # number of instructions that are conditional controls -system.cpu0.num_int_insts 43882265 # number of integer instructions +system.cpu0.num_func_calls 1185652 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5565345 # number of instructions that are conditional controls +system.cpu0.num_int_insts 43886449 # number of integer instructions system.cpu0.num_fp_insts 206939 # number of float instructions -system.cpu0.num_int_register_reads 60327433 # number of times the integer registers were read -system.cpu0.num_int_register_writes 32715156 # number of times the integer registers were written +system.cpu0.num_int_register_reads 60334275 # number of times the integer registers were read +system.cpu0.num_int_register_writes 32718467 # number of times the integer registers were written system.cpu0.num_fp_register_reads 100516 # number of times the floating registers were read system.cpu0.num_fp_register_writes 102286 # number of times the floating registers were written -system.cpu0.num_mem_refs 12460349 # number of memory refs -system.cpu0.num_load_insts 7443153 # Number of load instructions -system.cpu0.num_store_insts 5017196 # Number of store instructions -system.cpu0.num_idle_cycles 3699958327.970898 # Number of idle cycles -system.cpu0.num_busy_cycles 264893565.029101 # Number of busy cycles -system.cpu0.not_idle_fraction 0.066810 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.933190 # Percentage of idle cycles -system.cpu0.Branches 7132898 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2702955 5.71% 5.71% # Class of executed instruction -system.cpu0.op_class::IntAlu 31171442 65.87% 71.59% # Class of executed instruction -system.cpu0.op_class::IntMult 51645 0.11% 71.69% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.69% # Class of executed instruction +system.cpu0.num_mem_refs 12460893 # number of memory refs +system.cpu0.num_load_insts 7443480 # Number of load instructions +system.cpu0.num_store_insts 5017413 # Number of store instructions +system.cpu0.num_idle_cycles 3699956428.707181 # Number of idle cycles +system.cpu0.num_busy_cycles 264895448.292820 # Number of busy cycles +system.cpu0.not_idle_fraction 0.066811 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.933189 # Percentage of idle cycles +system.cpu0.Branches 7133641 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2703037 5.71% 5.71% # Class of executed instruction +system.cpu0.op_class::IntAlu 31175022 65.87% 71.59% # Class of executed instruction +system.cpu0.op_class::IntMult 51696 0.11% 71.70% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 71.70% # Class of executed instruction system.cpu0.op_class::FloatAdd 25566 0.05% 71.75% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 71.75% # Class of executed instruction system.cpu0.op_class::FloatCvt 0 0.00% 71.75% # Class of executed instruction @@ -496,98 +483,98 @@ system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.75% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 71.75% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.75% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::MemRead 7616230 16.10% 87.85% # Class of executed instruction -system.cpu0.op_class::MemWrite 5023298 10.62% 98.46% # Class of executed instruction -system.cpu0.op_class::IprAccess 727657 1.54% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 7616572 16.09% 87.85% # Class of executed instruction +system.cpu0.op_class::MemWrite 5023515 10.61% 98.46% # Class of executed instruction +system.cpu0.op_class::IprAccess 727706 1.54% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 47320449 # Class of executed instruction -system.cpu0.dcache.tags.replacements 1172797 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.333348 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11236424 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1173216 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.577455 # Average number of references to valid blocks. +system.cpu0.op_class::total 47324770 # Class of executed instruction +system.cpu0.dcache.tags.replacements 1172753 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.332741 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11237004 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1173173 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.578301 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 144706500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.333348 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986979 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986979 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 419 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.332741 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986978 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986978 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 420 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 371 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.818359 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 50906675 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 50906675 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6342506 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6342506 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4600881 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4600881 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138108 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 138108 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145430 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 145430 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10943387 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10943387 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10943387 # number of overall hits -system.cpu0.dcache.overall_hits::total 10943387 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 934212 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 934212 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 249094 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 249094 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13595 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13595 # number of LoadLockedReq misses +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 372 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.820312 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 50908772 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 50908772 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6342827 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6342827 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4601104 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4601104 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138127 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 138127 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145435 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 145435 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10943931 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10943931 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10943931 # number of overall hits +system.cpu0.dcache.overall_hits::total 10943931 # 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number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 42884699000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 42884699000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 16803448000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 16803448000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 151690000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 151690000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 97426500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 97426500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 59688147000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 59688147000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 59688147000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 59688147000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7276718 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7276718 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4849975 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4849975 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 151703 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 151703 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 151169 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 151169 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12126693 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12126693 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12126693 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12126693 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.128384 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.128384 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051360 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051360 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.089616 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.089616 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037964 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037964 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097579 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.097579 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097579 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097579 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 45904.675812 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 45904.675812 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 67458.260737 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 67458.260737 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11157.778595 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11157.778595 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 16976.215369 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16976.215369 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50441.852741 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 50441.852741 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50441.852741 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 50441.852741 # average overall miss latency +system.cpu0.dcache.demand_misses::cpu0.data 1183287 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1183287 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1183287 # number of overall misses +system.cpu0.dcache.overall_misses::total 1183287 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 42886334500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 42886334500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 16793569500 # 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number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.128378 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.128378 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051355 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051355 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.089515 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.089515 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037963 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037963 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097573 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.097573 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097573 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.097573 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 45906.623043 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 45906.623043 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 67422.663091 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 67422.663091 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11175.294551 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11175.294551 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 16514.288204 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16514.288204 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50435.696496 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 50435.696496 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50435.696496 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 50435.696496 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -596,126 +583,126 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 672822 # number of writebacks -system.cpu0.dcache.writebacks::total 672822 # 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number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 91687500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 58504841000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 58504841000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 58504841000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 58504841000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1566158000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1566158000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2451078500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2451078500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4017236500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4017236500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128384 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128384 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051360 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051360 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.089616 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.089616 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037964 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037964 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097579 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097579 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097579 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097579 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 44904.675812 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 44904.675812 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 66458.260737 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 66458.260737 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10157.778595 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10157.778595 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 15976.215369 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15976.215369 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 49441.852741 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 49441.852741 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 49441.852741 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 49441.852741 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221208.757062 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221208.757062 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227372.773655 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227372.773655 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 224929.255319 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 224929.255319 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1183287 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1183287 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1183287 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1183287 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7086 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7086 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10784 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10784 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17870 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17870 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 41952126500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 41952126500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 16544490500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 16544490500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 138180500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 138180500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 89036500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 89036500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 58496617000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 58496617000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 58496617000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 58496617000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1567540500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1567540500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2452068500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2452068500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4019609000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4019609000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128378 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128378 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051355 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051355 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.089515 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.089515 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037963 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037963 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097573 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097573 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097573 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097573 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 44906.623043 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 44906.623043 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 66422.663091 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 66422.663091 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10175.294551 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10175.294551 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 15514.288204 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15514.288204 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 49435.696496 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 49435.696496 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 49435.696496 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 49435.696496 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221216.553768 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221216.553768 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227380.239243 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227380.239243 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 224936.149972 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 224936.149972 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 686460 # number of replacements -system.cpu0.icache.tags.tagsinuse 506.490701 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 46633355 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 686972 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.882468 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 686592 # number of replacements +system.cpu0.icache.tags.tagsinuse 506.490691 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 46637544 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 687104 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.875524 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 58998281500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 506.490701 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 506.490691 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.989240 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.989240 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 417 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 48007543 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 48007543 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 46633355 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 46633355 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 46633355 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 46633355 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 46633355 # number of overall hits -system.cpu0.icache.overall_hits::total 46633355 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 687094 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 687094 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 687094 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 687094 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 687094 # number of overall misses -system.cpu0.icache.overall_misses::total 687094 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10621840000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10621840000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10621840000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10621840000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10621840000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10621840000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47320449 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47320449 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47320449 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47320449 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47320449 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47320449 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014520 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014520 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014520 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014520 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014520 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014520 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15459.078379 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 15459.078379 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15459.078379 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 15459.078379 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15459.078379 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 15459.078379 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 48011996 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 48011996 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 46637544 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 46637544 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 46637544 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 46637544 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 46637544 # number of overall hits +system.cpu0.icache.overall_hits::total 46637544 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 687226 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 687226 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 687226 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 687226 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 687226 # number of overall misses +system.cpu0.icache.overall_misses::total 687226 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10626395500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10626395500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10626395500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10626395500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10626395500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10626395500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47324770 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47324770 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47324770 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47324770 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47324770 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47324770 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014521 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014521 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014521 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014521 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014521 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014521 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15462.737877 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 15462.737877 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15462.737877 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 15462.737877 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15462.737877 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 15462.737877 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -724,53 +711,53 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 686460 # number of writebacks -system.cpu0.icache.writebacks::total 686460 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 687094 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 687094 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 687094 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 687094 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 687094 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 687094 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9934746000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9934746000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9934746000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9934746000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9934746000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9934746000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014520 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014520 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014520 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014520 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014520 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014520 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14459.078379 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14459.078379 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14459.078379 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 14459.078379 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14459.078379 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 14459.078379 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 686592 # number of writebacks +system.cpu0.icache.writebacks::total 686592 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 687226 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 687226 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 687226 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 687226 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 687226 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 687226 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9939169500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9939169500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9939169500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9939169500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9939169500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9939169500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014521 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014521 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014521 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014521 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014521 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014521 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14462.737877 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14462.737877 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14462.737877 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 14462.737877 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14462.737877 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 14462.737877 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2510685 # DTB read hits +system.cpu1.dtb.read_hits 2511145 # DTB read hits system.cpu1.dtb.read_misses 2993 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 239364 # DTB read accesses -system.cpu1.dtb.write_hits 1829711 # DTB write hits +system.cpu1.dtb.write_hits 1829996 # DTB write hits system.cpu1.dtb.write_misses 342 # DTB write misses system.cpu1.dtb.write_acv 29 # DTB write access violations system.cpu1.dtb.write_accesses 105248 # DTB write accesses -system.cpu1.dtb.data_hits 4340396 # DTB hits +system.cpu1.dtb.data_hits 4341141 # DTB hits system.cpu1.dtb.data_misses 3335 # DTB misses system.cpu1.dtb.data_acv 29 # DTB access violations system.cpu1.dtb.data_accesses 344612 # DTB accesses -system.cpu1.itb.fetch_hits 1990327 # ITB hits +system.cpu1.itb.fetch_hits 1990273 # ITB hits system.cpu1.itb.fetch_misses 1216 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1991543 # ITB accesses +system.cpu1.itb.fetch_accesses 1991489 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -783,32 +770,32 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3965188292 # number of cpu cycles simulated +system.cpu1.numCycles 3965186264 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2870 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 81053 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 27549 38.53% 38.53% # number of times we switched to this ipl +system.cpu1.kern.inst.quiesce 2869 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 81047 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 27546 38.52% 38.52% # number of times we switched to this ipl system.cpu1.kern.ipl_count::22 1971 2.76% 41.28% # number of times we switched to this ipl system.cpu1.kern.ipl_count::30 524 0.73% 42.01% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 41464 57.99% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 71508 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 26681 48.22% 48.22% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_count::31 41461 57.99% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 71502 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 26678 48.22% 48.22% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::22 1971 3.56% 51.78% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::30 524 0.95% 52.73% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 26157 47.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 55333 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1912242644500 96.45% 96.45% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 731132000 0.04% 96.49% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 374834500 0.02% 96.51% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 69244798000 3.49% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1982593409000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.968493 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_good::31 26154 47.27% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 55327 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1912240588500 96.45% 96.45% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 731240000 0.04% 96.49% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 374509500 0.02% 96.51% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 69246057000 3.49% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1982592395000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.968489 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.630836 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.773802 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.630810 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.773783 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed @@ -827,10 +814,10 @@ system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu1.kern.callpal::wripir 435 0.59% 0.59% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed -system.cpu1.kern.callpal::swpctx 2066 2.79% 3.38% # number of callpals executed +system.cpu1.kern.callpal::swpctx 2066 2.79% 3.39% # number of callpals executed system.cpu1.kern.callpal::tbi 3 0.00% 3.39% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 3.40% # number of callpals executed -system.cpu1.kern.callpal::swpipl 65186 88.12% 91.52% # number of callpals executed +system.cpu1.kern.callpal::swpipl 65180 88.12% 91.52% # number of callpals executed system.cpu1.kern.callpal::rdps 2261 3.06% 94.57% # number of callpals executed system.cpu1.kern.callpal::wrkgp 1 0.00% 94.57% # number of callpals executed system.cpu1.kern.callpal::wrusp 4 0.01% 94.58% # number of callpals executed @@ -839,164 +826,164 @@ system.cpu1.kern.callpal::rti 3826 5.17% 99.76% # nu system.cpu1.kern.callpal::callsys 136 0.18% 99.94% # number of callpals executed system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 73976 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2114 # number of protection mode switches +system.cpu1.kern.callpal::total 73970 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2115 # number of protection mode switches system.cpu1.kern.mode_switch::user 464 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2922 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2921 # number of protection mode switches system.cpu1.kern.mode_good::kernel 912 system.cpu1.kern.mode_good::user 464 system.cpu1.kern.mode_good::idle 448 -system.cpu1.kern.mode_switch_good::kernel 0.431410 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.431206 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.153320 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::idle 0.153372 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::total 0.331636 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 19465916000 0.98% 0.98% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1729420000 0.09% 1.07% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1961398071000 98.93% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::kernel 19470103000 0.98% 0.98% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1729907500 0.09% 1.07% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1961392382500 98.93% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 2067 # number of times the context was actually changed -system.cpu1.committedInsts 13677260 # Number of instructions committed -system.cpu1.committedOps 13677260 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 12615003 # Number of integer alu accesses +system.cpu1.committedInsts 13686479 # Number of instructions committed +system.cpu1.committedOps 13686479 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 12624111 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 178612 # Number of float alu accesses -system.cpu1.num_func_calls 430048 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1358006 # number of instructions that are conditional controls -system.cpu1.num_int_insts 12615003 # number of integer instructions +system.cpu1.num_func_calls 430158 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1359705 # number of instructions that are conditional controls +system.cpu1.num_int_insts 12624111 # number of integer instructions system.cpu1.num_fp_insts 178612 # number of float instructions -system.cpu1.num_int_register_reads 17367613 # number of times the integer registers were read -system.cpu1.num_int_register_writes 9253143 # number of times the integer registers were written +system.cpu1.num_int_register_reads 17383206 # number of times the integer registers were read +system.cpu1.num_int_register_writes 9260208 # number of times the integer registers were written system.cpu1.num_fp_register_reads 93246 # number of times the floating registers were read system.cpu1.num_fp_register_writes 95234 # number of times the floating registers were written -system.cpu1.num_mem_refs 4364552 # number of memory refs -system.cpu1.num_load_insts 2525340 # Number of load instructions -system.cpu1.num_store_insts 1839212 # Number of store instructions -system.cpu1.num_idle_cycles 3912229588.998027 # Number of idle cycles -system.cpu1.num_busy_cycles 52958703.001973 # Number of busy cycles -system.cpu1.not_idle_fraction 0.013356 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.986644 # Percentage of idle cycles -system.cpu1.Branches 1948315 # Number of branches fetched -system.cpu1.op_class::No_OpClass 733682 5.36% 5.36% # Class of executed instruction -system.cpu1.op_class::IntAlu 8093046 59.16% 64.52% # Class of executed instruction -system.cpu1.op_class::IntMult 23046 0.17% 64.69% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.69% # Class of executed instruction -system.cpu1.op_class::FloatAdd 14372 0.11% 64.79% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1986 0.01% 64.81% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::MemRead 2600021 19.01% 83.81% # Class of executed instruction -system.cpu1.op_class::MemWrite 1840236 13.45% 97.26% # Class of executed instruction -system.cpu1.op_class::IprAccess 374235 2.74% 100.00% # Class of executed instruction +system.cpu1.num_mem_refs 4365297 # number of memory refs +system.cpu1.num_load_insts 2525800 # Number of load instructions +system.cpu1.num_store_insts 1839497 # Number of store instructions +system.cpu1.num_idle_cycles 3912233484.998027 # Number of idle cycles +system.cpu1.num_busy_cycles 52952779.001973 # Number of busy cycles +system.cpu1.not_idle_fraction 0.013354 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.986646 # Percentage of idle cycles +system.cpu1.Branches 1950120 # Number of branches fetched +system.cpu1.op_class::No_OpClass 733810 5.36% 5.36% # Class of executed instruction +system.cpu1.op_class::IntAlu 8101284 59.18% 64.54% # Class of executed instruction +system.cpu1.op_class::IntMult 23184 0.17% 64.71% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.71% # Class of executed instruction +system.cpu1.op_class::FloatAdd 14372 0.10% 64.81% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1986 0.01% 64.83% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::MemRead 2600475 19.00% 83.82% # Class of executed instruction +system.cpu1.op_class::MemWrite 1840521 13.44% 97.27% # Class of executed instruction +system.cpu1.op_class::IprAccess 374211 2.73% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 13680624 # Class of executed instruction -system.cpu1.dcache.tags.replacements 173715 # number of replacements -system.cpu1.dcache.tags.tagsinuse 481.481115 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 4164110 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 174227 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 23.900486 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 90323581500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.481115 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.940393 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.940393 # Average percentage of cache occupancy +system.cpu1.op_class::total 13689843 # Class of executed instruction +system.cpu1.dcache.tags.replacements 173686 # number of replacements +system.cpu1.dcache.tags.tagsinuse 481.983606 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 4164884 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 174198 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 23.908908 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 90321767000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.983606 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.941374 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.941374 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 17605365 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 17605365 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2339052 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2339052 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1706902 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1706902 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 50404 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 50404 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 53074 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 53074 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 4045954 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 4045954 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 4045954 # number of overall hits -system.cpu1.dcache.overall_hits::total 4045954 # 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miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044646 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.044646 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12610.587940 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12610.587940 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 28653.621531 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 28653.621531 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9199.751995 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9199.751995 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 16293.780687 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 16293.780687 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18174.940104 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 18174.940104 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18174.940104 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 18174.940104 # average overall miss latency +system.cpu1.dcache.tags.tag_accesses 17608316 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 17608316 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 2339523 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2339523 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1707175 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1707175 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 50425 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 50425 # 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number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 789483500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 814534500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 814534500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050151 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050151 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036999 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036999 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155401 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155401 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103237 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103237 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044646 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.044646 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044646 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.044646 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11610.587940 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11610.587940 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27653.621531 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27653.621531 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8199.751995 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8199.751995 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15293.780687 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 15293.780687 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17174.940104 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17174.940104 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17174.940104 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17174.940104 # average overall mshr miss latency +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 789482000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 789482000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 814533000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 814533000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050136 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050136 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036998 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036998 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155091 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155091 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103215 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103215 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044637 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.044637 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044637 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.044637 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11600.433251 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11600.433251 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27523.151748 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27523.151748 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8191.335350 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8191.335350 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14870.928139 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14870.928139 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17123.959402 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17123.959402 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17123.959402 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17123.959402 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 212296.610169 # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 212296.610169 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 235807.497013 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 235807.497013 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 235007.068667 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 235007.068667 # average overall mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 235807.048984 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 235807.048984 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 235006.635892 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 235006.635892 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 331421 # number of replacements -system.cpu1.icache.tags.tagsinuse 442.918144 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 13348652 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 331933 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 40.214899 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1976561020500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 442.918144 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.865074 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.865074 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 331505 # number of replacements +system.cpu1.icache.tags.tagsinuse 442.932847 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 13357787 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 332017 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 40.232238 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1975288394500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 442.932847 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.865103 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.865103 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 405 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 32 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 14012598 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 14012598 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 13348652 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 13348652 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 13348652 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 13348652 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 13348652 # number of overall hits -system.cpu1.icache.overall_hits::total 13348652 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 331973 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 331973 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 331973 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 331973 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 331973 # number of overall misses -system.cpu1.icache.overall_misses::total 331973 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4541836000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4541836000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4541836000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4541836000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4541836000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4541836000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13680625 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13680625 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13680625 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13680625 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13680625 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13680625 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024266 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024266 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024266 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024266 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024266 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024266 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13681.341555 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13681.341555 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13681.341555 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13681.341555 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13681.341555 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13681.341555 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 14021901 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 14021901 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 13357787 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 13357787 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 13357787 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 13357787 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 13357787 # number of overall hits +system.cpu1.icache.overall_hits::total 13357787 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 332057 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 332057 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 332057 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 332057 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 332057 # number of overall misses +system.cpu1.icache.overall_misses::total 332057 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4541544500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4541544500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4541544500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4541544500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4541544500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4541544500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 13689844 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13689844 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 13689844 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 13689844 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 13689844 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 13689844 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024256 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024256 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024256 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024256 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024256 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024256 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13677.002744 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13677.002744 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13677.002744 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13677.002744 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13677.002744 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13677.002744 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1135,32 +1122,32 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 331421 # number of writebacks -system.cpu1.icache.writebacks::total 331421 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 331973 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 331973 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 331973 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 331973 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 331973 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 331973 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4209863000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4209863000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4209863000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4209863000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4209863000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4209863000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024266 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024266 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024266 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024266 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024266 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024266 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12681.341555 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12681.341555 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12681.341555 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12681.341555 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12681.341555 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12681.341555 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 331505 # number of writebacks +system.cpu1.icache.writebacks::total 331505 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 332057 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 332057 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 332057 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 332057 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 332057 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 332057 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4209487500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4209487500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4209487500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4209487500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4209487500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4209487500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024256 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024256 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024256 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024256 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024256 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024256 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12677.002744 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12677.002744 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12677.002744 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12677.002744 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12677.002744 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12677.002744 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1174,37 +1161,37 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 7373 # Transaction distribution -system.iobus.trans_dist::ReadResp 7373 # Transaction distribution -system.iobus.trans_dist::WriteReq 55680 # Transaction distribution -system.iobus.trans_dist::WriteResp 55680 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14048 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 7379 # Transaction distribution +system.iobus.trans_dist::ReadResp 7379 # Transaction distribution +system.iobus.trans_dist::WriteReq 55684 # Transaction distribution +system.iobus.trans_dist::WriteResp 55684 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14066 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2476 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 42652 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 42672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 126106 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 56192 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 126126 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 56264 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9884 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 82434 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 82507 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2744058 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 15110500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2744131 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 15127500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 758000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1214,29 +1201,29 @@ system.iobus.reqLayer6.occupancy 10000 # La system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 175000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 15842500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 15843000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2460000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6039500 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6055000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 83000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 215050235 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 215669663 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28524000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 28540000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41950000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41695 # number of replacements -system.iocache.tags.tagsinuse 0.566864 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.566874 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1775104150000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.566864 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035429 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035429 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1775103309000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.566874 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035430 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035430 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1252,8 +1239,8 @@ system.iocache.overall_misses::tsunami.ide 175 # system.iocache.overall_misses::total 175 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21956883 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21956883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5428160352 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5428160352 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5245212780 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5245212780 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::tsunami.ide 21956883 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 21956883 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::tsunami.ide 21956883 # number of overall miss cycles @@ -1276,17 +1263,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125467.902857 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 125467.902857 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130635.356950 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130635.356950 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126232.498556 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 126232.498556 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 125467.902857 # average overall miss latency system.iocache.demand_avg_miss_latency::total 125467.902857 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 125467.902857 # average overall miss latency system.iocache.overall_avg_miss_latency::total 125467.902857 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 14 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1302,8 +1289,8 @@ system.iocache.overall_mshr_misses::tsunami.ide 175 system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13206883 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 13206883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3350560352 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3350560352 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165805993 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3165805993 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::tsunami.ide 13206883 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 13206883 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::tsunami.ide 13206883 # number of overall MSHR miss cycles @@ -1318,197 +1305,197 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75467.902857 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 75467.902857 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80635.356950 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80635.356950 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76189.016004 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76189.016004 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75467.902857 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 75467.902857 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75467.902857 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 75467.902857 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 342160 # number of replacements -system.l2c.tags.tagsinuse 65166.105156 # Cycle average of tags in use -system.l2c.tags.total_refs 3684821 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 407166 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 9.049923 # Average number of references to valid blocks. +system.l2c.tags.replacements 342144 # number of replacements +system.l2c.tags.tagsinuse 65164.214079 # Cycle average of tags in use +system.l2c.tags.total_refs 3686310 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 407150 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 9.053936 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 12928623000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54852.926968 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4798.887710 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5355.521606 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 119.450047 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 39.318825 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.836989 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.073225 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.081719 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.001823 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 54851.914684 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4798.806705 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5354.570072 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 119.591740 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 39.330879 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.836974 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.073224 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.081704 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.001825 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.000600 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.994356 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.994327 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65006 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 513 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5372 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6320 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52699 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 517 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 5381 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6294 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52712 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.991913 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 35902652 # Number of tag accesses -system.l2c.tags.data_accesses 35902652 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 792572 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 792572 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 746399 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 746399 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 184 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 546 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 730 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 39 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits +system.l2c.tags.tag_accesses 35907872 # Number of tag accesses +system.l2c.tags.data_accesses 35907872 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 792557 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 792557 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 746952 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 746952 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 186 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 548 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 734 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 40 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 23 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 63 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 124130 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 48550 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 172680 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 674563 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 331022 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1005585 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 659479 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 113775 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 773254 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 674563 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 783609 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 331022 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 162325 # number of demand (read+write) hits -system.l2c.demand_hits::total 1951519 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 674563 # number of overall hits -system.l2c.overall_hits::cpu0.data 783609 # number of overall hits -system.l2c.overall_hits::cpu1.inst 331022 # number of overall hits -system.l2c.overall_hits::cpu1.data 162325 # number of overall hits -system.l2c.overall_hits::total 1951519 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 2975 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1806 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 4781 # number of UpgradeReq misses +system.l2c.ReadExReq_hits::cpu0.data 124117 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 48557 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 172674 # 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average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71429.494080 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 117149.551649 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 122041.814721 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 117463.339492 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 121150.939624 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122203.940362 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 121224.486760 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 113986.583879 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 118393.175074 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 113992.046006 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121150.939624 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 114927.472601 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122203.940362 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121892.174760 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 115275.081644 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121150.939624 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 114927.472601 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122203.940362 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121892.174760 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 115275.081644 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208703.460452 # average ReadReq mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941102 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.767698 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.866957 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.958592 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.975866 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.967170 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.480886 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.139579 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.415710 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.018196 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.002795 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013178 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.291657 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.002954 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260147 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018196 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.330323 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002795 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.048176 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.172959 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018196 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.330323 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002795 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.048176 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.172959 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 68753.701211 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 68858.917725 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68793.539619 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 68479.481641 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 68922.043011 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68701.239224 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 117141.871853 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121624.666751 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 117429.294121 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 121368.002239 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122773.707974 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 121465.120682 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 113994.501670 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 118394.658754 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 113999.955862 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121368.002239 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 114930.755419 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122773.707974 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121492.147553 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 115277.837125 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121368.002239 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 114930.755419 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122773.707974 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121492.147553 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 115277.837125 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208711.191081 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 199792.372881 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208557.377049 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215865.074212 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 224303.614098 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 217864.807475 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213026.091825 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 223469.128679 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 214723.342399 # average overall mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208565.102721 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215871.939911 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 224303.166069 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 217869.374469 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213032.484611 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 223468.695903 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 214727.830896 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 7198 # Transaction distribution -system.membus.trans_dist::ReadResp 292693 # Transaction distribution -system.membus.trans_dist::WriteReq 14128 # Transaction distribution -system.membus.trans_dist::WriteResp 14128 # Transaction distribution -system.membus.trans_dist::WritebackDirty 120940 # Transaction distribution -system.membus.trans_dist::CleanEvict 261948 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16888 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11786 # Transaction distribution -system.membus.trans_dist::UpgradeResp 7203 # Transaction distribution -system.membus.trans_dist::ReadExReq 123166 # Transaction distribution -system.membus.trans_dist::ReadExResp 122293 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 285495 # Transaction distribution +system.membus.trans_dist::ReadReq 7204 # Transaction distribution +system.membus.trans_dist::ReadResp 292685 # Transaction distribution +system.membus.trans_dist::WriteReq 14132 # Transaction distribution +system.membus.trans_dist::WriteResp 14132 # Transaction distribution +system.membus.trans_dist::WritebackDirty 120936 # Transaction distribution +system.membus.trans_dist::CleanEvict 262098 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16894 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 11785 # Transaction distribution +system.membus.trans_dist::UpgradeResp 3 # Transaction distribution +system.membus.trans_dist::ReadExReq 123162 # Transaction distribution +system.membus.trans_dist::ReadExResp 122291 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 285481 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42652 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1193065 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1235717 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124827 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124827 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1360544 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82434 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31153280 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31235714 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42672 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1185820 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1228492 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83437 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83437 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1311929 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82507 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31152000 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31234507 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33893954 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 22770 # Total snoops (count) -system.membus.snoop_fanout::samples 883282 # Request fanout histogram +system.membus.pkt_size::total 33892747 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 22774 # Total snoops (count) +system.membus.snoop_fanout::samples 883255 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 883282 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 883255 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 883282 # Request fanout histogram -system.membus.reqLayer0.occupancy 40488000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 883255 # Request fanout histogram +system.membus.reqLayer0.occupancy 40521000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1327709899 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1327609723 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2192713302 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2178253250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 69791959 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 898617 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 4790563 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2395444 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 362000 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1241 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1181 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 4790864 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2395593 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 361656 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1242 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1182 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 60 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 7198 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2107005 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14128 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14128 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 913531 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 746399 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 756600 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 17054 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11849 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 28903 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 297620 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 297620 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1019067 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1080755 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 7204 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2107176 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 14132 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 14132 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 913504 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1018097 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 816785 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 17065 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11848 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 28913 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 297603 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 297603 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1019283 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1080704 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1917007 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3544626 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 867499 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 539645 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6868777 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 78714432 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118015028 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 34273664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 18604942 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 249608066 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 484792 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 2873097 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.137110 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.344206 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2061018 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3585479 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 995618 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 558881 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7200996 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 87922688 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118013949 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 42467904 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 18601358 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 267005899 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 484765 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2873241 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.136986 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.344076 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2479406 86.30% 86.30% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 393455 13.69% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2479885 86.31% 86.31% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 393120 13.68% 99.99% # Request fanout histogram system.toL2Bus.snoop_fanout::2 234 0.01% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2873097 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4223463995 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2873241 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4223821996 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 297883 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1030900979 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1031213250 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1802313287 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1802267282 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 499097220 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 499176813 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 293862892 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 293823888 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index bc2bfd41e..04e45bbeb 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -4,13 +4,13 @@ sim_seconds 1.941276 # Nu sim_ticks 1941275996000 # Number of ticks simulated final_tick 1941275996000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 450874 # Simulator instruction rate (inst/s) -host_op_rate 450874 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15578984909 # Simulator tick rate (ticks/s) -host_mem_usage 311244 # Number of bytes of host memory used -host_seconds 124.61 # Real time elapsed on the host -sim_insts 56182743 # Number of instructions simulated -sim_ops 56182743 # Number of ops (including micro ops) simulated +host_inst_rate 1255554 # Simulator instruction rate (inst/s) +host_op_rate 1255553 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43383023327 # Simulator tick rate (ticks/s) +host_mem_usage 332188 # Number of bytes of host memory used +host_seconds 44.75 # Real time elapsed on the host +sim_insts 56182685 # Number of instructions simulated +sim_ops 56182685 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 844800 # Number of bytes read from this memory @@ -51,7 +51,7 @@ system.physmem.bytesReadSys 25702272 # To system.physmem.bytesWrittenSys 7410752 # Total written bytes from the system interface side system.physmem.servicedByWrQ 117 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 303100 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 25225 # Per bank write bursts system.physmem.perBankRdBursts::1 25628 # Per bank write bursts system.physmem.perBankRdBursts::2 25541 # Per bank write bursts @@ -85,7 +85,7 @@ system.physmem.perBankWrBursts::13 7822 # Pe system.physmem.perBankWrBursts::14 7863 # Per bank write bursts system.physmem.perBankWrBursts::15 7687 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 16 # Number of times write queue was full causing retry +system.physmem.numWrRetry 8 # Number of times write queue was full causing retry system.physmem.totGap 1941264122500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) @@ -148,123 +148,112 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5822 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7624 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6622 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5554 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 51 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64945 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 509.715729 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 310.174215 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 406.042967 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15358 23.65% 23.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11454 17.64% 41.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4958 7.63% 48.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3153 4.85% 53.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2453 3.78% 57.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4205 6.47% 64.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1430 2.20% 66.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2063 3.18% 69.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19871 30.60% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64945 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5113 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 78.517700 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2951.127633 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5110 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6714 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5907 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6941 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 34 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64912 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 509.974858 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 310.431433 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 406.117715 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15298 23.57% 23.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11509 17.73% 41.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4967 7.65% 48.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3096 4.77% 53.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2467 3.80% 57.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4201 6.47% 63.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1427 2.20% 66.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2061 3.18% 69.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19886 30.64% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64912 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5093 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 78.826036 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2956.913485 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5090 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5113 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5113 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.640524 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.158069 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.669047 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4483 87.68% 87.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 26 0.51% 88.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 11 0.22% 88.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 181 3.54% 91.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 5 0.10% 92.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 20 0.39% 92.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 39 0.76% 93.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 6 0.12% 93.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 12 0.23% 93.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 31 0.61% 94.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.06% 94.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 3 0.06% 94.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 9 0.18% 94.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 1 0.02% 94.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 22 0.43% 94.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 27 0.53% 95.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 2 0.04% 95.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 26 0.51% 95.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.06% 96.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 161 3.15% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 5 0.10% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.04% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 3 0.06% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.02% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 4 0.08% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 4 0.08% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 11 0.22% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 5 0.10% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5113 # Writes before turning the bus around for reads -system.physmem.totQLat 2718840250 # Total ticks spent queuing -system.physmem.totMemAccLat 10246609000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.rdPerTurnAround::total 5093 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5093 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.729433 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.333640 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.082746 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4499 88.34% 88.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 29 0.57% 88.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 20 0.39% 89.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 41 0.81% 90.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 209 4.10% 94.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 11 0.22% 94.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 11 0.22% 94.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 30 0.59% 95.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 184 3.61% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 6 0.12% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 5 0.10% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 4 0.08% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 1 0.02% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 8 0.16% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 5 0.10% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 1 0.02% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 4 0.08% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 5 0.10% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 5 0.10% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 1 0.02% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 2 0.04% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 7 0.14% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 4 0.08% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5093 # Writes before turning the bus around for reads +system.physmem.totQLat 2720413750 # Total ticks spent queuing +system.physmem.totMemAccLat 10248182500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2007405000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6772.03 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6775.95 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25522.03 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25525.95 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.24 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.82 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.24 # Average system read bandwidth in MiByte/s @@ -274,55 +263,55 @@ system.physmem.busUtil 0.13 # Da system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.09 # Average write queue length when enqueuing -system.physmem.readRowHits 358828 # Number of row buffer hits during reads -system.physmem.writeRowHits 93469 # Number of row buffer hits during writes +system.physmem.avgWrQLen 22.10 # Average write queue length when enqueuing +system.physmem.readRowHits 358846 # Number of row buffer hits during reads +system.physmem.writeRowHits 93484 # Number of row buffer hits during writes system.physmem.readRowHitRate 89.38 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.72 # Row buffer hit rate for writes +system.physmem.writeRowHitRate 80.73 # Row buffer hit rate for writes system.physmem.avgGap 3752025.30 # Average gap between requests system.physmem.pageHitRate 87.44 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 240377760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 131158500 # Energy for precharge commands per rank (pJ) +system.physmem_0.actEnergy 240264360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 131096625 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 1565912400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 373358160 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 126794687760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 71534855790 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1102015656000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1302656006370 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.030850 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1833021874000 # Time in different power states +system.physmem_0.actBackEnergy 71567841690 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1101986721000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1302659881995 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.032847 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1832974788000 # Time in different power states system.physmem_0.memoryStateTime::REF 64823460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 43430562250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 43477648250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 250606440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 136739625 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 250470360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 136665375 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1565639400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 376773120 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 126794687760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 72705843270 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1100988474000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1302818763615 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.114691 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1831312114000 # Time in different power states +system.physmem_1.actBackEnergy 72629101890 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1101055791000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1302809128905 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.109728 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1831423384000 # Time in different power states system.physmem_1.memoryStateTime::REF 64823460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 45140322250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 45029052250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9064657 # DTB read hits +system.cpu.dtb.read_hits 9064642 # DTB read hits system.cpu.dtb.read_misses 10324 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations system.cpu.dtb.read_accesses 728853 # DTB read accesses -system.cpu.dtb.write_hits 6356207 # DTB write hits +system.cpu.dtb.write_hits 6356200 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 15420864 # DTB hits +system.cpu.dtb.data_hits 15420842 # DTB hits system.cpu.dtb.data_misses 11466 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations system.cpu.dtb.data_accesses 1020784 # DTB accesses @@ -358,10 +347,10 @@ system.cpu.kern.ipl_good::21 131 0.09% 49.40% # nu system.cpu.kern.ipl_good::22 1935 1.30% 50.69% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73545 49.31% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 149156 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1860509805500 95.84% 95.84% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 94040000 0.00% 95.84% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 770515500 0.04% 95.88% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 79900901000 4.12% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1860509936500 95.84% 95.84% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 94066500 0.00% 95.84% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 770529000 0.04% 95.88% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 79900730000 4.12% 100.00% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::total 1941275262000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981752 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl @@ -426,32 +415,32 @@ system.cpu.kern.mode_switch_good::kernel 0.323121 # fr system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081184 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.391952 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 48611852500 2.50% 2.50% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5602941000 0.29% 2.79% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1887060466500 97.21% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::kernel 48613441500 2.50% 2.50% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5603081000 0.29% 2.79% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1887058737500 97.21% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed -system.cpu.committedInsts 56182743 # Number of instructions committed -system.cpu.committedOps 56182743 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52054633 # Number of integer alu accesses +system.cpu.committedInsts 56182685 # Number of instructions committed +system.cpu.committedOps 56182685 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52054580 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses -system.cpu.num_func_calls 1483394 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6468678 # number of instructions that are conditional controls -system.cpu.num_int_insts 52054633 # number of integer instructions +system.cpu.num_func_calls 1483390 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6468674 # number of instructions that are conditional controls +system.cpu.num_int_insts 52054580 # number of integer instructions system.cpu.num_fp_insts 324393 # number of float instructions -system.cpu.num_int_register_reads 71322499 # number of times the integer registers were read -system.cpu.num_int_register_writes 38520900 # number of times the integer registers were written +system.cpu.num_int_register_reads 71322431 # number of times the integer registers were read +system.cpu.num_int_register_writes 38520860 # number of times the integer registers were written system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written -system.cpu.num_mem_refs 15473474 # number of memory refs -system.cpu.num_load_insts 9101503 # Number of load instructions -system.cpu.num_store_insts 6371971 # Number of store instructions -system.cpu.num_idle_cycles 3583834697.998154 # Number of idle cycles -system.cpu.num_busy_cycles 298717294.001846 # Number of busy cycles -system.cpu.not_idle_fraction 0.076938 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.923062 # Percentage of idle cycles -system.cpu.Branches 8422724 # Number of branches fetched -system.cpu.op_class::No_OpClass 3200638 5.70% 5.70% # Class of executed instruction -system.cpu.op_class::IntAlu 36231019 64.47% 70.17% # Class of executed instruction +system.cpu.num_mem_refs 15473452 # number of memory refs +system.cpu.num_load_insts 9101488 # Number of load instructions +system.cpu.num_store_insts 6371964 # Number of store instructions +system.cpu.num_idle_cycles 3583831790.000154 # Number of idle cycles +system.cpu.num_busy_cycles 298720201.999846 # Number of busy cycles +system.cpu.not_idle_fraction 0.076939 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.923061 # Percentage of idle cycles +system.cpu.Branches 8422715 # Number of branches fetched +system.cpu.op_class::No_OpClass 3200634 5.70% 5.70% # Class of executed instruction +system.cpu.op_class::IntAlu 36230987 64.47% 70.17% # Class of executed instruction system.cpu.op_class::IntMult 61043 0.11% 70.28% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 70.28% # Class of executed instruction system.cpu.op_class::FloatAdd 38085 0.07% 70.35% # Class of executed instruction @@ -480,16 +469,16 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 70.35% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::MemRead 9328633 16.60% 86.95% # Class of executed instruction -system.cpu.op_class::MemWrite 6378052 11.35% 98.30% # Class of executed instruction +system.cpu.op_class::MemRead 9328618 16.60% 86.95% # Class of executed instruction +system.cpu.op_class::MemWrite 6378045 11.35% 98.30% # Class of executed instruction system.cpu.op_class::IprAccess 953470 1.70% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 56194576 # Class of executed instruction -system.cpu.dcache.tags.replacements 1390387 # number of replacements +system.cpu.op_class::total 56194518 # Class of executed instruction +system.cpu.dcache.tags.replacements 1390402 # number of replacements system.cpu.dcache.tags.tagsinuse 511.973391 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14048998 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1390899 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 10.100660 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 14048961 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1390914 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.100525 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 145150500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.973391 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999948 # Average percentage of cache occupancy @@ -499,72 +488,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 system.cpu.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63150492 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63150492 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7814415 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7814415 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5852271 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5852271 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183035 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183035 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 63150419 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63150419 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7814383 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7814383 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5852265 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5852265 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183036 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183036 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 199260 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 199260 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13666686 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13666686 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13666686 # number of overall hits -system.cpu.dcache.overall_hits::total 13666686 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1069342 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1069342 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304328 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304328 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17247 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17247 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1373670 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1373670 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1373670 # number of overall misses -system.cpu.dcache.overall_misses::total 1373670 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 44771016500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 44771016500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 17634519000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 17634519000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232810500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 232810500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 62405535500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 62405535500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 62405535500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 62405535500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 8883757 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 8883757 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6156599 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6156599 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 13666648 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13666648 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13666648 # number of overall hits +system.cpu.dcache.overall_hits::total 13666648 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1069359 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1069359 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304327 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304327 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17246 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17246 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1373686 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1373686 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1373686 # number of overall misses +system.cpu.dcache.overall_misses::total 1373686 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 44772641000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 44772641000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 17635172000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 17635172000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232797500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 232797500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 62407813000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 62407813000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 62407813000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 62407813000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8883742 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8883742 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6156592 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6156592 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200282 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 200282 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 199260 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 199260 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15040356 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15040356 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15040356 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15040356 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120370 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120370 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 15040334 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15040334 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15040334 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15040334 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120373 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120373 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049431 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.049431 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086114 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086114 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091332 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091332 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091332 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091332 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41867.818247 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41867.818247 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57945.765753 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 57945.765753 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13498.608454 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13498.608454 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45429.786994 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45429.786994 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45429.786994 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45429.786994 # average overall miss latency +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086109 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086109 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091333 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091333 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091333 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091333 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41868.671793 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41868.671793 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57948.101877 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 57948.101877 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13498.637365 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13498.637365 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45430.915799 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45430.915799 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45430.915799 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45430.915799 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -573,74 +562,74 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 834936 # number of writebacks -system.cpu.dcache.writebacks::total 834936 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069342 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069342 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304328 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304328 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17247 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17247 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1373670 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1373670 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1373670 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1373670 # number of overall MSHR misses +system.cpu.dcache.writebacks::writebacks 834944 # number of writebacks +system.cpu.dcache.writebacks::total 834944 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069359 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1069359 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304327 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304327 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17246 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17246 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1373686 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1373686 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1373686 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1373686 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9653 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 9653 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16583 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 16583 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43701674500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 43701674500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17330191000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 17330191000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 215563500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 215563500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61031865500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 61031865500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61031865500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 61031865500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43703282000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 43703282000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17330845000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 17330845000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 215551500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 215551500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61034127000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 61034127000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61034127000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 61034127000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1526978500 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1526978500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2172467000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2172467000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3699445500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3699445500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120370 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120370 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2172486500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2172486500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3699465000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3699465000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120373 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120373 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049431 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049431 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086114 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086114 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091332 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091332 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091332 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091332 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40867.818247 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40867.818247 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56945.765753 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56945.765753 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12498.608454 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12498.608454 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44429.786994 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 44429.786994 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44429.786994 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44429.786994 # average overall mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086109 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086109 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091333 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091333 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091333 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091333 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40868.671793 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40868.671793 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56948.101877 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56948.101877 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12498.637365 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12498.637365 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44430.915799 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 44430.915799 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44430.915799 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44430.915799 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220343.217893 # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220343.217893 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 225056.148348 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 225056.148348 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 223086.624857 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 223086.624857 # average overall mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 225058.168445 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 225058.168445 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 223087.800760 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 223087.800760 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 928920 # number of replacements -system.cpu.icache.tags.tagsinuse 506.355618 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 55264986 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 929431 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 59.461096 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 928931 # number of replacements +system.cpu.icache.tags.tagsinuse 506.355616 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 55264917 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 929442 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 59.460318 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 58592056500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 506.355618 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 506.355616 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.988976 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.988976 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id @@ -649,44 +638,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 1 system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 57124168 # Number of tag accesses -system.cpu.icache.tags.data_accesses 57124168 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 55264986 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55264986 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55264986 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55264986 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55264986 # number of overall hits -system.cpu.icache.overall_hits::total 55264986 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 929591 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 929591 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 929591 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 929591 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 929591 # number of overall misses -system.cpu.icache.overall_misses::total 929591 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13686841500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13686841500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13686841500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13686841500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13686841500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13686841500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56194577 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56194577 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56194577 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56194577 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 56194577 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56194577 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016542 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016542 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.016542 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.016542 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.016542 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.016542 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14723.509049 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14723.509049 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14723.509049 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14723.509049 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14723.509049 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14723.509049 # average overall miss latency +system.cpu.icache.tags.tag_accesses 57124121 # Number of tag accesses +system.cpu.icache.tags.data_accesses 57124121 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 55264917 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55264917 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55264917 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55264917 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55264917 # number of overall hits +system.cpu.icache.overall_hits::total 55264917 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 929602 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 929602 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 929602 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 929602 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 929602 # number of overall misses +system.cpu.icache.overall_misses::total 929602 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13686117000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13686117000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13686117000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13686117000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13686117000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13686117000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 56194519 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56194519 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 56194519 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 56194519 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 56194519 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 56194519 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016543 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016543 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016543 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016543 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016543 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016543 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14722.555459 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14722.555459 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14722.555459 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14722.555459 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14722.555459 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14722.555459 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -695,44 +684,44 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 928920 # number of writebacks -system.cpu.icache.writebacks::total 928920 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929591 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 929591 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 929591 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 929591 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 929591 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 929591 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12757250500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12757250500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12757250500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12757250500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12757250500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12757250500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016542 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.016542 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.016542 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13723.509049 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13723.509049 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13723.509049 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13723.509049 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13723.509049 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13723.509049 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 928931 # number of writebacks +system.cpu.icache.writebacks::total 928931 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929602 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 929602 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 929602 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 929602 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 929602 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 929602 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12756515000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12756515000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12756515000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12756515000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12756515000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12756515000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016543 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.016543 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.016543 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13722.555459 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13722.555459 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13722.555459 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13722.555459 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13722.555459 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13722.555459 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 336393 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65234.360010 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3930350 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 65234.360001 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3930403 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 401556 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 9.787800 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 9.787932 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 10619817000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 55072.826279 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4686.115262 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 5475.418469 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 55072.820493 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4686.121272 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 5475.418237 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.840345 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.071504 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.071505 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.083548 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.995397 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id @@ -742,26 +731,26 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5220 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3221 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55822 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 37812565 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 37812565 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 834936 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 834936 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 928699 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 928699 # number of WritebackClean hits +system.cpu.l2cache.tags.tag_accesses 37812972 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 37812972 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 834944 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 834944 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 928709 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 928709 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187491 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187491 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 916371 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 916371 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 814618 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 814618 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 916371 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1002109 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1918480 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 916371 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1002109 # number of overall hits -system.cpu.l2cache.overall_hits::total 1918480 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 187490 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187490 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 916382 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 916382 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 814634 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 814634 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 916382 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1002124 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1918506 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 916382 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1002124 # number of overall hits +system.cpu.l2cache.overall_hits::total 1918506 # number of overall hits system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 116820 # number of ReadExReq misses @@ -776,66 +765,66 @@ system.cpu.l2cache.demand_misses::total 401991 # nu system.cpu.l2cache.overall_misses::cpu.inst 13200 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 388791 # number of overall misses system.cpu.l2cache.overall_misses::total 401991 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 320500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 320500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14900653000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 14900653000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1727668500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 1727668500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33719834000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 33719834000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1727668500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 48620487000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 50348155500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1727668500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 48620487000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 50348155500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 834936 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 834936 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 928699 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 928699 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 315000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 315000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14901349500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 14901349500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1726796000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 1726796000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33721236500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 33721236500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1726796000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 48622586000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 50349382000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1726796000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 48622586000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 50349382000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 834944 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 834944 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 928709 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 928709 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304311 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304311 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 929571 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 929571 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1086589 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1086589 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 929571 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1390900 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2320471 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 929571 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1390900 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2320471 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304310 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304310 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 929582 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 929582 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1086605 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1086605 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 929582 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1390915 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2320497 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 929582 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1390915 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2320497 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383884 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383884 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383885 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383885 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014200 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014200 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.250298 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.250298 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.250294 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.250294 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014200 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.279525 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.173237 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.279522 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.173235 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014200 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.279525 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.173237 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 24653.846154 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 24653.846154 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127552.242767 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127552.242767 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130883.977273 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130883.977273 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123983.196738 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123983.196738 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130883.977273 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 125055.587707 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 125246.971947 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130883.977273 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 125055.587707 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 125246.971947 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.279522 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.173235 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 24230.769231 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 24230.769231 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127558.204931 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127558.204931 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130817.878788 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130817.878788 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123988.353538 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123988.353538 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130817.878788 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 125060.986494 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 125250.023010 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130817.878788 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 125060.986494 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 125250.023010 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -866,106 +855,106 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9653 system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9653 # number of WriteReq MSHR uncacheable system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16583 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16583 # number of overall MSHR uncacheable misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 924500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 924500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13732453000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13732453000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1595668500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1595668500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31000124000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31000124000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1595668500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44732577000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 46328245500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1595668500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44732577000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 46328245500 # number of overall MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 893500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 893500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13733149500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13733149500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1594796000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1594796000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31001526500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31001526500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1594796000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44734676000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 46329472000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1594796000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44734676000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 46329472000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1440322500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1440322500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2061377000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2061377000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3501699500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3501699500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2061396500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2061396500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3501719000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3501719000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383884 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383884 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383885 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383885 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014200 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014200 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250298 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250298 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250294 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250294 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014200 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279525 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173237 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279522 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.173235 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014200 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279525 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173237 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71115.384615 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71115.384615 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117552.242767 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117552.242767 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120883.977273 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120883.977273 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113983.196738 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113983.196738 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120883.977273 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 115055.587707 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115246.971947 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120883.977273 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 115055.587707 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115246.971947 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279522 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.173235 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68730.769231 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68730.769231 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117558.204931 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117558.204931 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120817.878788 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120817.878788 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113988.353538 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113988.353538 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120817.878788 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 115060.986494 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115250.023010 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120817.878788 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 115060.986494 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115250.023010 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 207838.744589 # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 207838.744589 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213547.808971 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213547.808971 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211162.003256 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211162.003256 # average overall mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213549.829069 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213549.829069 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211163.179159 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211163.179159 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 4639815 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319473 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1501 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 4639867 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319499 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1502 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 1136 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1136 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2023267 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2023294 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9653 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9653 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 950745 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 928699 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 816471 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 928931 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 817743 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304311 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304311 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 929591 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1086762 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304310 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304310 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 929602 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1086778 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2787861 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4204279 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6992140 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118929280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142508140 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 261437420 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 419996 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2756910 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2788115 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4205589 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6993704 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118944832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142509612 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 261454444 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 419988 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2756928 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.001015 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.031841 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.031847 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2754112 99.90% 99.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2798 0.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2754129 99.90% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2799 0.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2756910 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4096881500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2756928 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4096926500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 293383 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1394386500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1394403000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2098115000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2098137500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1019,15 +1008,15 @@ system.iobus.reqLayer6.occupancy 10000 # La system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 174000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 15817000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 15817500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 1891500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6032000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6038000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 215014002 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 215662167 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23513000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) @@ -1038,7 +1027,7 @@ system.iocache.tags.tagsinuse 1.339384 # Cy system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1774106672000 # Cycle when the warmup percentage was hit. +system.iocache.tags.warmup_cycle 1774106669000 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::tsunami.ide 1.339384 # Average occupied blocks per requestor system.iocache.tags.occ_percent::tsunami.ide 0.083712 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.083712 # Average percentage of cache occupancy @@ -1057,8 +1046,8 @@ system.iocache.overall_misses::tsunami.ide 173 # system.iocache.overall_misses::total 173 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21742883 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21742883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5428926119 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5428926119 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5244713284 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5244713284 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::tsunami.ide 21742883 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 21742883 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::tsunami.ide 21742883 # number of overall miss cycles @@ -1081,17 +1070,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125681.404624 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 125681.404624 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130653.786075 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130653.786075 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126220.477570 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 126220.477570 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 125681.404624 # average overall miss latency system.iocache.demand_avg_miss_latency::total 125681.404624 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 125681.404624 # average overall miss latency system.iocache.overall_avg_miss_latency::total 125681.404624 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 32 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 29 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 14.500000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1107,8 +1096,8 @@ system.iocache.overall_mshr_misses::tsunami.ide 173 system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13092883 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 13092883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3351326119 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3351326119 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165314984 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3165314984 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::tsunami.ide 13092883 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 13092883 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::tsunami.ide 13092883 # number of overall MSHR miss cycles @@ -1123,8 +1112,8 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75681.404624 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 75681.404624 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80653.786075 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80653.786075 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76177.199268 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76177.199268 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75681.404624 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 75681.404624 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75681.404624 # average overall mshr miss latency @@ -1135,20 +1124,19 @@ system.membus.trans_dist::ReadResp 292274 # Tr system.membus.trans_dist::WriteReq 9653 # Transaction distribution system.membus.trans_dist::WriteResp 9653 # Transaction distribution system.membus.trans_dist::WritebackDirty 115793 # Transaction distribution -system.membus.trans_dist::CleanEvict 261400 # Transaction distribution +system.membus.trans_dist::CleanEvict 261560 # Transaction distribution system.membus.trans_dist::UpgradeReq 150 # Transaction distribution -system.membus.trans_dist::UpgradeResp 150 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2 # Transaction distribution system.membus.trans_dist::ReadExReq 116683 # Transaction distribution system.membus.trans_dist::ReadExResp 116683 # Transaction distribution system.membus.trans_dist::ReadSharedReq 285344 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33166 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139403 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172569 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1297386 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139255 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172421 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1255846 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44588 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30455296 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30499884 # Cumulative packet size per connected master and slave (bytes) @@ -1156,24 +1144,24 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 33157612 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 431 # Total snoops (count) -system.membus.snoop_fanout::samples 837681 # Request fanout histogram +system.membus.snoop_fanout::samples 837673 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 837681 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 837673 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 837681 # Request fanout histogram -system.membus.reqLayer0.occupancy 30116000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 837673 # Request fanout histogram +system.membus.reqLayer0.occupancy 30122500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1287207146 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1287200967 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2143289352 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2143013000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 69814679 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 887117 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA |