diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha/linux')
4 files changed, 3458 insertions, 3446 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 973b187d4..01efe7b2f 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -1,309 +1,76 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.869358 # Number of seconds simulated -sim_ticks 1869357988000 # Number of ticks simulated -final_tick 1869357988000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1869358498000 # Number of ticks simulated +final_tick 1869358498000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2868261 # Simulator instruction rate (inst/s) -host_op_rate 2868259 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 82489350498 # Simulator tick rate (ticks/s) -host_mem_usage 370556 # Number of bytes of host memory used -host_seconds 22.66 # Real time elapsed on the host -sim_insts 64999904 # Number of instructions simulated -sim_ops 64999904 # Number of ops (including micro ops) simulated +host_inst_rate 1825215 # Simulator instruction rate (inst/s) +host_op_rate 1825215 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52491614317 # Simulator tick rate (ticks/s) +host_mem_usage 318168 # Number of bytes of host memory used +host_seconds 35.61 # Real time elapsed on the host +sim_insts 65000470 # Number of instructions simulated +sim_ops 65000470 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 765760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 66552064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 66539648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 106432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 766208 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 106560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 771648 # Number of bytes read from this memory -system.physmem.bytes_read::total 68196992 # Number of bytes read from this memory +system.physmem.bytes_read::total 68179008 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 765760 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 106560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 872320 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5174080 # Number of bytes written to this memory -system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory -system.physmem.bytes_written::total 7833408 # Number of bytes written to this memory +system.physmem.bytes_inst_read::cpu1.inst 106432 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 872192 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7831360 # Number of bytes written to this memory +system.physmem.bytes_written::total 7831360 # Number of bytes written to this memory system.physmem.num_reads::cpu0.inst 11965 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 1039876 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 1039682 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1663 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 11972 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1665 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 12057 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1065578 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 80845 # Number of write requests responded to by this memory -system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122397 # Number of write requests responded to by this memory +system.physmem.num_reads::total 1065297 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122365 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122365 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.inst 409638 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 35601562 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 35594910 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 56935 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 409878 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 514 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 57004 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 412788 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36481505 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 36471874 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 409638 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 57004 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 466641 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2767838 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::tsunami.ide 1422589 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4190427 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2767838 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 56935 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 466573 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4189330 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4189330 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4189330 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 409638 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 35601562 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1423102 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 57004 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 412788 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40671931 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 948901 # Transaction distribution -system.membus.trans_dist::ReadResp 948901 # Transaction distribution -system.membus.trans_dist::WriteReq 14588 # Transaction distribution -system.membus.trans_dist::WriteResp 14588 # Transaction distribution -system.membus.trans_dist::Writeback 80845 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 19618 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 14179 # Transaction distribution -system.membus.trans_dist::UpgradeResp 8160 # Transaction distribution -system.membus.trans_dist::ReadExReq 126515 # Transaction distribution -system.membus.trans_dist::ReadExResp 124290 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 44074 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2256153 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 2300227 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83462 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 83462 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2383689 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 86162 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73370112 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 73456274 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2670784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2670784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 76127058 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 1224161 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 1224161 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 1224161 # Request fanout histogram +system.physmem.bw_total::cpu0.data 35594910 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 56935 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 409878 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 514 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 40661204 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 999765 # number of replacements -system.l2c.tags.tagsinuse 65320.982867 # Cycle average of tags in use -system.l2c.tags.total_refs 2387620 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1064815 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.242286 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 56016.884833 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4834.504330 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4176.028554 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 178.991920 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 114.573230 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.854750 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.073769 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.063721 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002731 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.001748 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996719 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65050 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 768 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 3271 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 6128 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5934 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 48949 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.992584 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 31465722 # Number of tag accesses -system.l2c.tags.data_accesses 31465722 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 606953 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 626726 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 379523 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 129013 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1742215 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 777631 # number of Writeback hits -system.l2c.Writeback_hits::total 777631 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 116 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 577 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 693 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 37 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 13 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 50 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 111430 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 56603 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 168033 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 606953 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 738156 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 379523 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 185616 # number of demand (read+write) hits -system.l2c.demand_hits::total 1910248 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 606953 # number of overall hits -system.l2c.overall_hits::cpu0.data 738156 # number of overall hits -system.l2c.overall_hits::cpu1.inst 379523 # number of overall hits -system.l2c.overall_hits::cpu1.data 185616 # number of overall hits -system.l2c.overall_hits::total 1910248 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 11965 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 926610 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1665 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1033 # number of ReadReq misses -system.l2c.ReadReq_misses::total 941273 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 3006 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 2175 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 5181 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 1175 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1110 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2285 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 113916 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 11068 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 124984 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 11965 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 1040526 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1665 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 12101 # number of demand (read+write) misses -system.l2c.demand_misses::total 1066257 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 11965 # number of overall misses -system.l2c.overall_misses::cpu0.data 1040526 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1665 # number of overall misses -system.l2c.overall_misses::cpu1.data 12101 # number of overall misses -system.l2c.overall_misses::total 1066257 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.inst 618918 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1553336 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 381188 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 130046 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2683488 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 777631 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 777631 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 3122 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 2752 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 5874 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 1212 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1123 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2335 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 225346 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 67671 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 293017 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 618918 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1778682 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 381188 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 197717 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2976505 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 618918 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1778682 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 381188 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 197717 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2976505 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.019332 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.596529 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.004368 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.007943 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.350765 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.962844 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.790334 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.882022 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.969472 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.988424 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.978587 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.505516 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.163556 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.426542 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.019332 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.584998 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.004368 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.061204 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.358224 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.019332 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.584998 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.004368 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.061204 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.358224 # miss rate for overall accesses -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 80845 # number of writebacks -system.l2c.writebacks::total 80845 # number of writebacks -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 41699 # number of replacements -system.iocache.tags.tagsinuse 0.434096 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1685787163517 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.434096 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.027131 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.027131 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375579 # Number of tag accesses -system.iocache.tags.data_accesses 375579 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits -system.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses -system.iocache.ReadReq_misses::total 179 # number of ReadReq misses -system.iocache.demand_misses::tsunami.ide 179 # number of demand (read+write) misses -system.iocache.demand_misses::total 179 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 179 # number of overall misses -system.iocache.overall_misses::total 179 # number of overall misses -system.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 179 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 179 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 179 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 179 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 41552 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. -system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_txs 395 # Number of DMA write transactions. -system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. -system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. -system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7758808 # DTB read hits +system.cpu0.dtb.read_hits 7758839 # DTB read hits system.cpu0.dtb.read_misses 7155 # DTB read misses system.cpu0.dtb.read_acv 152 # DTB read access violations system.cpu0.dtb.read_accesses 531148 # DTB read accesses -system.cpu0.dtb.write_hits 4740251 # DTB write hits +system.cpu0.dtb.write_hits 4740268 # DTB write hits system.cpu0.dtb.write_misses 732 # DTB write misses system.cpu0.dtb.write_acv 102 # DTB write access violations system.cpu0.dtb.write_accesses 201714 # DTB write accesses -system.cpu0.dtb.data_hits 12499059 # DTB hits +system.cpu0.dtb.data_hits 12499107 # DTB hits system.cpu0.dtb.data_misses 7887 # DTB misses system.cpu0.dtb.data_acv 254 # DTB access violations system.cpu0.dtb.data_accesses 732862 # DTB accesses -system.cpu0.itb.fetch_hits 3525726 # ITB hits +system.cpu0.itb.fetch_hits 3525737 # ITB hits system.cpu0.itb.fetch_misses 3572 # ITB misses system.cpu0.itb.fetch_acv 127 # ITB acv -system.cpu0.itb.fetch_accesses 3529298 # ITB accesses +system.cpu0.itb.fetch_accesses 3529309 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -316,32 +83,32 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3738722771 # number of cpu cycles simulated +system.cpu0.numCycles 3738723791 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 49477745 # Number of instructions committed -system.cpu0.committedOps 49477745 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 46201705 # Number of integer alu accesses +system.cpu0.committedInsts 49478313 # Number of instructions committed +system.cpu0.committedOps 49478313 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 46202260 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 197598 # Number of float alu accesses -system.cpu0.num_func_calls 1124633 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 6043603 # number of instructions that are conditional controls -system.cpu0.num_int_insts 46201705 # number of integer instructions +system.cpu0.num_func_calls 1124639 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 6043708 # number of instructions that are conditional controls +system.cpu0.num_int_insts 46202260 # number of integer instructions system.cpu0.num_fp_insts 197598 # number of float instructions -system.cpu0.num_int_register_reads 64003225 # number of times the integer registers were read -system.cpu0.num_int_register_writes 34834421 # number of times the integer registers were written +system.cpu0.num_int_register_reads 64004164 # number of times the integer registers were read +system.cpu0.num_int_register_writes 34834852 # number of times the integer registers were written system.cpu0.num_fp_register_reads 97440 # number of times the floating registers were read system.cpu0.num_fp_register_writes 98967 # number of times the floating registers were written -system.cpu0.num_mem_refs 12536107 # number of memory refs -system.cpu0.num_load_insts 7783754 # Number of load instructions -system.cpu0.num_store_insts 4752353 # Number of store instructions -system.cpu0.num_idle_cycles 3689239788.666409 # Number of idle cycles -system.cpu0.num_busy_cycles 49482982.333591 # Number of busy cycles +system.cpu0.num_mem_refs 12536155 # number of memory refs +system.cpu0.num_load_insts 7783785 # Number of load instructions +system.cpu0.num_store_insts 4752370 # Number of store instructions +system.cpu0.num_idle_cycles 3689240240.665401 # Number of idle cycles +system.cpu0.num_busy_cycles 49483550.334599 # Number of busy cycles system.cpu0.not_idle_fraction 0.013235 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.986765 # Percentage of idle cycles -system.cpu0.Branches 7530826 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2589816 5.23% 5.23% # Class of executed instruction -system.cpu0.op_class::IntAlu 33436017 67.57% 72.80% # Class of executed instruction -system.cpu0.op_class::IntMult 50540 0.10% 72.90% # Class of executed instruction +system.cpu0.Branches 7530941 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2589824 5.23% 5.23% # Class of executed instruction +system.cpu0.op_class::IntAlu 33436514 67.57% 72.80% # Class of executed instruction +system.cpu0.op_class::IntMult 50547 0.10% 72.90% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 72.90% # Class of executed instruction system.cpu0.op_class::FloatAdd 27840 0.06% 72.96% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 72.96% # Class of executed instruction @@ -369,38 +136,38 @@ system.cpu0.op_class::SimdFloatMisc 0 0.00% 72.96% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 72.96% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.96% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::MemRead 7945590 16.06% 89.02% # Class of executed instruction -system.cpu0.op_class::MemWrite 4758292 9.62% 98.63% # Class of executed instruction -system.cpu0.op_class::IprAccess 675558 1.37% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 7945621 16.06% 89.02% # Class of executed instruction +system.cpu0.op_class::MemWrite 4758309 9.62% 98.63% # Class of executed instruction +system.cpu0.op_class::IprAccess 675566 1.37% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 49485886 # Class of executed instruction +system.cpu0.op_class::total 49486454 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 150435 # number of hwrei instructions executed +system.cpu0.kern.inst.hwrei 150436 # number of hwrei instructions executed system.cpu0.kern.ipl_count::0 51398 40.00% 40.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 243 0.19% 40.19% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 243 0.19% 40.18% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1907 1.48% 41.67% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 514 0.40% 42.07% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 74446 57.93% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 128508 # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 74447 57.93% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 128509 # number of times we switched to this ipl system.cpu0.kern.ipl_good::0 51050 48.97% 48.97% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 243 0.23% 49.20% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1907 1.83% 51.03% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 514 0.49% 51.52% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 50536 48.48% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 104250 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1853222721000 99.14% 99.14% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1853222948500 99.14% 99.14% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.14% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::22 82001000 0.00% 99.14% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::30 57621500 0.00% 99.15% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 15975327000 0.85% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1869357780500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 15975609500 0.85% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1869358290500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.993229 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.678828 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.811234 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.678818 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.811227 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 6 2.63% 2.63% # number of syscalls executed system.cpu0.kern.syscall::3 20 8.77% 11.40% # number of syscalls executed system.cpu0.kern.syscall::4 2 0.88% 12.28% # number of syscalls executed @@ -440,7 +207,7 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.46% # nu system.cpu0.kern.callpal::swpctx 2743 2.02% 2.47% # number of callpals executed system.cpu0.kern.callpal::tbi 39 0.03% 2.50% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.01% 2.51% # number of callpals executed -system.cpu0.kern.callpal::swpipl 121668 89.51% 92.02% # number of callpals executed +system.cpu0.kern.callpal::swpipl 121669 89.51% 92.02% # number of callpals executed system.cpu0.kern.callpal::rdps 6149 4.52% 96.54% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.54% # number of callpals executed system.cpu0.kern.callpal::wrusp 3 0.00% 96.54% # number of callpals executed @@ -449,179 +216,28 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.55% # nu system.cpu0.kern.callpal::rti 4175 3.07% 99.62% # number of callpals executed system.cpu0.kern.callpal::callsys 369 0.27% 99.89% # number of callpals executed system.cpu0.kern.callpal::imb 146 0.11% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 135929 # number of callpals executed +system.cpu0.kern.callpal::total 135930 # number of callpals executed system.cpu0.kern.mode_switch::kernel 6593 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1173 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1174 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1172 -system.cpu0.kern.mode_good::user 1173 +system.cpu0.kern.mode_good::kernel 1173 +system.cpu0.kern.mode_good::user 1174 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.177764 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.177916 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.301957 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1868349152500 99.95% 99.95% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1008627000 0.05% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.302176 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1868349657500 99.95% 99.95% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1008632000 0.05% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 2744 # number of times the context was actually changed -system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 2732156 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2732156 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14588 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 777631 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 19617 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 14229 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 33846 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 295242 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 295242 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1237878 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4301883 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 762376 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 627158 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6929295 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39612096 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155765243 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24396032 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23357911 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 243131282 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 41895 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3873157 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.010774 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.103239 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 3831426 98.92% 98.92% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 41731 1.08% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3873157 # Request fanout histogram -system.iobus.trans_dist::ReadReq 7628 # Transaction distribution -system.iobus.trans_dist::ReadResp 7628 # Transaction distribution -system.iobus.trans_dist::WriteReq 56140 # Transaction distribution -system.iobus.trans_dist::WriteResp 14588 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14686 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18036 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 44074 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83462 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83462 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 127536 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 58744 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 1392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9018 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 86162 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661656 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2747818 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.icache.tags.replacements 618292 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.240644 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 48866947 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 618804 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 78.969992 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 9786048500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.240644 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998517 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998517 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 333 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 50104825 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 50104825 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 48866947 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 48866947 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 48866947 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 48866947 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 48866947 # number of overall hits -system.cpu0.icache.overall_hits::total 48866947 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 618939 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 618939 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 618939 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 618939 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 618939 # number of overall misses -system.cpu0.icache.overall_misses::total 618939 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 49485886 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 49485886 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 49485886 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 49485886 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 49485886 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 49485886 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012507 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.012507 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012507 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.012507 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012507 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.012507 # miss rate for overall accesses -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1781371 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.187328 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10705763 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1781883 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 6.008118 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1781373 # number of replacements +system.cpu0.dcache.tags.tagsinuse 506.187448 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10705809 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1781885 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 6.008137 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.187328 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.187448 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988647 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.988647 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -629,56 +245,56 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 446 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51822042 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51822042 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6068881 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6068881 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4360082 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4360082 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 127592 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 127592 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 132846 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 132846 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10428963 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10428963 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10428963 # number of overall hits -system.cpu0.dcache.overall_hits::total 10428963 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1560069 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1560069 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 236541 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 236541 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 12626 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 12626 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6924 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 6924 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1796610 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1796610 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1796610 # number of overall misses -system.cpu0.dcache.overall_misses::total 1796610 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7628950 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7628950 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4596623 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4596623 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.tags.tag_accesses 51822236 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 51822236 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6068914 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6068914 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4360098 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4360098 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 127591 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 127591 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 132845 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 132845 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10429012 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10429012 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10429012 # number of overall hits +system.cpu0.dcache.overall_hits::total 10429012 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1560067 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1560067 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 236542 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 236542 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 12627 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 12627 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6925 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 6925 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1796609 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1796609 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1796609 # number of overall misses +system.cpu0.dcache.overall_misses::total 1796609 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7628981 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7628981 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4596640 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4596640 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 140218 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 140218 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 139770 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 139770 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12225573 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12225573 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12225573 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12225573 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.204493 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.204493 # miss rate for ReadReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 12225621 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12225621 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12225621 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12225621 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.204492 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.204492 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051460 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.051460 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.090046 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.090046 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049539 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.049539 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.146955 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.146955 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.146955 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.146955 # miss rate for overall accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.090053 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.090053 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049546 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.049546 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.146954 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.146954 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.146954 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.146954 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -687,14 +303,63 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 633103 # number of writebacks -system.cpu0.dcache.writebacks::total 633103 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 632997 # number of writebacks +system.cpu0.dcache.writebacks::total 632997 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.tags.replacements 618298 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.240646 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 48867509 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 618810 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 78.970135 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 9786048500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.240646 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998517 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998517 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 333 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 50105399 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 50105399 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 48867509 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 48867509 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 48867509 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 48867509 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 48867509 # number of overall hits +system.cpu0.icache.overall_hits::total 48867509 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 618945 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 618945 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 618945 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 618945 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 618945 # number of overall misses +system.cpu0.icache.overall_misses::total 618945 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 49486454 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 49486454 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 49486454 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 49486454 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 49486454 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 49486454 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012507 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.012507 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012507 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.012507 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012507 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.012507 # miss rate for overall accesses +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2831559 # DTB read hits +system.cpu1.dtb.read_hits 2831558 # DTB read hits system.cpu1.dtb.read_misses 3191 # DTB read misses system.cpu1.dtb.read_acv 58 # DTB read access violations system.cpu1.dtb.read_accesses 198160 # DTB read accesses @@ -702,7 +367,7 @@ system.cpu1.dtb.write_hits 2101673 # DT system.cpu1.dtb.write_misses 412 # DTB write misses system.cpu1.dtb.write_acv 55 # DTB write access violations system.cpu1.dtb.write_accesses 90619 # DTB write accesses -system.cpu1.dtb.data_hits 4933232 # DTB hits +system.cpu1.dtb.data_hits 4933231 # DTB hits system.cpu1.dtb.data_misses 3603 # DTB misses system.cpu1.dtb.data_acv 113 # DTB access violations system.cpu1.dtb.data_accesses 288779 # DTB accesses @@ -722,31 +387,31 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3738296587 # number of cpu cycles simulated +system.cpu1.numCycles 3738297607 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 15522159 # Number of instructions committed -system.cpu1.committedOps 15522159 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 14295544 # Number of integer alu accesses +system.cpu1.committedInsts 15522157 # Number of instructions committed +system.cpu1.committedOps 15522157 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 14295542 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 198941 # Number of float alu accesses system.cpu1.num_func_calls 493140 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1540068 # number of instructions that are conditional controls -system.cpu1.num_int_insts 14295544 # number of integer instructions +system.cpu1.num_conditional_control_insts 1540067 # number of instructions that are conditional controls +system.cpu1.num_int_insts 14295542 # number of integer instructions system.cpu1.num_fp_insts 198941 # number of float instructions -system.cpu1.num_int_register_reads 19514289 # number of times the integer registers were read -system.cpu1.num_int_register_writes 10457600 # number of times the integer registers were written +system.cpu1.num_int_register_reads 19514287 # number of times the integer registers were read +system.cpu1.num_int_register_writes 10457599 # number of times the integer registers were written system.cpu1.num_fp_register_reads 101734 # number of times the floating registers were read system.cpu1.num_fp_register_writes 104129 # number of times the floating registers were written -system.cpu1.num_mem_refs 4961786 # number of memory refs -system.cpu1.num_load_insts 2849090 # Number of load instructions +system.cpu1.num_mem_refs 4961785 # number of memory refs +system.cpu1.num_load_insts 2849089 # Number of load instructions system.cpu1.num_store_insts 2112696 # Number of store instructions -system.cpu1.num_idle_cycles 3722773649.474793 # Number of idle cycles -system.cpu1.num_busy_cycles 15522937.525207 # Number of busy cycles +system.cpu1.num_idle_cycles 3722774671.474094 # Number of idle cycles +system.cpu1.num_busy_cycles 15522935.525906 # Number of busy cycles system.cpu1.not_idle_fraction 0.004152 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.995848 # Percentage of idle cycles -system.cpu1.Branches 2214163 # Number of branches fetched +system.cpu1.Branches 2214162 # Number of branches fetched system.cpu1.op_class::No_OpClass 856043 5.51% 5.51% # Class of executed instruction -system.cpu1.op_class::IntAlu 9156766 58.98% 64.49% # Class of executed instruction +system.cpu1.op_class::IntAlu 9156765 58.98% 64.49% # Class of executed instruction system.cpu1.op_class::IntMult 25065 0.16% 64.65% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 64.65% # Class of executed instruction system.cpu1.op_class::FloatAdd 12426 0.08% 64.73% # Class of executed instruction @@ -775,11 +440,11 @@ system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.74% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 64.74% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.74% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::MemRead 2937016 18.92% 83.66% # Class of executed instruction +system.cpu1.op_class::MemRead 2937015 18.92% 83.66% # Class of executed instruction system.cpu1.op_class::MemWrite 2113897 13.62% 97.27% # Class of executed instruction system.cpu1.op_class::IprAccess 423253 2.73% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 15525875 # Class of executed instruction +system.cpu1.op_class::total 15525873 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 2704 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 92290 # number of hwrei instructions executed @@ -793,11 +458,11 @@ system.cpu1.kern.ipl_good::22 1906 2.99% 51.49% # nu system.cpu1.kern.ipl_good::30 616 0.97% 52.46% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::31 30319 47.54% 100.00% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::total 63776 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1856123490500 99.30% 99.30% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::0 1856124001500 99.30% 99.30% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::22 81958000 0.00% 99.31% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::30 70736500 0.00% 99.31% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 12870743500 0.69% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1869146928500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 12870742500 0.69% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1869147438500 # number of cycles we spent at this ipl system.cpu1.kern.ipl_used::0 0.967808 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl @@ -849,115 +514,67 @@ system.cpu1.kern.mode_switch_good::kernel 0.434066 # f system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle 0.177356 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::total 0.358625 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 5986368000 0.32% 0.32% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::kernel 5986367000 0.32% 0.32% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::user 456602000 0.02% 0.34% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1862102404500 99.66% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1862102855500 99.66% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 2507 # number of times the context was actually changed -system.cpu1.icache.tags.replacements 380647 # number of replacements -system.cpu1.icache.tags.tagsinuse 453.133719 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 15144687 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 381159 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 39.733253 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1859777157500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 453.133719 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.885027 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.885027 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 509 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 15907063 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 15907063 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 15144687 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 15144687 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 15144687 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 15144687 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 15144687 # number of overall hits -system.cpu1.icache.overall_hits::total 15144687 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 381188 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 381188 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 381188 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 381188 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 381188 # number of overall misses -system.cpu1.icache.overall_misses::total 381188 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 15525875 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 15525875 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 15525875 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 15525875 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 15525875 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 15525875 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024552 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024552 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024552 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024552 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024552 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024552 # miss rate for overall accesses -system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 201757 # number of replacements -system.cpu1.dcache.tags.tagsinuse 497.601960 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 4718401 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 202065 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 23.350907 # Average number of references to valid blocks. +system.cpu1.dcache.tags.replacements 201756 # number of replacements +system.cpu1.dcache.tags.tagsinuse 497.613037 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 4718402 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 202064 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 23.351027 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 15869420000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 497.601960 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.971879 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.971879 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 497.613037 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.971900 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.971900 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.601562 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 20020608 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 20020608 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2632688 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2632688 # number of ReadReq hits +system.cpu1.dcache.tags.tag_accesses 20020602 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 20020602 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 2632689 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2632689 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 1954642 # number of WriteReq hits system.cpu1.dcache.WriteReq_hits::total 1954642 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 61098 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 61098 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 61099 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 61099 # number of LoadLockedReq hits system.cpu1.dcache.StoreCondReq_hits::cpu1.data 64210 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 64210 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 4587330 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 4587330 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 4587330 # number of overall hits -system.cpu1.dcache.overall_hits::total 4587330 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 140885 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 140885 # number of ReadReq misses +system.cpu1.dcache.demand_hits::cpu1.data 4587331 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 4587331 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 4587331 # number of overall hits +system.cpu1.dcache.overall_hits::total 4587331 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 140883 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 140883 # number of ReadReq misses system.cpu1.dcache.WriteReq_misses::cpu1.data 78318 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 78318 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11000 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 11000 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10999 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 10999 # number of LoadLockedReq misses system.cpu1.dcache.StoreCondReq_misses::cpu1.data 7305 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 7305 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 219203 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 219203 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 219203 # number of overall misses -system.cpu1.dcache.overall_misses::total 219203 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2773573 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2773573 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.demand_misses::cpu1.data 219201 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 219201 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 219201 # number of overall misses +system.cpu1.dcache.overall_misses::total 219201 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2773572 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2773572 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 2032960 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::total 2032960 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 72098 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 72098 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 71515 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 71515 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4806533 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4806533 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4806533 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4806533 # number of overall (read+write) accesses +system.cpu1.dcache.demand_accesses::cpu1.data 4806532 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4806532 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4806532 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4806532 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050795 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.050795 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.038524 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_miss_rate::total 0.038524 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.152570 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.152570 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.152556 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.152556 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.102146 # miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::total 0.102146 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.045605 # miss rate for demand accesses @@ -972,8 +589,392 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 144528 # number of writebacks -system.cpu1.dcache.writebacks::total 144528 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 144531 # number of writebacks +system.cpu1.dcache.writebacks::total 144531 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.tags.replacements 380671 # number of replacements +system.cpu1.icache.tags.tagsinuse 453.133725 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 15144661 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 381183 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 39.730683 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1859779767500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 453.133725 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.885027 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.885027 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 509 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 15907085 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 15907085 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 15144661 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 15144661 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 15144661 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 15144661 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 15144661 # number of overall hits +system.cpu1.icache.overall_hits::total 15144661 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 381212 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 381212 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 381212 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 381212 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 381212 # number of overall misses +system.cpu1.icache.overall_misses::total 381212 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 15525873 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 15525873 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 15525873 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 15525873 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 15525873 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 15525873 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024553 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024553 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024553 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024553 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024553 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024553 # miss rate for overall accesses +system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. +system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_txs 395 # Number of DMA write transactions. +system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. +system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. +system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.iobus.trans_dist::ReadReq 7628 # Transaction distribution +system.iobus.trans_dist::ReadResp 7628 # Transaction distribution +system.iobus.trans_dist::WriteReq 56140 # Transaction distribution +system.iobus.trans_dist::WriteResp 14588 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14686 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18036 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 44074 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83462 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83462 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 127536 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 58744 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 1392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9018 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 86162 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661656 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2747818 # Cumulative packet size per connected master and slave (bytes) +system.iocache.tags.replacements 41699 # number of replacements +system.iocache.tags.tagsinuse 0.434101 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 1685787163517 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.434101 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.027131 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.027131 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 375579 # Number of tag accesses +system.iocache.tags.data_accesses 375579 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses +system.iocache.ReadReq_misses::total 179 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses +system.iocache.demand_misses::tsunami.ide 179 # number of demand (read+write) misses +system.iocache.demand_misses::total 179 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 179 # number of overall misses +system.iocache.overall_misses::total 179 # number of overall misses +system.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::tsunami.ide 179 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 179 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 179 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 179 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 41520 # number of writebacks +system.iocache.writebacks::total 41520 # number of writebacks +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.tags.replacements 999763 # number of replacements +system.l2c.tags.tagsinuse 65320.982513 # Cycle average of tags in use +system.l2c.tags.total_refs 2387511 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1064813 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.242188 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 56016.894287 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4834.499535 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4176.023150 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 178.992489 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 114.573052 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.854750 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.073769 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.063721 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.002731 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.001748 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.996719 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65050 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 768 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 3271 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 6125 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5943 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 48943 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.992584 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 31464842 # Number of tag accesses +system.l2c.tags.data_accesses 31464842 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.inst 606959 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 626686 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 379549 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 129013 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1742207 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 777528 # number of Writeback hits +system.l2c.Writeback_hits::total 777528 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 116 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 577 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 693 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 37 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 13 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 50 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 111433 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 56603 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 168036 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 606959 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 738119 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 379549 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 185616 # number of demand (read+write) hits +system.l2c.demand_hits::total 1910243 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 606959 # number of overall hits +system.l2c.overall_hits::cpu0.data 738119 # number of overall hits +system.l2c.overall_hits::cpu1.inst 379549 # number of overall hits +system.l2c.overall_hits::cpu1.data 185616 # number of overall hits +system.l2c.overall_hits::total 1910243 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 11965 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 926610 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1663 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1033 # number of ReadReq misses +system.l2c.ReadReq_misses::total 941271 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 3006 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 2174 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 5180 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 1175 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1110 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 2285 # 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number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 1553296 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 381212 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 130046 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2683478 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 777528 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 777528 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 3122 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 2751 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 5873 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 1212 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1123 # 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number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 197718 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2976499 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.019332 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.596544 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.004362 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.007943 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.350765 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.962844 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.790258 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.882002 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.969472 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.988424 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.978587 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.505509 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.163568 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.426539 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.019332 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.585010 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.004362 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.061208 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.358225 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.019332 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.585010 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.004362 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.061208 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.358225 # miss rate for overall accesses +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.writebacks::writebacks 80845 # number of writebacks +system.l2c.writebacks::total 80845 # number of writebacks +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 948899 # Transaction distribution +system.membus.trans_dist::ReadResp 948899 # Transaction distribution +system.membus.trans_dist::WriteReq 14588 # Transaction distribution +system.membus.trans_dist::WriteResp 14588 # Transaction distribution +system.membus.trans_dist::Writeback 122365 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.membus.trans_dist::UpgradeReq 19616 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 14180 # Transaction distribution +system.membus.trans_dist::UpgradeResp 8160 # Transaction distribution +system.membus.trans_dist::ReadExReq 126515 # Transaction distribution +system.membus.trans_dist::ReadExResp 124290 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 44074 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2256148 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 2300222 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124982 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124982 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2425204 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 86162 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73369984 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 73456146 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5328064 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 5328064 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 78784210 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 1265678 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 1265678 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 1265678 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 2732182 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2732182 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 14588 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 777528 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 19614 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 14230 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 33844 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 295246 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 295246 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1237890 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4301779 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 762424 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 627155 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6929248 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39612480 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155758587 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24397568 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23357975 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 243126610 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 41895 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3873082 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.010775 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.103240 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 3831351 98.92% 98.92% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 41731 1.08% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3873082 # Request fanout histogram +system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR +system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU +system.tsunami.ethernet.droppedPackets 0 # number of packets dropped ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index d02473de7..608395ba3 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -1,146 +1,51 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.829332 # Number of seconds simulated -sim_ticks 1829331993500 # Number of ticks simulated -final_tick 1829331993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1829332273500 # Number of ticks simulated +final_tick 1829332273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2920462 # Simulator instruction rate (inst/s) -host_op_rate 2920460 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 88984410684 # Simulator tick rate (ticks/s) -host_mem_usage 366200 # Number of bytes of host memory used -host_seconds 20.56 # Real time elapsed on the host -sim_insts 60038469 # Number of instructions simulated -sim_ops 60038469 # Number of ops (including micro ops) simulated +host_inst_rate 1690642 # Simulator instruction rate (inst/s) +host_op_rate 1690641 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51512796649 # Simulator tick rate (ticks/s) +host_mem_usage 313048 # Number of bytes of host memory used +host_seconds 35.51 # Real time elapsed on the host +sim_insts 60038341 # Number of instructions simulated +sim_ops 60038341 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 66856000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 66839040 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 67714944 # Number of bytes read from this memory +system.physmem.bytes_read::total 67697984 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4753856 # Number of bytes written to this memory -system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory -system.physmem.bytes_written::total 7413184 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 7411008 # Number of bytes written to this memory +system.physmem.bytes_written::total 7411008 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 13406 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1044625 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1044360 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1058046 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 74279 # Number of write requests responded to by this memory -system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115831 # Number of write requests responded to by this memory +system.physmem.num_reads::total 1057781 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115797 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115797 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 469015 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 36546674 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 36537397 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 37016214 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 37006937 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 469015 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 469015 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2598684 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::tsunami.ide 1453715 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4052399 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2598684 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 4051209 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4051209 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4051209 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 469015 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 36546674 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1454240 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 41068613 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 948404 # Transaction distribution -system.membus.trans_dist::ReadResp 948404 # Transaction distribution -system.membus.trans_dist::WriteReq 9838 # Transaction distribution -system.membus.trans_dist::WriteResp 9838 # Transaction distribution -system.membus.trans_dist::Writeback 74279 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 132 # Transaction distribution -system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 116985 # Transaction distribution -system.membus.trans_dist::ReadExResp 116985 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2190605 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 2224649 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83452 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 83452 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2308101 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72467840 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72513966 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2670464 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2670464 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 75184430 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 1174168 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 1174168 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 1174168 # Request fanout histogram -system.iocache.tags.replacements 41686 # number of replacements -system.iocache.tags.tagsinuse 1.225569 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1685780587017 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.225569 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375534 # Number of tag accesses -system.iocache.tags.data_accesses 375534 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits -system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses -system.iocache.ReadReq_misses::total 174 # number of ReadReq misses -system.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses -system.iocache.demand_misses::total 174 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 174 # number of overall misses -system.iocache.overall_misses::total 174 # number of overall misses -system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 174 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 174 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 41552 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. -system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_txs 395 # Number of DMA write transactions. -system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. -system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. -system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.physmem.bw_total::cpu.data 36537397 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 525 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 41058146 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9710423 # DTB read hits +system.cpu.dtb.read_hits 9710422 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations system.cpu.dtb.read_accesses 728856 # DTB read accesses @@ -148,14 +53,14 @@ system.cpu.dtb.write_hits 6352496 # DT system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 16062919 # DTB hits +system.cpu.dtb.data_hits 16062918 # DTB hits system.cpu.dtb.data_misses 11471 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations system.cpu.dtb.data_accesses 1020787 # DTB accesses -system.cpu.itb.fetch_hits 4974637 # ITB hits +system.cpu.itb.fetch_hits 4974648 # ITB hits system.cpu.itb.fetch_misses 5006 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979643 # ITB accesses +system.cpu.itb.fetch_accesses 4979654 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -168,31 +73,31 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3658670345 # number of cpu cycles simulated +system.cpu.numCycles 3658670905 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60038469 # Number of instructions committed -system.cpu.committedOps 60038469 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 55913692 # Number of integer alu accesses +system.cpu.committedInsts 60038341 # Number of instructions committed +system.cpu.committedOps 60038341 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 55913563 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses system.cpu.num_func_calls 1484182 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7110791 # number of instructions that are conditional controls -system.cpu.num_int_insts 55913692 # number of integer instructions +system.cpu.num_conditional_control_insts 7110761 # number of instructions that are conditional controls +system.cpu.num_int_insts 55913563 # number of integer instructions system.cpu.num_fp_insts 324460 # number of float instructions -system.cpu.num_int_register_reads 76954245 # number of times the integer registers were read -system.cpu.num_int_register_writes 41740352 # number of times the integer registers were written +system.cpu.num_int_register_reads 76954014 # number of times the integer registers were read +system.cpu.num_int_register_writes 41740254 # number of times the integer registers were written system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written -system.cpu.num_mem_refs 16115703 # number of memory refs -system.cpu.num_load_insts 9747509 # Number of load instructions +system.cpu.num_mem_refs 16115702 # number of memory refs +system.cpu.num_load_insts 9747508 # Number of load instructions system.cpu.num_store_insts 6368194 # Number of store instructions -system.cpu.num_idle_cycles 3598621002.088897 # Number of idle cycles -system.cpu.num_busy_cycles 60049342.911103 # Number of busy cycles +system.cpu.num_idle_cycles 3598621691.055137 # Number of idle cycles +system.cpu.num_busy_cycles 60049213.944863 # Number of busy cycles system.cpu.not_idle_fraction 0.016413 # Percentage of non-idle cycles system.cpu.idle_fraction 0.983587 # Percentage of idle cycles -system.cpu.Branches 9064428 # Number of branches fetched -system.cpu.op_class::No_OpClass 3199100 5.33% 5.33% # Class of executed instruction -system.cpu.op_class::IntAlu 39448406 65.69% 71.02% # Class of executed instruction +system.cpu.Branches 9064400 # Number of branches fetched +system.cpu.op_class::No_OpClass 3199098 5.33% 5.33% # Class of executed instruction +system.cpu.op_class::IntAlu 39448273 65.69% 71.02% # Class of executed instruction system.cpu.op_class::IntMult 60677 0.10% 71.12% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction system.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction @@ -221,34 +126,34 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::MemRead 9975077 16.61% 87.80% # Class of executed instruction +system.cpu.op_class::MemRead 9975076 16.61% 87.80% # Class of executed instruction system.cpu.op_class::MemWrite 6374115 10.61% 98.42% # Class of executed instruction -system.cpu.op_class::IprAccess 951209 1.58% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 951217 1.58% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 60050307 # Class of executed instruction +system.cpu.op_class::total 60050179 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211318 # number of hwrei instructions executed +system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105622 57.86% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182561 # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105623 57.86% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182562 # number of times we switched to this ipl system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1811929127500 99.05% 99.05% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1811929473000 99.05% 99.05% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 17302310500 0.95% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1829331786000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 17302245000 0.95% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1829332066000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.695527 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.816357 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.695521 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.816353 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -287,7 +192,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175248 91.19% 93.40% # number of callpals executed +system.cpu.kern.callpal::swpipl 175249 91.19% 93.40% # number of callpals executed system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed @@ -296,96 +201,99 @@ system.cpu.kern.callpal::whami 2 0.00% 96.93% # nu system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192179 # number of callpals executed +system.cpu.kern.callpal::total 192180 # number of callpals executed system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches -system.cpu.kern.mode_switch::user 1737 # number of protection mode switches +system.cpu.kern.mode_switch::user 1738 # number of protection mode switches system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1908 -system.cpu.kern.mode_good::user 1737 +system.cpu.kern.mode_good::kernel 1909 +system.cpu.kern.mode_good::user 1738 system.cpu.kern.mode_good::idle 171 -system.cpu.kern.mode_switch_good::kernel 0.320726 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.390064 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 26833316500 1.47% 1.47% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 1465069000 0.08% 1.55% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1801033399500 98.45% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 0.390229 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 26833319500 1.47% 1.47% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1801033671500 98.45% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed -system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.trans_dist::ReadReq 7358 # Transaction distribution -system.iobus.trans_dist::ReadResp 7358 # Transaction distribution -system.iobus.trans_dist::WriteReq 51390 # Transaction distribution -system.iobus.trans_dist::WriteResp 9838 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5248 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18012 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 34044 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 117496 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20992 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 1392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9006 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 46126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2707742 # Cumulative packet size per connected master and slave (bytes) -system.cpu.icache.tags.replacements 919603 # number of replacements -system.cpu.icache.tags.tagsinuse 511.215257 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 59130077 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 920115 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 64.263790 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 2042728 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 14038398 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2043240 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 6.870655 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 443 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 66369797 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 66369797 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7807758 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7807758 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5848202 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5848202 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183140 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183140 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13655960 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13655960 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13655960 # number of overall hits +system.cpu.dcache.overall_hits::total 13655960 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1721724 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1721724 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304370 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304370 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17163 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17163 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2026094 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2026094 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2026094 # number of overall misses +system.cpu.dcache.overall_misses::total 2026094 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 9529482 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9529482 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6152572 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6152572 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15682054 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15682054 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15682054 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15682054 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180673 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.180673 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049470 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049470 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085685 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085685 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.129198 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.129198 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.129198 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.129198 # miss rate for overall accesses +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 833501 # number of writebacks +system.cpu.dcache.writebacks::total 833501 # number of writebacks +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 919605 # number of replacements +system.cpu.icache.tags.tagsinuse 511.215260 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 59129947 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 920117 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 64.263509 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 9686452000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.215257 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 511.215260 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -393,26 +301,26 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 63 system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 332 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 60970537 # Number of tag accesses -system.cpu.icache.tags.data_accesses 60970537 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 59130077 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 59130077 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 59130077 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 59130077 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 59130077 # number of overall hits -system.cpu.icache.overall_hits::total 59130077 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 920230 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 920230 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 920230 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 920230 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 920230 # number of overall misses -system.cpu.icache.overall_misses::total 920230 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 60050307 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 60050307 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 60050307 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 60050307 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 60050307 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 60050307 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 60970411 # Number of tag accesses +system.cpu.icache.tags.data_accesses 60970411 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 59129947 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 59129947 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 59129947 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 59129947 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 59129947 # number of overall hits +system.cpu.icache.overall_hits::total 59129947 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 920232 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 920232 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 920232 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 920232 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 920232 # number of overall misses +system.cpu.icache.overall_misses::total 920232 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 60050179 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 60050179 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 60050179 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 60050179 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 60050179 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 60050179 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses @@ -428,15 +336,15 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 992289 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65424.374569 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2433258 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1057452 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.301058 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 992295 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65424.374284 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2433284 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1057458 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.301069 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 56310.337833 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4866.106258 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4247.930478 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 56310.352234 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4866.099732 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 4247.922318 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.859228 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074251 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy @@ -445,66 +353,66 @@ system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 781 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3260 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4024 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3048 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54050 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3055 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54043 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 31737481 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 31737481 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 906806 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 811234 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1718040 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 833484 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 833484 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 31737815 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 31737815 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 906808 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 811247 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1718055 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 833501 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 833501 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187241 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187241 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 906806 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 998475 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1905281 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 906806 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 998475 # number of overall hits -system.cpu.l2cache.overall_hits::total 1905281 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 187243 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187243 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 906808 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 998490 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1905298 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 906808 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 998490 # number of overall hits +system.cpu.l2cache.overall_hits::total 1905298 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 941046 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 117105 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 117105 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 117111 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 117111 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 13406 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1044745 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1058151 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1044751 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1058157 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 13406 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1044745 # number of overall misses -system.cpu.l2cache.overall_misses::total 1058151 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 920212 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1738874 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2659086 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 833484 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 833484 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 1044751 # number of overall misses +system.cpu.l2cache.overall_misses::total 1058157 # number of overall misses +system.cpu.l2cache.ReadReq_accesses::cpu.inst 920214 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1738887 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2659101 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 833501 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 833501 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304346 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 920212 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2043220 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2963432 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 920212 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2043220 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2963432 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304354 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304354 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 920214 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2043241 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2963455 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 920214 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2043241 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2963455 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014568 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533472 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.353898 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533468 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.353896 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384776 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.384776 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384785 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.384785 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014568 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.511323 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.511320 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.357069 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014568 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.511323 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.511320 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.357069 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -514,106 +422,199 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 74279 # number of writebacks -system.cpu.l2cache.writebacks::total 74279 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 74285 # number of writebacks +system.cpu.l2cache.writebacks::total 74285 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2042707 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14038420 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2043219 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 6.870737 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 443 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 66369780 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 66369780 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7807771 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7807771 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5848210 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5848210 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13655981 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13655981 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13655981 # number of overall hits -system.cpu.dcache.overall_hits::total 13655981 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1721712 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1721712 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304362 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2026074 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2026074 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2026074 # number of overall misses -system.cpu.dcache.overall_misses::total 2026074 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 9529483 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9529483 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6152572 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6152572 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15682055 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15682055 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15682055 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15682055 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 833484 # number of writebacks -system.cpu.dcache.writebacks::total 833484 # number of writebacks -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2666288 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2666288 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2666303 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2666303 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 833484 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 833501 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304346 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304346 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1840460 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4954000 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6794460 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58894720 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184155182 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 243049902 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 304354 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304354 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1840464 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4954059 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6794523 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58894848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184157614 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 243052462 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 41883 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3838676 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 3838716 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1.010870 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.103691 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.103690 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3796950 98.91% 98.91% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3796990 98.91% 98.91% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 41726 1.09% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3838676 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3838716 # Request fanout histogram +system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. +system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_txs 395 # Number of DMA write transactions. +system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. +system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. +system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.iobus.trans_dist::ReadReq 7358 # Transaction distribution +system.iobus.trans_dist::ReadResp 7358 # Transaction distribution +system.iobus.trans_dist::WriteReq 51390 # Transaction distribution +system.iobus.trans_dist::WriteResp 9838 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5248 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18012 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 34044 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 117496 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20992 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 1392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9006 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 46126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2707742 # Cumulative packet size per connected master and slave (bytes) +system.iocache.tags.replacements 41686 # number of replacements +system.iocache.tags.tagsinuse 1.225572 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 1685780587017 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.225572 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 375534 # Number of tag accesses +system.iocache.tags.data_accesses 375534 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses +system.iocache.ReadReq_misses::total 174 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses +system.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses +system.iocache.demand_misses::total 174 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 174 # number of overall misses +system.iocache.overall_misses::total 174 # number of overall misses +system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 174 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 174 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 41512 # number of writebacks +system.iocache.writebacks::total 41512 # number of writebacks +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 948404 # Transaction distribution +system.membus.trans_dist::ReadResp 948404 # Transaction distribution +system.membus.trans_dist::WriteReq 9838 # Transaction distribution +system.membus.trans_dist::WriteResp 9838 # Transaction distribution +system.membus.trans_dist::Writeback 115797 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.membus.trans_dist::UpgradeReq 132 # Transaction distribution +system.membus.trans_dist::UpgradeResp 132 # Transaction distribution +system.membus.trans_dist::ReadExReq 116991 # Transaction distribution +system.membus.trans_dist::ReadExResp 116991 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2190623 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 2224667 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124964 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124964 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2349631 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72468608 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72514734 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5327232 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 5327232 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 77841966 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 1215692 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 1215692 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 1215692 # Request fanout histogram +system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR +system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU +system.tsunami.ethernet.droppedPackets 0 # number of packets dropped ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index dd52d45d1..9ca2241e2 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,121 +1,118 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.961827 # Number of seconds simulated -sim_ticks 1961826628500 # Number of ticks simulated -final_tick 1961826628500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.962845 # Number of seconds simulated +sim_ticks 1962844580000 # Number of ticks simulated +final_tick 1962844580000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1248737 # Simulator instruction rate (inst/s) -host_op_rate 1248737 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40231703865 # Simulator tick rate (ticks/s) -host_mem_usage 312404 # Number of bytes of host memory used -host_seconds 48.76 # Real time elapsed on the host -sim_insts 60892387 # Number of instructions simulated -sim_ops 60892387 # Number of ops (including micro ops) simulated +host_inst_rate 1184099 # Simulator instruction rate (inst/s) +host_op_rate 1184098 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38148129943 # Simulator tick rate (ticks/s) +host_mem_usage 318172 # Number of bytes of host memory used +host_seconds 51.45 # Real time elapsed on the host +sim_insts 60925667 # Number of instructions simulated +sim_ops 60925667 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 833152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24900864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 823168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24882816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 41728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 386368 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 31872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 336832 # Number of bytes read from this memory -system.physmem.bytes_read::total 26103680 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 833152 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 31872 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 865024 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5078656 # Number of bytes written to this memory -system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory -system.physmem.bytes_written::total 7737984 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13018 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 389076 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26135040 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 823168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 41728 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 864896 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7758336 # Number of bytes written to this memory +system.physmem.bytes_written::total 7758336 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12862 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 388794 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 652 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6037 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 498 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 5263 # Number of read requests responded to by this memory -system.physmem.num_reads::total 407870 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 79354 # Number of write requests responded to by this memory -system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120906 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 424682 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12692693 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 408360 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 121224 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121224 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 419375 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12676916 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 21259 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 196841 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 16246 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 171693 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13305804 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 424682 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 16246 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 440928 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2588738 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::tsunami.ide 1355537 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3944275 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2588738 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 424682 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12692693 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1356026 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 16246 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 171693 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17250079 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 407870 # Number of read requests accepted -system.physmem.writeReqs 120906 # Number of write requests accepted -system.physmem.readBursts 407870 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 120906 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26092032 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 11648 # Total number of bytes read from write queue -system.physmem.bytesWritten 7736064 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26103680 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7737984 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 182 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 6995 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25277 # Per bank write bursts -system.physmem.perBankRdBursts::1 25718 # Per bank write bursts -system.physmem.perBankRdBursts::2 25598 # Per bank write bursts -system.physmem.perBankRdBursts::3 25075 # Per bank write bursts -system.physmem.perBankRdBursts::4 25186 # Per bank write bursts -system.physmem.perBankRdBursts::5 25258 # Per bank write bursts -system.physmem.perBankRdBursts::6 25824 # Per bank write bursts -system.physmem.perBankRdBursts::7 25548 # Per bank write bursts -system.physmem.perBankRdBursts::8 25573 # Per bank write bursts -system.physmem.perBankRdBursts::9 25196 # Per bank write bursts -system.physmem.perBankRdBursts::10 25177 # Per bank write bursts -system.physmem.perBankRdBursts::11 25610 # Per bank write bursts -system.physmem.perBankRdBursts::12 25669 # Per bank write bursts -system.physmem.perBankRdBursts::13 25717 # Per bank write bursts -system.physmem.perBankRdBursts::14 26016 # Per bank write bursts -system.physmem.perBankRdBursts::15 25246 # Per bank write bursts -system.physmem.perBankWrBursts::0 7929 # Per bank write bursts -system.physmem.perBankWrBursts::1 7788 # Per bank write bursts -system.physmem.perBankWrBursts::2 7545 # Per bank write bursts -system.physmem.perBankWrBursts::3 7026 # Per bank write bursts -system.physmem.perBankWrBursts::4 7134 # Per bank write bursts -system.physmem.perBankWrBursts::5 7133 # Per bank write bursts -system.physmem.perBankWrBursts::6 7657 # Per bank write bursts -system.physmem.perBankWrBursts::7 7252 # Per bank write bursts -system.physmem.perBankWrBursts::8 7395 # Per bank write bursts -system.physmem.perBankWrBursts::9 7084 # Per bank write bursts -system.physmem.perBankWrBursts::10 7119 # Per bank write bursts -system.physmem.perBankWrBursts::11 7401 # Per bank write bursts -system.physmem.perBankWrBursts::12 7832 # Per bank write bursts -system.physmem.perBankWrBursts::13 8315 # Per bank write bursts -system.physmem.perBankWrBursts::14 8567 # Per bank write bursts -system.physmem.perBankWrBursts::15 7699 # Per bank write bursts +system.physmem.bw_read::total 13314880 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 419375 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 21259 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 440634 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3952598 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3952598 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3952598 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 419375 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12676916 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 21259 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 196841 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 489 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17267478 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 408360 # Number of read requests accepted +system.physmem.writeReqs 162776 # Number of write requests accepted +system.physmem.readBursts 408360 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 162776 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26127936 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue +system.physmem.bytesWritten 10271680 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26135040 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10417664 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2254 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 7048 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25705 # Per bank write bursts +system.physmem.perBankRdBursts::1 25985 # Per bank write bursts +system.physmem.perBankRdBursts::2 25732 # Per bank write bursts +system.physmem.perBankRdBursts::3 25537 # Per bank write bursts +system.physmem.perBankRdBursts::4 24847 # Per bank write bursts +system.physmem.perBankRdBursts::5 24747 # Per bank write bursts +system.physmem.perBankRdBursts::6 25534 # Per bank write bursts +system.physmem.perBankRdBursts::7 25495 # Per bank write bursts +system.physmem.perBankRdBursts::8 25150 # Per bank write bursts +system.physmem.perBankRdBursts::9 25518 # Per bank write bursts +system.physmem.perBankRdBursts::10 25462 # Per bank write bursts +system.physmem.perBankRdBursts::11 25292 # Per bank write bursts +system.physmem.perBankRdBursts::12 25577 # Per bank write bursts +system.physmem.perBankRdBursts::13 25454 # Per bank write bursts +system.physmem.perBankRdBursts::14 26241 # Per bank write bursts +system.physmem.perBankRdBursts::15 25973 # Per bank write bursts +system.physmem.perBankWrBursts::0 10613 # Per bank write bursts +system.physmem.perBankWrBursts::1 10753 # Per bank write bursts +system.physmem.perBankWrBursts::2 9796 # Per bank write bursts +system.physmem.perBankWrBursts::3 9387 # Per bank write bursts +system.physmem.perBankWrBursts::4 8893 # Per bank write bursts +system.physmem.perBankWrBursts::5 9110 # Per bank write bursts +system.physmem.perBankWrBursts::6 9958 # Per bank write bursts +system.physmem.perBankWrBursts::7 9669 # Per bank write bursts +system.physmem.perBankWrBursts::8 9689 # Per bank write bursts +system.physmem.perBankWrBursts::9 9901 # Per bank write bursts +system.physmem.perBankWrBursts::10 9876 # Per bank write bursts +system.physmem.perBankWrBursts::11 10215 # Per bank write bursts +system.physmem.perBankWrBursts::12 10815 # Per bank write bursts +system.physmem.perBankWrBursts::13 10652 # Per bank write bursts +system.physmem.perBankWrBursts::14 10531 # Per bank write bursts +system.physmem.perBankWrBursts::15 10637 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 8 # Number of times write queue was full causing retry -system.physmem.totGap 1961819616500 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 1962839541500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 407870 # Read request sizes (log2) +system.physmem.readPktSize::6 408360 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 120906 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 407616 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 59 # What read queue length does an incoming req see +system.physmem.writePktSize::6 162776 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 408168 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 68 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see @@ -161,632 +158,180 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1871 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2613 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8598 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8791 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6804 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5901 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5617 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 19 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 66427 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 509.252202 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 306.095148 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 413.238328 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15972 24.04% 24.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 12116 18.24% 42.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5140 7.74% 50.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2994 4.51% 54.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3304 4.97% 59.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1746 2.63% 62.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1491 2.24% 64.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1317 1.98% 66.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22347 33.64% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 66427 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5433 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 75.036996 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2192.886898 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 5428 99.91% 99.91% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 8312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 9464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 10119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 11465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11871 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11907 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10784 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8090 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 69162 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 526.295017 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 318.923666 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 416.254848 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16035 23.18% 23.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 12178 17.61% 40.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5186 7.50% 48.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3086 4.46% 52.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3308 4.78% 57.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1800 2.60% 60.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1507 2.18% 62.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1316 1.90% 64.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 24746 35.78% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 69162 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5880 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 69.428401 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2107.963348 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 5875 99.91% 99.91% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-8191 1 0.02% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-45055 1 0.02% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-45055 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::73728-77823 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::122880-126975 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5433 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5433 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.248482 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.059784 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 19.984616 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4773 87.85% 87.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 17 0.31% 88.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 17 0.31% 88.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 237 4.36% 92.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 33 0.61% 93.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 9 0.17% 93.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 6 0.11% 93.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 9 0.17% 93.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 24 0.44% 94.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 1 0.02% 94.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 10 0.18% 94.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 6 0.11% 94.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.06% 94.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 4 0.07% 94.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 32 0.59% 95.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 11 0.20% 95.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.06% 95.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 9 0.17% 95.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 180 3.31% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.07% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.02% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 3 0.06% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 4 0.07% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 4 0.07% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 5 0.09% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 7 0.13% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 13 0.24% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.04% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 2 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5433 # Writes before turning the bus around for reads -system.physmem.totQLat 2198653000 # Total ticks spent queuing -system.physmem.totMemAccLat 9842803000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2038440000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5392.98 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5880 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5880 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.295068 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.802481 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 33.368634 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4837 82.26% 82.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 186 3.16% 85.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 281 4.78% 90.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 57 0.97% 91.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 98 1.67% 92.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 42 0.71% 93.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 21 0.36% 93.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 12 0.20% 94.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 21 0.36% 94.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 6 0.10% 94.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 10 0.17% 94.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 8 0.14% 94.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 13 0.22% 95.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 5 0.09% 95.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 22 0.37% 95.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 44 0.75% 96.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 23 0.39% 96.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 6 0.10% 96.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 80 1.36% 98.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 40 0.68% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 14 0.24% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 24 0.41% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 14 0.24% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 2 0.03% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 5 0.09% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 2 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 4 0.07% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5880 # Writes before turning the bus around for reads +system.physmem.totQLat 2202002500 # Total ticks spent queuing +system.physmem.totMemAccLat 9856671250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2041245000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5393.77 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24142.98 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.30 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.94 # Average achieved write bandwidth in MiByte/s +system.physmem.avgMemAccLat 24143.77 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.31 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 5.23 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.31 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.94 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 5.31 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.13 # Data bus utilization in percentage +system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.12 # Average write queue length when enqueuing -system.physmem.readRowHits 365377 # Number of row buffer hits during reads -system.physmem.writeRowHits 96760 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.62 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.03 # Row buffer hit rate for writes -system.physmem.avgGap 3710114.71 # Average gap between requests -system.physmem.pageHitRate 87.43 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1840052567250 # Time in different power states -system.physmem.memoryStateTime::REF 65509600000 # Time in different power states +system.physmem.avgWrQLen 26.11 # Average write queue length when enqueuing +system.physmem.readRowHits 365785 # Number of row buffer hits during reads +system.physmem.writeRowHits 133797 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.60 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 83.35 # Row buffer hit rate for writes +system.physmem.avgGap 3436728.80 # Average gap between requests +system.physmem.pageHitRate 87.84 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1840639787000 # Time in different power states +system.physmem.memoryStateTime::REF 65543660000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 56261656500 # Time in different power states +system.physmem.memoryStateTime::ACT 56660375500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 248270400 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 253917720 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 135465000 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 138546375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1587175200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1592791200 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 385326720 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 397949760 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 128136777600 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 128136777600 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 65365947855 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 65768853780 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1119755735250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1119402309000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1315614698025 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1315691145435 # Total energy per rank (pJ) -system.physmem.averagePower::0 670.607978 # Core power per rank (mW) -system.physmem.averagePower::1 670.646945 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 292757 # Transaction distribution -system.membus.trans_dist::ReadResp 292757 # Transaction distribution -system.membus.trans_dist::WriteReq 14067 # Transaction distribution -system.membus.trans_dist::WriteResp 14067 # Transaction distribution -system.membus.trans_dist::Writeback 79354 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16159 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11272 # Transaction distribution -system.membus.trans_dist::UpgradeResp 6995 # Transaction distribution -system.membus.trans_dist::ReadExReq 123294 # Transaction distribution -system.membus.trans_dist::ReadExResp 122471 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42532 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 930313 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 972845 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83293 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 83293 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1056138 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 81954 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31181376 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31263330 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33923618 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 21418 # Total snoops (count) -system.membus.snoop_fanout::samples 557197 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 557197 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 557197 # Request fanout histogram -system.membus.reqLayer0.occupancy 40794500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1536995500 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3833296255 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 43122000 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.physmem.actEnergy::0 257115600 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 265749120 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 140291250 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 145002000 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 1587939600 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 1596402600 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 506599920 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 533407680 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 128203398960 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 128203398960 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 65563204050 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 65997539775 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1120194702750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1119813706500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1316453252130 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1316555206635 # Total energy per rank (pJ) +system.physmem.averagePower::0 670.686708 # Core power per rank (mW) +system.physmem.averagePower::1 670.738650 # Core power per rank (mW) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 342092 # number of replacements -system.l2c.tags.tagsinuse 65220.775537 # Cycle average of tags in use -system.l2c.tags.total_refs 2444844 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 407280 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.002858 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 8652068750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55275.158075 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4808.073812 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4934.415131 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 159.916198 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 43.212322 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.843432 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.073365 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.075293 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002440 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000659 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995190 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65188 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 763 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5265 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7161 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 51884 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.994690 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 25951455 # Number of tag accesses -system.l2c.tags.data_accesses 25951455 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 690677 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 668171 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 311497 # 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miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.138541 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.941964 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.763135 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.866605 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.955914 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.975322 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.965628 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.474650 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.106488 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.415771 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.018504 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.327842 # 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mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018499 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.327842 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001596 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.034750 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.173343 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60477.358273 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52555.421897 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60406.124498 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 59444.327731 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 52936.231534 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10002.692620 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.064509 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56495.967982 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61784.943816 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 56712.609070 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60477.358273 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53748.356465 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60406.124498 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61679.338768 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 54073.440389 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60477.358273 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53748.356465 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60406.124498 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61679.338768 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 54073.440389 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 41694 # number of replacements -system.iocache.tags.tagsinuse 0.569739 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1755504878000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.569739 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035609 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035609 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375534 # Number of tag accesses -system.iocache.tags.data_accesses 375534 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits -system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses -system.iocache.ReadReq_misses::total 174 # number of ReadReq misses -system.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses -system.iocache.demand_misses::total 174 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 174 # number of overall misses -system.iocache.overall_misses::total 174 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21248383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21248383 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21248383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21248383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21248383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21248383 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 174 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 174 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122117.143678 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122117.143678 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 122117.143678 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 122117.143678 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 122117.143678 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 122117.143678 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 41552 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 174 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 174 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 174 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12199383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12199383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2501404806 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2501404806 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12199383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12199383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12199383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12199383 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70111.396552 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70111.396552 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70111.396552 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70111.396552 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70111.396552 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70111.396552 # average overall mshr miss latency -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. -system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_txs 395 # Number of DMA write transactions. -system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. -system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. -system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7562596 # DTB read hits +system.cpu0.dtb.read_hits 7534386 # DTB read hits system.cpu0.dtb.read_misses 7765 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 524069 # DTB read accesses -system.cpu0.dtb.write_hits 5147185 # DTB write hits +system.cpu0.dtb.write_hits 5126601 # DTB write hits system.cpu0.dtb.write_misses 910 # DTB write misses system.cpu0.dtb.write_acv 133 # DTB write access violations system.cpu0.dtb.write_accesses 202595 # DTB write accesses -system.cpu0.dtb.data_hits 12709781 # DTB hits +system.cpu0.dtb.data_hits 12660987 # DTB hits system.cpu0.dtb.data_misses 8675 # DTB misses system.cpu0.dtb.data_acv 343 # DTB access violations system.cpu0.dtb.data_accesses 726664 # DTB accesses -system.cpu0.itb.fetch_hits 3660706 # ITB hits +system.cpu0.itb.fetch_hits 3654300 # ITB hits system.cpu0.itb.fetch_misses 3984 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3664690 # ITB accesses +system.cpu0.itb.fetch_accesses 3658284 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -799,91 +344,91 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3923653257 # number of cpu cycles simulated +system.cpu0.numCycles 3925689160 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 48127777 # Number of instructions committed -system.cpu0.committedOps 48127777 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 44643925 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 213512 # Number of float alu accesses -system.cpu0.num_func_calls 1209739 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5647172 # number of instructions that are conditional controls -system.cpu0.num_int_insts 44643925 # number of integer instructions -system.cpu0.num_fp_insts 213512 # number of float instructions -system.cpu0.num_int_register_reads 61387452 # number of times the integer registers were read -system.cpu0.num_int_register_writes 33242964 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 104337 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 106136 # number of times the floating registers were written -system.cpu0.num_mem_refs 12750882 # number of memory refs -system.cpu0.num_load_insts 7590433 # Number of load instructions -system.cpu0.num_store_insts 5160449 # Number of store instructions -system.cpu0.num_idle_cycles 3699495012.998114 # Number of idle cycles -system.cpu0.num_busy_cycles 224158244.001886 # Number of busy cycles -system.cpu0.not_idle_fraction 0.057130 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.942870 # Percentage of idle cycles -system.cpu0.Branches 7246936 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2741568 5.70% 5.70% # Class of executed instruction -system.cpu0.op_class::IntAlu 31634980 65.72% 71.41% # Class of executed instruction -system.cpu0.op_class::IntMult 52525 0.11% 71.52% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.52% # Class of executed instruction -system.cpu0.op_class::FloatAdd 26830 0.06% 71.58% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1883 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::MemRead 7767201 16.14% 87.72% # Class of executed instruction -system.cpu0.op_class::MemWrite 5166567 10.73% 98.45% # Class of executed instruction -system.cpu0.op_class::IprAccess 745241 1.55% 100.00% # Class of executed instruction +system.cpu0.committedInsts 47974635 # Number of instructions committed +system.cpu0.committedOps 47974635 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44501266 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 212945 # Number of float alu accesses +system.cpu0.num_func_calls 1202793 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5632199 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44501266 # number of integer instructions +system.cpu0.num_fp_insts 212945 # number of float instructions +system.cpu0.num_int_register_reads 61193579 # number of times the integer registers were read +system.cpu0.num_int_register_writes 33138119 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 104073 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 105864 # number of times the floating registers were written +system.cpu0.num_mem_refs 12702031 # number of memory refs +system.cpu0.num_load_insts 7562183 # Number of load instructions +system.cpu0.num_store_insts 5139848 # Number of store instructions +system.cpu0.num_idle_cycles 3702096779.998114 # Number of idle cycles +system.cpu0.num_busy_cycles 223592380.001886 # Number of busy cycles +system.cpu0.not_idle_fraction 0.056956 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.943044 # Percentage of idle cycles +system.cpu0.Branches 7223323 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2734296 5.70% 5.70% # Class of executed instruction +system.cpu0.op_class::IntAlu 31541688 65.73% 71.43% # Class of executed instruction +system.cpu0.op_class::IntMult 52334 0.11% 71.54% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 71.54% # Class of executed instruction +system.cpu0.op_class::FloatAdd 26783 0.06% 71.60% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1883 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::MemRead 7738218 16.13% 87.73% # Class of executed instruction +system.cpu0.op_class::MemWrite 5145965 10.72% 98.45% # Class of executed instruction +system.cpu0.op_class::IprAccess 742486 1.55% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 48136795 # Class of executed instruction +system.cpu0.op_class::total 47983653 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6805 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 166328 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 57239 40.25% 40.25% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.34% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1975 1.39% 41.73% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 424 0.30% 42.03% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 82449 57.97% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 142218 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 56706 49.09% 49.09% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 165589 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 56925 40.22% 40.22% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.31% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1976 1.40% 41.70% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 424 0.30% 42.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 82092 58.00% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 141548 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 56392 49.08% 49.08% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1975 1.71% 50.91% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 424 0.37% 51.28% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 56283 48.72% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 115519 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1902225794500 96.96% 96.96% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 94977500 0.00% 96.97% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 767421000 0.04% 97.01% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 314336500 0.02% 97.02% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 58423341500 2.98% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1961825871000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.990688 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::22 1976 1.72% 50.92% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 424 0.37% 51.29% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 55969 48.71% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 114892 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1903342573000 96.97% 96.97% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 94358500 0.00% 96.97% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 767882500 0.04% 97.01% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 314406500 0.02% 97.03% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 58324587500 2.97% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1962843808000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.990637 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.682640 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.812267 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.681784 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.811682 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed @@ -915,355 +460,125 @@ system.cpu0.kern.syscall::144 2 0.85% 99.15% # nu system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 234 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 506 0.34% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wripir 512 0.34% 0.34% # number of callpals executed system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3105 2.06% 2.40% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.43% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.44% # number of callpals executed -system.cpu0.kern.callpal::swpipl 135265 89.81% 92.25% # number of callpals executed -system.cpu0.kern.callpal::rdps 6701 4.45% 96.70% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.70% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 96.70% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.71% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.71% # number of callpals executed -system.cpu0.kern.callpal::rti 4423 2.94% 99.65% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3097 2.07% 2.41% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed +system.cpu0.kern.callpal::swpipl 134593 89.81% 92.26% # number of callpals executed +system.cpu0.kern.callpal::rdps 6634 4.43% 96.68% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.68% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 96.69% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.69% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.69% # number of callpals executed +system.cpu0.kern.callpal::rti 4424 2.95% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 394 0.26% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 150611 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7020 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1371 # number of protection mode switches +system.cpu0.kern.callpal::total 149871 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7013 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1370 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1370 -system.cpu0.kern.mode_good::user 1371 +system.cpu0.kern.mode_good::kernel 1369 +system.cpu0.kern.mode_good::user 1370 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.195157 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.195209 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.326660 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1958053140500 99.81% 99.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3772726000 0.19% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.326733 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1959059969000 99.81% 99.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3783834500 0.19% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3106 # number of times the context was actually changed -system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 2102030 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2102015 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14067 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14067 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 792816 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 41560 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 16382 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11336 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 27718 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 297616 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 297616 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1407417 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3134555 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 624007 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 452565 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5618544 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 45036672 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 120042720 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 19968192 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16553666 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 201601250 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 98838 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3254541 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.012823 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.112512 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 3212807 98.72% 98.72% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 41734 1.28% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3254541 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4795402363 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 715500 # Layer occupancy (ticks) -system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3169257997 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5536514081 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1404115991 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 776560164 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 7373 # Transaction distribution -system.iobus.trans_dist::ReadResp 7373 # Transaction distribution -system.iobus.trans_dist::WriteReq 55619 # Transaction distribution -system.iobus.trans_dist::WriteResp 55619 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13922 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 42532 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 125984 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55688 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 81954 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2743570 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 13277000 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) -system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 2453000 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 374410189 # Layer occupancy (ticks) -system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) -system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28465000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42017000 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 703089 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.385515 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 47433077 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 703601 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.414738 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 40276505250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.385515 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992940 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.992940 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 48840515 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 48840515 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 47433077 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 47433077 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 47433077 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 47433077 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 47433077 # number of overall hits -system.cpu0.icache.overall_hits::total 47433077 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 703719 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 703719 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 703719 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 703719 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 703719 # number of overall misses -system.cpu0.icache.overall_misses::total 703719 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10017635497 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10017635497 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10017635497 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10017635497 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10017635497 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10017635497 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 48136796 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 48136796 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 48136796 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 48136796 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 48136796 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 48136796 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014619 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014619 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014619 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014619 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014619 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014619 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14235.277855 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14235.277855 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14235.277855 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14235.277855 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14235.277855 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14235.277855 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 703719 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 703719 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 703719 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 703719 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 703719 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 703719 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8605152503 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 8605152503 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8605152503 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 8605152503 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8605152503 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 8605152503 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014619 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014619 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014619 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014619 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014619 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014619 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12228.108809 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12228.108809 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12228.108809 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12228.108809 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12228.108809 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12228.108809 # average overall mshr miss latency -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1191194 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.224955 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11513307 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1191706 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.661197 # Average number of references to valid blocks. +system.cpu0.kern.swap_context 3098 # number of times the context was actually changed +system.cpu0.dcache.tags.replacements 1190018 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.199068 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11465472 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1190530 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.630561 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 108210250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.224955 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986767 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986767 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.199068 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986717 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986717 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 328 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 52084143 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 52084143 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6477469 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6477469 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4731394 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4731394 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 141563 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 141563 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149256 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 149256 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11208863 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11208863 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11208863 # number of overall hits -system.cpu0.dcache.overall_hits::total 11208863 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 942620 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 942620 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 258040 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 258040 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13696 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13696 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5452 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5452 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1200660 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1200660 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1200660 # number of overall misses -system.cpu0.dcache.overall_misses::total 1200660 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27232981250 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 27232981250 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10355566942 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 10355566942 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 149859500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 149859500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 42011389 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 42011389 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 37588548192 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 37588548192 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 37588548192 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 37588548192 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7420089 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7420089 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4989434 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4989434 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 155259 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 155259 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 154708 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 154708 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12409523 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12409523 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12409523 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12409523 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127036 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.127036 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051717 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051717 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088214 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088214 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035241 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035241 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.096753 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.096753 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096753 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.096753 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28890.731419 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 28890.731419 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40131.634406 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 40131.634406 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10941.844334 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10941.844334 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7705.683969 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7705.683969 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31306.571546 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 31306.571546 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31306.571546 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 31306.571546 # average overall miss latency +system.cpu0.dcache.tags.tag_accesses 51888213 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 51888213 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6450398 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6450398 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4712072 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4712072 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140773 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 140773 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148356 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 148356 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11162470 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11162470 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11162470 # number of overall hits +system.cpu0.dcache.overall_hits::total 11162470 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 942246 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 942246 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 257610 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 257610 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13707 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13707 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5575 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 5575 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1199856 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1199856 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1199856 # number of overall misses +system.cpu0.dcache.overall_misses::total 1199856 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27226306250 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 27226306250 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10348541688 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 10348541688 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 149709000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 149709000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 42660894 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 42660894 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 37574847938 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 37574847938 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 37574847938 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 37574847938 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7392644 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7392644 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4969682 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4969682 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154480 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 154480 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153931 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 153931 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12362326 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12362326 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12362326 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12362326 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127457 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.127457 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051836 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051836 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088730 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088730 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.036218 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.036218 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097057 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.097057 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097057 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.097057 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28895.114705 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 28895.114705 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40171.350833 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 40171.350833 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10922.083607 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10922.083607 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7652.178296 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7652.178296 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31316.131217 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 31316.131217 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31316.131217 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 31316.131217 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1272,62 +587,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 686359 # number of writebacks -system.cpu0.dcache.writebacks::total 686359 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 942620 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 942620 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 258040 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 258040 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13696 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13696 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5452 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 5452 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1200660 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1200660 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1200660 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1200660 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25222171750 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25222171750 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9786377058 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9786377058 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 122453500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 122453500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31105611 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31105611 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 35008548808 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 35008548808 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 35008548808 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 35008548808 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465625500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465625500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2277904000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2277904000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3743529500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3743529500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127036 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127036 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051717 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051717 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088214 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088214 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035241 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035241 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096753 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.096753 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096753 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.096753 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26757.518141 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26757.518141 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37925.814052 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37925.814052 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8940.822138 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8940.822138 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5705.357850 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5705.357850 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29157.753909 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29157.753909 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29157.753909 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29157.753909 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 685854 # number of writebacks +system.cpu0.dcache.writebacks::total 685854 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 942246 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 942246 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 257610 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 257610 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13707 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13707 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5575 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5575 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1199856 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1199856 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1199856 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1199856 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25216322750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25216322750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9780175312 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9780175312 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 122281000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 122281000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31509106 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31509106 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34996498062 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 34996498062 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34996498062 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 34996498062 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1461499500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1461499500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2267126500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2267126500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3728626000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3728626000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127457 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127457 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051836 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051836 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088730 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088730 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.036218 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.036218 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097057 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097057 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097057 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097057 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26761.931332 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26761.931332 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37965.045270 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37965.045270 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8921.062231 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8921.062231 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5651.857578 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5651.857578 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29167.248455 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29167.248455 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29167.248455 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29167.248455 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1335,26 +650,112 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.tags.replacements 699671 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.391653 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 47283349 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 700182 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.530084 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 40276505250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.391653 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992952 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.992952 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 436 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 48683959 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 48683959 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 47283349 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 47283349 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 47283349 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 47283349 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 47283349 # number of overall hits +system.cpu0.icache.overall_hits::total 47283349 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 700305 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 700305 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 700305 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 700305 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 700305 # number of overall misses +system.cpu0.icache.overall_misses::total 700305 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9967517496 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 9967517496 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 9967517496 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 9967517496 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 9967517496 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 9967517496 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47983654 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47983654 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47983654 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47983654 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47983654 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47983654 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014595 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014595 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014595 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014595 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014595 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014595 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14233.109140 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14233.109140 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14233.109140 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14233.109140 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14233.109140 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14233.109140 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 700305 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 700305 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 700305 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 700305 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 700305 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 700305 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8561918504 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 8561918504 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8561918504 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 8561918504 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8561918504 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 8561918504 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014595 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014595 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014595 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12225.985112 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12225.985112 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12225.985112 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12225.985112 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12225.985112 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12225.985112 # average overall mshr miss latency +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2348280 # DTB read hits +system.cpu1.dtb.read_hits 2382379 # DTB read hits system.cpu1.dtb.read_misses 2620 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 205337 # DTB read accesses -system.cpu1.dtb.write_hits 1676993 # DTB write hits +system.cpu1.dtb.write_hits 1702197 # DTB write hits system.cpu1.dtb.write_misses 235 # DTB write misses system.cpu1.dtb.write_acv 24 # DTB write access violations system.cpu1.dtb.write_accesses 89739 # DTB write accesses -system.cpu1.dtb.data_hits 4025273 # DTB hits +system.cpu1.dtb.data_hits 4084576 # DTB hits system.cpu1.dtb.data_misses 2855 # DTB misses system.cpu1.dtb.data_acv 24 # DTB access violations system.cpu1.dtb.data_accesses 295076 # DTB accesses -system.cpu1.itb.fetch_hits 1801078 # ITB hits +system.cpu1.itb.fetch_hits 1808740 # ITB hits system.cpu1.itb.fetch_misses 1064 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1802142 # ITB accesses +system.cpu1.itb.fetch_accesses 1809804 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1367,87 +768,87 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3921880878 # number of cpu cycles simulated +system.cpu1.numCycles 3923834014 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 12764610 # Number of instructions committed -system.cpu1.committedOps 12764610 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 11762987 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 170364 # Number of float alu accesses -system.cpu1.num_func_calls 404048 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1265459 # number of instructions that are conditional controls -system.cpu1.num_int_insts 11762987 # number of integer instructions -system.cpu1.num_fp_insts 170364 # number of float instructions -system.cpu1.num_int_register_reads 16177090 # number of times the integer registers were read -system.cpu1.num_int_register_writes 8656212 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 88600 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 90534 # number of times the floating registers were written -system.cpu1.num_mem_refs 4047820 # number of memory refs -system.cpu1.num_load_insts 2361802 # Number of load instructions -system.cpu1.num_store_insts 1686018 # Number of store instructions -system.cpu1.num_idle_cycles 3873240792.459649 # Number of idle cycles -system.cpu1.num_busy_cycles 48640085.540351 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012402 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987598 # Percentage of idle cycles -system.cpu1.Branches 1821460 # Number of branches fetched -system.cpu1.op_class::No_OpClass 690637 5.41% 5.41% # Class of executed instruction -system.cpu1.op_class::IntAlu 7566798 59.27% 64.68% # Class of executed instruction -system.cpu1.op_class::IntMult 21839 0.17% 64.85% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.85% # Class of executed instruction -system.cpu1.op_class::FloatAdd 13058 0.10% 64.95% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1759 0.01% 64.96% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::MemRead 2432293 19.05% 84.01% # Class of executed instruction -system.cpu1.op_class::MemWrite 1686990 13.21% 97.23% # Class of executed instruction -system.cpu1.op_class::IprAccess 354115 2.77% 100.00% # Class of executed instruction +system.cpu1.committedInsts 12951032 # Number of instructions committed +system.cpu1.committedOps 12951032 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 11936898 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 171199 # Number of float alu accesses +system.cpu1.num_func_calls 411532 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1284277 # number of instructions that are conditional controls +system.cpu1.num_int_insts 11936898 # number of integer instructions +system.cpu1.num_fp_insts 171199 # number of float instructions +system.cpu1.num_int_register_reads 16412569 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8783541 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 88996 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 90942 # number of times the floating registers were written +system.cpu1.num_mem_refs 4107226 # number of memory refs +system.cpu1.num_load_insts 2395961 # Number of load instructions +system.cpu1.num_store_insts 1711265 # Number of store instructions +system.cpu1.num_idle_cycles 3874307298.691787 # Number of idle cycles +system.cpu1.num_busy_cycles 49526715.308213 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012622 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987378 # Percentage of idle cycles +system.cpu1.Branches 1849703 # Number of branches fetched +system.cpu1.op_class::No_OpClass 699491 5.40% 5.40% # Class of executed instruction +system.cpu1.op_class::IntAlu 7680347 59.29% 64.69% # Class of executed instruction +system.cpu1.op_class::IntMult 22457 0.17% 64.86% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.86% # Class of executed instruction +system.cpu1.op_class::FloatAdd 13113 0.10% 64.96% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1759 0.01% 64.98% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::MemRead 2467292 19.05% 84.02% # Class of executed instruction +system.cpu1.op_class::MemWrite 1712246 13.22% 97.24% # Class of executed instruction +system.cpu1.op_class::IprAccess 357206 2.76% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 12767489 # Class of executed instruction +system.cpu1.op_class::total 12953911 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2740 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 77083 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 26133 38.19% 38.19% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1969 2.88% 41.07% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 506 0.74% 41.81% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 39822 58.19% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 68430 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 25289 48.13% 48.13% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1969 3.75% 51.87% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 506 0.96% 52.84% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 24783 47.16% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 52547 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1909614154000 97.38% 97.38% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 700846000 0.04% 97.42% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 353816000 0.02% 97.44% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 50271593000 2.56% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1960940409000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.967704 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2765 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 77892 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 26462 38.26% 38.26% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1970 2.85% 41.11% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 512 0.74% 41.85% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 40213 58.15% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 69157 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 25618 48.15% 48.15% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1970 3.70% 51.85% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 512 0.96% 52.81% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 25106 47.19% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 53206 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1910435586500 97.38% 97.38% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 701157000 0.04% 97.41% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 358940000 0.02% 97.43% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 50421293500 2.57% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1961916977000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.968105 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.622344 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.767894 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.624325 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.769351 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed @@ -1463,207 +864,123 @@ system.cpu1.kern.syscall::74 9 9.78% 96.74% # nu system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 92 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 424 0.60% 0.60% # number of callpals executed +system.cpu1.kern.callpal::wripir 424 0.59% 0.59% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.60% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1955 2.77% 3.37% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 3.38% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.39% # number of callpals executed -system.cpu1.kern.callpal::swpipl 62269 88.12% 91.51% # number of callpals executed -system.cpu1.kern.callpal::rdps 2146 3.04% 94.54% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.54% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.00% 94.55% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.55% # number of callpals executed -system.cpu1.kern.callpal::rti 3685 5.21% 99.77% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1967 2.75% 3.35% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 3.35% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.36% # number of callpals executed +system.cpu1.kern.callpal::swpipl 62982 88.13% 91.49% # number of callpals executed +system.cpu1.kern.callpal::rdps 2216 3.10% 94.59% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.60% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.00% 94.60% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.60% # number of callpals executed +system.cpu1.kern.callpal::rti 3692 5.17% 99.77% # number of callpals executed system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 70663 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1918 # number of protection mode switches +system.cpu1.kern.callpal::total 71465 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1923 # number of protection mode switches system.cpu1.kern.mode_switch::user 367 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2888 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 797 +system.cpu1.kern.mode_switch::idle 2902 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 803 system.cpu1.kern.mode_good::user 367 -system.cpu1.kern.mode_good::idle 430 -system.cpu1.kern.mode_switch_good::kernel 0.415537 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::idle 436 +system.cpu1.kern.mode_switch_good::kernel 0.417577 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.148892 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.308138 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 17565031500 0.90% 0.90% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1483893000 0.08% 0.97% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1941003590000 99.03% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1956 # number of times the context was actually changed -system.cpu1.icache.tags.replacements 311453 # number of replacements -system.cpu1.icache.tags.tagsinuse 446.345950 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 12455485 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 311964 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 39.926033 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1960014862500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.345950 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.871769 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.871769 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 71 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 440 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 13079493 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 13079493 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 12455485 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 12455485 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 12455485 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 12455485 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 12455485 # number of overall hits -system.cpu1.icache.overall_hits::total 12455485 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 312004 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 312004 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 312004 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 312004 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 312004 # number of overall misses -system.cpu1.icache.overall_misses::total 312004 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4105450991 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4105450991 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4105450991 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4105450991 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4105450991 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4105450991 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 12767489 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 12767489 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 12767489 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 12767489 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 12767489 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 12767489 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024437 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024437 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024437 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024437 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024437 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024437 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13158.328070 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13158.328070 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13158.328070 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13158.328070 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13158.328070 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13158.328070 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 312004 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 312004 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 312004 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 312004 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 312004 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 312004 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3481247009 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3481247009 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3481247009 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3481247009 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3481247009 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3481247009 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024437 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024437 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024437 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024437 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024437 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024437 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11157.699930 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11157.699930 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11157.699930 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11157.699930 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11157.699930 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11157.699930 # average overall mshr miss latency -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 155174 # number of replacements -system.cpu1.dcache.tags.tagsinuse 486.308424 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 3855056 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 155503 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 24.790879 # Average number of references to valid blocks. +system.cpu1.kern.mode_switch_good::idle 0.150241 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.309322 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 17997631500 0.92% 0.92% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1494992000 0.08% 0.99% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1941547962000 99.01% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1968 # number of times the context was actually changed +system.cpu1.dcache.tags.replacements 157269 # number of replacements +system.cpu1.dcache.tags.tagsinuse 486.065602 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 3912422 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 157596 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 24.825643 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 1048852145500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.308424 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949821 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.949821 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 329 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.065602 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949347 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.949347 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 327 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 297 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.642578 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 16322131 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 16322131 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2189503 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2189503 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1567525 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1567525 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 46972 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 46972 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 49481 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 49481 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3757028 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3757028 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3757028 # number of overall hits -system.cpu1.dcache.overall_hits::total 3757028 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 113756 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 113756 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 55958 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 55958 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8862 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 8862 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5884 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 5884 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 169714 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 169714 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 169714 # number of overall misses -system.cpu1.dcache.overall_misses::total 169714 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1372027750 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1372027750 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1020320505 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1020320505 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 80442000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 80442000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 43305909 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 43305909 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 2392348255 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 2392348255 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 2392348255 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 2392348255 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2303259 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2303259 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1623483 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1623483 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 55834 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 55834 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 55365 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 55365 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 3926742 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3926742 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 3926742 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3926742 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049389 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.049389 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034468 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.034468 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.158720 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.158720 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106277 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106277 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043220 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.043220 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043220 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.043220 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12061.146225 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12061.146225 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18233.684281 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18233.684281 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9077.183480 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9077.183480 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7359.943746 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7359.943746 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14096.351833 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14096.351833 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14096.351833 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14096.351833 # average overall miss latency +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 295 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.638672 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 16561703 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 16561703 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 2221454 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2221454 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1590675 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1590675 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 47775 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 47775 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50240 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 50240 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3812129 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3812129 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3812129 # number of overall hits +system.cpu1.dcache.overall_hits::total 3812129 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 115097 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 115097 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 57126 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 57126 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8902 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 8902 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5962 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 5962 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 172223 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 172223 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 172223 # number of overall misses +system.cpu1.dcache.overall_misses::total 172223 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1389994499 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1389994499 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1079772299 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1079772299 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 80592000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 80592000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 43791416 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 43791416 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 2469766798 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 2469766798 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 2469766798 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 2469766798 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2336551 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2336551 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1647801 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1647801 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 56677 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 56677 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56202 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 56202 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 3984352 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3984352 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 3984352 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 3984352 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049259 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.049259 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034668 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.034668 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.157065 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.157065 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106082 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106082 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043225 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.043225 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043225 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.043225 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12076.722234 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12076.722234 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18901.591202 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18901.591202 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9053.246461 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9053.246461 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7345.088225 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7345.088225 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14340.516644 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14340.516644 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14340.516644 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14340.516644 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1672,62 +989,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 106457 # number of writebacks -system.cpu1.dcache.writebacks::total 106457 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 113756 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 113756 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 55958 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 55958 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8862 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8862 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5884 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 5884 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 169714 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 169714 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 169714 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 169714 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1144439250 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1144439250 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 906162495 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 906162495 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 62718000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 62718000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31536091 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31536091 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2050601745 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2050601745 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2050601745 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2050601745 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18765500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18765500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 713325000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 713325000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 732090500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 732090500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049389 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049389 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034468 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034468 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.158720 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.158720 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106277 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106277 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043220 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.043220 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043220 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.043220 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10060.473733 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10060.473733 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16193.618339 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16193.618339 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7077.183480 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7077.183480 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5359.634772 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5359.634772 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12082.690556 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12082.690556 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12082.690556 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12082.690556 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 107940 # number of writebacks +system.cpu1.dcache.writebacks::total 107940 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 115097 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 115097 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 57126 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 57126 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8902 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8902 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5962 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 5962 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 172223 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 172223 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 172223 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 172223 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1159712501 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1159712501 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 962952701 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 962952701 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 62788000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 62788000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31865584 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31865584 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2122665202 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2122665202 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2122665202 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2122665202 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 22446500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 22446500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 726758000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 726758000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 749204500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 749204500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049259 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049259 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034668 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034668 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.157065 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.157065 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106082 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106082 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043225 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.043225 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043225 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.043225 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10075.957679 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10075.957679 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16856.644978 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16856.644978 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7053.246461 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7053.246461 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5344.780946 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5344.780946 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12325.097124 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12325.097124 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12325.097124 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12325.097124 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1735,5 +1052,696 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.tags.replacements 318302 # number of replacements +system.cpu1.icache.tags.tagsinuse 446.541764 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 12635057 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 318814 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 39.631437 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1956986830500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.541764 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.872152 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.872152 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 72 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 439 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 13272765 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 13272765 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 12635057 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 12635057 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 12635057 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 12635057 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 12635057 # number of overall hits +system.cpu1.icache.overall_hits::total 12635057 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 318854 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 318854 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 318854 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 318854 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 318854 # number of overall misses +system.cpu1.icache.overall_misses::total 318854 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4204550742 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4204550742 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4204550742 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4204550742 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4204550742 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4204550742 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 12953911 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 12953911 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 12953911 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 12953911 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 12953911 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 12953911 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024614 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024614 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024614 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024614 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024614 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024614 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13186.445025 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13186.445025 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13186.445025 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13186.445025 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13186.445025 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13186.445025 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 318854 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 318854 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 318854 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 318854 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 318854 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 318854 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3566590258 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3566590258 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3566590258 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3566590258 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3566590258 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3566590258 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024614 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024614 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024614 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024614 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024614 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024614 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11185.653177 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11185.653177 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11185.653177 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11185.653177 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11185.653177 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11185.653177 # average overall mshr miss latency +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. +system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_txs 395 # Number of DMA write transactions. +system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. +system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. +system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.iobus.trans_dist::ReadReq 7373 # Transaction distribution +system.iobus.trans_dist::ReadResp 7373 # Transaction distribution +system.iobus.trans_dist::WriteReq 55631 # Transaction distribution +system.iobus.trans_dist::WriteResp 14079 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13950 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 42552 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83456 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83456 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 126008 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55800 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 82034 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661632 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661632 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2743666 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 13305000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) +system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 2453000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer29.occupancy 406206788 # Layer occupancy (ticks) +system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 28473000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer1.occupancy 42016500 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) +system.iocache.tags.replacements 41696 # number of replacements +system.iocache.tags.tagsinuse 0.577792 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 41712 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 1755504938000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.577792 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.036112 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.036112 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 375552 # Number of tag accesses +system.iocache.tags.data_accesses 375552 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses +system.iocache.ReadReq_misses::total 176 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses +system.iocache.demand_misses::tsunami.ide 176 # number of demand (read+write) misses +system.iocache.demand_misses::total 176 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 176 # number of overall misses +system.iocache.overall_misses::total 176 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21474383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21474383 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13634244905 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 13634244905 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21474383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21474383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21474383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21474383 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::tsunami.ide 176 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 176 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 176 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 176 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122013.539773 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122013.539773 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328124.877383 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 328124.877383 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 122013.539773 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 122013.539773 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 206283 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 23550 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.759363 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 41520 # number of writebacks +system.iocache.writebacks::total 41520 # number of writebacks +system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 176 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 176 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 176 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12321383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12321383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11473540905 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11473540905 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12321383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12321383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12321383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12321383 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70007.857955 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276124.877383 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276124.877383 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.tags.replacements 342754 # number of replacements +system.l2c.tags.tagsinuse 65220.433043 # Cycle average of tags in use +system.l2c.tags.total_refs 2449371 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 407927 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.004435 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 8652068750 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 55272.994922 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4808.176589 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4932.064474 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 162.933205 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 44.263854 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.843399 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.073367 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.075257 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.002486 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000675 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.995185 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65173 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 764 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 5225 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 7223 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 51853 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.994461 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 25998619 # Number of tag accesses +system.l2c.tags.data_accesses 25998619 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.inst 687419 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 668122 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 318193 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 105248 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1778982 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 793794 # number of Writeback hits +system.l2c.Writeback_hits::total 793794 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 182 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 544 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 726 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 43 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 23 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 66 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 129870 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 42509 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 172379 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 687419 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 797992 # 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mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018367 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.328016 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002045 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.039472 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.173317 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60793.986161 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52556.207467 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60230.828221 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 58242.320819 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 52950.882923 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10053.381548 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10008.588533 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10036.562896 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10035.675615 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10015.192140 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10025.309392 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56475.322591 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61281.194151 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 56699.748311 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60793.986161 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53743.165348 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60230.828221 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61134.555501 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 54084.877339 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60793.986161 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53743.165348 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60230.828221 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61134.555501 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 54084.877339 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 292732 # Transaction distribution +system.membus.trans_dist::ReadResp 292732 # Transaction distribution +system.membus.trans_dist::WriteReq 14079 # Transaction distribution +system.membus.trans_dist::WriteResp 14079 # Transaction distribution +system.membus.trans_dist::Writeback 121224 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16421 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 11471 # Transaction distribution +system.membus.trans_dist::UpgradeResp 7051 # Transaction distribution +system.membus.trans_dist::ReadExReq 124094 # Transaction distribution +system.membus.trans_dist::ReadExResp 123249 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42552 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 932442 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 974994 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124815 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124815 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1099809 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82034 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31235136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31317170 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 36634738 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 22113 # Total snoops (count) +system.membus.snoop_fanout::samples 600297 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 600297 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 600297 # Request fanout histogram +system.membus.reqLayer0.occupancy 40801500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 1914880000 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 3840416202 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer2.occupancy 43136500 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.trans_dist::ReadReq 2106484 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2106469 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 14079 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 14079 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 793794 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 16644 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11537 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 28181 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 298092 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 298092 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1400589 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3132441 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 637707 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 458977 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5629714 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44818176 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119962112 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20406592 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16779186 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 201966066 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 99450 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3260906 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.012796 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.112395 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 3219178 98.72% 98.72% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 41728 1.28% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3260906 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4802513358 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 3153866996 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 5532423832 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 1434969242 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 787756714 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR +system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU +system.tsunami.ethernet.droppedPackets 0 # number of packets dropped ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 04dd39221..166d29f48 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,110 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.919439 # Number of seconds simulated -sim_ticks 1919439025000 # Number of ticks simulated -final_tick 1919439025000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.920428 # Number of seconds simulated +sim_ticks 1920427877000 # Number of ticks simulated +final_tick 1920427877000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1406989 # Simulator instruction rate (inst/s) -host_op_rate 1406988 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48137648137 # Simulator tick rate (ticks/s) -host_mem_usage 309300 # Number of bytes of host memory used -host_seconds 39.87 # Real time elapsed on the host -sim_insts 56102180 # Number of instructions simulated -sim_ops 56102180 # Number of ops (including micro ops) simulated +host_inst_rate 694902 # Simulator instruction rate (inst/s) +host_op_rate 694902 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 23785763794 # Simulator tick rate (ticks/s) +host_mem_usage 317148 # Number of bytes of host memory used +host_seconds 80.74 # Real time elapsed on the host +sim_insts 56105324 # Number of instructions simulated +sim_ops 56105324 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 850816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24875904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 850752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24858304 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25727680 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 850816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 850816 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4747520 # Number of bytes written to this memory -system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory -system.physmem.bytes_written::total 7406848 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13294 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388686 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25710016 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 850752 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 850752 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7404096 # Number of bytes written to this memory +system.physmem.bytes_written::total 7404096 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13293 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388411 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 401995 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 74180 # Number of write requests responded to by this memory -system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115732 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 443263 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12959987 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 401719 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115689 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115689 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 443001 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12944149 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 500 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13403750 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 443263 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 443263 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2473389 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::tsunami.ide 1385471 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3858861 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2473389 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 443263 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12959987 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1385972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17262610 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 401995 # Number of read requests accepted -system.physmem.writeReqs 115732 # Number of write requests accepted -system.physmem.readBursts 401995 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 115732 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25715968 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 11712 # Total number of bytes read from write queue -system.physmem.bytesWritten 7405120 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25727680 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7406848 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 183 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 132 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25161 # Per bank write bursts +system.physmem.bw_read::total 13387650 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 443001 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 443001 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3855441 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3855441 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3855441 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 443001 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12944149 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 500 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17243091 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 401719 # Number of read requests accepted +system.physmem.writeReqs 157241 # Number of write requests accepted +system.physmem.readBursts 401719 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 157241 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25703424 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6592 # Total number of bytes read from write queue +system.physmem.bytesWritten 9932992 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25710016 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10063424 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 103 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2011 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 130 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25160 # Per bank write bursts system.physmem.perBankRdBursts::1 25539 # Per bank write bursts -system.physmem.perBankRdBursts::2 25618 # Per bank write bursts -system.physmem.perBankRdBursts::3 25536 # Per bank write bursts -system.physmem.perBankRdBursts::4 24982 # Per bank write bursts -system.physmem.perBankRdBursts::5 24977 # Per bank write bursts -system.physmem.perBankRdBursts::6 24228 # Per bank write bursts -system.physmem.perBankRdBursts::7 24506 # Per bank write bursts -system.physmem.perBankRdBursts::8 25158 # Per bank write bursts -system.physmem.perBankRdBursts::9 24823 # Per bank write bursts -system.physmem.perBankRdBursts::10 25363 # Per bank write bursts -system.physmem.perBankRdBursts::11 24839 # Per bank write bursts -system.physmem.perBankRdBursts::12 24418 # Per bank write bursts -system.physmem.perBankRdBursts::13 25388 # Per bank write bursts -system.physmem.perBankRdBursts::14 25795 # Per bank write bursts -system.physmem.perBankRdBursts::15 25481 # Per bank write bursts -system.physmem.perBankWrBursts::0 7550 # Per bank write bursts -system.physmem.perBankWrBursts::1 7529 # Per bank write bursts -system.physmem.perBankWrBursts::2 7880 # Per bank write bursts -system.physmem.perBankWrBursts::3 7553 # Per bank write bursts -system.physmem.perBankWrBursts::4 7115 # Per bank write bursts -system.physmem.perBankWrBursts::5 6983 # Per bank write bursts -system.physmem.perBankWrBursts::6 6321 # Per bank write bursts -system.physmem.perBankWrBursts::7 6315 # Per bank write bursts -system.physmem.perBankWrBursts::8 7293 # Per bank write bursts -system.physmem.perBankWrBursts::9 6555 # Per bank write bursts -system.physmem.perBankWrBursts::10 7205 # Per bank write bursts -system.physmem.perBankWrBursts::11 6861 # Per bank write bursts -system.physmem.perBankWrBursts::12 6964 # Per bank write bursts -system.physmem.perBankWrBursts::13 7821 # Per bank write bursts -system.physmem.perBankWrBursts::14 7980 # Per bank write bursts -system.physmem.perBankWrBursts::15 7780 # Per bank write bursts +system.physmem.perBankRdBursts::2 25602 # Per bank write bursts +system.physmem.perBankRdBursts::3 25522 # Per bank write bursts +system.physmem.perBankRdBursts::4 24974 # Per bank write bursts +system.physmem.perBankRdBursts::5 24970 # Per bank write bursts +system.physmem.perBankRdBursts::6 24210 # Per bank write bursts +system.physmem.perBankRdBursts::7 24489 # Per bank write bursts +system.physmem.perBankRdBursts::8 25140 # Per bank write bursts +system.physmem.perBankRdBursts::9 24800 # Per bank write bursts +system.physmem.perBankRdBursts::10 25361 # Per bank write bursts +system.physmem.perBankRdBursts::11 24836 # Per bank write bursts +system.physmem.perBankRdBursts::12 24395 # Per bank write bursts +system.physmem.perBankRdBursts::13 25368 # Per bank write bursts +system.physmem.perBankRdBursts::14 25772 # Per bank write bursts +system.physmem.perBankRdBursts::15 25478 # Per bank write bursts +system.physmem.perBankWrBursts::0 10040 # Per bank write bursts +system.physmem.perBankWrBursts::1 9905 # Per bank write bursts +system.physmem.perBankWrBursts::2 10447 # Per bank write bursts +system.physmem.perBankWrBursts::3 9982 # Per bank write bursts +system.physmem.perBankWrBursts::4 9551 # Per bank write bursts +system.physmem.perBankWrBursts::5 9392 # Per bank write bursts +system.physmem.perBankWrBursts::6 8805 # Per bank write bursts +system.physmem.perBankWrBursts::7 8555 # Per bank write bursts +system.physmem.perBankWrBursts::8 9942 # Per bank write bursts +system.physmem.perBankWrBursts::9 8777 # Per bank write bursts +system.physmem.perBankWrBursts::10 9524 # Per bank write bursts +system.physmem.perBankWrBursts::11 9288 # Per bank write bursts +system.physmem.perBankWrBursts::12 9847 # Per bank write bursts +system.physmem.perBankWrBursts::13 10608 # Per bank write bursts +system.physmem.perBankWrBursts::14 10278 # Per bank write bursts +system.physmem.perBankWrBursts::15 10262 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 12 # Number of times write queue was full causing retry -system.physmem.totGap 1919427104000 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 1920415956000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 401995 # Read request sizes (log2) +system.physmem.readPktSize::6 401719 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 115732 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 401798 # What read queue length does an incoming req see +system.physmem.writePktSize::6 157241 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 401602 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see @@ -151,327 +148,180 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6566 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8473 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6888 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5617 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 202 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 27 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63991 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 517.589786 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 312.394273 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 414.375602 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15074 23.56% 23.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11584 18.10% 41.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4587 7.17% 48.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3091 4.83% 53.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3045 4.76% 58.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1807 2.82% 61.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1323 2.07% 63.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1474 2.30% 65.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22006 34.39% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63991 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5109 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 78.644353 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2952.702952 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5106 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 9080 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9749 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 11119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11614 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6526 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5950 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5885 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 66429 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 536.458715 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 326.725513 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 417.454187 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15065 22.68% 22.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11458 17.25% 39.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4677 7.04% 46.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3146 4.74% 51.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3014 4.54% 56.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1853 2.79% 59.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1319 1.99% 61.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1472 2.22% 63.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 24425 36.77% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 66429 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5535 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 72.556098 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2836.858046 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5532 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5109 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5109 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.647289 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.199358 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.195525 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4460 87.30% 87.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 21 0.41% 87.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 12 0.23% 87.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 224 4.38% 92.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 41 0.80% 93.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 20 0.39% 93.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 7 0.14% 93.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 6 0.12% 93.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 14 0.27% 94.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 4 0.08% 94.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.06% 94.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 1 0.02% 94.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 9 0.18% 94.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.10% 94.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.08% 94.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 25 0.49% 95.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 9 0.18% 95.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 15 0.29% 95.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 168 3.29% 98.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.04% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.02% 98.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.04% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.02% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 2 0.04% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 8 0.16% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 5 0.10% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 5 0.10% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 9 0.18% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 13 0.25% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.02% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.04% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 5 0.10% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 3 0.06% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5109 # Writes before turning the bus around for reads -system.physmem.totQLat 2129492750 # Total ticks spent queuing -system.physmem.totMemAccLat 9663467750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2009060000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5299.72 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5535 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5535 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 28.040289 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 21.079799 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 34.913440 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4499 81.28% 81.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 176 3.18% 84.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 297 5.37% 89.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 50 0.90% 90.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 97 1.75% 92.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 48 0.87% 93.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 11 0.20% 93.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 7 0.13% 93.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 21 0.38% 94.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 7 0.13% 94.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 14 0.25% 94.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 6 0.11% 94.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 14 0.25% 94.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 3 0.05% 94.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 11 0.20% 95.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 48 0.87% 95.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 16 0.29% 96.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 19 0.34% 96.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 91 1.64% 98.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 36 0.65% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 6 0.11% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 14 0.25% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 14 0.25% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 5 0.09% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 9 0.16% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 3 0.05% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 5 0.09% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 1 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 3 0.05% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 2 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5535 # Writes before turning the bus around for reads +system.physmem.totQLat 2119831750 # Total ticks spent queuing +system.physmem.totMemAccLat 9650131750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2008080000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5278.26 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24049.72 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.40 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.86 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.40 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.86 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 24028.26 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.38 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 5.17 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.39 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 5.24 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.13 # Data bus utilization in percentage +system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.48 # Average write queue length when enqueuing -system.physmem.readRowHits 359991 # Number of row buffer hits during reads -system.physmem.writeRowHits 93535 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.59 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.82 # Row buffer hit rate for writes -system.physmem.avgGap 3707411.64 # Average gap between requests -system.physmem.pageHitRate 87.63 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1800186005000 # Time in different power states -system.physmem.memoryStateTime::REF 64094160000 # Time in different power states +system.physmem.avgWrQLen 24.55 # Average write queue length when enqueuing +system.physmem.readRowHits 359880 # Number of row buffer hits during reads +system.physmem.writeRowHits 130510 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.61 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 84.08 # Row buffer hit rate for writes +system.physmem.avgGap 3435694.78 # Average gap between requests +system.physmem.pageHitRate 88.07 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1801057353000 # Time in different power states +system.physmem.memoryStateTime::REF 64127180000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 55155300000 # Time in different power states +system.physmem.memoryStateTime::ACT 55239785750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 236499480 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 247272480 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 129042375 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 134920500 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1564266600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1569867000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 370954080 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 378814320 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 125368176960 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 125368176960 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 63948324510 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 64460493450 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1095566249250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1095116978250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1287183513255 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1287276522960 # Total energy per rank (pJ) -system.physmem.averagePower::0 670.605262 # Core power per rank (mW) -system.physmem.averagePower::1 670.653719 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 292357 # Transaction distribution -system.membus.trans_dist::ReadResp 292357 # Transaction distribution -system.membus.trans_dist::WriteReq 9649 # Transaction distribution -system.membus.trans_dist::WriteResp 9649 # Transaction distribution -system.membus.trans_dist::Writeback 74180 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 132 # Transaction distribution -system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 116726 # Transaction distribution -system.membus.trans_dist::ReadExResp 116726 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33158 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878404 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911562 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83292 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 83292 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 994854 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30474240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30518796 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33179084 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 158 # Total snoops (count) -system.membus.snoop_fanout::samples 518029 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 518029 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 518029 # Request fanout histogram -system.membus.reqLayer0.occupancy 30371000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1451093000 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3752017868 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 43114250 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.344808 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1753524972000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.344808 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.084051 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.084051 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375557 # Number of tag accesses -system.iocache.tags.data_accesses 375557 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits -system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses -system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::tsunami.ide 4 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 4 # number of WriteInvalidateReq misses -system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses -system.iocache.demand_misses::total 173 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 173 # number of overall misses -system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 24523133 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 24523133 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 24523133 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 24523133 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 24523133 # number of overall miss cycles -system.iocache.overall_miss_latency::total 24523133 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41556 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 41556 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 0.000096 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.000096 # miss rate for WriteInvalidateReq accesses -system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 141752.213873 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 141752.213873 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 141752.213873 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 141752.213873 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 141752.213873 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 141752.213873 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 41552 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 15526633 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 15526633 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2512178304 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2512178304 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 15526633 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 15526633 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 15526633 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 15526633 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 89749.323699 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 89749.323699 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 89749.323699 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 89749.323699 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 89749.323699 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 89749.323699 # average overall mshr miss latency -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. -system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_txs 395 # Number of DMA write transactions. -system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. -system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. -system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.physmem.actEnergy::0 245964600 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 256238640 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 134206875 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 139812750 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 1563634800 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 1568970000 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 496866960 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 508848480 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 125432764080 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 125432764080 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 64118860245 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 64485707400 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1096009968750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1095688173000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1288002266310 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1288080514350 # Total energy per rank (pJ) +system.physmem.averagePower::0 670.686297 # Core power per rank (mW) +system.physmem.averagePower::1 670.727042 # Core power per rank (mW) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9052455 # DTB read hits -system.cpu.dtb.read_misses 10357 # DTB read misses +system.cpu.dtb.read_hits 9053154 # DTB read hits +system.cpu.dtb.read_misses 10325 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728916 # DTB read accesses -system.cpu.dtb.write_hits 6349129 # DTB write hits -system.cpu.dtb.write_misses 1143 # DTB write misses +system.cpu.dtb.read_accesses 728854 # DTB read accesses +system.cpu.dtb.write_hits 6349573 # DTB write hits +system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291932 # DTB write accesses -system.cpu.dtb.data_hits 15401584 # DTB hits -system.cpu.dtb.data_misses 11500 # DTB misses +system.cpu.dtb.write_accesses 291931 # DTB write accesses +system.cpu.dtb.data_hits 15402727 # DTB hits +system.cpu.dtb.data_misses 11467 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020848 # DTB accesses -system.cpu.itb.fetch_hits 4974880 # ITB hits +system.cpu.dtb.data_accesses 1020785 # DTB accesses +system.cpu.itb.fetch_hits 4974627 # ITB hits system.cpu.itb.fetch_misses 5010 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979890 # ITB accesses +system.cpu.itb.fetch_accesses 4979637 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -484,34 +334,34 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3838878050 # number of cpu cycles simulated +system.cpu.numCycles 3840855754 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56102180 # Number of instructions committed -system.cpu.committedOps 56102180 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 51977296 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324326 # Number of float alu accesses -system.cpu.num_func_calls 1481232 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6461044 # number of instructions that are conditional controls -system.cpu.num_int_insts 51977296 # number of integer instructions -system.cpu.num_fp_insts 324326 # number of float instructions -system.cpu.num_int_register_reads 71206831 # number of times the integer registers were read -system.cpu.num_int_register_writes 38459262 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163576 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166452 # number of times the floating registers were written -system.cpu.num_mem_refs 15454224 # number of memory refs -system.cpu.num_load_insts 9089337 # Number of load instructions -system.cpu.num_store_insts 6364887 # Number of store instructions -system.cpu.num_idle_cycles 3587231475.998131 # Number of idle cycles -system.cpu.num_busy_cycles 251646574.001869 # Number of busy cycles -system.cpu.not_idle_fraction 0.065552 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.934448 # Percentage of idle cycles -system.cpu.Branches 8412776 # Number of branches fetched -system.cpu.op_class::No_OpClass 3197684 5.70% 5.70% # Class of executed instruction -system.cpu.op_class::IntAlu 36172751 64.46% 70.16% # Class of executed instruction -system.cpu.op_class::IntMult 60997 0.11% 70.27% # Class of executed instruction +system.cpu.committedInsts 56105324 # Number of instructions committed +system.cpu.committedOps 56105324 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 51980283 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324527 # Number of float alu accesses +system.cpu.num_func_calls 1481352 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6461346 # number of instructions that are conditional controls +system.cpu.num_int_insts 51980283 # number of integer instructions +system.cpu.num_fp_insts 324527 # number of float instructions +system.cpu.num_int_register_reads 71211532 # number of times the integer registers were read +system.cpu.num_int_register_writes 38461399 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163675 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166554 # number of times the floating registers were written +system.cpu.num_mem_refs 15455353 # number of memory refs +system.cpu.num_load_insts 9090013 # Number of load instructions +system.cpu.num_store_insts 6365340 # Number of store instructions +system.cpu.num_idle_cycles 3589191785.998131 # Number of idle cycles +system.cpu.num_busy_cycles 251663968.001869 # Number of busy cycles +system.cpu.not_idle_fraction 0.065523 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.934477 # Percentage of idle cycles +system.cpu.Branches 8413247 # Number of branches fetched +system.cpu.op_class::No_OpClass 3197750 5.70% 5.70% # Class of executed instruction +system.cpu.op_class::IntAlu 36174854 64.46% 70.16% # Class of executed instruction +system.cpu.op_class::IntMult 61015 0.11% 70.27% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction -system.cpu.op_class::FloatAdd 38083 0.07% 70.34% # Class of executed instruction +system.cpu.op_class::FloatAdd 38089 0.07% 70.34% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction @@ -537,34 +387,34 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 70.34% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::MemRead 9316413 16.60% 86.95% # Class of executed instruction -system.cpu.op_class::MemWrite 6370959 11.35% 98.30% # Class of executed instruction -system.cpu.op_class::IprAccess 953524 1.70% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 9317103 16.60% 86.95% # Class of executed instruction +system.cpu.op_class::MemWrite 6371414 11.35% 98.30% # Class of executed instruction +system.cpu.op_class::IprAccess 953297 1.70% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 56114047 # Class of executed instruction +system.cpu.op_class::total 56117158 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6380 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 212017 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74895 40.89% 40.89% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6382 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 212003 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74898 40.89% 40.89% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1931 1.05% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106211 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183168 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73528 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 106222 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183183 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73531 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1931 1.29% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73528 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149118 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1857251860000 96.76% 96.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 91366000 0.00% 96.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 736784000 0.04% 96.80% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 61358281000 3.20% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1919438291000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73531 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149125 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1858233349500 96.76% 96.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 91228000 0.00% 96.77% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 737074000 0.04% 96.80% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 61365491500 3.20% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1920427143000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692282 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814105 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692239 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814077 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -600,184 +450,229 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4175 2.16% 2.17% # number of callpals executed -system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed +system.cpu.kern.callpal::swpctx 4178 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175949 91.22% 93.41% # number of callpals executed -system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 175962 91.21% 93.41% # number of callpals executed +system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed +system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192892 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5903 # number of protection mode switches -system.cpu.kern.mode_switch::user 1742 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1911 -system.cpu.kern.mode_good::user 1742 -system.cpu.kern.mode_good::idle 169 -system.cpu.kern.mode_switch_good::kernel 0.323734 # fraction of useful protection mode switches +system.cpu.kern.callpal::total 192910 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5901 # number of protection mode switches +system.cpu.kern.mode_switch::user 1743 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2100 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1914 +system.cpu.kern.mode_good::user 1743 +system.cpu.kern.mode_good::idle 171 +system.cpu.kern.mode_switch_good::kernel 0.324352 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392443 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46142250000 2.40% 2.40% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5192719000 0.27% 2.67% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1868103320000 97.33% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4176 # number of times the context was actually changed -system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.trans_dist::ReadReq 7103 # Transaction distribution -system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51197 # Transaction distribution -system.iobus.trans_dist::WriteResp 51201 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 4 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5154 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33158 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116608 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 44556 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2706164 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) -system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 374412187 # Layer occupancy (ticks) -system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) -system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23509000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42016750 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 927651 # number of replacements -system.cpu.icache.tags.tagsinuse 508.304035 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 55185726 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 928162 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 59.456998 # Average number of references to valid blocks. +system.cpu.kern.mode_switch_good::idle 0.081429 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392857 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 46106755000 2.40% 2.40% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5190620000 0.27% 2.67% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1869129766000 97.33% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4179 # number of times the context was actually changed +system.cpu.dcache.tags.replacements 1390139 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.978885 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 14031130 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1390651 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.089613 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 107775250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.978885 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 63077780 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63077780 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7803062 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7803062 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5845783 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5845783 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183030 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183030 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199238 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199238 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13648845 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13648845 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13648845 # number of overall hits +system.cpu.dcache.overall_hits::total 13648845 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1069228 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1069228 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304213 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304213 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17228 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17228 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1373441 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1373441 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1373441 # number of overall misses +system.cpu.dcache.overall_misses::total 1373441 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29002641750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29002641750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10915376130 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10915376130 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228802500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 228802500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39918017880 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39918017880 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39918017880 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39918017880 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8872290 # 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number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424273000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2009178000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2009178000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3433451000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3433451000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120512 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120512 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049468 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049468 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085970 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085970 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091427 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091427 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091427 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091427 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25001.869504 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25001.869504 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33730.654123 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33730.654123 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11259.265176 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11259.265176 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26935.366419 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26935.366419 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26935.366419 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26935.366419 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2021774 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2021757 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9649 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9649 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 834448 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41564 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2022188 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2022171 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 834534 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304189 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304189 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1856624 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3648872 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5505496 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59411328 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142453644 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 201864972 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 41913 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3195062 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.013063 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.113544 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 304196 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304196 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1857238 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3649188 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5506426 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59430976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142466452 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 201897428 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 41901 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3195557 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.013057 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.113520 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3153325 98.69% 98.69% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41737 1.31% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3153832 98.69% 98.69% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 41725 1.31% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3195062 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2424224500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3195557 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2424565000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1395050000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1395517500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2186768132 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2186897880 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. +system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_txs 395 # Number of DMA write transactions. +system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. +system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. +system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.iobus.trans_dist::ReadReq 7103 # Transaction distribution +system.iobus.trans_dist::ReadResp 7103 # Transaction distribution +system.iobus.trans_dist::WriteReq 51202 # Transaction distribution +system.iobus.trans_dist::WriteResp 9650 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5156 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33160 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 116610 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 44564 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2706172 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 4767000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) +system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer29.occupancy 406189794 # Layer occupancy (ticks) +system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer1.occupancy 42010500 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) +system.iocache.tags.replacements 41685 # number of replacements +system.iocache.tags.tagsinuse 1.352352 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 1753525032000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.352352 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.084522 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.084522 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 375525 # Number of tag accesses +system.iocache.tags.data_accesses 375525 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses +system.iocache.ReadReq_misses::total 173 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses +system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses +system.iocache.demand_misses::total 173 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 173 # number of overall misses +system.iocache.overall_misses::total 173 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13634918911 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 13634918911 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328141.098166 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 328141.098166 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 206323 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 23561 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.756971 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 41512 # number of writebacks +system.iocache.writebacks::total 41512 # number of writebacks +system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11474214911 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11474214911 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276141.098166 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276141.098166 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 292355 # Transaction distribution +system.membus.trans_dist::ReadResp 292355 # Transaction distribution +system.membus.trans_dist::WriteReq 9650 # Transaction distribution +system.membus.trans_dist::WriteResp 9650 # Transaction distribution +system.membus.trans_dist::Writeback 115689 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.membus.trans_dist::UpgradeReq 132 # Transaction distribution +system.membus.trans_dist::UpgradeResp 132 # Transaction distribution +system.membus.trans_dist::ReadExReq 116723 # Transaction distribution +system.membus.trans_dist::ReadExResp 116723 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878118 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911278 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1036082 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30456384 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30500948 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 35818004 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 431 # Total snoops (count) +system.membus.snoop_fanout::samples 559521 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 559521 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 559521 # Request fanout histogram +system.membus.reqLayer0.occupancy 30373000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 1824623000 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 3751921620 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer2.occupancy 43109500 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR +system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU +system.tsunami.ethernet.droppedPackets 0 # number of packets dropped ---------- End Simulation Statistics ---------- |