diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha')
6 files changed, 1680 insertions, 1300 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index f697c291f..730b05e22 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -13,15 +15,16 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/dist/m5/system/binaries/console +console=/scratch/nilay/GEM5/system/binaries/console +eventq_index=0 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=atomic mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/dist/m5/system/binaries/ts_osfpal +pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -39,6 +42,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=8796093022208:18446744073709551615 req_size=16 resp_size=16 @@ -48,6 +52,7 @@ slave=system.membus.master[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -60,6 +65,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -93,6 +99,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -115,11 +122,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu0.icache] @@ -128,6 +137,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -150,21 +160,26 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu0.isa] type=AlphaISA +eventq_index=0 [system.cpu0.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu0.tracer] type=ExeTracer +eventq_index=0 [system.cpu1] type=AtomicSimpleCPU @@ -176,6 +191,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -209,6 +225,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -231,11 +248,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu1.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu1.icache] @@ -244,6 +263,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -266,25 +286,31 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu1.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu1.isa] type=AlphaISA +eventq_index=0 [system.cpu1.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu1.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.disk0] @@ -292,19 +318,22 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.disk0.image [system.disk0.image] type=CowDiskImage children=child child=system.disk0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -312,28 +341,33 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.disk2.image [system.disk2.image] type=CowDiskImage children=child child=system.disk2.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=true width=8 @@ -347,6 +381,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -369,6 +404,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -378,6 +414,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -400,6 +437,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 @@ -407,6 +445,7 @@ size=4194304 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -418,6 +457,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -433,51 +473,34 @@ warn_access= pio=system.membus.default [system.physmem] -type=SimpleDRAM -activation_limit=4 -addr_mapping=RaBaChCo -banks_per_rank=8 -burst_length=8 -channels=1 +type=SimpleMemory +bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true -device_bus_width=8 -device_rowbuffer_size=1024 -devices_per_rank=8 +eventq_index=0 in_addr_map=true -mem_sched_policy=frfcfs +latency=30000 +latency_var=0 null=false -page_policy=open range=0:134217727 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCL=13750 -tRCD=13750 -tREFI=7800000 -tRFC=300000 -tRP=13750 -tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_thresh_perc=70 port=system.membus.master[1] [system.simple_disk] type=SimpleDisk children=disk disk=system.simple_disk.disk +eventq_index=0 system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -486,6 +509,7 @@ port=3456 [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -496,6 +520,7 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache [system.tsunami] type=Tsunami children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +eventq_index=0 intrctrl=system.intrctrl system=system @@ -504,6 +529,7 @@ type=AlphaBackdoor clk_domain=system.clk_domain cpu=system.cpu0 disk=system.simple_disk +eventq_index=0 pio_addr=8804682956800 pio_latency=100000 platform=system.tsunami @@ -514,6 +540,7 @@ pio=system.iobus.master[24] [system.tsunami.cchip] type=TsunamiCChip clk_domain=system.clk_domain +eventq_index=0 pio_addr=8803072344064 pio_latency=100000 system=system @@ -542,6 +569,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=2 Command=0 @@ -551,8 +579,40 @@ HeaderType=0 InterruptLine=30 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=52 MinimumGrant=176 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=0 Revision=0 Status=656 @@ -569,6 +629,7 @@ dma_read_delay=0 dma_read_factor=0 dma_write_delay=0 dma_write_factor=0 +eventq_index=0 hardware_address=00:90:00:00:00:01 intr_delay=10000000 pci_bus=0 @@ -592,6 +653,7 @@ pio=system.iobus.master[27] [system.tsunami.fake_OROM] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8796093677568 pio_latency=100000 @@ -609,6 +671,7 @@ pio=system.iobus.master[8] [system.tsunami.fake_ata0] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848432 pio_latency=100000 @@ -626,6 +689,7 @@ pio=system.iobus.master[19] [system.tsunami.fake_ata1] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848304 pio_latency=100000 @@ -643,6 +707,7 @@ pio=system.iobus.master[20] [system.tsunami.fake_pnp_addr] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848569 pio_latency=100000 @@ -660,6 +725,7 @@ pio=system.iobus.master[9] [system.tsunami.fake_pnp_read0] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848451 pio_latency=100000 @@ -677,6 +743,7 @@ pio=system.iobus.master[11] [system.tsunami.fake_pnp_read1] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848515 pio_latency=100000 @@ -694,6 +761,7 @@ pio=system.iobus.master[12] [system.tsunami.fake_pnp_read2] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848579 pio_latency=100000 @@ -711,6 +779,7 @@ pio=system.iobus.master[13] [system.tsunami.fake_pnp_read3] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848643 pio_latency=100000 @@ -728,6 +797,7 @@ pio=system.iobus.master[14] [system.tsunami.fake_pnp_read4] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848707 pio_latency=100000 @@ -745,6 +815,7 @@ pio=system.iobus.master[15] [system.tsunami.fake_pnp_read5] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848771 pio_latency=100000 @@ -762,6 +833,7 @@ pio=system.iobus.master[16] [system.tsunami.fake_pnp_read6] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848835 pio_latency=100000 @@ -779,6 +851,7 @@ pio=system.iobus.master[17] [system.tsunami.fake_pnp_read7] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848899 pio_latency=100000 @@ -796,6 +869,7 @@ pio=system.iobus.master[18] [system.tsunami.fake_pnp_write] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615850617 pio_latency=100000 @@ -813,6 +887,7 @@ pio=system.iobus.master[10] [system.tsunami.fake_ppc] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848891 pio_latency=100000 @@ -830,6 +905,7 @@ pio=system.iobus.master[7] [system.tsunami.fake_sm_chip] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848816 pio_latency=100000 @@ -847,6 +923,7 @@ pio=system.iobus.master[2] [system.tsunami.fake_uart1] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848696 pio_latency=100000 @@ -864,6 +941,7 @@ pio=system.iobus.master[3] [system.tsunami.fake_uart2] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848936 pio_latency=100000 @@ -881,6 +959,7 @@ pio=system.iobus.master[4] [system.tsunami.fake_uart3] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848680 pio_latency=100000 @@ -898,6 +977,7 @@ pio=system.iobus.master[5] [system.tsunami.fake_uart4] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848944 pio_latency=100000 @@ -916,6 +996,7 @@ pio=system.iobus.master[6] type=BadDevice clk_domain=system.clk_domain devicename=FrameBuffer +eventq_index=0 pio_addr=8804615848912 pio_latency=100000 system=system @@ -943,6 +1024,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=0 @@ -952,8 +1034,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -965,6 +1079,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 disks=system.disk0 system.disk2 +eventq_index=0 io_shift=0 pci_bus=0 pci_dev=0 @@ -979,6 +1094,7 @@ pio=system.iobus.master[25] [system.tsunami.io] type=TsunamiIO clk_domain=system.clk_domain +eventq_index=0 frequency=976562500 pio_addr=8804615847936 pio_latency=100000 @@ -991,6 +1107,7 @@ pio=system.iobus.master[22] [system.tsunami.pchip] type=TsunamiPChip clk_domain=system.clk_domain +eventq_index=0 pio_addr=8802535473152 pio_latency=100000 system=system @@ -1001,6 +1118,7 @@ pio=system.iobus.master[1] type=PciConfigAll bus=0 clk_domain=system.clk_domain +eventq_index=0 pio_addr=0 pio_latency=30000 platform=system.tsunami @@ -1011,6 +1129,7 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 clk_domain=system.clk_domain +eventq_index=0 pio_addr=8804615848952 pio_latency=100000 platform=system.tsunami @@ -1020,5 +1139,6 @@ pio=system.iobus.master[23] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 447e2a06f..e7342cf46 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.870336 # Nu sim_ticks 1870335522500 # Number of ticks simulated final_tick 1870335522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2234616 # Simulator instruction rate (inst/s) -host_op_rate 2234615 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 66179117761 # Simulator tick rate (ticks/s) -host_mem_usage 308940 # Number of bytes of host memory used -host_seconds 28.26 # Real time elapsed on the host +host_inst_rate 1806360 # Simulator instruction rate (inst/s) +host_op_rate 1806359 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53496127424 # Simulator tick rate (ticks/s) +host_mem_usage 353980 # Number of bytes of host memory used +host_seconds 34.96 # Real time elapsed on the host sim_insts 63154034 # Number of instructions simulated sim_ops 63154034 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 761216 # Number of bytes read from this memory @@ -267,7 +267,7 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3740670933 # number of cpu cycles simulated +system.cpu0.numCycles 3740671046 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.committedInsts 57222076 # Number of instructions committed @@ -285,8 +285,8 @@ system.cpu0.num_fp_register_writes 150835 # nu system.cpu0.num_mem_refs 15135515 # number of memory refs system.cpu0.num_load_insts 9184477 # Number of load instructions system.cpu0.num_store_insts 5951038 # Number of store instructions -system.cpu0.num_idle_cycles 3683437089.313678 # Number of idle cycles -system.cpu0.num_busy_cycles 57233843.686322 # Number of busy cycles +system.cpu0.num_idle_cycles 3683437200.584730 # Number of idle cycles +system.cpu0.num_busy_cycles 57233845.415270 # Number of busy cycles system.cpu0.not_idle_fraction 0.015300 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.984700 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index ac72e998f..7f56b644f 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -13,15 +15,16 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/dist/m5/system/binaries/console +console=/scratch/nilay/GEM5/system/binaries/console +eventq_index=0 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=atomic mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/dist/m5/system/binaries/ts_osfpal +pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -39,6 +42,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=8796093022208:18446744073709551615 req_size=16 resp_size=16 @@ -48,6 +52,7 @@ slave=system.membus.master[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -60,6 +65,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -93,6 +99,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -115,11 +122,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.icache] @@ -128,6 +137,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -150,17 +160,21 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -169,6 +183,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -191,12 +206,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -206,10 +223,12 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.disk0] @@ -217,19 +236,22 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.disk0.image [system.disk0.image] type=CowDiskImage children=child child=system.disk0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -237,28 +259,33 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.disk2.image [system.disk2.image] type=CowDiskImage children=child child=system.disk2.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=true width=8 @@ -272,6 +299,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -294,6 +322,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -301,6 +330,7 @@ size=1024 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -312,6 +342,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -327,51 +358,34 @@ warn_access= pio=system.membus.default [system.physmem] -type=SimpleDRAM -activation_limit=4 -addr_mapping=RaBaChCo -banks_per_rank=8 -burst_length=8 -channels=1 +type=SimpleMemory +bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true -device_bus_width=8 -device_rowbuffer_size=1024 -devices_per_rank=8 +eventq_index=0 in_addr_map=true -mem_sched_policy=frfcfs +latency=30000 +latency_var=0 null=false -page_policy=open range=0:134217727 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCL=13750 -tRCD=13750 -tREFI=7800000 -tRFC=300000 -tRP=13750 -tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_thresh_perc=70 port=system.membus.master[1] [system.simple_disk] type=SimpleDisk children=disk disk=system.simple_disk.disk +eventq_index=0 system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -380,6 +394,7 @@ port=3456 [system.tsunami] type=Tsunami children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +eventq_index=0 intrctrl=system.intrctrl system=system @@ -388,6 +403,7 @@ type=AlphaBackdoor clk_domain=system.clk_domain cpu=system.cpu disk=system.simple_disk +eventq_index=0 pio_addr=8804682956800 pio_latency=100000 platform=system.tsunami @@ -398,6 +414,7 @@ pio=system.iobus.master[24] [system.tsunami.cchip] type=TsunamiCChip clk_domain=system.clk_domain +eventq_index=0 pio_addr=8803072344064 pio_latency=100000 system=system @@ -426,6 +443,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=2 Command=0 @@ -435,8 +453,40 @@ HeaderType=0 InterruptLine=30 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=52 MinimumGrant=176 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=0 Revision=0 Status=656 @@ -453,6 +503,7 @@ dma_read_delay=0 dma_read_factor=0 dma_write_delay=0 dma_write_factor=0 +eventq_index=0 hardware_address=00:90:00:00:00:01 intr_delay=10000000 pci_bus=0 @@ -476,6 +527,7 @@ pio=system.iobus.master[27] [system.tsunami.fake_OROM] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8796093677568 pio_latency=100000 @@ -493,6 +545,7 @@ pio=system.iobus.master[8] [system.tsunami.fake_ata0] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848432 pio_latency=100000 @@ -510,6 +563,7 @@ pio=system.iobus.master[19] [system.tsunami.fake_ata1] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848304 pio_latency=100000 @@ -527,6 +581,7 @@ pio=system.iobus.master[20] [system.tsunami.fake_pnp_addr] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848569 pio_latency=100000 @@ -544,6 +599,7 @@ pio=system.iobus.master[9] [system.tsunami.fake_pnp_read0] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848451 pio_latency=100000 @@ -561,6 +617,7 @@ pio=system.iobus.master[11] [system.tsunami.fake_pnp_read1] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848515 pio_latency=100000 @@ -578,6 +635,7 @@ pio=system.iobus.master[12] [system.tsunami.fake_pnp_read2] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848579 pio_latency=100000 @@ -595,6 +653,7 @@ pio=system.iobus.master[13] [system.tsunami.fake_pnp_read3] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848643 pio_latency=100000 @@ -612,6 +671,7 @@ pio=system.iobus.master[14] [system.tsunami.fake_pnp_read4] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848707 pio_latency=100000 @@ -629,6 +689,7 @@ pio=system.iobus.master[15] [system.tsunami.fake_pnp_read5] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848771 pio_latency=100000 @@ -646,6 +707,7 @@ pio=system.iobus.master[16] [system.tsunami.fake_pnp_read6] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848835 pio_latency=100000 @@ -663,6 +725,7 @@ pio=system.iobus.master[17] [system.tsunami.fake_pnp_read7] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848899 pio_latency=100000 @@ -680,6 +743,7 @@ pio=system.iobus.master[18] [system.tsunami.fake_pnp_write] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615850617 pio_latency=100000 @@ -697,6 +761,7 @@ pio=system.iobus.master[10] [system.tsunami.fake_ppc] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848891 pio_latency=100000 @@ -714,6 +779,7 @@ pio=system.iobus.master[7] [system.tsunami.fake_sm_chip] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848816 pio_latency=100000 @@ -731,6 +797,7 @@ pio=system.iobus.master[2] [system.tsunami.fake_uart1] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848696 pio_latency=100000 @@ -748,6 +815,7 @@ pio=system.iobus.master[3] [system.tsunami.fake_uart2] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848936 pio_latency=100000 @@ -765,6 +833,7 @@ pio=system.iobus.master[4] [system.tsunami.fake_uart3] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848680 pio_latency=100000 @@ -782,6 +851,7 @@ pio=system.iobus.master[5] [system.tsunami.fake_uart4] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848944 pio_latency=100000 @@ -800,6 +870,7 @@ pio=system.iobus.master[6] type=BadDevice clk_domain=system.clk_domain devicename=FrameBuffer +eventq_index=0 pio_addr=8804615848912 pio_latency=100000 system=system @@ -827,6 +898,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=0 @@ -836,8 +908,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -849,6 +953,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 disks=system.disk0 system.disk2 +eventq_index=0 io_shift=0 pci_bus=0 pci_dev=0 @@ -863,6 +968,7 @@ pio=system.iobus.master[25] [system.tsunami.io] type=TsunamiIO clk_domain=system.clk_domain +eventq_index=0 frequency=976562500 pio_addr=8804615847936 pio_latency=100000 @@ -875,6 +981,7 @@ pio=system.iobus.master[22] [system.tsunami.pchip] type=TsunamiPChip clk_domain=system.clk_domain +eventq_index=0 pio_addr=8802535473152 pio_latency=100000 system=system @@ -885,6 +992,7 @@ pio=system.iobus.master[1] type=PciConfigAll bus=0 clk_domain=system.clk_domain +eventq_index=0 pio_addr=0 pio_latency=30000 platform=system.tsunami @@ -895,6 +1003,7 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 clk_domain=system.clk_domain +eventq_index=0 pio_addr=8804615848952 pio_latency=100000 platform=system.tsunami @@ -904,5 +1013,6 @@ pio=system.iobus.master[23] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 066f6fce7..01a06923f 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.829332 # Nu sim_ticks 1829332258000 # Number of ticks simulated final_tick 1829332258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1630624 # Simulator instruction rate (inst/s) -host_op_rate 1630623 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49684114233 # Simulator tick rate (ticks/s) -host_mem_usage 305868 # Number of bytes of host memory used -host_seconds 36.82 # Real time elapsed on the host +host_inst_rate 1538182 # Simulator instruction rate (inst/s) +host_op_rate 1538181 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46867449524 # Simulator tick rate (ticks/s) +host_mem_usage 350908 # Number of bytes of host memory used +host_seconds 39.03 # Real time elapsed on the host sim_insts 60038305 # Number of instructions simulated sim_ops 60038305 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory @@ -129,7 +129,7 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3658664408 # number of cpu cycles simulated +system.cpu.numCycles 3658664517 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 60038305 # Number of instructions committed @@ -147,8 +147,8 @@ system.cpu.num_fp_register_writes 166520 # nu system.cpu.num_mem_refs 16115709 # number of memory refs system.cpu.num_load_insts 9747513 # Number of load instructions system.cpu.num_store_insts 6368196 # Number of store instructions -system.cpu.num_idle_cycles 3598608979.180807 # Number of idle cycles -system.cpu.num_busy_cycles 60055428.819193 # Number of busy cycles +system.cpu.num_idle_cycles 3598609086.391618 # Number of idle cycles +system.cpu.num_busy_cycles 60055430.608382 # Number of busy cycles system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles system.cpu.idle_fraction 0.983585 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 4764f4e77..c1c2c449d 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -13,15 +15,16 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/dist/m5/system/binaries/console +console=/scratch/nilay/GEM5/system/binaries/console +eventq_index=0 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/dist/m5/system/binaries/ts_osfpal +pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -39,6 +42,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=8796093022208:18446744073709551615 req_size=16 resp_size=16 @@ -48,6 +52,7 @@ slave=system.membus.master[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -60,6 +65,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu0.interrupts @@ -86,6 +92,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -108,11 +115,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu0.icache] @@ -121,6 +130,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -143,21 +153,26 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu0.isa] type=AlphaISA +eventq_index=0 [system.cpu0.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu0.tracer] type=ExeTracer +eventq_index=0 [system.cpu1] type=TimingSimpleCPU @@ -169,6 +184,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu1.interrupts @@ -195,6 +211,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -217,11 +234,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu1.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu1.icache] @@ -230,6 +249,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -252,25 +272,31 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu1.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu1.isa] type=AlphaISA +eventq_index=0 [system.cpu1.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu1.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.disk0] @@ -278,19 +304,22 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.disk0.image [system.disk0.image] type=CowDiskImage children=child child=system.disk0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -298,28 +327,33 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.disk2.image [system.disk2.image] type=CowDiskImage children=child child=system.disk2.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=true width=8 @@ -333,6 +367,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -355,6 +390,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -364,6 +400,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -386,6 +423,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 @@ -393,6 +431,7 @@ size=4194304 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -404,6 +443,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -430,6 +470,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -441,29 +482,35 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[1] [system.simple_disk] type=SimpleDisk children=disk disk=system.simple_disk.disk +eventq_index=0 system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -472,6 +519,7 @@ port=3456 [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -482,6 +530,7 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache [system.tsunami] type=Tsunami children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +eventq_index=0 intrctrl=system.intrctrl system=system @@ -490,6 +539,7 @@ type=AlphaBackdoor clk_domain=system.clk_domain cpu=system.cpu0 disk=system.simple_disk +eventq_index=0 pio_addr=8804682956800 pio_latency=100000 platform=system.tsunami @@ -500,6 +550,7 @@ pio=system.iobus.master[24] [system.tsunami.cchip] type=TsunamiCChip clk_domain=system.clk_domain +eventq_index=0 pio_addr=8803072344064 pio_latency=100000 system=system @@ -528,6 +579,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=2 Command=0 @@ -537,8 +589,40 @@ HeaderType=0 InterruptLine=30 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=52 MinimumGrant=176 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=0 Revision=0 Status=656 @@ -555,6 +639,7 @@ dma_read_delay=0 dma_read_factor=0 dma_write_delay=0 dma_write_factor=0 +eventq_index=0 hardware_address=00:90:00:00:00:01 intr_delay=10000000 pci_bus=0 @@ -578,6 +663,7 @@ pio=system.iobus.master[27] [system.tsunami.fake_OROM] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8796093677568 pio_latency=100000 @@ -595,6 +681,7 @@ pio=system.iobus.master[8] [system.tsunami.fake_ata0] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848432 pio_latency=100000 @@ -612,6 +699,7 @@ pio=system.iobus.master[19] [system.tsunami.fake_ata1] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848304 pio_latency=100000 @@ -629,6 +717,7 @@ pio=system.iobus.master[20] [system.tsunami.fake_pnp_addr] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848569 pio_latency=100000 @@ -646,6 +735,7 @@ pio=system.iobus.master[9] [system.tsunami.fake_pnp_read0] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848451 pio_latency=100000 @@ -663,6 +753,7 @@ pio=system.iobus.master[11] [system.tsunami.fake_pnp_read1] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848515 pio_latency=100000 @@ -680,6 +771,7 @@ pio=system.iobus.master[12] [system.tsunami.fake_pnp_read2] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848579 pio_latency=100000 @@ -697,6 +789,7 @@ pio=system.iobus.master[13] [system.tsunami.fake_pnp_read3] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848643 pio_latency=100000 @@ -714,6 +807,7 @@ pio=system.iobus.master[14] [system.tsunami.fake_pnp_read4] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848707 pio_latency=100000 @@ -731,6 +825,7 @@ pio=system.iobus.master[15] [system.tsunami.fake_pnp_read5] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848771 pio_latency=100000 @@ -748,6 +843,7 @@ pio=system.iobus.master[16] [system.tsunami.fake_pnp_read6] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848835 pio_latency=100000 @@ -765,6 +861,7 @@ pio=system.iobus.master[17] [system.tsunami.fake_pnp_read7] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848899 pio_latency=100000 @@ -782,6 +879,7 @@ pio=system.iobus.master[18] [system.tsunami.fake_pnp_write] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615850617 pio_latency=100000 @@ -799,6 +897,7 @@ pio=system.iobus.master[10] [system.tsunami.fake_ppc] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848891 pio_latency=100000 @@ -816,6 +915,7 @@ pio=system.iobus.master[7] [system.tsunami.fake_sm_chip] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848816 pio_latency=100000 @@ -833,6 +933,7 @@ pio=system.iobus.master[2] [system.tsunami.fake_uart1] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848696 pio_latency=100000 @@ -850,6 +951,7 @@ pio=system.iobus.master[3] [system.tsunami.fake_uart2] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848936 pio_latency=100000 @@ -867,6 +969,7 @@ pio=system.iobus.master[4] [system.tsunami.fake_uart3] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848680 pio_latency=100000 @@ -884,6 +987,7 @@ pio=system.iobus.master[5] [system.tsunami.fake_uart4] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848944 pio_latency=100000 @@ -902,6 +1006,7 @@ pio=system.iobus.master[6] type=BadDevice clk_domain=system.clk_domain devicename=FrameBuffer +eventq_index=0 pio_addr=8804615848912 pio_latency=100000 system=system @@ -929,6 +1034,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=0 @@ -938,8 +1044,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -951,6 +1089,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 disks=system.disk0 system.disk2 +eventq_index=0 io_shift=0 pci_bus=0 pci_dev=0 @@ -965,6 +1104,7 @@ pio=system.iobus.master[25] [system.tsunami.io] type=TsunamiIO clk_domain=system.clk_domain +eventq_index=0 frequency=976562500 pio_addr=8804615847936 pio_latency=100000 @@ -977,6 +1117,7 @@ pio=system.iobus.master[22] [system.tsunami.pchip] type=TsunamiPChip clk_domain=system.clk_domain +eventq_index=0 pio_addr=8802535473152 pio_latency=100000 system=system @@ -987,6 +1128,7 @@ pio=system.iobus.master[1] type=PciConfigAll bus=0 clk_domain=system.clk_domain +eventq_index=0 pio_addr=0 pio_latency=30000 platform=system.tsunami @@ -997,6 +1139,7 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 clk_domain=system.clk_domain +eventq_index=0 pio_addr=8804615848952 pio_latency=100000 platform=system.tsunami @@ -1006,5 +1149,6 @@ pio=system.iobus.master[23] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 676e01409..8b5007cf5 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,135 +1,135 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.961837 # Number of seconds simulated -sim_ticks 1961837389000 # Number of ticks simulated -final_tick 1961837389000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.960910 # Number of seconds simulated +sim_ticks 1960909874500 # Number of ticks simulated +final_tick 1960909874500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1325125 # Simulator instruction rate (inst/s) -host_op_rate 1325124 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42668778131 # Simulator tick rate (ticks/s) -host_mem_usage 308960 # Number of bytes of host memory used -host_seconds 45.98 # Real time elapsed on the host -sim_insts 60926932 # Number of instructions simulated -sim_ops 60926932 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 833280 # Number of bytes read from this memory +host_inst_rate 787846 # Simulator instruction rate (inst/s) +host_op_rate 787845 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25353578812 # Simulator tick rate (ticks/s) +host_mem_usage 353976 # Number of bytes of host memory used +host_seconds 77.34 # Real time elapsed on the host +sim_insts 60933947 # Number of instructions simulated +sim_ops 60933947 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 833472 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 24887104 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650688 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 31680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 338432 # Number of bytes read from this memory -system.physmem.bytes_read::total 28741376 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 833280 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.data 338304 # Number of bytes read from this memory +system.physmem.bytes_read::total 28741248 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 833472 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 31680 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 864960 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7742464 # Number of bytes written to this memory -system.physmem.bytes_written::total 7742464 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13020 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::total 865152 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7743680 # Number of bytes written to this memory +system.physmem.bytes_written::total 7743680 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13023 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 388861 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41417 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 495 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 5288 # Number of read requests responded to by this memory -system.physmem.num_reads::total 449084 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120976 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120976 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 424745 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12685610 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1351223 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 16148 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 172508 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14650234 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 424745 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 16148 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 440893 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3946537 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3946537 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3946537 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 424745 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12685610 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1351223 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 16148 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 172508 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18596771 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 449084 # Number of read requests accepted -system.physmem.writeReqs 120976 # Number of write requests accepted -system.physmem.readBursts 449084 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 120976 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28737920 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 3456 # Total number of bytes read from write queue -system.physmem.bytesWritten 7741568 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28741376 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7742464 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 54 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::cpu1.data 5286 # Number of read requests responded to by this memory +system.physmem.num_reads::total 449082 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120995 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120995 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 425044 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12691610 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1351764 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 16156 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 172524 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14657098 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 425044 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 16156 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 441199 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3949024 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3949024 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3949024 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 425044 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12691610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1351764 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 16156 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 172524 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18606122 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 449082 # Number of read requests accepted +system.physmem.writeReqs 120995 # Number of write requests accepted +system.physmem.readBursts 449082 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 120995 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28737664 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3584 # Total number of bytes read from write queue +system.physmem.bytesWritten 7742592 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28741248 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7743680 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 56 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 7077 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 7094 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 28167 # Per bank write bursts -system.physmem.perBankRdBursts::1 28458 # Per bank write bursts -system.physmem.perBankRdBursts::2 28055 # Per bank write bursts -system.physmem.perBankRdBursts::3 27665 # Per bank write bursts +system.physmem.perBankRdBursts::1 28459 # Per bank write bursts +system.physmem.perBankRdBursts::2 28057 # Per bank write bursts +system.physmem.perBankRdBursts::3 27664 # Per bank write bursts system.physmem.perBankRdBursts::4 27762 # Per bank write bursts -system.physmem.perBankRdBursts::5 27792 # Per bank write bursts -system.physmem.perBankRdBursts::6 28261 # Per bank write bursts -system.physmem.perBankRdBursts::7 27879 # Per bank write bursts -system.physmem.perBankRdBursts::8 28077 # Per bank write bursts -system.physmem.perBankRdBursts::9 27735 # Per bank write bursts -system.physmem.perBankRdBursts::10 27671 # Per bank write bursts +system.physmem.perBankRdBursts::5 27793 # Per bank write bursts +system.physmem.perBankRdBursts::6 28259 # Per bank write bursts +system.physmem.perBankRdBursts::7 27872 # Per bank write bursts +system.physmem.perBankRdBursts::8 28083 # Per bank write bursts +system.physmem.perBankRdBursts::9 27730 # Per bank write bursts +system.physmem.perBankRdBursts::10 27672 # Per bank write bursts system.physmem.perBankRdBursts::11 28135 # Per bank write bursts -system.physmem.perBankRdBursts::12 28173 # Per bank write bursts +system.physmem.perBankRdBursts::12 28179 # Per bank write bursts system.physmem.perBankRdBursts::13 28505 # Per bank write bursts -system.physmem.perBankRdBursts::14 28655 # Per bank write bursts -system.physmem.perBankRdBursts::15 28040 # Per bank write bursts -system.physmem.perBankWrBursts::0 7931 # Per bank write bursts -system.physmem.perBankWrBursts::1 7869 # Per bank write bursts -system.physmem.perBankWrBursts::2 7539 # Per bank write bursts +system.physmem.perBankRdBursts::14 28654 # Per bank write bursts +system.physmem.perBankRdBursts::15 28035 # Per bank write bursts +system.physmem.perBankWrBursts::0 7928 # Per bank write bursts +system.physmem.perBankWrBursts::1 7868 # Per bank write bursts +system.physmem.perBankWrBursts::2 7543 # Per bank write bursts system.physmem.perBankWrBursts::3 7157 # Per bank write bursts system.physmem.perBankWrBursts::4 7275 # Per bank write bursts -system.physmem.perBankWrBursts::5 7313 # Per bank write bursts -system.physmem.perBankWrBursts::6 7748 # Per bank write bursts -system.physmem.perBankWrBursts::7 7258 # Per bank write bursts -system.physmem.perBankWrBursts::8 7316 # Per bank write bursts -system.physmem.perBankWrBursts::9 7114 # Per bank write bursts -system.physmem.perBankWrBursts::10 7078 # Per bank write bursts +system.physmem.perBankWrBursts::5 7314 # Per bank write bursts +system.physmem.perBankWrBursts::6 7747 # Per bank write bursts +system.physmem.perBankWrBursts::7 7251 # Per bank write bursts +system.physmem.perBankWrBursts::8 7322 # Per bank write bursts +system.physmem.perBankWrBursts::9 7110 # Per bank write bursts +system.physmem.perBankWrBursts::10 7099 # Per bank write bursts system.physmem.perBankWrBursts::11 7523 # Per bank write bursts -system.physmem.perBankWrBursts::12 7676 # Per bank write bursts +system.physmem.perBankWrBursts::12 7681 # Per bank write bursts system.physmem.perBankWrBursts::13 8141 # Per bank write bursts -system.physmem.perBankWrBursts::14 8336 # Per bank write bursts -system.physmem.perBankWrBursts::15 7688 # Per bank write bursts +system.physmem.perBankWrBursts::14 8335 # Per bank write bursts +system.physmem.perBankWrBursts::15 7684 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 12 # Number of times write queue was full causing retry -system.physmem.totGap 1961830378000 # Total gap between requests +system.physmem.numWrRetry 11 # Number of times write queue was full causing retry +system.physmem.totGap 1960902862500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 449084 # Read request sizes (log2) +system.physmem.readPktSize::6 449082 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 120976 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 409885 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 10531 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5358 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2695 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2315 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2316 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1356 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1333 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1333 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1442 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1324 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 977 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 963 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 963 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 961 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 960 # What read queue length does an incoming req see +system.physmem.writePktSize::6 120995 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 409890 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 10611 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5423 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2684 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2293 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2304 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1329 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1317 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1416 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1243 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1099 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 987 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 972 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 967 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 966 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 958 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 963 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 961 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 962 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -141,444 +141,446 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4919 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5791 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 6087 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 6069 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4927 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4882 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5778 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5200 # What write queue length does an incoming req see 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length does an incoming req see +system.physmem.wrQLenPdf::23 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 28 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 24 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 49252 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 740.628604 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 223.502021 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1737.958624 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 17638 35.81% 35.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 7255 14.73% 50.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 4934 10.02% 60.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2938 5.97% 66.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1843 3.74% 70.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1471 2.99% 73.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1137 2.31% 75.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 871 1.77% 77.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 749 1.52% 78.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 678 1.38% 80.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 696 1.41% 81.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 441 0.90% 82.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 346 0.70% 83.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 295 0.60% 83.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 325 0.66% 84.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 366 0.74% 85.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 215 0.44% 85.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 196 0.40% 86.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 200 0.41% 86.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 126 0.26% 86.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 182 0.37% 87.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 862 1.75% 88.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 228 0.46% 89.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 113 0.23% 89.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 126 0.26% 89.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 100 0.20% 90.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 86 0.17% 90.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 47 0.10% 90.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 73 0.15% 90.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 75 0.15% 90.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 79 0.16% 90.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 32 0.06% 90.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 84 0.17% 90.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 62 0.13% 91.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 61 0.12% 91.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 26 0.05% 91.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 60 0.12% 91.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 59 0.12% 91.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 68 0.14% 91.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 29 0.06% 91.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 67 0.14% 91.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 63 0.13% 91.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 57 0.12% 92.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 25 0.05% 92.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 61 0.12% 92.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 59 0.12% 92.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 69 0.14% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 25 0.05% 92.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 65 0.13% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 58 0.12% 92.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 65 0.13% 92.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 25 0.05% 93.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 59 0.12% 93.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 53 0.11% 93.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 71 0.14% 93.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 22 0.04% 93.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 70 0.14% 93.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 53 0.11% 93.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 60 0.12% 93.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 27 0.05% 93.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 61 0.12% 93.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 53 0.11% 94.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 63 0.13% 94.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 34 0.07% 94.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 63 0.13% 94.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 57 0.12% 94.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 62 0.13% 94.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 28 0.06% 94.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 58 0.12% 94.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 54 0.11% 94.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 66 0.13% 95.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 361 0.73% 95.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 57 0.12% 95.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 23 0.05% 95.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 53 0.11% 96.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 23 0.05% 96.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 58 0.12% 96.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 23 0.05% 96.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 51 0.10% 96.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 22 0.04% 96.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 54 0.11% 96.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 39 0.08% 96.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 55 0.11% 96.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 21 0.04% 96.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5443 55 0.11% 96.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 27 0.05% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5571 50 0.10% 97.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5635 22 0.04% 97.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 54 0.11% 97.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 25 0.05% 97.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5827 53 0.11% 97.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 22 0.04% 97.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5955 52 0.11% 97.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 23 0.05% 97.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 54 0.11% 97.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 23 0.05% 97.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6211 52 0.11% 97.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6275 23 0.05% 97.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6339 54 0.11% 97.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 23 0.05% 98.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6467 53 0.11% 98.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6531 23 0.05% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 55 0.11% 98.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6659 26 0.05% 98.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 57 0.12% 98.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6787 421 0.85% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 12 0.02% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 1 0.00% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7363 2 0.00% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.wrQLenPdf::27 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 26 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 49380 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 738.726934 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 222.746795 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1735.319745 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 17723 35.89% 35.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 7354 14.89% 50.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 4892 9.91% 60.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2955 5.98% 66.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1860 3.77% 70.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1462 2.96% 73.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1143 2.31% 75.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 851 1.72% 77.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 746 1.51% 78.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 676 1.37% 80.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 661 1.34% 81.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 443 0.90% 82.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 337 0.68% 83.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 276 0.56% 83.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 300 0.61% 84.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 399 0.81% 85.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 192 0.39% 85.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 178 0.36% 85.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 196 0.40% 86.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 170 0.34% 86.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 202 0.41% 87.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 873 1.77% 88.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 184 0.37% 89.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 168 0.34% 89.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 96 0.19% 89.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 82 0.17% 89.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 107 0.22% 90.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 72 0.15% 90.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 81 0.16% 90.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 51 0.10% 90.58% # Bytes accessed per row activation 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99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8707 2 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8835 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9024-9027 2 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.41% # Bytes accessed per row activation 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0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8771 2 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8835 1 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9091 3 0.01% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.42% # Bytes accessed per row activation system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.42% # Bytes accessed per row activation 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1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10944-10947 4 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11072-11075 2 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11267 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11648-11651 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11712-11715 2 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11779 2 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11840-11843 1 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11968-11971 1 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12035 2 0.00% 99.47% # Bytes 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-system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 2 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 2 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 2 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 40 0.08% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 2 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 179 0.36% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 49252 # Bytes accessed per row activation -system.physmem.totQLat 6314810500 # Total ticks spent queuing -system.physmem.totMemAccLat 14686644250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2245150000 # Total ticks spent in databus transfers -system.physmem.totBankLat 6126683750 # Total ticks spent accessing banks -system.physmem.avgQLat 14063.23 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13644.26 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 2 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 2 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 3 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 2 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 36 0.07% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 2 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15619 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 180 0.36% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 49380 # Bytes accessed per row activation +system.physmem.totQLat 6346588750 # Total ticks spent queuing +system.physmem.totMemAccLat 14721193750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2245130000 # Total ticks spent in databus transfers +system.physmem.totBankLat 6129475000 # Total ticks spent accessing banks +system.physmem.avgQLat 14134.12 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13650.60 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32707.49 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 14.65 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 32784.72 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 14.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 14.65 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 14.66 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.95 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 11.09 # Average write queue length when enqueuing -system.physmem.readRowHits 424855 # Number of row buffer hits during reads -system.physmem.writeRowHits 95885 # Number of row buffer hits during writes -system.physmem.readRowHitRate 94.62 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.26 # Row buffer hit rate for writes -system.physmem.avgGap 3441445.42 # Average gap between requests -system.physmem.pageHitRate 91.36 # Row buffer hit rate, read and write combined +system.physmem.avgWrQLen 10.65 # Average write queue length when enqueuing +system.physmem.readRowHits 424775 # Number of row buffer hits during reads +system.physmem.writeRowHits 95849 # Number of row buffer hits during writes +system.physmem.readRowHitRate 94.60 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.22 # Row buffer hit rate for writes +system.physmem.avgGap 3439715.80 # Average gap between requests +system.physmem.pageHitRate 91.33 # Row buffer hit rate, read and write combined system.physmem.prechargeAllPercent 0.53 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 18657286 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 292799 # Transaction distribution -system.membus.trans_dist::ReadResp 292799 # Transaction distribution -system.membus.trans_dist::WriteReq 14111 # Transaction distribution -system.membus.trans_dist::WriteResp 14111 # Transaction distribution -system.membus.trans_dist::Writeback 120976 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16467 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11554 # Transaction distribution -system.membus.trans_dist::UpgradeResp 7080 # Transaction distribution -system.membus.trans_dist::ReadExReq 164905 # Transaction distribution -system.membus.trans_dist::ReadExResp 164053 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42620 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 930997 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 973617 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124666 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124666 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1098283 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 82306 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31175680 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 31257986 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5308160 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5308160 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36566146 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36566146 # Total data (bytes) -system.membus.snoop_data_through_bus 36416 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 43190000 # Layer occupancy (ticks) +system.membus.throughput 18666756 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 292805 # Transaction distribution +system.membus.trans_dist::ReadResp 292805 # Transaction distribution +system.membus.trans_dist::WriteReq 14109 # Transaction distribution +system.membus.trans_dist::WriteResp 14109 # Transaction distribution +system.membus.trans_dist::Writeback 120995 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16488 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 11559 # Transaction distribution +system.membus.trans_dist::UpgradeResp 7097 # Transaction distribution +system.membus.trans_dist::ReadExReq 164894 # Transaction distribution +system.membus.trans_dist::ReadExResp 164048 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42616 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 931055 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 973671 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124663 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124663 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1098334 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 82290 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31176960 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 31259250 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5307968 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5307968 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 36567218 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36567218 # Total data (bytes) +system.membus.snoop_data_through_bus 36608 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 43251000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1566162500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1579578000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3824002662 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3830990646 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376301000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376315500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.l2c.tags.replacements 342163 # number of replacements -system.l2c.tags.tagsinuse 65223.750612 # Cycle average of tags in use -system.l2c.tags.total_refs 2442870 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 407350 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 5.996980 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 8613125750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55316.946263 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4805.666179 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4897.139369 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 159.783438 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 44.215363 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.844070 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.073329 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.074724 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002438 # Average percentage of cache occupancy +system.l2c.tags.replacements 342160 # number of replacements +system.l2c.tags.tagsinuse 65219.945305 # Cycle average of tags in use +system.l2c.tags.total_refs 2443226 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 407347 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 5.997899 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 8615385750 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 55312.026017 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4807.093964 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4897.564051 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 159.017352 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 44.243921 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.843995 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.073350 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.074731 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.002426 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.000675 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995235 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 684304 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 664415 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 317640 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 107160 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1773519 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 792069 # number of Writeback hits -system.l2c.Writeback_hits::total 792069 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 188 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 543 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 731 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 37 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 22 # number of SCUpgradeReq hits +system.l2c.tags.occ_percent::total 0.995177 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 684719 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 664525 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 317383 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 107430 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1774057 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 791641 # number of Writeback hits +system.l2c.Writeback_hits::total 791641 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 180 # number of 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miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.329322 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001556 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.034023 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.173485 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63928.725730 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52109.177904 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64197.979798 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67046.487603 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 52681.968395 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10051.708925 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10012.601585 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10037.084021 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.477523 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.105249 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.416919 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018664 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.329295 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001557 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.034020 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.173468 # mshr miss rate for demand accesses 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mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57783.838384 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 64152.541250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 54204.014986 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -714,14 +716,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.tags.replacements 41694 # number of replacements -system.iocache.tags.tagsinuse 0.571330 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.570482 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1754532770000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.571330 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035708 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035708 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1754531382000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.570482 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035655 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035655 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses system.iocache.ReadReq_misses::total 174 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -730,14 +732,14 @@ system.iocache.demand_misses::tsunami.ide 41726 # n system.iocache.demand_misses::total 41726 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses system.iocache.overall_misses::total 41726 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21248383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21248383 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 12952701816 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 12952701816 # number of WriteReq miss cycles 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311722.704467 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 311722.704467 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 310932.037555 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 310932.037555 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 310932.037555 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 310932.037555 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 405757 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122121.454023 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122121.454023 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312052.435839 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 312052.435839 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 311260.411901 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 311260.411901 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 311260.411901 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 311260.411901 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 401197 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 29467 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 28980 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 13.769878 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.843927 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -780,14 +782,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41726 system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12199383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12199383 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10790464816 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 10790464816 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 10802664199 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10802664199 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 10802664199 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10802664199 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12200133 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12200133 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10804136814 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10804136814 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 10816336947 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10816336947 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 10816336947 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10816336947 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -796,14 +798,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70111.396552 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70111.396552 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 259685.810936 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 259685.810936 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 258895.273906 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 258895.273906 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 258895.273906 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 258895.273906 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70115.706897 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70115.706897 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260014.844388 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 260014.844388 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259222.953243 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 259222.953243 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259222.953243 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 259222.953243 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -821,22 +823,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7530179 # DTB read hits -system.cpu0.dtb.read_misses 7765 # DTB read misses +system.cpu0.dtb.read_hits 7532654 # DTB read hits +system.cpu0.dtb.read_misses 7812 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations -system.cpu0.dtb.read_accesses 524069 # DTB read accesses -system.cpu0.dtb.write_hits 5118893 # DTB write hits -system.cpu0.dtb.write_misses 910 # DTB write misses -system.cpu0.dtb.write_acv 133 # DTB write access violations -system.cpu0.dtb.write_accesses 202595 # DTB write accesses -system.cpu0.dtb.data_hits 12649072 # DTB hits -system.cpu0.dtb.data_misses 8675 # DTB misses -system.cpu0.dtb.data_acv 343 # DTB access violations -system.cpu0.dtb.data_accesses 726664 # DTB accesses -system.cpu0.itb.fetch_hits 3650586 # ITB hits -system.cpu0.itb.fetch_misses 3984 # ITB misses +system.cpu0.dtb.read_accesses 524694 # DTB read accesses +system.cpu0.dtb.write_hits 5120278 # DTB write hits +system.cpu0.dtb.write_misses 919 # DTB write misses +system.cpu0.dtb.write_acv 139 # DTB write access violations +system.cpu0.dtb.write_accesses 202960 # DTB write accesses +system.cpu0.dtb.data_hits 12652932 # DTB hits +system.cpu0.dtb.data_misses 8731 # DTB misses +system.cpu0.dtb.data_acv 349 # DTB access violations +system.cpu0.dtb.data_accesses 727654 # DTB accesses +system.cpu0.itb.fetch_hits 3655515 # ITB hits +system.cpu0.itb.fetch_misses 4023 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3654570 # ITB accesses +system.cpu0.itb.fetch_accesses 3659538 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -849,55 +851,55 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3923674778 # number of cpu cycles simulated +system.cpu0.numCycles 3921819749 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 47959136 # Number of instructions committed -system.cpu0.committedOps 47959136 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 44491652 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 211334 # Number of float alu accesses -system.cpu0.num_func_calls 1203195 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5632072 # number of instructions that are conditional controls -system.cpu0.num_int_insts 44491652 # number of integer instructions -system.cpu0.num_fp_insts 211334 # number of float instructions -system.cpu0.num_int_register_reads 61191395 # number of times the integer registers were read -system.cpu0.num_int_register_writes 33136181 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 103249 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 105046 # number of times the floating registers were written -system.cpu0.num_mem_refs 12690027 # number of memory refs -system.cpu0.num_load_insts 7557911 # Number of load instructions -system.cpu0.num_store_insts 5132116 # Number of store instructions -system.cpu0.num_idle_cycles 3700191977.998114 # Number of idle cycles -system.cpu0.num_busy_cycles 223482800.001886 # Number of busy cycles -system.cpu0.not_idle_fraction 0.056958 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.943042 # Percentage of idle cycles +system.cpu0.committedInsts 47983654 # Number of instructions committed +system.cpu0.committedOps 47983654 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44515044 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 211401 # Number of float alu accesses +system.cpu0.num_func_calls 1203620 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5635723 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44515044 # number of integer instructions +system.cpu0.num_fp_insts 211401 # number of float instructions +system.cpu0.num_int_register_reads 61226145 # number of times the integer registers were read +system.cpu0.num_int_register_writes 33154260 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 103282 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 105080 # number of times the floating registers were written +system.cpu0.num_mem_refs 12694028 # number of memory refs +system.cpu0.num_load_insts 7560495 # Number of load instructions +system.cpu0.num_store_insts 5133533 # Number of store instructions +system.cpu0.num_idle_cycles 3698209766.998114 # Number of idle cycles +system.cpu0.num_busy_cycles 223609982.001886 # Number of busy cycles +system.cpu0.not_idle_fraction 0.057017 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.942983 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6812 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 165228 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 56779 40.23% 40.23% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6813 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 165343 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 56789 40.24% 40.24% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 131 0.09% 40.33% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1974 1.40% 41.72% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 435 0.31% 42.03% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 81809 57.97% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 141128 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 56269 49.08% 49.08% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::22 1973 1.40% 41.73% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 435 0.31% 42.04% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 81806 57.96% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 141134 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 56279 49.08% 49.08% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1974 1.72% 50.92% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 435 0.38% 51.30% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 55834 48.70% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 114643 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1902446374500 96.97% 96.97% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 95095000 0.00% 96.98% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 766988500 0.04% 97.02% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 322426000 0.02% 97.03% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 58205747500 2.97% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1961836631500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.991018 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::31 55844 48.70% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 114662 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1901501471500 96.97% 96.97% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 95150500 0.00% 96.98% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 767153500 0.04% 97.01% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 322241000 0.02% 97.03% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 58223100500 2.97% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1960909117000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.991019 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.682492 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.812333 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.682639 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.812434 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed @@ -933,33 +935,33 @@ system.cpu0.kern.callpal::wripir 517 0.35% 0.35% # nu system.cpu0.kern.callpal::wrmces 1 0.00% 0.35% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.35% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.35% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3084 2.06% 2.41% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.45% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3090 2.07% 2.42% # number of callpals executed +system.cpu0.kern.callpal::tbi 52 0.03% 2.45% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed -system.cpu0.kern.callpal::swpipl 134176 89.75% 92.20% # number of callpals executed -system.cpu0.kern.callpal::rdps 6701 4.48% 96.68% # number of callpals executed +system.cpu0.kern.callpal::swpipl 134176 89.74% 92.20% # number of callpals executed +system.cpu0.kern.callpal::rdps 6700 4.48% 96.68% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.68% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 96.69% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 96.68% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.01% 96.69% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 96.69% # number of callpals executed -system.cpu0.kern.callpal::rti 4411 2.95% 99.64% # number of callpals executed -system.cpu0.kern.callpal::callsys 394 0.26% 99.91% # number of callpals executed +system.cpu0.kern.callpal::rti 4418 2.95% 99.64% # number of callpals executed +system.cpu0.kern.callpal::callsys 396 0.26% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 149500 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7010 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1373 # number of protection mode switches +system.cpu0.kern.callpal::total 149515 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7023 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1378 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1372 -system.cpu0.kern.mode_good::user 1373 +system.cpu0.kern.mode_good::kernel 1377 +system.cpu0.kern.mode_good::user 1378 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.195720 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.196070 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.327448 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1958037655500 99.81% 99.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3798971500 0.19% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.327937 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1957102433500 99.81% 99.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3806679000 0.19% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3085 # number of times the context was actually changed +system.cpu0.kern.swap_context 3091 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -991,47 +993,47 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 103908079 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2101783 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2101768 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14111 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14111 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 792069 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 16689 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11613 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 28302 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 338794 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 297244 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1394675 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3121086 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 636287 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 464415 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5616463 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44628928 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119461456 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20361152 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17008562 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 201460098 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 201449794 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 2400960 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4792055385 # Layer occupancy (ticks) +system.toL2Bus.throughput 103937669 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2101927 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2101912 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 14109 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 14109 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 791641 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 16698 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11618 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 28316 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 338479 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296929 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1395511 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3121357 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 635773 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 463473 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5616114 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44655680 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119473096 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20344704 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16974250 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 201447730 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 201437426 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 2374976 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4790041400 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3140628756 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3142512505 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5519397625 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 5519878863 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1431747492 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 1430590492 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 796288703 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 794307231 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1398649 # Throughput (bytes/s) +system.iobus.throughput 1399302 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7373 # Transaction distribution system.iobus.trans_dist::ReadResp 7373 # Transaction distribution -system.iobus.trans_dist::WriteReq 55663 # Transaction distribution -system.iobus.trans_dist::WriteResp 55663 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14010 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 55661 # Transaction distribution +system.iobus.trans_dist::WriteResp 55661 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14006 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -1043,11 +1045,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 42620 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 42616 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 126072 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 56040 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 126068 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 56024 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1059,12 +1061,12 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 82306 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 82290 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2743922 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2743922 # Total data (bytes) -system.iobus.reqLayer0.occupancy 13365000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 2743906 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2743906 # Total data (bytes) +system.iobus.reqLayer0.occupancy 13361000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1086,59 +1088,59 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 377760199 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 377744447 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28509000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 28507000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42664000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42681500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 696718 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.401211 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 47270807 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 697230 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.798011 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 40083254250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.401211 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992971 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.992971 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 47270807 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 47270807 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 47270807 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 47270807 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 47270807 # number of overall hits -system.cpu0.icache.overall_hits::total 47270807 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 697348 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 697348 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 697348 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 697348 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 697348 # number of overall misses -system.cpu0.icache.overall_misses::total 697348 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9977651756 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 9977651756 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 9977651756 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 9977651756 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 9977651756 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 9977651756 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47968155 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47968155 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47968155 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47968155 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47968155 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47968155 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014538 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014538 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014538 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014538 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014538 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014538 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14307.995084 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14307.995084 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14307.995084 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14307.995084 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14307.995084 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14307.995084 # average overall miss latency +system.cpu0.icache.tags.replacements 697136 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.398756 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 47294969 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 697648 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.792023 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 40091069250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.398756 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992966 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.992966 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 47294969 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 47294969 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 47294969 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 47294969 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 47294969 # number of overall hits +system.cpu0.icache.overall_hits::total 47294969 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 697766 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 697766 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 697766 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 697766 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 697766 # number of overall misses +system.cpu0.icache.overall_misses::total 697766 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9984385005 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 9984385005 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 9984385005 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 9984385005 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 9984385005 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 9984385005 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47992735 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47992735 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47992735 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47992735 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47992735 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47992735 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014539 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014539 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014539 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014539 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014539 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014539 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14309.073536 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14309.073536 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14309.073536 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14309.073536 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14309.073536 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14309.073536 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1147,112 +1149,112 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 697348 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 697348 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 697348 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 697348 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 697348 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 697348 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8577830244 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 8577830244 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8577830244 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 8577830244 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8577830244 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 8577830244 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014538 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014538 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014538 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014538 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014538 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014538 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12300.645078 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12300.645078 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12300.645078 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12300.645078 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12300.645078 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12300.645078 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 697766 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 697766 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 697766 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 697766 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 697766 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 697766 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8583721995 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 8583721995 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8583721995 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 8583721995 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8583721995 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 8583721995 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014539 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014539 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014539 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014539 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014539 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014539 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12301.720054 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12301.720054 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12301.720054 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12301.720054 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12301.720054 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12301.720054 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1186136 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.274988 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11457169 # Total number of references to valid blocks. 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140478 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 147984 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 147984 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11154817 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11154817 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11154817 # number of overall hits -system.cpu0.dcache.overall_hits::total 11154817 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 939343 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 939343 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 256772 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 256772 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13639 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13639 # 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LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 148878750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 43336419 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 43336419 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 37523052456 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 37523052456 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 37523052456 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 37523052456 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7388709 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7388709 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4962223 # number of WriteReq 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ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.127132 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051745 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051745 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088498 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088498 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.036406 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.036406 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.096844 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.096844 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096844 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.096844 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28822.609528 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 28822.609528 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40692.661014 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 40692.661014 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10915.664638 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10915.664638 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7751.103380 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7751.103380 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31370.773258 # average overall miss latency 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0.088443 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.036458 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.036458 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.096822 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.096822 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096822 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.096822 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28820.165453 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 28820.165453 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40741.492015 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 40741.492015 # average WriteReq miss latency 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system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1261,62 +1263,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 682430 # number of writebacks -system.cpu0.dcache.writebacks::total 682430 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 939343 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 939343 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 256772 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 256772 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13639 # number of LoadLockedReq MSHR misses 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26682.187974 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26682.187974 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38479.172363 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38479.172363 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8914.748149 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8914.748149 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5752.161181 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5752.161181 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29214.666269 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29214.666269 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29214.666269 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29214.666269 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 682519 # number of writebacks +system.cpu0.dcache.writebacks::total 682519 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 939483 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 939483 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 256736 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 256736 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13633 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13633 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5600 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5600 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1196219 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1196219 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1196219 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1196219 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25065202500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25065202500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9891526306 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9891526306 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 121052250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 121052250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 32145581 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32145581 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34956728806 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 34956728806 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34956728806 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 34956728806 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465602000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465602000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2284723500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2284723500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3750325500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3750325500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127108 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127108 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051724 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051724 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088443 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088443 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.036458 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.036458 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096822 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.096822 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096822 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.096822 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26679.782923 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26679.782923 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38528.006614 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38528.006614 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8879.355241 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8879.355241 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5740.282321 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5740.282321 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29222.683142 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29222.683142 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29222.683142 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29222.683142 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1328,22 +1334,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2385380 # DTB read hits +system.cpu1.dtb.read_hits 2383442 # DTB read hits system.cpu1.dtb.read_misses 2620 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 205337 # DTB read accesses -system.cpu1.dtb.write_hits 1707840 # DTB write hits +system.cpu1.dtb.write_hits 1706844 # DTB write hits system.cpu1.dtb.write_misses 235 # DTB write misses system.cpu1.dtb.write_acv 24 # DTB write access violations system.cpu1.dtb.write_accesses 89739 # DTB write accesses -system.cpu1.dtb.data_hits 4093220 # DTB hits +system.cpu1.dtb.data_hits 4090286 # DTB hits system.cpu1.dtb.data_misses 2855 # DTB misses system.cpu1.dtb.data_acv 24 # DTB access violations system.cpu1.dtb.data_accesses 295076 # DTB accesses -system.cpu1.itb.fetch_hits 1814538 # ITB hits +system.cpu1.itb.fetch_hits 1814139 # ITB hits system.cpu1.itb.fetch_misses 1064 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1815602 # ITB accesses +system.cpu1.itb.fetch_accesses 1815203 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1356,51 +1362,51 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3921880904 # number of cpu cycles simulated +system.cpu1.numCycles 3919927793 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 12967796 # Number of instructions committed -system.cpu1.committedOps 12967796 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 11946960 # Number of integer alu accesses +system.cpu1.committedInsts 12950293 # Number of instructions committed +system.cpu1.committedOps 12950293 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 11929999 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 174217 # Number of float alu accesses -system.cpu1.num_func_calls 410982 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1284197 # number of instructions that are conditional controls -system.cpu1.num_int_insts 11946960 # number of integer instructions +system.cpu1.num_func_calls 410658 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1281658 # number of instructions that are conditional controls +system.cpu1.num_int_insts 11929999 # number of integer instructions system.cpu1.num_fp_insts 174217 # number of float instructions -system.cpu1.num_int_register_reads 16422187 # number of times the integer registers were read -system.cpu1.num_int_register_writes 8787604 # number of times the integer registers were written +system.cpu1.num_int_register_reads 16394755 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8774296 # number of times the integer registers were written system.cpu1.num_fp_register_reads 90513 # number of times the floating registers were read system.cpu1.num_fp_register_writes 92474 # number of times the floating registers were written -system.cpu1.num_mem_refs 4116157 # number of memory refs -system.cpu1.num_load_insts 2399132 # Number of load instructions -system.cpu1.num_store_insts 1717025 # Number of store instructions -system.cpu1.num_idle_cycles 3872385828.119347 # Number of idle cycles -system.cpu1.num_busy_cycles 49495075.880653 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012620 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987380 # Percentage of idle cycles +system.cpu1.num_mem_refs 4113222 # number of memory refs +system.cpu1.num_load_insts 2397194 # Number of load instructions +system.cpu1.num_store_insts 1716028 # Number of store instructions +system.cpu1.num_idle_cycles 3870487590.349789 # Number of idle cycles +system.cpu1.num_busy_cycles 49440202.650211 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012613 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987387 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2742 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 78306 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 26634 38.27% 38.27% # number of times we switched to this ipl +system.cpu1.kern.inst.quiesce 2744 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 78268 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 26619 38.27% 38.27% # number of times we switched to this ipl system.cpu1.kern.ipl_count::22 1969 2.83% 41.10% # number of times we switched to this ipl system.cpu1.kern.ipl_count::30 517 0.74% 41.84% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 40476 58.16% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 69596 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 25767 48.16% 48.16% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_count::31 40454 58.16% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 69559 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 25752 48.16% 48.16% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::22 1969 3.68% 51.84% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::30 517 0.97% 52.81% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 25250 47.19% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 53503 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1909643308000 97.38% 97.38% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 700945000 0.04% 97.42% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 361639500 0.02% 97.44% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 50234529500 2.56% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1960940422000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.967448 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_good::31 25236 47.19% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 53474 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1908686801000 97.38% 97.38% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 700508000 0.04% 97.42% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 362068000 0.02% 97.44% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 50214489500 2.56% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1959963866500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.967429 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.623826 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.768765 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.623820 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.768757 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed @@ -1419,78 +1425,78 @@ system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu1.kern.callpal::wripir 435 0.61% 0.61% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.61% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.61% # number of callpals executed -system.cpu1.kern.callpal::swpctx 2001 2.78% 3.39% # number of callpals executed +system.cpu1.kern.callpal::swpctx 2001 2.79% 3.40% # number of callpals executed system.cpu1.kern.callpal::tbi 3 0.00% 3.40% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 3.41% # number of callpals executed -system.cpu1.kern.callpal::swpipl 63390 88.19% 91.60% # number of callpals executed -system.cpu1.kern.callpal::rdps 2146 2.99% 94.59% # number of callpals executed +system.cpu1.kern.callpal::swpipl 63355 88.19% 91.60% # number of callpals executed +system.cpu1.kern.callpal::rdps 2145 2.99% 94.59% # number of callpals executed system.cpu1.kern.callpal::wrkgp 1 0.00% 94.59% # number of callpals executed system.cpu1.kern.callpal::wrusp 3 0.00% 94.59% # number of callpals executed system.cpu1.kern.callpal::whami 3 0.00% 94.60% # number of callpals executed -system.cpu1.kern.callpal::rti 3719 5.17% 99.77% # number of callpals executed +system.cpu1.kern.callpal::rti 3718 5.18% 99.77% # number of callpals executed system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 71875 # number of callpals executed +system.cpu1.kern.callpal::total 71838 # number of callpals executed system.cpu1.kern.mode_switch::kernel 1956 # number of protection mode switches system.cpu1.kern.mode_switch::user 368 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2907 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2906 # number of protection mode switches system.cpu1.kern.mode_good::kernel 809 system.cpu1.kern.mode_good::user 368 system.cpu1.kern.mode_good::idle 441 system.cpu1.kern.mode_switch_good::kernel 0.413599 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.151703 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.309310 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 17986321500 0.92% 0.92% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1483696000 0.08% 0.99% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1940592550000 99.01% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_switch_good::idle 0.151755 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.309369 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 17986814000 0.92% 0.92% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1484472500 0.08% 0.99% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1939632240000 99.01% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 2002 # number of times the context was actually changed -system.cpu1.icache.tags.replacements 317593 # number of replacements -system.cpu1.icache.tags.tagsinuse 446.454785 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 12652531 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 318104 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 39.774825 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1959964216000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.454785 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.871982 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.871982 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 12652531 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 12652531 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 12652531 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 12652531 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 12652531 # number of overall hits -system.cpu1.icache.overall_hits::total 12652531 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 318144 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 318144 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 318144 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 318144 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 318144 # number of overall misses -system.cpu1.icache.overall_misses::total 318144 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4187615492 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4187615492 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4187615492 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4187615492 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4187615492 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4187615492 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 12970675 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 12970675 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 12970675 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 12970675 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 12970675 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 12970675 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024528 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024528 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024528 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024528 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024528 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024528 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13162.641735 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13162.641735 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13162.641735 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13162.641735 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13162.641735 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13162.641735 # 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+system.cpu1.dcache.demand_accesses::cpu1.data 3989545 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3989545 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 3989545 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 3989545 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049930 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.049930 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034433 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.034433 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.159003 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.159003 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106283 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106283 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043512 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.043512 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043512 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.043512 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12094.581163 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12094.581163 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18351.892352 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18351.892352 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9069.155379 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9069.155379 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7340.908290 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7340.908290 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14145.194818 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14145.194818 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14145.194818 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14145.194818 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1613,62 +1619,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 109639 # number of writebacks -system.cpu1.dcache.writebacks::total 109639 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 116850 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 116850 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 57159 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 57159 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9086 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9086 # number of LoadLockedReq MSHR misses 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-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.159069 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.159069 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106338 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106338 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043584 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.043584 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043584 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.043584 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10078.833984 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10078.833984 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16247.362148 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16247.362148 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7082.049307 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7082.049307 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5350.916985 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5350.916985 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12105.090679 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12105.090679 # average overall mshr miss latency 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cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 64195000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32145073 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32145073 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2105938196 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2105938196 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2105938196 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2105938196 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18776000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18776000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 718207000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 718207000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 736983000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 736983000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049930 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049930 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034433 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034433 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.159003 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.159003 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106283 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106283 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043512 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.043512 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043512 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.043512 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10093.912805 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10093.912805 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16311.381743 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16311.381743 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7069.155379 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7069.155379 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5340.600266 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5340.600266 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12131.469564 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12131.469564 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12131.469564 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12131.469564 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency |