diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha')
4 files changed, 2390 insertions, 2344 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index b3504c645..a85398f56 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -4,52 +4,52 @@ sim_seconds 1.869358 # Nu sim_ticks 1869358498000 # Number of ticks simulated final_tick 1869358498000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2576820 # Simulator instruction rate (inst/s) -host_op_rate 2576818 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 74107088123 # Simulator tick rate (ticks/s) -host_mem_usage 319644 # Number of bytes of host memory used -host_seconds 25.23 # Real time elapsed on the host +host_inst_rate 2452265 # Simulator instruction rate (inst/s) +host_op_rate 2452264 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 70524991939 # Simulator tick rate (ticks/s) +host_mem_usage 374768 # Number of bytes of host memory used +host_seconds 26.51 # Real time elapsed on the host sim_insts 65000470 # Number of instructions simulated sim_ops 65000470 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 765760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 66539648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 106432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 763584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 66536960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 106240 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 766208 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 68179008 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 765760 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 106432 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 872192 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7831360 # Number of bytes written to this memory -system.physmem.bytes_written::total 7831360 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11965 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 1039682 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1663 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 68173952 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 763584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 106240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 869824 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7835712 # Number of bytes written to this memory +system.physmem.bytes_written::total 7835712 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11931 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 1039640 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1660 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 11972 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1065297 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122365 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122365 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 409638 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 35594910 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 56935 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 1065218 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122433 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122433 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 408474 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 35593472 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 56832 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.data 409878 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 514 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36471874 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 409638 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 56935 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 466573 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4189330 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4189330 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4189330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 409638 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 35594910 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 56935 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 36469170 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 408474 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 56832 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 465306 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4191658 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4191658 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4191658 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 408474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 35593472 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 56832 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 409878 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40661204 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 40660828 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses @@ -303,8 +303,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 632997 # number of writebacks -system.cpu0.dcache.writebacks::total 632997 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 632989 # number of writebacks +system.cpu0.dcache.writebacks::total 632989 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 618298 # number of replacements system.cpu0.icache.tags.tagsinuse 511.240646 # Cycle average of tags in use @@ -655,8 +655,7 @@ system.disk2.dma_write_txs 1 # Nu system.iobus.trans_dist::ReadReq 7628 # Transaction distribution system.iobus.trans_dist::ReadResp 7628 # Transaction distribution system.iobus.trans_dist::WriteReq 56140 # Transaction distribution -system.iobus.trans_dist::WriteResp 14588 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.iobus.trans_dist::WriteResp 56140 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14686 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) @@ -705,24 +704,24 @@ system.iocache.tags.tag_accesses 375579 # Nu system.iocache.tags.data_accesses 375579 # Number of data accesses system.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses system.iocache.ReadReq_misses::total 179 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses system.iocache.demand_misses::tsunami.ide 179 # number of demand (read+write) misses system.iocache.demand_misses::total 179 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 179 # number of overall misses system.iocache.overall_misses::total 179 # number of overall misses system.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::tsunami.ide 179 # number of demand (read+write) accesses system.iocache.demand_accesses::total 179 # number of demand (read+write) accesses system.iocache.overall_accesses::tsunami.ide 179 # number of overall (read+write) accesses system.iocache.overall_accesses::total 179 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses @@ -738,89 +737,86 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 999763 # number of replacements -system.l2c.tags.tagsinuse 65320.982513 # Cycle average of tags in use -system.l2c.tags.total_refs 2387511 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1064813 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.242188 # Average number of references to valid blocks. +system.l2c.tags.replacements 999684 # number of replacements +system.l2c.tags.tagsinuse 65320.982503 # Cycle average of tags in use +system.l2c.tags.total_refs 4588619 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1064734 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.309639 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 56016.894287 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4834.499535 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4176.023150 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 178.992489 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 114.573052 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.854750 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.073769 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.063721 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002731 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 55911.037805 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4939.570238 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4176.759225 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 179.034361 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 114.580874 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.853135 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.075372 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.063732 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.002732 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.001748 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.996719 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65050 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 768 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 3271 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 6125 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 6123 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::3 5943 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 48943 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 48945 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.992584 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 31464842 # Number of tag accesses -system.l2c.tags.data_accesses 31464842 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 606959 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 626686 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 379549 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 129013 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1742207 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 777528 # number of Writeback hits -system.l2c.Writeback_hits::total 777528 # number of Writeback hits +system.l2c.tags.tag_accesses 49101323 # Number of tag accesses +system.l2c.tags.data_accesses 49101323 # Number of data accesses +system.l2c.Writeback_hits::writebacks 777520 # number of Writeback hits +system.l2c.Writeback_hits::total 777520 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 116 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 577 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 693 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 37 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 13 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 50 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 111433 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu0.data 111476 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu1.data 56603 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 168036 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 606959 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 738119 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 379549 # number of demand (read+write) hits +system.l2c.ReadExReq_hits::total 168079 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 606993 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 379552 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 986545 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 626685 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 129013 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 755698 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.inst 606993 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 738161 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 379552 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 185616 # number of demand (read+write) hits -system.l2c.demand_hits::total 1910243 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 606959 # number of overall hits -system.l2c.overall_hits::cpu0.data 738119 # number of overall hits -system.l2c.overall_hits::cpu1.inst 379549 # number of overall hits +system.l2c.demand_hits::total 1910322 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 606993 # number of overall hits +system.l2c.overall_hits::cpu0.data 738161 # number of overall hits +system.l2c.overall_hits::cpu1.inst 379552 # number of overall hits system.l2c.overall_hits::cpu1.data 185616 # number of overall hits -system.l2c.overall_hits::total 1910243 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 11965 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 926610 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1663 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1033 # number of ReadReq misses -system.l2c.ReadReq_misses::total 941271 # number of ReadReq misses +system.l2c.overall_hits::total 1910322 # number of overall hits system.l2c.UpgradeReq_misses::cpu0.data 3006 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 2174 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 5180 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu0.data 1175 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 1110 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2285 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 113916 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 113873 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 11069 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 124985 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 11965 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 1040526 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1663 # number of demand (read+write) misses +system.l2c.ReadExReq_misses::total 124942 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 11931 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 1660 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 13591 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 926611 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 1033 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 927644 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.inst 11931 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 1040484 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1660 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 12102 # number of demand (read+write) misses -system.l2c.demand_misses::total 1066256 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 11965 # number of overall misses -system.l2c.overall_misses::cpu0.data 1040526 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1663 # number of overall misses +system.l2c.demand_misses::total 1066177 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 11931 # number of overall misses +system.l2c.overall_misses::cpu0.data 1040484 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1660 # number of overall misses system.l2c.overall_misses::cpu1.data 12102 # number of overall misses -system.l2c.overall_misses::total 1066256 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.inst 618924 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1553296 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 381212 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 130046 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2683478 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 777528 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 777528 # number of Writeback accesses(hits+misses) +system.l2c.overall_misses::total 1066177 # number of overall misses +system.l2c.Writeback_accesses::writebacks 777520 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 777520 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 3122 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 2751 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 5873 # number of UpgradeReq accesses(hits+misses) @@ -830,6 +826,12 @@ system.l2c.SCUpgradeReq_accesses::total 2335 # nu system.l2c.ReadExReq_accesses::cpu0.data 225349 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 67672 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 293021 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 618924 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 381212 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1000136 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 1553296 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 130046 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 1683342 # number of ReadSharedReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.inst 618924 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 1778645 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 381212 # number of demand (read+write) accesses @@ -840,30 +842,31 @@ system.l2c.overall_accesses::cpu0.data 1778645 # nu system.l2c.overall_accesses::cpu1.inst 381212 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.data 197718 # number of overall (read+write) accesses system.l2c.overall_accesses::total 2976499 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.019332 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.596544 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.004362 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.007943 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.350765 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.962844 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.790258 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.882002 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.969472 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.988424 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 0.978587 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.505509 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.505318 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.163568 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.426539 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.019332 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.585010 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.004362 # miss rate for demand accesses +system.l2c.ReadExReq_miss_rate::total 0.426393 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.019277 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004355 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.013589 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596545 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.007943 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.551073 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.019277 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.584987 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.004355 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.061208 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.358225 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.019332 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.585010 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.004362 # miss rate for overall accesses +system.l2c.demand_miss_rate::total 0.358198 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.019277 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.584987 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.004355 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.061208 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.358225 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.358198 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -872,79 +875,84 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 80845 # number of writebacks -system.l2c.writebacks::total 80845 # number of writebacks +system.l2c.writebacks::writebacks 80913 # number of writebacks +system.l2c.writebacks::total 80913 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 948899 # Transaction distribution -system.membus.trans_dist::ReadResp 948899 # Transaction distribution +system.membus.trans_dist::ReadReq 7449 # Transaction distribution +system.membus.trans_dist::ReadResp 948863 # Transaction distribution system.membus.trans_dist::WriteReq 14588 # Transaction distribution system.membus.trans_dist::WriteResp 14588 # Transaction distribution -system.membus.trans_dist::Writeback 122365 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.membus.trans_dist::Writeback 122433 # Transaction distribution +system.membus.trans_dist::CleanEvict 922490 # Transaction distribution system.membus.trans_dist::UpgradeReq 19616 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 14180 # Transaction distribution system.membus.trans_dist::UpgradeResp 8160 # Transaction distribution -system.membus.trans_dist::ReadExReq 126515 # Transaction distribution -system.membus.trans_dist::ReadExResp 124290 # Transaction distribution +system.membus.trans_dist::ReadExReq 126472 # Transaction distribution +system.membus.trans_dist::ReadExResp 124247 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 941414 # Transaction distribution +system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 44074 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2256148 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 2300222 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124982 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124982 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2425204 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3178369 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3222443 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125161 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 125161 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3347604 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 86162 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73369984 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 73456146 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5328064 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 5328064 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 78784210 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73369280 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 73455442 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2668736 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2668736 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 76124178 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 1287715 # Request fanout histogram +system.membus.snoop_fanout::samples 2210194 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 1287715 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2210194 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 1287715 # Request fanout histogram -system.toL2Bus.trans_dist::ReadReq 2732182 # Transaction distribution +system.membus.snoop_fanout::total 2210194 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 7449 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 2732182 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 14588 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 777528 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 777520 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2204578 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 19614 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 14230 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 33844 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 295246 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 295246 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1237890 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4301779 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 762424 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 627155 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6929248 # Packet count per connected master and slave (bytes) +system.toL2Bus.trans_dist::ReadCleanReq 1000157 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1724576 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1856188 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5450155 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1143095 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 684380 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 9133818 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39612480 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155758587 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155758075 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24397568 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23357975 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 243126610 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 243126098 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 41895 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3895119 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.010714 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.102951 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 6099689 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.006841 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.082430 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 3853388 98.93% 98.93% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 41731 1.07% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 6057958 99.32% 99.32% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 41731 0.68% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3895119 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 6099689 # Request fanout histogram system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 3fe61f3f7..60a4f6e98 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -4,42 +4,42 @@ sim_seconds 1.829332 # Nu sim_ticks 1829332273500 # Number of ticks simulated final_tick 1829332273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2059947 # Simulator instruction rate (inst/s) -host_op_rate 2059945 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62765242809 # Simulator tick rate (ticks/s) -host_mem_usage 317596 # Number of bytes of host memory used -host_seconds 29.15 # Real time elapsed on the host +host_inst_rate 2495393 # Simulator instruction rate (inst/s) +host_op_rate 2495392 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 76033049021 # Simulator tick rate (ticks/s) +host_mem_usage 371696 # Number of bytes of host memory used +host_seconds 24.06 # Real time elapsed on the host sim_insts 60038341 # Number of instructions simulated sim_ops 60038341 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 66839040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 856000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 66836224 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 67697984 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7411008 # Number of bytes written to this memory -system.physmem.bytes_written::total 7411008 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13406 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1044360 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 67693184 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 856000 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 856000 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7414144 # Number of bytes written to this memory +system.physmem.bytes_written::total 7414144 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13375 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1044316 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1057781 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115797 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115797 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 469015 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 36537397 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 1057706 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115846 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115846 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 467930 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 36535858 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 37006937 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 469015 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 469015 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4051209 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4051209 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4051209 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 469015 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 36537397 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 37004313 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 467930 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 467930 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4052924 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4052924 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4052924 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 467930 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 36535858 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 525 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 41058146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 41057237 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -284,8 +284,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 833501 # number of writebacks -system.cpu.dcache.writebacks::total 833501 # number of writebacks +system.cpu.dcache.writebacks::writebacks 833493 # number of writebacks +system.cpu.dcache.writebacks::total 833493 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 919605 # number of replacements system.cpu.icache.tags.tagsinuse 511.215260 # Cycle average of tags in use @@ -336,84 +336,88 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 992295 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65424.374284 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2433284 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1057458 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.301069 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 992219 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65424.374112 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4561879 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1057382 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.314315 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 56310.352234 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4866.099732 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4247.922318 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.859228 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074251 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 56252.896873 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4923.444270 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 4248.032969 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.858351 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.075126 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.064820 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 781 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3260 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4024 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3055 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54043 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3053 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54045 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 31737815 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 31737815 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 906808 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 811247 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1718055 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 833501 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 833501 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 48768396 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 48768396 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 833493 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 833493 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187243 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187243 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 906808 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 998490 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1905298 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 906808 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 998490 # number of overall hits -system.cpu.l2cache.overall_hits::total 1905298 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 941046 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_hits::cpu.data 187288 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187288 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 906839 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 906839 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 811246 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 811246 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 906839 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 998534 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1905373 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 906839 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 998534 # number of overall hits +system.cpu.l2cache.overall_hits::total 1905373 # number of overall hits system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 117111 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 117111 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 13406 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1044751 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1058157 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 13406 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1044751 # number of overall misses -system.cpu.l2cache.overall_misses::total 1058157 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 920214 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1738887 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2659101 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 833501 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 833501 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 117066 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 117066 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13375 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 13375 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 927641 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 927641 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 13375 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1044707 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1058082 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 13375 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1044707 # number of overall misses +system.cpu.l2cache.overall_misses::total 1058082 # number of overall misses +system.cpu.l2cache.Writeback_accesses::writebacks 833493 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 833493 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 304354 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 304354 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 920214 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 920214 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1738887 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1738887 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 920214 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 2043241 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 2963455 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 920214 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2043241 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 2963455 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014568 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533468 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.353896 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384785 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.384785 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014568 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.511320 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.357069 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014568 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.511320 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.357069 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384638 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.384638 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014535 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014535 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.533468 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.533468 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014535 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.511299 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.357043 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014535 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.511299 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.357043 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -422,36 +426,39 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 74285 # number of writebacks -system.cpu.l2cache.writebacks::total 74285 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 74334 # number of writebacks +system.cpu.l2cache.writebacks::total 74334 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2666303 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 7184 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 2666303 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 833501 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 833493 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2128840 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 304354 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 304354 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1840464 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4954059 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6794523 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 920232 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1738887 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2760069 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6163286 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8923355 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58894848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184157614 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 243052462 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184157102 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 243051950 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 41883 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3855738 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.010822 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.103463 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 5984570 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.006972 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.083208 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3814012 98.92% 98.92% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41726 1.08% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5942844 99.30% 99.30% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 41726 0.70% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3855738 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5984570 # Request fanout histogram system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -467,8 +474,7 @@ system.disk2.dma_write_txs 1 # Nu system.iobus.trans_dist::ReadReq 7358 # Transaction distribution system.iobus.trans_dist::ReadResp 7358 # Transaction distribution system.iobus.trans_dist::WriteReq 51390 # Transaction distribution -system.iobus.trans_dist::WriteResp 9838 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.iobus.trans_dist::WriteResp 51390 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5248 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) @@ -517,24 +523,24 @@ system.iocache.tags.tag_accesses 375534 # Nu system.iocache.tags.data_accesses 375534 # Number of data accesses system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses system.iocache.ReadReq_misses::total 174 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses system.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses system.iocache.demand_misses::total 174 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 174 # number of overall misses system.iocache.overall_misses::total 174 # number of overall misses system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses system.iocache.demand_accesses::total 174 # number of demand (read+write) accesses system.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses system.iocache.overall_accesses::total 174 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses @@ -550,41 +556,43 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 948404 # Transaction distribution -system.membus.trans_dist::ReadResp 948404 # Transaction distribution +system.membus.trans_dist::ReadReq 7184 # Transaction distribution +system.membus.trans_dist::ReadResp 948374 # Transaction distribution system.membus.trans_dist::WriteReq 9838 # Transaction distribution system.membus.trans_dist::WriteResp 9838 # Transaction distribution -system.membus.trans_dist::Writeback 115797 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.membus.trans_dist::Writeback 115846 # Transaction distribution +system.membus.trans_dist::CleanEvict 918371 # Transaction distribution system.membus.trans_dist::UpgradeReq 132 # Transaction distribution system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 116991 # Transaction distribution -system.membus.trans_dist::ReadExResp 116991 # Transaction distribution +system.membus.trans_dist::ReadExReq 116946 # Transaction distribution +system.membus.trans_dist::ReadExResp 116946 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 941190 # Transaction distribution +system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2190623 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 2224667 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124964 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124964 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2349631 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3108719 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3142763 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125138 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 125138 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3267901 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72468608 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72514734 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5327232 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 5327232 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 77841966 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72466944 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72513070 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2667904 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2667904 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 75180974 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 1232714 # Request fanout histogram +system.membus.snoop_fanout::samples 2151059 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 1232714 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2151059 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 1232714 # Request fanout histogram +system.membus.snoop_fanout::total 2151059 # Request fanout histogram system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 3f2e8762f..67605a567 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,117 +1,117 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.962613 # Number of seconds simulated -sim_ticks 1962612686500 # Number of ticks simulated -final_tick 1962612686500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.962608 # Number of seconds simulated +sim_ticks 1962608482500 # Number of ticks simulated +final_tick 1962608482500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1118839 # Simulator instruction rate (inst/s) -host_op_rate 1118839 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36057415911 # Simulator tick rate (ticks/s) -host_mem_usage 319640 # Number of bytes of host memory used -host_seconds 54.43 # Real time elapsed on the host -sim_insts 60898638 # Number of instructions simulated -sim_ops 60898638 # Number of ops (including micro ops) simulated +host_inst_rate 1019388 # Simulator instruction rate (inst/s) +host_op_rate 1019388 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32859851956 # Simulator tick rate (ticks/s) +host_mem_usage 375280 # Number of bytes of host memory used +host_seconds 59.73 # Real time elapsed on the host +sim_insts 60884587 # Number of instructions simulated +sim_ops 60884587 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 836288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24736704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 28736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 435776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 831936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24730240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 31616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 435904 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26038464 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 836288 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 28736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 865024 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7702400 # Number of bytes written to this memory -system.physmem.bytes_written::total 7702400 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13067 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 386511 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 449 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6809 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26030656 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 831936 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 31616 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 863552 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7705152 # Number of bytes written to this memory +system.physmem.bytes_written::total 7705152 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12999 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 386410 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 494 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6811 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 406851 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120350 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120350 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 426110 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12603966 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 14642 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 222039 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 406729 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120393 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120393 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 423893 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12600700 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 16109 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 222104 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13267245 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 426110 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 14642 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 440751 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3924564 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3924564 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3924564 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 426110 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12603966 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 14642 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 222039 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13263295 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 423893 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 16109 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 440002 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3925975 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3925975 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3925975 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 423893 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12600700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 16109 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 222104 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 489 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17191810 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 406851 # Number of read requests accepted -system.physmem.writeReqs 161902 # Number of write requests accepted -system.physmem.readBursts 406851 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 161902 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26031872 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6592 # Total number of bytes read from write queue -system.physmem.bytesWritten 8721536 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26038464 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10361728 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 103 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 25609 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 6974 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25141 # Per bank write bursts -system.physmem.perBankRdBursts::1 25398 # Per bank write bursts -system.physmem.perBankRdBursts::2 25524 # Per bank write bursts -system.physmem.perBankRdBursts::3 24918 # Per bank write bursts -system.physmem.perBankRdBursts::4 25169 # Per bank write bursts -system.physmem.perBankRdBursts::5 25258 # Per bank write bursts -system.physmem.perBankRdBursts::6 25808 # Per bank write bursts -system.physmem.perBankRdBursts::7 25541 # Per bank write bursts -system.physmem.perBankRdBursts::8 25675 # Per bank write bursts -system.physmem.perBankRdBursts::9 25330 # Per bank write bursts -system.physmem.perBankRdBursts::10 25284 # Per bank write bursts -system.physmem.perBankRdBursts::11 25615 # Per bank write bursts -system.physmem.perBankRdBursts::12 25647 # Per bank write bursts -system.physmem.perBankRdBursts::13 25653 # Per bank write bursts -system.physmem.perBankRdBursts::14 25754 # Per bank write bursts -system.physmem.perBankRdBursts::15 25033 # Per bank write bursts -system.physmem.perBankWrBursts::0 8965 # Per bank write bursts -system.physmem.perBankWrBursts::1 8625 # Per bank write bursts -system.physmem.perBankWrBursts::2 8456 # Per bank write bursts -system.physmem.perBankWrBursts::3 7799 # Per bank write bursts -system.physmem.perBankWrBursts::4 8065 # Per bank write bursts -system.physmem.perBankWrBursts::5 8041 # Per bank write bursts -system.physmem.perBankWrBursts::6 8610 # Per bank write bursts -system.physmem.perBankWrBursts::7 8172 # Per bank write bursts -system.physmem.perBankWrBursts::8 8465 # Per bank write bursts -system.physmem.perBankWrBursts::9 8053 # Per bank write bursts -system.physmem.perBankWrBursts::10 8222 # Per bank write bursts -system.physmem.perBankWrBursts::11 8481 # Per bank write bursts -system.physmem.perBankWrBursts::12 8850 # Per bank write bursts -system.physmem.perBankWrBursts::13 9510 # Per bank write bursts -system.physmem.perBankWrBursts::14 9309 # Per bank write bursts -system.physmem.perBankWrBursts::15 8651 # Per bank write bursts +system.physmem.bw_total::total 17189270 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 406729 # Number of read requests accepted +system.physmem.writeReqs 120393 # Number of write requests accepted +system.physmem.readBursts 406729 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 120393 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26023296 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue +system.physmem.bytesWritten 7703744 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26030656 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7705152 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 48492 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25025 # Per bank write bursts +system.physmem.perBankRdBursts::1 25421 # Per bank write bursts +system.physmem.perBankRdBursts::2 25447 # Per bank write bursts +system.physmem.perBankRdBursts::3 24899 # Per bank write bursts +system.physmem.perBankRdBursts::4 25181 # Per bank write bursts +system.physmem.perBankRdBursts::5 25235 # Per bank write bursts +system.physmem.perBankRdBursts::6 25799 # Per bank write bursts +system.physmem.perBankRdBursts::7 25539 # Per bank write bursts +system.physmem.perBankRdBursts::8 25681 # Per bank write bursts +system.physmem.perBankRdBursts::9 25348 # Per bank write bursts +system.physmem.perBankRdBursts::10 25259 # Per bank write bursts +system.physmem.perBankRdBursts::11 25592 # Per bank write bursts +system.physmem.perBankRdBursts::12 25653 # Per bank write bursts +system.physmem.perBankRdBursts::13 25554 # Per bank write bursts +system.physmem.perBankRdBursts::14 25887 # Per bank write bursts +system.physmem.perBankRdBursts::15 25094 # Per bank write bursts +system.physmem.perBankWrBursts::0 7701 # Per bank write bursts +system.physmem.perBankWrBursts::1 7641 # Per bank write bursts +system.physmem.perBankWrBursts::2 7454 # Per bank write bursts +system.physmem.perBankWrBursts::3 6926 # Per bank write bursts +system.physmem.perBankWrBursts::4 7165 # Per bank write bursts +system.physmem.perBankWrBursts::5 7117 # Per bank write bursts +system.physmem.perBankWrBursts::6 7626 # Per bank write bursts +system.physmem.perBankWrBursts::7 7252 # Per bank write bursts +system.physmem.perBankWrBursts::8 7527 # Per bank write bursts +system.physmem.perBankWrBursts::9 7238 # Per bank write bursts +system.physmem.perBankWrBursts::10 7225 # Per bank write bursts +system.physmem.perBankWrBursts::11 7418 # Per bank write bursts +system.physmem.perBankWrBursts::12 7843 # Per bank write bursts +system.physmem.perBankWrBursts::13 8207 # Per bank write bursts +system.physmem.perBankWrBursts::14 8447 # Per bank write bursts +system.physmem.perBankWrBursts::15 7584 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 56 # Number of times write queue was full causing retry -system.physmem.totGap 1962566141500 # Total gap between requests +system.physmem.numWrRetry 20 # Number of times write queue was full causing retry +system.physmem.totGap 1962561950500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 406851 # Read request sizes (log2) +system.physmem.readPktSize::6 406729 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 161902 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 406672 # What read queue length does an incoming req see +system.physmem.writePktSize::6 120393 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 406538 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 63 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see @@ -158,190 +158,181 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1460 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5516 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5615 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6772 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5982 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1933 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2085 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1989 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 2742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 2945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 98 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 67633 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 513.852823 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 307.797069 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 417.051196 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16141 23.87% 23.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 12717 18.80% 42.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5311 7.85% 50.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2897 4.28% 54.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2115 3.13% 57.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1690 2.50% 60.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2144 3.17% 63.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1403 2.07% 65.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 23215 34.32% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 67633 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4988 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 81.544306 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2972.635603 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 4985 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6416 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6086 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7401 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8835 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7633 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6911 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5875 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5577 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 58 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 67016 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 503.268473 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 299.027850 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 415.161234 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16754 25.00% 25.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 12205 18.21% 43.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5432 8.11% 51.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3034 4.53% 55.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2418 3.61% 59.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1895 2.83% 62.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1494 2.23% 64.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1474 2.20% 66.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22310 33.29% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 67016 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5361 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 75.845178 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2883.640505 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5358 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4988 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4988 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.320369 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.529999 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 62.006905 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 4741 95.05% 95.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 52 1.04% 96.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 5 0.10% 96.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 6 0.12% 96.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 4 0.08% 96.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 12 0.24% 96.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 26 0.52% 97.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 19 0.38% 97.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 10 0.20% 97.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 13 0.26% 98.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 3 0.06% 98.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 4 0.08% 98.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 2 0.04% 98.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 1 0.02% 98.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 2 0.04% 98.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 5 0.10% 98.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 5 0.10% 98.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 12 0.24% 98.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 16 0.32% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 4 0.08% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 10 0.20% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 2 0.04% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::432-447 1 0.02% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::464-479 4 0.08% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 2 0.04% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 2 0.04% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 2 0.04% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 10 0.20% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 3 0.06% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::576-591 1 0.02% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::672-687 1 0.02% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::688-703 2 0.04% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::704-719 2 0.04% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::720-735 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::736-751 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::816-831 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::928-943 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4988 # Writes before turning the bus around for reads -system.physmem.totQLat 2137457500 # Total ticks spent queuing -system.physmem.totMemAccLat 9763982500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2033740000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5254.99 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5361 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5361 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.453087 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.909523 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 23.339442 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4763 88.85% 88.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 210 3.92% 92.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 83 1.55% 94.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 15 0.28% 94.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 3 0.06% 94.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 2 0.04% 94.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 8 0.15% 94.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 9 0.17% 95.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 7 0.13% 95.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 35 0.65% 95.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 171 3.19% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 7 0.13% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 4 0.07% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 1 0.02% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 3 0.06% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 3 0.06% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 1 0.02% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 3 0.06% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 3 0.06% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 4 0.07% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 2 0.04% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 4 0.07% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.02% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 6 0.11% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 10 0.19% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5361 # Writes before turning the bus around for reads +system.physmem.totQLat 2204423500 # Total ticks spent queuing +system.physmem.totMemAccLat 9828436000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2033070000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5421.42 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24004.99 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 24171.42 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.26 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.44 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.27 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 5.28 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBW 3.93 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.26 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.93 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.14 # Data bus utilization in percentage +system.physmem.busUtil 0.13 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.00 # Average write queue length when enqueuing -system.physmem.readRowHits 364433 # Number of row buffer hits during reads -system.physmem.writeRowHits 110956 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.60 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.41 # Row buffer hit rate for writes -system.physmem.avgGap 3450647.54 # Average gap between requests -system.physmem.pageHitRate 87.54 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 253449000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 138290625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1581504600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 432429840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 128188142160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 66287824245 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1119418910250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1316300550720 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.688732 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1862013796212 # Time in different power states -system.physmem_0.memoryStateTime::REF 65535860000 # Time in different power states +system.physmem.avgWrQLen 24.74 # Average write queue length when enqueuing +system.physmem.readRowHits 363741 # Number of row buffer hits during reads +system.physmem.writeRowHits 96228 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.46 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.93 # Row buffer hit rate for writes +system.physmem.avgGap 3723164.56 # Average gap between requests +system.physmem.pageHitRate 87.28 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 249797520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 136298250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1579858800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 381555360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 128187633600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 65826808245 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1119818638500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1316180590275 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.630269 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1862676833500 # Time in different power states +system.physmem_0.memoryStateTime::REF 65535600000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 35060565038 # Time in different power states +system.physmem_0.memoryStateTime::ACT 34390001500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 257856480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 140695500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1591129800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 450625680 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 128188142160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 66523575105 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1119212111250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1316364135975 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.721130 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1861673236216 # Time in different power states -system.physmem_1.memoryStateTime::REF 65535860000 # Time in different power states +system.physmem_1.actEnergy 256843440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 140142750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1591730400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 398448720 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 128187633600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 66351904785 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1119358027500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1316284731195 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.683332 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1861912025250 # Time in different power states +system.physmem_1.memoryStateTime::REF 65535600000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 35401125034 # Time in different power states +system.physmem_1.memoryStateTime::ACT 35154809750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7492205 # DTB read hits +system.cpu0.dtb.read_hits 7500026 # DTB read hits system.cpu0.dtb.read_misses 7443 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 490673 # DTB read accesses -system.cpu0.dtb.write_hits 5067323 # DTB write hits +system.cpu0.dtb.write_hits 5074087 # DTB write hits system.cpu0.dtb.write_misses 813 # DTB write misses system.cpu0.dtb.write_acv 134 # DTB write access violations system.cpu0.dtb.write_accesses 187452 # DTB write accesses -system.cpu0.dtb.data_hits 12559528 # DTB hits +system.cpu0.dtb.data_hits 12574113 # DTB hits system.cpu0.dtb.data_misses 8256 # DTB misses system.cpu0.dtb.data_acv 344 # DTB access violations system.cpu0.dtb.data_accesses 678125 # DTB accesses -system.cpu0.itb.fetch_hits 3501951 # ITB hits +system.cpu0.itb.fetch_hits 3504450 # ITB hits system.cpu0.itb.fetch_misses 3871 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3505822 # ITB accesses +system.cpu0.itb.fetch_accesses 3508321 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -354,91 +345,91 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3923838766 # number of cpu cycles simulated +system.cpu0.numCycles 3923838721 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 47743384 # Number of instructions committed -system.cpu0.committedOps 47743384 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 44279734 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 210698 # Number of float alu accesses -system.cpu0.num_func_calls 1202353 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5609016 # number of instructions that are conditional controls -system.cpu0.num_int_insts 44279734 # number of integer instructions -system.cpu0.num_fp_insts 210698 # number of float instructions -system.cpu0.num_int_register_reads 60867436 # number of times the integer registers were read -system.cpu0.num_int_register_writes 32999466 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 102334 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 104190 # number of times the floating registers were written -system.cpu0.num_mem_refs 12599731 # number of memory refs -system.cpu0.num_load_insts 7519361 # Number of load instructions -system.cpu0.num_store_insts 5080370 # Number of store instructions -system.cpu0.num_idle_cycles 3698952400.393103 # Number of idle cycles -system.cpu0.num_busy_cycles 224886365.606898 # Number of busy cycles -system.cpu0.not_idle_fraction 0.057313 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.942687 # Percentage of idle cycles -system.cpu0.Branches 7198745 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2727567 5.71% 5.71% # Class of executed instruction -system.cpu0.op_class::IntAlu 31426598 65.81% 71.52% # Class of executed instruction -system.cpu0.op_class::IntMult 52886 0.11% 71.63% # Class of executed instruction +system.cpu0.committedInsts 47783493 # Number of instructions committed +system.cpu0.committedOps 47783493 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44315744 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 211234 # Number of float alu accesses +system.cpu0.num_func_calls 1203861 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5612503 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44315744 # number of integer instructions +system.cpu0.num_fp_insts 211234 # number of float instructions +system.cpu0.num_int_register_reads 60912860 # number of times the integer registers were read +system.cpu0.num_int_register_writes 33024751 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 102598 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 104462 # number of times the floating registers were written +system.cpu0.num_mem_refs 12614351 # number of memory refs +system.cpu0.num_load_insts 7527207 # Number of load instructions +system.cpu0.num_store_insts 5087144 # Number of store instructions +system.cpu0.num_idle_cycles 3699336863.028799 # Number of idle cycles +system.cpu0.num_busy_cycles 224501857.971201 # Number of busy cycles +system.cpu0.not_idle_fraction 0.057215 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.942785 # Percentage of idle cycles +system.cpu0.Branches 7204257 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2730537 5.71% 5.71% # Class of executed instruction +system.cpu0.op_class::IntAlu 31447784 65.80% 71.51% # Class of executed instruction +system.cpu0.op_class::IntMult 52772 0.11% 71.63% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 71.63% # Class of executed instruction -system.cpu0.op_class::FloatAdd 25715 0.05% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1656 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::MemRead 7694830 16.11% 87.81% # Class of executed instruction -system.cpu0.op_class::MemWrite 5086464 10.65% 98.46% # Class of executed instruction -system.cpu0.op_class::IprAccess 736268 1.54% 100.00% # Class of executed instruction +system.cpu0.op_class::FloatAdd 25731 0.05% 71.68% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1656 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::MemRead 7703007 16.12% 87.80% # Class of executed instruction +system.cpu0.op_class::MemWrite 5093240 10.66% 98.46% # Class of executed instruction +system.cpu0.op_class::IprAccess 737366 1.54% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 47751984 # Class of executed instruction +system.cpu0.op_class::total 47792093 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 6802 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 164994 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 56858 40.19% 40.19% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl +system.cpu0.kern.inst.hwrei 165261 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 56971 40.19% 40.19% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.29% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1973 1.39% 41.68% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 421 0.30% 41.97% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 82092 58.03% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 141475 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 56322 49.08% 49.08% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::30 419 0.30% 41.97% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 82246 58.03% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 141740 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 56429 49.08% 49.08% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 421 0.37% 51.28% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 55901 48.72% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 114748 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1900658476000 96.88% 96.88% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 90840500 0.00% 96.88% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 754578500 0.04% 96.92% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 304090000 0.02% 96.94% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 60111368000 3.06% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1961919353000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.990573 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::30 419 0.36% 51.28% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 56010 48.72% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 114962 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1900835958000 96.89% 96.89% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 91198500 0.00% 96.89% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 757506500 0.04% 96.93% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 303704500 0.02% 96.95% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 59930963000 3.05% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1961919330500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.990486 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.680956 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.811083 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.681006 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.811077 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed @@ -470,124 +461,124 @@ system.cpu0.kern.syscall::144 2 0.90% 99.10% # nu system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 222 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 503 0.34% 0.34% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wripir 500 0.33% 0.33% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.33% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3067 2.05% 2.39% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3072 2.05% 2.38% # number of callpals executed system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed -system.cpu0.kern.callpal::swpipl 134616 89.86% 92.28% # number of callpals executed -system.cpu0.kern.callpal::rdps 6699 4.47% 96.75% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed +system.cpu0.kern.callpal::swpipl 134879 89.87% 92.29% # number of callpals executed +system.cpu0.kern.callpal::rdps 6699 4.46% 96.76% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.76% # number of callpals executed system.cpu0.kern.callpal::wrusp 3 0.00% 96.76% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.76% # number of callpals executed -system.cpu0.kern.callpal::rti 4333 2.89% 99.65% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.77% # number of callpals executed +system.cpu0.kern.callpal::rti 4337 2.89% 99.66% # number of callpals executed system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 149812 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6888 # number of protection mode switches +system.cpu0.kern.callpal::total 150081 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6891 # number of protection mode switches system.cpu0.kern.mode_switch::user 1282 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches system.cpu0.kern.mode_good::kernel 1282 system.cpu0.kern.mode_good::user 1282 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.186121 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.186040 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.313831 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1958151397500 99.82% 99.82% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3535867500 0.18% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.313716 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1958152340000 99.82% 99.82% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3531530500 0.18% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3068 # number of times the context was actually changed -system.cpu0.dcache.tags.replacements 1180939 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.262035 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11368359 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1181356 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.623144 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 112435250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.262035 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986840 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986840 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 417 # Occupied blocks per task id +system.cpu0.kern.swap_context 3073 # number of times the context was actually changed +system.cpu0.dcache.tags.replacements 1181794 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.240594 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11382177 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1182212 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.627865 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 112405500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.240594 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986798 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986798 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 418 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 372 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 45 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.814453 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51471280 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51471280 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6411907 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6411907 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4659091 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4659091 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140391 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 140391 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148074 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 148074 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11070998 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11070998 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11070998 # number of overall hits -system.cpu0.dcache.overall_hits::total 11070998 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 938638 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 938638 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 251661 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 251661 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13662 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13662 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5430 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5430 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1190299 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1190299 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1190299 # number of overall misses -system.cpu0.dcache.overall_misses::total 1190299 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 29060390999 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 29060390999 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10906402435 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 10906402435 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150333500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 150333500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 48525392 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 48525392 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 39966793434 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 39966793434 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 39966793434 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 39966793434 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7350545 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7350545 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4910752 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4910752 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154053 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 154053 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153504 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 153504 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12261297 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12261297 # 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average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43191.191714 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 43191.191714 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10999.049082 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10999.049082 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8836.821634 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8836.821634 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33396.110258 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33396.110258 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33396.110258 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33396.110258 # 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number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1474416000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2293892500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2293892500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3768308500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3768308500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127696 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127696 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051247 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051247 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088684 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088684 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035374 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035374 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097078 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097078 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097078 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097078 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29326.090571 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29326.090571 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41631.210497 # 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number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127649 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127649 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051207 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051207 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088581 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088581 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035108 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035108 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097028 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097028 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097028 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097028 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29770.240157 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29770.240157 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42191.191714 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42191.191714 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9999.049082 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9999.049082 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7836.821634 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7836.821634 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32396.110258 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32396.110258 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32396.110258 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32396.110258 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209877.355837 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209877.355837 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 214227.490996 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 214227.490996 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 212503.344668 # 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Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 700401 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.179347 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 47091062 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 700913 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.185317 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 42246954500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.179347 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992538 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.992538 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 356 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 156 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 355 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 157 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 48451372 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 48451372 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 47052596 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 47052596 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 47052596 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 47052596 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 47052596 # number of overall hits -system.cpu0.icache.overall_hits::total 47052596 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 699388 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 699388 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 699388 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 699388 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 699388 # number of overall misses -system.cpu0.icache.overall_misses::total 699388 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10012837997 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10012837997 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10012837997 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10012837997 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10012837997 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10012837997 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47751984 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47751984 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47751984 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47751984 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47751984 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47751984 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014646 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014646 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014646 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014646 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014646 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014646 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14316.571055 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14316.571055 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14316.571055 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14316.571055 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14316.571055 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14316.571055 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 48493124 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 48493124 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 47091062 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 47091062 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 47091062 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 47091062 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 47091062 # number of overall hits +system.cpu0.icache.overall_hits::total 47091062 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 701031 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 701031 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 701031 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 701031 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 701031 # number of overall misses +system.cpu0.icache.overall_misses::total 701031 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10017639000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10017639000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10017639000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10017639000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10017639000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10017639000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47792093 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47792093 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47792093 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47792093 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47792093 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47792093 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014668 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014668 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014668 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014668 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014668 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014668 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14289.865926 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14289.865926 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14289.865926 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14289.865926 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14289.865926 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14289.865926 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -724,51 +715,51 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 699388 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 699388 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 699388 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 699388 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 699388 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 699388 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8958710003 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 8958710003 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8958710003 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 8958710003 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8958710003 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 8958710003 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014646 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014646 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014646 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014646 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014646 # 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mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014668 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014668 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014668 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014668 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014668 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13289.865926 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13289.865926 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13289.865926 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13289.865926 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13289.865926 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13289.865926 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2419579 # DTB read hits +system.cpu1.dtb.read_hits 2409623 # DTB read hits system.cpu1.dtb.read_misses 2992 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 239363 # DTB read accesses -system.cpu1.dtb.write_hits 1757217 # DTB write hits +system.cpu1.dtb.write_hits 1749165 # DTB write hits system.cpu1.dtb.write_misses 341 # DTB write misses system.cpu1.dtb.write_acv 29 # DTB write access violations system.cpu1.dtb.write_accesses 105247 # DTB write accesses -system.cpu1.dtb.data_hits 4176796 # DTB hits +system.cpu1.dtb.data_hits 4158788 # DTB hits system.cpu1.dtb.data_misses 3333 # DTB misses system.cpu1.dtb.data_acv 29 # DTB access violations system.cpu1.dtb.data_accesses 344610 # DTB accesses -system.cpu1.itb.fetch_hits 1964101 # ITB hits +system.cpu1.itb.fetch_hits 1960477 # ITB hits system.cpu1.itb.fetch_misses 1216 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1965317 # ITB accesses +system.cpu1.itb.fetch_accesses 1961693 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -781,87 +772,87 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3925225373 # number of cpu cycles simulated +system.cpu1.numCycles 3925216965 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 13155254 # Number of instructions committed -system.cpu1.committedOps 13155254 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 12132982 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 173111 # Number of float alu accesses -system.cpu1.num_func_calls 411301 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1304865 # number of instructions that are conditional controls -system.cpu1.num_int_insts 12132982 # number of integer instructions -system.cpu1.num_fp_insts 173111 # number of float instructions -system.cpu1.num_int_register_reads 16703630 # number of times the integer registers were read -system.cpu1.num_int_register_writes 8903954 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 90570 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 92446 # number of times the floating registers were written -system.cpu1.num_mem_refs 4200357 # number of memory refs -system.cpu1.num_load_insts 2433886 # Number of load instructions -system.cpu1.num_store_insts 1766471 # Number of store instructions -system.cpu1.num_idle_cycles 3876126901.998025 # Number of idle cycles -system.cpu1.num_busy_cycles 49098471.001975 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012508 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987492 # Percentage of idle cycles -system.cpu1.Branches 1871330 # Number of branches fetched -system.cpu1.op_class::No_OpClass 704516 5.35% 5.35% # Class of executed instruction -system.cpu1.op_class::IntAlu 7779367 59.12% 64.47% # Class of executed instruction -system.cpu1.op_class::IntMult 21509 0.16% 64.64% # Class of executed instruction +system.cpu1.committedInsts 13101094 # Number of instructions committed +system.cpu1.committedOps 13101094 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 12083765 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 172106 # Number of float alu accesses +system.cpu1.num_func_calls 409417 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1299945 # number of instructions that are conditional controls +system.cpu1.num_int_insts 12083765 # number of integer instructions +system.cpu1.num_fp_insts 172106 # number of float instructions +system.cpu1.num_int_register_reads 16637487 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8868500 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 90075 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 91936 # number of times the floating registers were written +system.cpu1.num_mem_refs 4182249 # number of memory refs +system.cpu1.num_load_insts 2423870 # Number of load instructions +system.cpu1.num_store_insts 1758379 # Number of store instructions +system.cpu1.num_idle_cycles 3876316507.998025 # Number of idle cycles +system.cpu1.num_busy_cycles 48900457.001975 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012458 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987542 # Percentage of idle cycles +system.cpu1.Branches 1864071 # Number of branches fetched +system.cpu1.op_class::No_OpClass 700818 5.35% 5.35% # Class of executed instruction +system.cpu1.op_class::IntAlu 7749061 59.13% 64.48% # Class of executed instruction +system.cpu1.op_class::IntMult 21359 0.16% 64.64% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 64.64% # Class of executed instruction -system.cpu1.op_class::FloatAdd 14171 0.11% 64.75% # Class of executed instruction +system.cpu1.op_class::FloatAdd 14141 0.11% 64.75% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 64.75% # Class of executed instruction system.cpu1.op_class::FloatCvt 0 0.00% 64.75% # Class of executed instruction system.cpu1.op_class::FloatMult 0 0.00% 64.75% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1986 0.02% 64.76% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::MemRead 2505658 19.04% 83.80% # Class of executed instruction -system.cpu1.op_class::MemWrite 1767460 13.43% 97.23% # Class of executed instruction -system.cpu1.op_class::IprAccess 363949 2.77% 100.00% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1986 0.02% 64.77% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::MemRead 2495218 19.04% 83.81% # Class of executed instruction +system.cpu1.op_class::MemWrite 1759360 13.43% 97.23% # Class of executed instruction +system.cpu1.op_class::IprAccess 362513 2.77% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 13158616 # Class of executed instruction +system.cpu1.op_class::total 13104456 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2740 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 78523 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 26526 38.34% 38.34% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1967 2.84% 41.19% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 503 0.73% 41.91% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 40183 58.09% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 69179 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 25685 48.16% 48.16% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1967 3.69% 51.84% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 503 0.94% 52.79% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 25182 47.21% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 53337 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1909492808500 97.29% 97.29% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 698045000 0.04% 97.33% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 344048000 0.02% 97.35% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 52077063000 2.65% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1962611964500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.968295 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2738 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 78185 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 26382 38.32% 38.32% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1969 2.86% 41.18% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 500 0.73% 41.90% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 40003 58.10% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 68854 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 25547 48.14% 48.14% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1969 3.71% 51.85% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 500 0.94% 52.80% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 25048 47.20% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 53064 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1909718189500 97.31% 97.31% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 702775500 0.04% 97.34% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 343141500 0.02% 97.36% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 51843654000 2.64% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1962607760500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.968350 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.626683 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.771000 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.626153 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.770674 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed @@ -877,124 +868,124 @@ system.cpu1.kern.syscall::74 10 9.62% 97.12% # nu system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 104 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 421 0.59% 0.59% # number of callpals executed +system.cpu1.kern.callpal::wripir 419 0.59% 0.59% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1997 2.79% 3.39% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1985 2.79% 3.38% # number of callpals executed system.cpu1.kern.callpal::tbi 3 0.00% 3.39% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 3.40% # number of callpals executed -system.cpu1.kern.callpal::swpipl 62934 88.05% 91.45% # number of callpals executed -system.cpu1.kern.callpal::rdps 2145 3.00% 94.46% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.46% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 94.46% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.47% # number of callpals executed -system.cpu1.kern.callpal::rti 3774 5.28% 99.75% # number of callpals executed +system.cpu1.kern.callpal::swpipl 62619 88.03% 91.42% # number of callpals executed +system.cpu1.kern.callpal::rdps 2146 3.02% 94.44% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.44% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 94.45% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.45% # number of callpals executed +system.cpu1.kern.callpal::rti 3766 5.29% 99.75% # number of callpals executed system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 71473 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2064 # number of protection mode switches -system.cpu1.kern.mode_switch::user 463 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2877 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 890 -system.cpu1.kern.mode_good::user 463 -system.cpu1.kern.mode_good::idle 427 -system.cpu1.kern.mode_switch_good::kernel 0.431202 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 71137 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2053 # number of protection mode switches +system.cpu1.kern.mode_switch::user 465 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2874 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 889 +system.cpu1.kern.mode_good::user 465 +system.cpu1.kern.mode_good::idle 424 +system.cpu1.kern.mode_switch_good::kernel 0.433025 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.148418 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.329386 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 17700699500 0.90% 0.90% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1706728000 0.09% 0.99% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1943204535000 99.01% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1998 # number of times the context was actually changed -system.cpu1.dcache.tags.replacements 166165 # number of replacements -system.cpu1.dcache.tags.tagsinuse 485.164459 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 4008469 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 166677 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 24.049323 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 79256927000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.164459 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.947587 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.947587 # Average percentage of cache occupancy +system.cpu1.kern.mode_switch_good::idle 0.147530 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.329748 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 17552018500 0.89% 0.89% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1707542500 0.09% 0.98% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1943348197500 99.02% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1986 # number of times the context was actually changed +system.cpu1.dcache.tags.replacements 165381 # number of replacements +system.cpu1.dcache.tags.tagsinuse 485.645767 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 3991235 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 165893 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 24.059092 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 1050804836500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.645767 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.948527 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.948527 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 16941101 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 16941101 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2255044 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2255044 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1640007 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1640007 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48683 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 48683 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50718 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 50718 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3895051 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3895051 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3895051 # number of overall hits -system.cpu1.dcache.overall_hits::total 3895051 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 118164 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 118164 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 62534 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 62534 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8914 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 8914 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5850 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 5850 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 180698 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 180698 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 180698 # number of overall misses -system.cpu1.dcache.overall_misses::total 180698 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1427964750 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1427964750 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1264688999 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1264688999 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 81193500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 81193500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 50099897 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 50099897 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 2692653749 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 2692653749 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 2692653749 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 2692653749 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2373208 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2373208 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1702541 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1702541 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57597 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 57597 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56568 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 56568 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4075749 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4075749 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4075749 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4075749 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049791 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.049791 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036730 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.036730 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.154765 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.154765 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103415 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103415 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044335 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.044335 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044335 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.044335 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12084.600640 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12084.600640 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20224.022116 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 20224.022116 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9108.537133 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9108.537133 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8564.084957 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8564.084957 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14901.403164 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14901.403164 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14901.403164 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14901.403164 # average overall miss latency +system.cpu1.dcache.tags.tag_accesses 16867850 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 16867850 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 2245744 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2245744 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1632527 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1632527 # 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number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 80743500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49386500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 49386500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 2681471500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 2681471500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 2681471500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 2681471500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2363341 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2363341 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1694806 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1694806 # 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miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.036747 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.154174 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.154174 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103394 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103394 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044325 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.044325 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044325 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.044325 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12123.021846 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12123.021846 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20164.750558 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 20164.750558 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9116.348651 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9116.348651 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8495.871323 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8495.871323 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14907.333385 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14907.333385 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14907.333385 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14907.333385 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1003,128 +994,128 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 114146 # number of writebacks -system.cpu1.dcache.writebacks::total 114146 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118164 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 118164 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62534 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 62534 # 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number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 67822500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 41323103 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 41323103 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2418558251 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2418558251 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2418558251 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2418558251 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18866000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18866000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 716370000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 716370000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 735236000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 735236000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049791 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049791 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036730 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036730 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.154765 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.154765 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103415 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103415 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044335 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.044335 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044335 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.044335 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10583.961697 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10583.961697 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18676.480011 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18676.480011 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7608.537133 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7608.537133 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7063.778291 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7063.778291 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13384.532485 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13384.532485 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13384.532485 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13384.532485 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 211977.528090 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 211977.528090 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 222613.424487 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 222613.424487 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 222327.184760 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 222327.184760 # average overall mshr uncacheable latency +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3214 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3214 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3303 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3303 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1308034000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1308034000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1193561500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1193561500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 71886500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 71886500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 43573500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 43573500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2501595500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2501595500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2501595500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2501595500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19086500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19086500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 723672500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 723672500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742759000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742759000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049759 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049759 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036747 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036747 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.154174 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.154174 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103394 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103394 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044325 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.044325 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044325 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.044325 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11123.021846 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11123.021846 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19164.750558 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19164.750558 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8116.348651 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8116.348651 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7495.871323 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7495.871323 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13907.333385 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13907.333385 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13907.333385 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13907.333385 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 214455.056180 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 214455.056180 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 225162.570006 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 225162.570006 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 224874.053890 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 224874.053890 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 315648 # number of replacements -system.cpu1.icache.tags.tagsinuse 445.931523 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 12842415 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 316160 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 40.619987 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1961765828000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.931523 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.870960 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.870960 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 313887 # number of replacements +system.cpu1.icache.tags.tagsinuse 445.952187 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 12790016 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 314399 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 40.680842 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1961762459500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.952187 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.871000 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.871000 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 13474819 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 13474819 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 12842415 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 12842415 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 12842415 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 12842415 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 12842415 # number of overall hits -system.cpu1.icache.overall_hits::total 12842415 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 316202 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 316202 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 316202 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 316202 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 316202 # number of overall misses -system.cpu1.icache.overall_misses::total 316202 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4145253739 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4145253739 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4145253739 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4145253739 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4145253739 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4145253739 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13158617 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13158617 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13158617 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13158617 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13158617 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13158617 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024030 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024030 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024030 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024030 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024030 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024030 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13109.511448 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13109.511448 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13109.511448 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13109.511448 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13109.511448 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13109.511448 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 13418898 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 13418898 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 12790016 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 12790016 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 12790016 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 12790016 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 12790016 # number of overall hits +system.cpu1.icache.overall_hits::total 12790016 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 314441 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 314441 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 314441 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 314441 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 314441 # number of overall misses +system.cpu1.icache.overall_misses::total 314441 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4125234500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4125234500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4125234500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4125234500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4125234500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4125234500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 13104457 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13104457 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 13104457 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 13104457 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 13104457 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 13104457 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023995 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.023995 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023995 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.023995 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023995 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.023995 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13119.264027 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13119.264027 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13119.264027 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13119.264027 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13119.264027 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13119.264027 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1133,30 +1124,30 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 316202 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 316202 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 316202 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 316202 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 316202 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 316202 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3670775261 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3670775261 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3670775261 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3670775261 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3670775261 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3670775261 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024030 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024030 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024030 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024030 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024030 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024030 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11608.956493 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11608.956493 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11608.956493 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11608.956493 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11608.956493 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11608.956493 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 314441 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 314441 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 314441 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 314441 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 314441 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 314441 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3810793500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3810793500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3810793500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3810793500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3810793500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3810793500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023995 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023995 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023995 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.023995 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023995 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.023995 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12119.264027 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12119.264027 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12119.264027 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12119.264027 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12119.264027 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12119.264027 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1172,10 +1163,9 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 7373 # Transaction distribution system.iobus.trans_dist::ReadResp 7373 # Transaction distribution -system.iobus.trans_dist::WriteReq 55604 # Transaction distribution -system.iobus.trans_dist::WriteResp 14052 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13892 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 55595 # Transaction distribution +system.iobus.trans_dist::WriteResp 55595 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13874 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -1187,11 +1177,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 42502 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 42484 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 125954 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 125936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55496 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1203,11 +1193,11 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 81834 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 81762 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2743450 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 13247000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2743378 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 13229000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1229,23 +1219,23 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 242106937 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 216079499 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28450000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 28441000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42027500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41948000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41694 # number of replacements -system.iocache.tags.tagsinuse 0.567924 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.567878 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1756483552000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.567924 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035495 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035495 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1756483227000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.567878 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035492 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035492 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1253,49 +1243,49 @@ system.iocache.tags.tag_accesses 375534 # Nu system.iocache.tags.data_accesses 375534 # Number of data accesses system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses system.iocache.ReadReq_misses::total 174 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses system.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses system.iocache.demand_misses::total 174 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 174 # number of overall misses system.iocache.overall_misses::total 174 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21822883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21822883 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8775454554 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 8775454554 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21822883 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21822883 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21822883 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21822883 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21744883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21744883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4908047616 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4908047616 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21744883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21744883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21744883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21744883 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses system.iocache.demand_accesses::total 174 # number of demand (read+write) accesses system.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses system.iocache.overall_accesses::total 174 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125418.867816 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125418.867816 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211192.109983 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 211192.109983 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 125418.867816 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125418.867816 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 125418.867816 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125418.867816 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 72753 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 124970.591954 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124970.591954 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118118.204082 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118118.204082 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 124970.591954 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124970.591954 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 124970.591954 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124970.591954 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 9972 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.295728 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1303,211 +1293,217 @@ system.iocache.writebacks::writebacks 41520 # nu system.iocache.writebacks::total 41520 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::tsunami.ide 174 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 174 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 174 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12615883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12615883 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6614750554 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6614750554 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12615883 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12615883 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12615883 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12615883 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13044883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13044883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2830447616 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2830447616 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 13044883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 13044883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 13044883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 13044883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72505.074713 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72505.074713 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159192.109983 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159192.109983 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72505.074713 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72505.074713 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72505.074713 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72505.074713 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 74970.591954 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 74970.591954 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68118.204082 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68118.204082 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 74970.591954 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 74970.591954 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 74970.591954 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 74970.591954 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 341367 # number of replacements -system.l2c.tags.tagsinuse 65207.739779 # Cycle average of tags in use -system.l2c.tags.total_refs 2440642 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 406370 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.005960 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 9165125750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55183.814884 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4854.166492 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5017.337774 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 113.675354 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 38.745274 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.842038 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.074069 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.076558 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.001735 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000591 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.994991 # Average percentage of cache occupancy +system.l2c.tags.replacements 341250 # number of replacements +system.l2c.tags.tagsinuse 65213.641245 # Cycle average of tags in use +system.l2c.tags.total_refs 3683713 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 406253 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 9.067534 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 9107201000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 55129.108381 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4852.505635 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5029.950253 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 158.753057 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 43.323918 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.841203 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.074043 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.076751 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.002422 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000661 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.995081 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65003 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 185 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 1104 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5014 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6093 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52607 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 1120 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 4999 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6097 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52602 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.991867 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 25960355 # Number of tag accesses -system.l2c.tags.data_accesses 25960355 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 686297 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 664438 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 315744 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 108706 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1775185 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 793248 # number of Writeback hits -system.l2c.Writeback_hits::total 793248 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 183 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 524 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 707 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 36 # number of SCUpgradeReq hits +system.l2c.tags.tag_accesses 35905885 # Number of tag accesses +system.l2c.tags.data_accesses 35905885 # Number of data accesses +system.l2c.Writeback_hits::writebacks 793586 # number of Writeback hits +system.l2c.Writeback_hits::total 793586 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 173 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 535 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 708 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 43 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 60 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 126541 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 47234 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 173775 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 686297 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 790979 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 315744 # 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number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 24600806000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 35012500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 488871500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 26033004000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1403353000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17974000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1421327000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2195335000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 686710000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2882045000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3598688000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 704684000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4303372000 # number of overall MSHR uncacheable cycles +system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.944337 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.764109 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.868304 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.953514 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.973828 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.963626 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.476737 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.122956 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.412685 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.018543 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.001571 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013288 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.289979 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.002168 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260015 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018543 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.328369 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001571 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.042012 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.172885 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018543 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.328369 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001571 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.042012 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.172885 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20637.989779 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20700.230814 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20661.096829 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20657.029478 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20520.156775 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20588.169014 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66275.263541 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71685.564663 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 66567.108818 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 69875.682745 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70875.506073 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 69912.287853 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 62378.890574 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 70368.644068 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 62385.826583 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69875.682745 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 63541.703688 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70875.506073 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71640.020516 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 63888.278357 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69875.682745 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 63541.703688 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70875.506073 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71640.020516 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 63888.278357 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197377.355837 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 201955.056180 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197433.949160 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 202727.398652 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 213662.103298 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 205230.007833 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 200606.945761 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 213346.654556 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 202587.891912 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 292759 # Transaction distribution -system.membus.trans_dist::ReadResp 292759 # Transaction distribution -system.membus.trans_dist::WriteReq 14052 # Transaction distribution -system.membus.trans_dist::WriteResp 14052 # Transaction distribution -system.membus.trans_dist::Writeback 120350 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16060 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11220 # Transaction distribution -system.membus.trans_dist::UpgradeResp 6977 # Transaction distribution -system.membus.trans_dist::ReadExReq 122543 # Transaction distribution -system.membus.trans_dist::ReadExResp 121713 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42502 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 927849 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 970351 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124813 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124813 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1095164 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 81834 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31082624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31164458 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36482026 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 21558 # Total snoops (count) -system.membus.snoop_fanout::samples 618592 # Request fanout histogram +system.membus.trans_dist::ReadReq 7199 # Transaction distribution +system.membus.trans_dist::ReadResp 292720 # Transaction distribution +system.membus.trans_dist::WriteReq 14043 # Transaction distribution +system.membus.trans_dist::WriteResp 14043 # Transaction distribution +system.membus.trans_dist::Writeback 120393 # Transaction distribution +system.membus.trans_dist::CleanEvict 261901 # Transaction distribution +system.membus.trans_dist::UpgradeReq 15996 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 11145 # Transaction distribution +system.membus.trans_dist::UpgradeResp 6943 # Transaction distribution +system.membus.trans_dist::ReadExReq 122456 # Transaction distribution +system.membus.trans_dist::ReadExResp 121630 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 285521 # Transaction distribution +system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42484 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1189359 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1231843 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124826 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124826 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1356669 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 81762 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31077568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31159330 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33817570 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 21449 # Total snoops (count) +system.membus.snoop_fanout::samples 880387 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 618592 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 880387 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 618592 # Request fanout histogram -system.membus.reqLayer0.occupancy 40208000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 880387 # Request fanout histogram +system.membus.reqLayer0.occupancy 40402000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1232118814 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1321574195 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2189522277 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2188968059 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 42501500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 72063409 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 2102341 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2102326 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14052 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14052 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 793248 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 41590 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 16264 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11280 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 27544 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 297931 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 297931 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1398755 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3106837 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 632403 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 482171 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5620166 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44759488 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118936680 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20236864 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17747522 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 201680554 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 98552 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3276706 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.012746 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.112175 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 7199 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2102214 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 14043 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 14043 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 913999 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1505100 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 16204 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11212 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 27416 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 297872 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 297872 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1015472 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1079558 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1960114 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3569990 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 818944 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 514014 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6863062 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44864640 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119041472 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20124160 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17694178 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 201724450 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 480853 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 5227539 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.081241 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.273205 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 3234942 98.73% 98.73% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 41764 1.27% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 4802849 91.88% 91.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 424690 8.12% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3276706 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2417745499 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoop_fanout::total 5227539 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3202032998 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 238500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1051604997 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1051547997 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1901998326 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1814279465 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 474390739 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 471668486 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 282399146 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 279553995 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 8fa2e66de..5922aa080 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.922414 # Number of seconds simulated -sim_ticks 1922413663500 # Number of ticks simulated -final_tick 1922413663500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.922397 # Number of seconds simulated +sim_ticks 1922397182500 # Number of ticks simulated +final_tick 1922397182500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 912210 # Simulator instruction rate (inst/s) -host_op_rate 912209 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 31217732593 # Simulator tick rate (ticks/s) -host_mem_usage 318584 # Number of bytes of host memory used -host_seconds 61.58 # Real time elapsed on the host -sim_insts 56174594 # Number of instructions simulated -sim_ops 56174594 # Number of ops (including micro ops) simulated +host_inst_rate 1085217 # Simulator instruction rate (inst/s) +host_op_rate 1085217 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 37124537063 # Simulator tick rate (ticks/s) +host_mem_usage 372212 # Number of bytes of host memory used +host_seconds 51.78 # Real time elapsed on the host +sim_insts 56195121 # Number of instructions simulated +sim_ops 56195121 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 850624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24859584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 848768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24858048 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25711168 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 850624 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 850624 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7404352 # Number of bytes written to this memory -system.physmem.bytes_written::total 7404352 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13291 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388431 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25707776 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 848768 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 848768 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7409088 # Number of bytes written to this memory +system.physmem.bytes_written::total 7409088 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13262 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388407 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 401737 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115693 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115693 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 442477 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12931444 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 401684 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115767 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115767 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 441515 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12930756 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 499 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13374420 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 442477 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 442477 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3851591 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3851591 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3851591 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 442477 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12931444 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13372770 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 441515 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 441515 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3854088 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3854088 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3854088 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 441515 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12930756 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17226012 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 401737 # Number of read requests accepted -system.physmem.writeReqs 157245 # Number of write requests accepted -system.physmem.readBursts 401737 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 157245 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25705152 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6016 # Total number of bytes read from write queue -system.physmem.bytesWritten 8387264 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25711168 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10063680 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 94 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 26167 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 130 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25230 # Per bank write bursts -system.physmem.perBankRdBursts::1 25660 # Per bank write bursts -system.physmem.perBankRdBursts::2 25603 # Per bank write bursts -system.physmem.perBankRdBursts::3 25523 # Per bank write bursts -system.physmem.perBankRdBursts::4 24970 # Per bank write bursts -system.physmem.perBankRdBursts::5 24976 # Per bank write bursts +system.physmem.bw_total::total 17226858 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 401684 # Number of read requests accepted +system.physmem.writeReqs 115767 # Number of write requests accepted +system.physmem.readBursts 401684 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115767 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25700352 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7424 # Total number of bytes read from write queue +system.physmem.bytesWritten 7407168 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25707776 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7409088 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 116 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 41682 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25233 # Per bank write bursts +system.physmem.perBankRdBursts::1 25641 # Per bank write bursts +system.physmem.perBankRdBursts::2 25574 # Per bank write bursts +system.physmem.perBankRdBursts::3 25503 # Per bank write bursts +system.physmem.perBankRdBursts::4 24973 # Per bank write bursts +system.physmem.perBankRdBursts::5 24969 # Per bank write bursts system.physmem.perBankRdBursts::6 24206 # Per bank write bursts -system.physmem.perBankRdBursts::7 24492 # Per bank write bursts -system.physmem.perBankRdBursts::8 25173 # Per bank write bursts -system.physmem.perBankRdBursts::9 24777 # Per bank write bursts -system.physmem.perBankRdBursts::10 25267 # Per bank write bursts -system.physmem.perBankRdBursts::11 24875 # Per bank write bursts -system.physmem.perBankRdBursts::12 24505 # Per bank write bursts -system.physmem.perBankRdBursts::13 25378 # Per bank write bursts -system.physmem.perBankRdBursts::14 25651 # Per bank write bursts -system.physmem.perBankRdBursts::15 25357 # Per bank write bursts -system.physmem.perBankWrBursts::0 8677 # Per bank write bursts -system.physmem.perBankWrBursts::1 8490 # Per bank write bursts -system.physmem.perBankWrBursts::2 8972 # Per bank write bursts -system.physmem.perBankWrBursts::3 8549 # Per bank write bursts -system.physmem.perBankWrBursts::4 8030 # Per bank write bursts -system.physmem.perBankWrBursts::5 7962 # Per bank write bursts -system.physmem.perBankWrBursts::6 7256 # Per bank write bursts -system.physmem.perBankWrBursts::7 7133 # Per bank write bursts -system.physmem.perBankWrBursts::8 8241 # Per bank write bursts -system.physmem.perBankWrBursts::9 7447 # Per bank write bursts -system.physmem.perBankWrBursts::10 7887 # Per bank write bursts -system.physmem.perBankWrBursts::11 7738 # Per bank write bursts -system.physmem.perBankWrBursts::12 8187 # Per bank write bursts -system.physmem.perBankWrBursts::13 8962 # Per bank write bursts -system.physmem.perBankWrBursts::14 8876 # Per bank write bursts -system.physmem.perBankWrBursts::15 8644 # Per bank write bursts +system.physmem.perBankRdBursts::7 24501 # Per bank write bursts +system.physmem.perBankRdBursts::8 25169 # Per bank write bursts +system.physmem.perBankRdBursts::9 24770 # Per bank write bursts +system.physmem.perBankRdBursts::10 25259 # Per bank write bursts +system.physmem.perBankRdBursts::11 24898 # Per bank write bursts +system.physmem.perBankRdBursts::12 24500 # Per bank write bursts +system.physmem.perBankRdBursts::13 25360 # Per bank write bursts +system.physmem.perBankRdBursts::14 25653 # Per bank write bursts +system.physmem.perBankRdBursts::15 25359 # Per bank write bursts +system.physmem.perBankWrBursts::0 7624 # Per bank write bursts +system.physmem.perBankWrBursts::1 7642 # Per bank write bursts +system.physmem.perBankWrBursts::2 7864 # Per bank write bursts +system.physmem.perBankWrBursts::3 7542 # Per bank write bursts +system.physmem.perBankWrBursts::4 7123 # Per bank write bursts +system.physmem.perBankWrBursts::5 6988 # Per bank write bursts +system.physmem.perBankWrBursts::6 6319 # Per bank write bursts +system.physmem.perBankWrBursts::7 6328 # Per bank write bursts +system.physmem.perBankWrBursts::8 7314 # Per bank write bursts +system.physmem.perBankWrBursts::9 6525 # Per bank write bursts +system.physmem.perBankWrBursts::10 7109 # Per bank write bursts +system.physmem.perBankWrBursts::11 6927 # Per bank write bursts +system.physmem.perBankWrBursts::12 7069 # Per bank write bursts +system.physmem.perBankWrBursts::13 7821 # Per bank write bursts +system.physmem.perBankWrBursts::14 7867 # Per bank write bursts +system.physmem.perBankWrBursts::15 7675 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 46 # Number of times write queue was full causing retry -system.physmem.totGap 1922401791500 # Total gap between requests +system.physmem.numWrRetry 15 # Number of times write queue was full causing retry +system.physmem.totGap 1922385313500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 401737 # Read request sizes (log2) +system.physmem.readPktSize::6 401684 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 157245 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 401629 # What read queue length does an incoming req see +system.physmem.writePktSize::6 115767 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 401554 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see @@ -148,189 +148,195 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6420 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5573 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1604 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1549 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1877 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 2468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 2834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1812 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 50 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64754 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 526.491275 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 319.634857 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 416.364161 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14682 22.67% 22.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11626 17.95% 40.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5040 7.78% 48.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3263 5.04% 53.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2595 4.01% 57.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1540 2.38% 59.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1251 1.93% 61.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1707 2.64% 64.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 23050 35.60% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64754 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4707 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 85.326110 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 3076.141166 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 4704 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5951 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7083 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5376 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 39 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64336 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 514.603333 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 307.690032 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 416.700723 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15764 24.50% 24.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11265 17.51% 42.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5118 7.96% 49.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3016 4.69% 54.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2317 3.60% 58.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1789 2.78% 61.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1464 2.28% 63.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1374 2.14% 65.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22229 34.55% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64336 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5099 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 78.750735 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2955.508201 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5096 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4707 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4707 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.841725 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.684188 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 62.214453 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 4459 94.73% 94.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 47 1.00% 95.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 10 0.21% 95.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 2 0.04% 95.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 12 0.25% 96.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 3 0.06% 96.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 7 0.15% 96.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 17 0.36% 96.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 21 0.45% 97.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 12 0.25% 97.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 17 0.36% 97.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 2 0.04% 97.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 5 0.11% 98.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 3 0.06% 98.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 1 0.02% 98.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 2 0.04% 98.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 4 0.08% 98.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 11 0.23% 98.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 21 0.45% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 6 0.13% 99.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 6 0.13% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 6 0.13% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::448-463 1 0.02% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::464-479 8 0.17% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 2 0.04% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 2 0.04% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 5 0.11% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 2 0.04% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 3 0.06% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 1 0.02% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::640-655 1 0.02% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::672-687 3 0.06% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::688-703 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::720-735 2 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::800-815 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::832-847 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4707 # Writes before turning the bus around for reads -system.physmem.totQLat 2057087750 # Total ticks spent queuing -system.physmem.totMemAccLat 9587894000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2008215000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5121.68 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5099 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5099 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.697980 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.062005 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 23.025558 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4477 87.80% 87.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 19 0.37% 88.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 190 3.73% 91.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 14 0.27% 92.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 27 0.53% 92.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 53 1.04% 93.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 14 0.27% 94.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 3 0.06% 94.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 6 0.12% 94.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 3 0.06% 94.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 3 0.06% 94.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 3 0.06% 94.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 8 0.16% 94.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 3 0.06% 94.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 2 0.04% 94.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 10 0.20% 94.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 4 0.08% 94.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 16 0.31% 95.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 21 0.41% 95.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 18 0.35% 95.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 148 2.90% 98.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 12 0.24% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.02% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.02% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 3 0.06% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.02% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.04% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 5 0.10% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 2 0.04% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 4 0.08% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.02% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 4 0.08% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 5 0.10% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.02% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 3 0.06% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 2 0.04% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 1 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 5 0.10% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5099 # Writes before turning the bus around for reads +system.physmem.totQLat 2147063750 # Total ticks spent queuing +system.physmem.totMemAccLat 9676463750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2007840000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5346.70 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23871.68 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 24096.70 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.37 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.36 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 3.85 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.37 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 5.23 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.85 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.14 # Data bus utilization in percentage +system.physmem.busUtil 0.13 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.61 # Average write queue length when enqueuing -system.physmem.readRowHits 360176 # Number of row buffer hits during reads -system.physmem.writeRowHits 107764 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 82.21 # Row buffer hit rate for writes -system.physmem.avgGap 3439112.16 # Average gap between requests -system.physmem.pageHitRate 87.84 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 240309720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 131121375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1565148000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 421647120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 125562446880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 64744742475 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1096652245500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1289317661070 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.677845 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1824141880650 # Time in different power states -system.physmem_0.memoryStateTime::REF 64193480000 # Time in different power states +system.physmem.avgWrQLen 23.55 # Average write queue length when enqueuing +system.physmem.readRowHits 359411 # Number of row buffer hits during reads +system.physmem.writeRowHits 93558 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.50 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.82 # Row buffer hit rate for writes +system.physmem.avgGap 3715106.00 # Average gap between requests +system.physmem.pageHitRate 87.56 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 236030760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 128786625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1564680000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 372146400 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 125561429760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 64059295815 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1097244171000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1289166540360 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.604667 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1825128497250 # Time in different power states +system.physmem_0.memoryStateTime::REF 64192960000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 34074451850 # Time in different power states +system.physmem_0.memoryStateTime::ACT 33072782750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 249230520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 135988875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1567667400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 427563360 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 125562446880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 65411599725 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1096067283000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1289421779760 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.732006 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1823167298902 # Time in different power states -system.physmem_1.memoryStateTime::REF 64193480000 # Time in different power states +system.physmem_1.actEnergy 250349400 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 136599375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1567550400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 377829360 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 125561429760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 65774789190 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1095739352250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1289407899735 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.730219 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1822618194250 # Time in different power states +system.physmem_1.memoryStateTime::REF 64192960000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 35049033598 # Time in different power states +system.physmem_1.memoryStateTime::ACT 35583085750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9063642 # DTB read hits -system.cpu.dtb.read_misses 10324 # DTB read misses +system.cpu.dtb.read_hits 9066440 # DTB read hits +system.cpu.dtb.read_misses 10312 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728853 # DTB read accesses -system.cpu.dtb.write_hits 6355525 # DTB write hits -system.cpu.dtb.write_misses 1142 # DTB write misses +system.cpu.dtb.read_accesses 728817 # DTB read accesses +system.cpu.dtb.write_hits 6357400 # DTB write hits +system.cpu.dtb.write_misses 1140 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 15419167 # DTB hits -system.cpu.dtb.data_misses 11466 # DTB misses +system.cpu.dtb.write_accesses 291929 # DTB write accesses +system.cpu.dtb.data_hits 15423840 # DTB hits +system.cpu.dtb.data_misses 11452 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020784 # DTB accesses -system.cpu.itb.fetch_hits 4974414 # ITB hits -system.cpu.itb.fetch_misses 5010 # ITB misses +system.cpu.dtb.data_accesses 1020746 # DTB accesses +system.cpu.itb.fetch_hits 4973902 # ITB hits +system.cpu.itb.fetch_misses 4997 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979424 # ITB accesses +system.cpu.itb.fetch_accesses 4978899 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -343,34 +349,34 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3844827327 # number of cpu cycles simulated +system.cpu.numCycles 3844794365 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56174594 # Number of instructions committed -system.cpu.committedOps 56174594 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52047018 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses -system.cpu.num_func_calls 1483106 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6467546 # number of instructions that are conditional controls -system.cpu.num_int_insts 52047018 # number of integer instructions -system.cpu.num_fp_insts 324460 # number of float instructions -system.cpu.num_int_register_reads 71310653 # number of times the integer registers were read -system.cpu.num_int_register_writes 38515122 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written -system.cpu.num_mem_refs 15471782 # number of memory refs -system.cpu.num_load_insts 9100493 # Number of load instructions -system.cpu.num_store_insts 6371289 # Number of store instructions -system.cpu.num_idle_cycles 3587399919.998134 # Number of idle cycles -system.cpu.num_busy_cycles 257427407.001866 # Number of busy cycles -system.cpu.not_idle_fraction 0.066954 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.933046 # Percentage of idle cycles -system.cpu.Branches 8421188 # Number of branches fetched -system.cpu.op_class::No_OpClass 3200330 5.70% 5.70% # Class of executed instruction -system.cpu.op_class::IntAlu 36225212 64.47% 70.17% # Class of executed instruction -system.cpu.op_class::IntMult 61016 0.11% 70.28% # Class of executed instruction +system.cpu.committedInsts 56195121 # Number of instructions committed +system.cpu.committedOps 56195121 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52066883 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324259 # Number of float alu accesses +system.cpu.num_func_calls 1483708 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6469750 # number of instructions that are conditional controls +system.cpu.num_int_insts 52066883 # number of integer instructions +system.cpu.num_fp_insts 324259 # number of float instructions +system.cpu.num_int_register_reads 71341331 # number of times the integer registers were read +system.cpu.num_int_register_writes 38530727 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163543 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166418 # number of times the floating registers were written +system.cpu.num_mem_refs 15476411 # number of memory refs +system.cpu.num_load_insts 9103258 # Number of load instructions +system.cpu.num_store_insts 6373153 # Number of store instructions +system.cpu.num_idle_cycles 3587818415.000134 # Number of idle cycles +system.cpu.num_busy_cycles 256975949.999866 # Number of busy cycles +system.cpu.not_idle_fraction 0.066837 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.933163 # Percentage of idle cycles +system.cpu.Branches 8423975 # Number of branches fetched +system.cpu.op_class::No_OpClass 3201032 5.70% 5.70% # Class of executed instruction +system.cpu.op_class::IntAlu 36240615 64.48% 70.17% # Class of executed instruction +system.cpu.op_class::IntMult 61007 0.11% 70.28% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 70.28% # Class of executed instruction -system.cpu.op_class::FloatAdd 38087 0.07% 70.35% # Class of executed instruction +system.cpu.op_class::FloatAdd 38081 0.07% 70.35% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 70.35% # Class of executed instruction @@ -396,34 +402,34 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 70.35% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::MemRead 9327578 16.60% 86.95% # Class of executed instruction -system.cpu.op_class::MemWrite 6377363 11.35% 98.30% # Class of executed instruction -system.cpu.op_class::IprAccess 953205 1.70% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 9330336 16.60% 86.95% # Class of executed instruction +system.cpu.op_class::MemWrite 6379227 11.35% 98.30% # Class of executed instruction +system.cpu.op_class::IprAccess 953006 1.70% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 56186427 # Class of executed instruction +system.cpu.op_class::total 56206940 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211986 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74892 40.89% 40.89% # number of times we switched to this ipl +system.cpu.kern.inst.hwrei 211964 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74896 40.89% 40.89% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106213 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183168 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73525 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 106217 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183176 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73529 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73525 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149113 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1857939859000 96.65% 96.65% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 91692000 0.00% 96.65% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 740049500 0.04% 96.69% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 63641329000 3.31% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1922412929500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981747 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73529 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149121 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1858096797000 96.66% 96.66% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 92317000 0.00% 96.66% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 743733500 0.04% 96.70% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 63463601000 3.30% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1922396448500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692241 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814078 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692253 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814086 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -459,10 +465,10 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4177 2.17% 2.17% # number of callpals executed -system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed +system.cpu.kern.callpal::swpctx 4174 2.16% 2.17% # number of callpals executed +system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175947 91.21% 93.41% # number of callpals executed +system.cpu.kern.callpal::swpipl 175955 91.22% 93.41% # number of callpals executed system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed @@ -471,28 +477,28 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192894 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5905 # number of protection mode switches -system.cpu.kern.mode_switch::user 1740 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches +system.cpu.kern.callpal::total 192899 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5904 # number of protection mode switches +system.cpu.kern.mode_switch::user 1741 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2093 # number of protection mode switches system.cpu.kern.mode_good::kernel 1910 -system.cpu.kern.mode_good::user 1740 -system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.323455 # fraction of useful protection mode switches +system.cpu.kern.mode_good::user 1741 +system.cpu.kern.mode_good::idle 169 +system.cpu.kern.mode_switch_good::kernel 0.323509 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392197 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46428613000 2.42% 2.42% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5237727500 0.27% 2.69% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1870746587000 97.31% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4178 # number of times the context was actually changed -system.cpu.dcache.tags.replacements 1391374 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.978196 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14046325 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1391886 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 10.091577 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 112435250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.978196 # Average occupied blocks per requestor +system.cpu.kern.mode_switch_good::idle 0.080745 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392278 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 46413360000 2.41% 2.41% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5233781000 0.27% 2.69% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1870749305500 97.31% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4175 # number of times the context was actually changed +system.cpu.dcache.tags.replacements 1390740 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.978175 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 14051600 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1391252 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.099968 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 112405500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.978175 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999957 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999957 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -500,72 +506,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63144735 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63144735 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7812525 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7812525 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5851580 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5851580 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 182969 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 182969 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199234 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199234 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13664105 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13664105 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13664105 # number of overall hits -system.cpu.dcache.overall_hits::total 13664105 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1070248 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1070248 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304369 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304369 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17287 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17287 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1374617 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1374617 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1374617 # number of overall misses -system.cpu.dcache.overall_misses::total 1374617 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 30897353500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 30897353500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11699394130 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11699394130 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 229714500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 229714500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 42596747630 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 42596747630 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 42596747630 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 42596747630 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 8882773 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 8882773 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6155949 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6155949 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200256 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200256 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199234 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199234 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15038722 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15038722 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15038722 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15038722 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120486 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120486 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049443 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049443 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086325 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086325 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091405 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091405 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091405 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091405 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28869.340097 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28869.340097 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38438.192227 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38438.192227 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13288.280211 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13288.280211 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30988.084412 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30988.084412 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30988.084412 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30988.084412 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63162665 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63162665 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7816092 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7816092 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5853262 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5853262 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183004 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183004 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199225 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199225 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13669354 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13669354 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13669354 # number of overall hits +system.cpu.dcache.overall_hits::total 13669354 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1069466 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1069466 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304560 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304560 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17244 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17244 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1374026 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1374026 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1374026 # number of overall misses +system.cpu.dcache.overall_misses::total 1374026 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 30729736500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 30729736500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11677039000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11677039000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228891000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 228891000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 42406775500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 42406775500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 42406775500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 42406775500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8885558 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8885558 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6157822 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6157822 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200248 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200248 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199225 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199225 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15043380 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15043380 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15043380 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15043380 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120360 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120360 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049459 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049459 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086113 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086113 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091338 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091338 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091338 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091338 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28733.719913 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28733.719913 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38340.684923 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38340.684923 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13273.660404 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13273.660404 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30863.153608 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30863.153608 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30863.153608 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30863.153608 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -574,120 +580,120 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # 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number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2025445000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3458204000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3458204000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120486 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120486 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049443 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049443 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086325 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086325 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091405 # 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average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29358.166580 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29358.166580 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29358.166580 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 206747.330447 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 206747.330447 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 209890.673575 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 209890.673575 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 208576.839566 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 208576.839566 # average overall mshr uncacheable latency +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29660270500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 29660270500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11372479000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11372479000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 211647000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 211647000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41032749500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 41032749500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41032749500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 41032749500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1450110500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1450110500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2049565500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2049565500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3499676000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3499676000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120360 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120360 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049459 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049459 # 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Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 57115304 # Number of tag accesses -system.cpu.icache.tags.data_accesses 57115304 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 55257552 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55257552 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55257552 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55257552 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55257552 # number of overall hits -system.cpu.icache.overall_hits::total 55257552 # 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average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 72386.053446 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80123.812396 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73640.401032 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73854.257708 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80123.812396 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73640.401032 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73854.257708 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -833,114 +845,125 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # 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number of ReadReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9650 # number of WriteReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9650 # number of WriteReq MSHR uncacheable system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16580 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16580 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 897481500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16318511000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17215992500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 327511 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 327511 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7455368119 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7455368119 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 897481500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23773879119 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 24671360619 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 897481500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23773879119 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 24671360619 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1335739000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1335739000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1899995000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1899995000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3235734000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3235734000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014309 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250074 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141468 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 364500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 364500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7775812500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7775812500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 929982000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 929982000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16967384500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16967384500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 929982000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 24743197000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 25673179000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 929982000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 24743197000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25673179000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1363485500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1363485500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1938590500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1938590500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3302076000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3302076000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383953 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383953 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014309 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279348 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173269 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014309 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279348 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173269 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67525.505981 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60002.467238 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60352.991183 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 25193.153846 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25193.153846 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63799.071677 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63799.071677 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67525.505981 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61143.505929 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61354.450051 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67525.505981 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61143.505929 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61354.450051 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 192747.330447 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 192747.330447 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 196890.673575 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 196890.673575 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 195158.866104 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 195158.866104 # average overall mshr uncacheable latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383601 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383601 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014276 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014276 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250273 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250273 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014276 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279458 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.173286 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014276 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279458 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.173286 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 28038.461538 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 28038.461538 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66560.630184 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66560.630184 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70123.812396 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70123.812396 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62386.053446 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62386.053446 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70123.812396 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63640.401032 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63854.257708 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70123.812396 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63640.401032 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63854.257708 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196751.154401 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196751.154401 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200890.207254 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200890.207254 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199160.193004 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199160.193004 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2023514 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2023497 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2022774 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 835634 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41588 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 951075 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1744381 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304352 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304352 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1857732 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3652758 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5510490 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59446784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142615892 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 202062676 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 41937 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3214755 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.012990 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.113233 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 304543 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304543 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 928977 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1086883 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2786015 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4205333 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6991348 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59453248 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142553556 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 202006804 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 419801 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5075497 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.082676 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.275393 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3172994 98.70% 98.70% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41761 1.30% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4655873 91.73% 91.73% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 419624 8.27% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3214755 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2426956000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 5075497 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3168054500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1395898500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1393465500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2188894130 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2098643000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -957,8 +980,7 @@ system.disk2.dma_write_txs 1 # Nu system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution system.iobus.trans_dist::WriteReq 51202 # Transaction distribution -system.iobus.trans_dist::WriteResp 9650 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.iobus.trans_dist::WriteResp 51202 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5156 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) @@ -1013,23 +1035,23 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 242042219 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 216066756 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42024000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.342966 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.342844 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1756462668000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.342966 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.083935 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.083935 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1756461860000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.342844 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.083928 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.083928 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1037,49 +1059,49 @@ system.iocache.tags.tag_accesses 375525 # Nu system.iocache.tags.data_accesses 375525 # Number of data accesses system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21714383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21714383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8755465836 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 8755465836 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21714383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21714383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21714383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21714383 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21632883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21632883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4907244873 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4907244873 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21632883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21632883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21632883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21632883 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125516.664740 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125516.664740 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 210711.056893 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 210711.056893 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125516.664740 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125516.664740 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 72960 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125045.566474 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125045.566474 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118098.885084 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118098.885084 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 125045.566474 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125045.566474 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 125045.566474 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125045.566474 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 9989 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.304034 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1087,79 +1109,81 @@ system.iocache.writebacks::writebacks 41512 # nu system.iocache.writebacks::total 41512 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12562383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12562383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6594761836 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6594761836 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12562383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12562383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12562383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12562383 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12982883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12982883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2829644873 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2829644873 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12982883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12982883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12982883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12982883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72614.930636 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 158711.056893 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 158711.056893 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75045.566474 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 75045.566474 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68098.885084 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68098.885084 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75045.566474 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75045.566474 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75045.566474 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 75045.566474 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 292358 # Transaction distribution -system.membus.trans_dist::ReadResp 292358 # Transaction distribution +system.membus.trans_dist::ReadReq 6930 # Transaction distribution +system.membus.trans_dist::ReadResp 292339 # Transaction distribution system.membus.trans_dist::WriteReq 9650 # Transaction distribution system.membus.trans_dist::WriteResp 9650 # Transaction distribution -system.membus.trans_dist::Writeback 115693 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.membus.trans_dist::Writeback 115767 # Transaction distribution +system.membus.trans_dist::CleanEvict 261512 # Transaction distribution system.membus.trans_dist::UpgradeReq 132 # Transaction distribution system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 116738 # Transaction distribution -system.membus.trans_dist::ReadExResp 116738 # Transaction distribution +system.membus.trans_dist::ReadExReq 116704 # Transaction distribution +system.membus.trans_dist::ReadExResp 116704 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 285409 # Transaction distribution +system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878158 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911318 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1036122 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139625 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172785 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1297602 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30457792 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30502356 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 35819412 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30459136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30503700 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33161428 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 431 # Total snoops (count) -system.membus.snoop_fanout::samples 576169 # Request fanout histogram +system.membus.snoop_fanout::samples 837831 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 576169 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 837831 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 576169 # Request fanout histogram -system.membus.reqLayer0.occupancy 30034000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 837831 # Request fanout histogram +system.membus.reqLayer0.occupancy 30056000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1195840311 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1285352189 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2144408870 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2143948368 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 42495000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 72076390 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA |