diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha')
3 files changed, 990 insertions, 985 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 99e580564..007c56f0a 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -331,6 +331,7 @@ children=badaddr_responder block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 default=system.membus.badaddr_responder.pio @@ -356,25 +357,28 @@ pio=system.membus.default [system.physmem] type=SimpleDRAM +activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 zero=false @@ -403,6 +407,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=8 master=system.l2c.cpu_side diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout index aa1334176..117d6c541 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout @@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/t gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 13:29:14 -gem5 started Jan 23 2013 13:46:42 +gem5 compiled Mar 26 2013 14:38:52 +gem5 started Mar 26 2013 14:39:13 gem5 executing on ribera.cs.wisc.edu command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 608846000 -Exiting @ tick 1950813955500 because m5_exit instruction encountered +info: Launching CPU 1 @ 614109000 +Exiting @ tick 1955749107000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index af1133d44..02fd81ba8 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,132 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.954691 # Number of seconds simulated -sim_ticks 1954691371500 # Number of ticks simulated -final_tick 1954691371500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.955749 # Number of seconds simulated +sim_ticks 1955749107000 # Number of ticks simulated +final_tick 1955749107000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1268205 # Simulator instruction rate (inst/s) -host_op_rate 1268205 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41788272650 # Simulator tick rate (ticks/s) -host_mem_usage 331540 # Number of bytes of host memory used -host_seconds 46.78 # Real time elapsed on the host -sim_insts 59321614 # Number of instructions simulated -sim_ops 59321614 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 829376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24757440 # Number of bytes read from this memory +host_inst_rate 473674 # Simulator instruction rate (inst/s) +host_op_rate 473674 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15599111797 # Simulator tick rate (ticks/s) +host_mem_usage 350548 # Number of bytes of host memory used +host_seconds 125.38 # Real time elapsed on the host +sim_insts 59387196 # Number of instructions simulated +sim_ops 59387196 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 829760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24747584 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 34176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 389696 # Number of bytes read from this memory -system.physmem.bytes_read::total 28661504 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 829376 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 34176 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 863552 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7676992 # Number of bytes written to this memory -system.physmem.bytes_written::total 7676992 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12959 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 386835 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 34368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 397760 # Number of bytes read from this memory +system.physmem.bytes_read::total 28660288 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 829760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 34368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 864128 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7682240 # Number of bytes written to this memory +system.physmem.bytes_written::total 7682240 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12965 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 386681 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 534 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6089 # Number of read requests responded to by this memory -system.physmem.num_reads::total 447836 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 119953 # Number of write requests responded to by this memory -system.physmem.num_writes::total 119953 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 424300 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12665652 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1356130 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 17484 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 199364 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14662931 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 424300 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 17484 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 441784 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3927470 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3927470 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3927470 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 424300 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12665652 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1356130 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 17484 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 199364 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18590401 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 447836 # Total number of read requests seen -system.physmem.writeReqs 119953 # Total number of write requests seen -system.physmem.cpureqs 570963 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28661504 # Total number of bytes read from memory -system.physmem.bytesWritten 7676992 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28661504 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7676992 # bytesWritten derated as per pkt->getSize() +system.physmem.num_reads::cpu1.inst 537 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6215 # Number of read requests responded to by this memory +system.physmem.num_reads::total 447817 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120035 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120035 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 424267 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12653762 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1355397 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 17573 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 203380 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14654379 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 424267 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 17573 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 441840 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3928029 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3928029 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3928029 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 424267 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12653762 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1355397 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 17573 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 203380 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18582408 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 447817 # Total number of read requests seen +system.physmem.writeReqs 120035 # Total number of write requests seen +system.physmem.cpureqs 571031 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28660288 # Total number of bytes read from memory +system.physmem.bytesWritten 7682240 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28660288 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7682240 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 69 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 3162 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28180 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 28120 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28097 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27826 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 27944 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 27900 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27858 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27869 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28342 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28141 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28250 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 28016 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27813 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 27987 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27674 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27750 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7637 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7504 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7585 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7374 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7488 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7379 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7353 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7437 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7887 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7685 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7821 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7507 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7382 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7492 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7142 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7280 # Track writes on a per bank basis +system.physmem.neitherReadNorWrite 3170 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28165 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 28096 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28057 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27780 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 28035 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 27969 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27895 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27905 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28286 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 28089 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28219 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 28029 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27787 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 27999 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27702 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27735 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7631 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7483 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7551 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7343 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7579 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7442 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7393 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7470 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7849 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7658 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7804 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7534 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7353 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7502 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7171 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7272 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 12 # Number of times wr buffer was full causing retry -system.physmem.totGap 1954684300500 # Total gap between requests +system.physmem.numWrRetry 9 # Number of times wr buffer was full causing retry +system.physmem.totGap 1955741979500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 447836 # Categorize read packet sizes +system.physmem.readPktSize::6 447817 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 119953 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 407019 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4805 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3654 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2220 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2947 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2702 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2702 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2646 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2596 # What read queue length does an incoming req see +system.physmem.writePktSize::6 120035 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 407051 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4718 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3658 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3124 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2939 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2694 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2706 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2651 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2603 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 1540 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1465 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1427 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1370 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1349 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1388 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1608 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1510 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 904 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 781 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1432 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1357 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1403 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1635 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1524 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 905 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 760 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -138,224 +138,224 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3708 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1508 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 944 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3855 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5219 # 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mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014149 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.290585 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.006144 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.115812 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.170351 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014149 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.290585 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.006144 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.115812 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.170351 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 49190.963886 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 30735.937160 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 51613.825843 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65764.211640 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 31636.559808 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10067.923864 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10056.876623 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_mshr_miss_latency::total 1010101 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4108313953 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 267375786 # 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number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 13399058734 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1372993500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 18178500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1391172000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1972884000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 501380500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2474264500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3345877500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 519559000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 3865436500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014148 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.260080 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.006176 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.005542 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.137051 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.935398 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.899814 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.929319 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.571429 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.776596 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.706294 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.401379 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.321868 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.396507 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014148 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.290602 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.006176 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.118264 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.170352 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014148 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.290602 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.006176 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.118264 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.170352 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 49743.922484 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 30703.788058 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 51726.780261 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63852.037234 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 31630.534136 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10069.653862 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10016.461856 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10060.855048 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 35536.680436 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 44509.775431 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 35973.592886 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 49190.963886 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32169.431745 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 51613.825843 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 45167.559686 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 32932.289205 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 49190.963886 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32169.431745 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 51613.825843 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 45167.559686 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 32932.289205 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 35575.361987 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 44230.899256 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 36005.906004 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 49743.922484 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32157.232950 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 51726.780261 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 44822.712819 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 32937.624868 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 49743.922484 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32157.232950 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 51726.780261 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 44822.712819 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 32937.624868 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -488,14 +488,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41694 # number of replacements -system.iocache.tagsinuse 0.572561 # Cycle average of tags in use +system.iocache.tagsinuse 0.572926 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41710 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1746701284000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.572561 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.035785 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.035785 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1747683301000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 0.572926 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.035808 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.035808 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses system.iocache.ReadReq_misses::total 174 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -506,12 +506,12 @@ system.iocache.overall_misses::tsunami.ide 41726 # system.iocache.overall_misses::total 41726 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21042998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21042998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10675582674 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10675582674 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10696625672 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10696625672 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10696625672 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10696625672 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10655791911 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10655791911 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10676834909 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10676834909 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10676834909 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10676834909 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -530,17 +530,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120936.770115 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 120936.770115 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256921.030853 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 256921.030853 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 256353.968077 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 256353.968077 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 256353.968077 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 256353.968077 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 286338 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256444.741793 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 256444.741793 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 255879.665173 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 255879.665173 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 255879.665173 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 255879.665173 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 285803 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27305 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27265 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.486651 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.482413 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -556,12 +556,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41726 system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11994249 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 11994249 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8513590923 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8513590923 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8525585172 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8525585172 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8525585172 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8525585172 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8493795674 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8493795674 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8505789923 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8505789923 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8505789923 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8505789923 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -572,12 +572,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68932.465517 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 68932.465517 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204890.039541 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 204890.039541 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 204323.088051 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 204323.088051 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 204323.088051 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 204323.088051 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204413.642520 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 204413.642520 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203848.677635 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 203848.677635 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203848.677635 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 203848.677635 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -595,22 +595,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8631552 # DTB read hits -system.cpu0.dtb.read_misses 7447 # DTB read misses +system.cpu0.dtb.read_hits 8641604 # DTB read hits +system.cpu0.dtb.read_misses 7443 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations -system.cpu0.dtb.read_accesses 490676 # DTB read accesses -system.cpu0.dtb.write_hits 6044616 # DTB write hits +system.cpu0.dtb.read_accesses 490673 # DTB read accesses +system.cpu0.dtb.write_hits 6049321 # DTB write hits system.cpu0.dtb.write_misses 813 # DTB write misses system.cpu0.dtb.write_acv 134 # DTB write access violations system.cpu0.dtb.write_accesses 187452 # DTB write accesses -system.cpu0.dtb.data_hits 14676168 # DTB hits -system.cpu0.dtb.data_misses 8260 # DTB misses +system.cpu0.dtb.data_hits 14690925 # DTB hits +system.cpu0.dtb.data_misses 8256 # DTB misses system.cpu0.dtb.data_acv 344 # DTB access violations -system.cpu0.dtb.data_accesses 678128 # DTB accesses -system.cpu0.itb.fetch_hits 3853435 # ITB hits +system.cpu0.dtb.data_accesses 678125 # DTB accesses +system.cpu0.itb.fetch_hits 3853653 # ITB hits system.cpu0.itb.fetch_misses 3871 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3857306 # ITB accesses +system.cpu0.itb.fetch_accesses 3857524 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -623,55 +623,55 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3908211536 # number of cpu cycles simulated +system.cpu0.numCycles 3910164768 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 54061829 # Number of instructions committed -system.cpu0.committedOps 54061829 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 50032862 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 294101 # Number of float alu accesses -system.cpu0.num_func_calls 1426501 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 6236445 # number of instructions that are conditional controls -system.cpu0.num_int_insts 50032862 # number of integer instructions -system.cpu0.num_fp_insts 294101 # number of float instructions -system.cpu0.num_int_register_reads 68513770 # number of times the integer registers were read -system.cpu0.num_int_register_writes 37070851 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 143419 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 146520 # number of times the floating registers were written -system.cpu0.num_mem_refs 14722187 # number of memory refs -system.cpu0.num_load_insts 8662865 # Number of load instructions -system.cpu0.num_store_insts 6059322 # Number of store instructions -system.cpu0.num_idle_cycles 3679287255.686766 # Number of idle cycles -system.cpu0.num_busy_cycles 228924280.313234 # Number of busy cycles -system.cpu0.not_idle_fraction 0.058575 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.941425 # Percentage of idle cycles +system.cpu0.committedInsts 54125350 # Number of instructions committed +system.cpu0.committedOps 54125350 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 50093853 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 294168 # Number of float alu accesses +system.cpu0.num_func_calls 1428171 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 6241814 # number of instructions that are conditional controls +system.cpu0.num_int_insts 50093853 # number of integer instructions +system.cpu0.num_fp_insts 294168 # number of float instructions +system.cpu0.num_int_register_reads 68603455 # number of times the integer registers were read +system.cpu0.num_int_register_writes 37120934 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 143452 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 146554 # number of times the floating registers were written +system.cpu0.num_mem_refs 14736943 # number of memory refs +system.cpu0.num_load_insts 8672910 # Number of load instructions +system.cpu0.num_store_insts 6064033 # Number of store instructions +system.cpu0.num_idle_cycles 3679227117.452844 # Number of idle cycles +system.cpu0.num_busy_cycles 230937650.547156 # Number of busy cycles +system.cpu0.not_idle_fraction 0.059061 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.940939 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6369 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 202997 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 72749 40.62% 40.62% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.07% 40.70% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1975 1.10% 41.80% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 6 0.00% 41.80% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 104220 58.20% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 179081 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 71382 49.27% 49.27% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.inst.quiesce 6366 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 203014 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 72751 40.62% 40.62% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.07% 40.69% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1976 1.10% 41.80% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 7 0.00% 41.80% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 104234 58.20% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 179099 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 71384 49.27% 49.27% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1975 1.36% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 71376 49.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 144870 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1898301427500 97.14% 97.14% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 93023500 0.00% 97.15% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 762226000 0.04% 97.19% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 5235500 0.00% 97.19% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 54943825500 2.81% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1954105738000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981209 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::22 1976 1.36% 50.73% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 7 0.00% 50.73% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 71377 49.27% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 144875 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1898825619000 97.12% 97.12% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 94636000 0.00% 97.13% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 768885000 0.04% 97.17% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 5899500 0.00% 97.17% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 55387314500 2.83% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1955082354000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981210 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684859 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.808964 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.684777 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.808910 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed @@ -703,37 +703,37 @@ system.cpu0.kern.syscall::144 2 0.90% 99.10% # nu system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 222 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 88 0.05% 0.05% # number of callpals executed +system.cpu0.kern.callpal::wripir 89 0.05% 0.05% # number of callpals executed system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3896 2.07% 2.12% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3897 2.07% 2.12% # number of callpals executed system.cpu0.kern.callpal::tbi 51 0.03% 2.15% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.15% # number of callpals executed -system.cpu0.kern.callpal::swpipl 172217 91.50% 93.65% # number of callpals executed -system.cpu0.kern.callpal::rdps 6678 3.55% 97.19% # number of callpals executed +system.cpu0.kern.callpal::swpipl 172231 91.49% 93.64% # number of callpals executed +system.cpu0.kern.callpal::rdps 6679 3.55% 97.19% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 97.19% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 97.20% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 97.19% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.00% 97.20% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 97.20% # number of callpals executed -system.cpu0.kern.callpal::rti 4751 2.52% 99.73% # number of callpals executed +system.cpu0.kern.callpal::rti 4753 2.52% 99.73% # number of callpals executed system.cpu0.kern.callpal::callsys 381 0.20% 99.93% # number of callpals executed system.cpu0.kern.callpal::imb 136 0.07% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 188224 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7304 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches +system.cpu0.kern.callpal::total 188243 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7307 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1284 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1283 -system.cpu0.kern.mode_good::user 1283 +system.cpu0.kern.mode_good::kernel 1284 +system.cpu0.kern.mode_good::user 1284 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.175657 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.175722 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.298824 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1950347158000 99.82% 99.82% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3454773000 0.18% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.298917 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1951356000500 99.82% 99.82% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3486973000 0.18% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3897 # number of times the context was actually changed +system.cpu0.kern.swap_context 3898 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -765,51 +765,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 915312 # number of replacements -system.cpu0.icache.tagsinuse 509.170564 # Cycle average of tags in use -system.cpu0.icache.total_refs 53154487 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 915824 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 58.040068 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 32594703000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.170564 # Average occupied blocks per requestor +system.cpu0.icache.replacements 915791 # number of replacements +system.cpu0.icache.tagsinuse 509.170825 # Cycle average of tags in use +system.cpu0.icache.total_refs 53217526 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 916303 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 58.078524 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 32591402000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.170825 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.994474 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.994474 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 53154487 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 53154487 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 53154487 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 53154487 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 53154487 # number of overall hits -system.cpu0.icache.overall_hits::total 53154487 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 915946 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 915946 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 915946 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 915946 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 915946 # number of overall misses -system.cpu0.icache.overall_misses::total 915946 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12645308000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 12645308000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 12645308000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 12645308000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 12645308000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 12645308000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 54070433 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 54070433 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 54070433 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 54070433 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 54070433 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 54070433 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016940 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.016940 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016940 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.016940 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016940 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.016940 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13805.735273 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13805.735273 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13805.735273 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13805.735273 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13805.735273 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13805.735273 # average overall miss latency +system.cpu0.icache.ReadReq_hits::cpu0.inst 53217526 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 53217526 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 53217526 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 53217526 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 53217526 # number of overall hits +system.cpu0.icache.overall_hits::total 53217526 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 916424 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 916424 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 916424 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 916424 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 916424 # number of overall misses +system.cpu0.icache.overall_misses::total 916424 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12661489500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 12661489500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 12661489500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 12661489500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 12661489500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 12661489500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 54133950 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 54133950 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 54133950 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 54133950 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 54133950 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 54133950 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016929 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.016929 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016929 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.016929 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016929 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.016929 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13816.191523 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13816.191523 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13816.191523 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13816.191523 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13816.191523 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13816.191523 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -818,112 +818,112 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10813416000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10813416000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10813416000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016940 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016940 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016940 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.016940 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016940 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.016940 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11805.735273 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11805.735273 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11805.735273 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11805.735273 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11805.735273 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11805.735273 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 916424 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 916424 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 916424 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 916424 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 916424 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 916424 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10828641500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10828641500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10828641500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10828641500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10828641500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10828641500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016929 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016929 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016929 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.016929 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016929 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.016929 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11816.191523 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11816.191523 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11816.191523 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11816.191523 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11816.191523 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11816.191523 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # 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number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5560492 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 176356 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 176356 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191669 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 191669 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12979614 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12979614 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12979614 # number of overall hits -system.cpu0.dcache.overall_hits::total 12979614 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1035915 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1035915 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 291040 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 291040 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16710 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 16710 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 430 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 430 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1326955 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1326955 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1326955 # number of overall misses -system.cpu0.dcache.overall_misses::total 1326955 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 22391266500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 22391266500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8190691500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 8190691500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 219165000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 219165000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 2509000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 2509000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 30581958000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 30581958000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 30581958000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 30581958000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8455037 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8455037 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5851532 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5851532 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 193066 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 193066 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 192099 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 192099 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14306569 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14306569 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14306569 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14306569 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122520 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.122520 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049737 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.049737 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086551 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086551 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002238 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002238 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092751 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.092751 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092751 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.092751 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21614.965031 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 21614.965031 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 28142.837754 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 28142.837754 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13115.798923 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13115.798923 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5834.883721 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5834.883721 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23046.718238 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 23046.718238 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23046.718238 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 23046.718238 # average overall miss latency +system.cpu0.dcache.replacements 1338546 # number of replacements +system.cpu0.dcache.tagsinuse 506.515538 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13360558 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1338960 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 9.978310 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 94365000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 506.515538 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.989288 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.989288 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 7428425 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7428425 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5564911 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5564911 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 176719 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 176719 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191683 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 191683 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12993336 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12993336 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12993336 # number of overall hits +system.cpu0.dcache.overall_hits::total 12993336 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1036642 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1036642 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 291308 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 291308 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16366 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 16366 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 435 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 435 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1327950 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1327950 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1327950 # number of overall misses +system.cpu0.dcache.overall_misses::total 1327950 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 22380575500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 22380575500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8193151000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 8193151000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 214111000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 214111000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 2551500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 2551500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 30573726500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 30573726500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 30573726500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 30573726500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8465067 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8465067 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5856219 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5856219 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 193085 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 193085 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 192118 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 192118 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 14321286 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14321286 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14321286 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14321286 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122461 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.122461 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049743 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.049743 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.084761 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.084761 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002264 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002264 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092726 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.092726 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092726 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.092726 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21589.493287 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 21589.493287 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 28125.389622 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 28125.389622 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13082.671392 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13082.671392 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5865.517241 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5865.517241 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23023.251252 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 23023.251252 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23023.251252 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 23023.251252 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -932,62 +932,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 789801 # number of writebacks -system.cpu0.dcache.writebacks::total 789801 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1035915 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1035915 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 291040 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 291040 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16710 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16710 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 430 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 430 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1326955 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1326955 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1326955 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1326955 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 20319436500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 20319436500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7608611500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7608611500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 185745000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 185745000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1649000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1649000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 27928048000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 27928048000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 27928048000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 27928048000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465347500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465347500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2092159000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2092159000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3557506500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3557506500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122520 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122520 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049737 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049737 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086551 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086551 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002238 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002238 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092751 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.092751 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092751 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.092751 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 19614.965031 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 19614.965031 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26142.837754 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26142.837754 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11115.798923 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11115.798923 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3834.883721 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3834.883721 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21046.718238 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21046.718238 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21046.718238 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21046.718238 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 791336 # number of writebacks +system.cpu0.dcache.writebacks::total 791336 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1036642 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1036642 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 291308 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 291308 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16366 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16366 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 435 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 435 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1327950 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1327950 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1327950 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1327950 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 20307291500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 20307291500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7610535000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7610535000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 181379000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 181379000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1681500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1681500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 27917826500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 27917826500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 27917826500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 27917826500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465371000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465371000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2092831000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2092831000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3558202000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3558202000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122461 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122461 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049743 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049743 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.084761 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.084761 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002264 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002264 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092726 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.092726 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092726 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.092726 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 19589.493287 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 19589.493287 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26125.389622 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26125.389622 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11082.671392 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11082.671392 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3865.517241 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3865.517241 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21023.251252 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21023.251252 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21023.251252 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21023.251252 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -999,22 +999,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1047086 # DTB read hits +system.cpu1.dtb.read_hits 1047303 # DTB read hits system.cpu1.dtb.read_misses 2992 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 239363 # DTB read accesses -system.cpu1.dtb.write_hits 650181 # DTB write hits +system.cpu1.dtb.write_hits 650380 # DTB write hits system.cpu1.dtb.write_misses 341 # DTB write misses system.cpu1.dtb.write_acv 29 # DTB write access violations system.cpu1.dtb.write_accesses 105247 # DTB write accesses -system.cpu1.dtb.data_hits 1697267 # DTB hits +system.cpu1.dtb.data_hits 1697683 # DTB hits system.cpu1.dtb.data_misses 3333 # DTB misses system.cpu1.dtb.data_acv 29 # DTB access violations system.cpu1.dtb.data_accesses 344610 # DTB accesses -system.cpu1.itb.fetch_hits 1487534 # ITB hits +system.cpu1.itb.fetch_hits 1487846 # ITB hits system.cpu1.itb.fetch_misses 1216 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1488750 # ITB accesses +system.cpu1.itb.fetch_accesses 1489062 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1027,51 +1027,51 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3909382743 # number of cpu cycles simulated +system.cpu1.numCycles 3911498214 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 5259785 # Number of instructions committed -system.cpu1.committedOps 5259785 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 4928462 # Number of integer alu accesses +system.cpu1.committedInsts 5261846 # Number of instructions committed +system.cpu1.committedOps 5261846 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 4930311 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 34031 # Number of float alu accesses -system.cpu1.num_func_calls 156703 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 508760 # number of instructions that are conditional controls -system.cpu1.num_int_insts 4928462 # number of integer instructions +system.cpu1.num_func_calls 156775 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 508835 # number of instructions that are conditional controls +system.cpu1.num_int_insts 4930311 # number of integer instructions system.cpu1.num_fp_insts 34031 # number of float instructions -system.cpu1.num_int_register_reads 6858583 # number of times the integer registers were read -system.cpu1.num_int_register_writes 3715950 # number of times the integer registers were written +system.cpu1.num_int_register_reads 6861337 # number of times the integer registers were read +system.cpu1.num_int_register_writes 3717514 # number of times the integer registers were written system.cpu1.num_fp_register_reads 22062 # number of times the floating registers were read system.cpu1.num_fp_register_writes 21862 # number of times the floating registers were written -system.cpu1.num_mem_refs 1706720 # number of memory refs -system.cpu1.num_load_insts 1053093 # Number of load instructions -system.cpu1.num_store_insts 653627 # Number of store instructions -system.cpu1.num_idle_cycles 3890042730.998010 # Number of idle cycles -system.cpu1.num_busy_cycles 19340012.001990 # Number of busy cycles -system.cpu1.not_idle_fraction 0.004947 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.995053 # Percentage of idle cycles +system.cpu1.num_mem_refs 1707139 # number of memory refs +system.cpu1.num_load_insts 1053310 # Number of load instructions +system.cpu1.num_store_insts 653829 # Number of store instructions +system.cpu1.num_idle_cycles 3891938527.998010 # Number of idle cycles +system.cpu1.num_busy_cycles 19559686.001990 # Number of busy cycles +system.cpu1.not_idle_fraction 0.005001 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.994999 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2297 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 35535 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 8961 31.73% 31.73% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1969 6.97% 38.70% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 88 0.31% 39.01% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 17223 60.99% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 28241 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 8951 45.05% 45.05% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1969 9.91% 54.95% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 88 0.44% 55.40% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 8863 44.60% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 19871 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1917858601000 98.12% 98.12% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 705516000 0.04% 98.15% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 59546500 0.00% 98.15% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 36066950000 1.85% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1954690613500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.998884 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2300 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 35556 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 8967 31.73% 31.73% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1970 6.97% 38.70% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 89 0.31% 39.02% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 17234 60.98% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 28260 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 8957 45.05% 45.05% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1970 9.91% 54.95% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 89 0.45% 55.40% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 8868 44.60% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 19884 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1918859770000 98.11% 98.11% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 708002500 0.04% 98.15% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 60314000 0.00% 98.15% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 36120248500 1.85% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1955748335000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.998885 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.514603 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.703622 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.514564 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.703609 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed @@ -1087,81 +1087,81 @@ system.cpu1.kern.syscall::74 10 9.62% 97.12% # nu system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 104 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 6 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wripir 7 0.02% 0.03% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed system.cpu1.kern.callpal::swpctx 337 1.17% 1.20% # number of callpals executed system.cpu1.kern.callpal::tbi 3 0.01% 1.21% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.02% 1.23% # number of callpals executed -system.cpu1.kern.callpal::swpipl 23653 81.85% 83.08% # number of callpals executed -system.cpu1.kern.callpal::rdps 2170 7.51% 90.59% # number of callpals executed +system.cpu1.kern.callpal::swpipl 23668 81.85% 83.08% # number of callpals executed +system.cpu1.kern.callpal::rdps 2171 7.51% 90.59% # number of callpals executed system.cpu1.kern.callpal::wrkgp 1 0.00% 90.59% # number of callpals executed system.cpu1.kern.callpal::wrusp 4 0.01% 90.61% # number of callpals executed system.cpu1.kern.callpal::whami 3 0.01% 90.62% # number of callpals executed -system.cpu1.kern.callpal::rti 2530 8.75% 99.37% # number of callpals executed +system.cpu1.kern.callpal::rti 2532 8.76% 99.37% # number of callpals executed system.cpu1.kern.callpal::callsys 136 0.47% 99.84% # number of callpals executed system.cpu1.kern.callpal::imb 44 0.15% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 28898 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 803 # number of protection mode switches +system.cpu1.kern.callpal::total 28917 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 802 # number of protection mode switches system.cpu1.kern.mode_switch::user 464 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2065 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2068 # number of protection mode switches system.cpu1.kern.mode_good::kernel 477 system.cpu1.kern.mode_good::user 464 system.cpu1.kern.mode_good::idle 13 -system.cpu1.kern.mode_switch_good::kernel 0.594022 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.594763 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.006295 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.286315 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 3558805000 0.18% 0.18% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1714794500 0.09% 0.27% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1949417010500 99.73% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_switch_good::idle 0.006286 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.286143 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 3597793000 0.18% 0.18% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1722339500 0.09% 0.27% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1950428198000 99.73% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 338 # number of times the context was actually changed -system.cpu1.icache.replacements 86368 # number of replacements -system.cpu1.icache.tagsinuse 420.702382 # Cycle average of tags in use -system.cpu1.icache.total_refs 5176232 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 86880 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 59.579098 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1938927920500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 420.702382 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.821684 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.821684 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 5176232 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 5176232 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 5176232 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 5176232 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 5176232 # number of overall hits -system.cpu1.icache.overall_hits::total 5176232 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 86916 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 86916 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 86916 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 86916 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 86916 # number of overall misses -system.cpu1.icache.overall_misses::total 86916 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1175956500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 1175956500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 1175956500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 1175956500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 1175956500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 1175956500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 5263148 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 5263148 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 5263148 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 5263148 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 5263148 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 5263148 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016514 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.016514 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016514 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.016514 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016514 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.016514 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13529.804639 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13529.804639 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13529.804639 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13529.804639 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13529.804639 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13529.804639 # average overall miss latency +system.cpu1.icache.replacements 86405 # number of replacements +system.cpu1.icache.tagsinuse 422.462851 # Cycle average of tags in use +system.cpu1.icache.total_refs 5178256 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 86917 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 59.577022 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1939963886500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 422.462851 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.825123 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.825123 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 5178256 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 5178256 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 5178256 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 5178256 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 5178256 # number of overall hits +system.cpu1.icache.overall_hits::total 5178256 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 86953 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 86953 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 86953 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 86953 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 86953 # number of overall misses +system.cpu1.icache.overall_misses::total 86953 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1177160000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 1177160000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 1177160000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 1177160000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 1177160000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 1177160000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 5265209 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 5265209 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 5265209 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 5265209 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 5265209 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 5265209 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016515 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.016515 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016515 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.016515 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016515 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.016515 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13537.888284 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13537.888284 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13537.888284 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13537.888284 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13537.888284 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13537.888284 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1170,112 +1170,112 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 86916 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 86916 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 86916 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 86916 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 86916 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 86916 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1002124500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 1002124500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1002124500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 1002124500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1002124500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 1002124500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016514 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016514 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016514 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.016514 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016514 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.016514 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11529.804639 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11529.804639 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11529.804639 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11529.804639 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11529.804639 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11529.804639 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 86953 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 86953 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 86953 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 86953 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 86953 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 86953 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1003254000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 1003254000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1003254000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 1003254000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1003254000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 1003254000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016515 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016515 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016515 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.016515 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016515 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.016515 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11537.888284 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11537.888284 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11537.888284 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11537.888284 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11537.888284 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11537.888284 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 52807 # number of replacements -system.cpu1.dcache.tagsinuse 417.673106 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1641017 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 53319 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 30.777340 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1938580812000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 417.673106 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.815768 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.815768 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1001237 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1001237 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 616220 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 616220 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 10806 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 10806 # number of LoadLockedReq hits +system.cpu1.dcache.replacements 52787 # number of replacements +system.cpu1.dcache.tagsinuse 417.162104 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1641435 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 53299 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 30.796732 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1919955450000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 417.162104 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.814770 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.814770 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1001433 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1001433 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 616401 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 616401 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 10836 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 10836 # number of LoadLockedReq hits system.cpu1.dcache.StoreCondReq_hits::cpu1.data 11203 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 11203 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1617457 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1617457 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1617457 # number of overall hits -system.cpu1.dcache.overall_hits::total 1617457 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 37009 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 37009 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 20401 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 20401 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 956 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 956 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 500 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 500 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 57410 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 57410 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 57410 # number of overall misses -system.cpu1.dcache.overall_misses::total 57410 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 463717500 # 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number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1038246 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1038246 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 636621 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 636621 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 11762 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 11762 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 11703 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 11703 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 1674867 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 1674867 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 1674867 # 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average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1284,62 +1284,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 30630 # number of writebacks -system.cpu1.dcache.writebacks::total 30630 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 37009 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 37009 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 20401 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 20401 # 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number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035651 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035651 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032049 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032049 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.079354 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.079354 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.043378 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.043378 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034282 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.034282 # 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average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15536.574324 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15536.574324 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15536.574324 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15536.574324 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency |