diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha')
4 files changed, 1660 insertions, 1596 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 6b719babe..a5d2b415b 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -197,7 +197,7 @@ system.physmem.avgRdBW 0.00 # Av system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.00 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time @@ -440,8 +440,8 @@ system.cpu0.num_fp_register_writes 150767 # nu system.cpu0.num_mem_refs 15124548 # number of memory refs system.cpu0.num_load_insts 9178366 # Number of load instructions system.cpu0.num_store_insts 5946182 # Number of store instructions -system.cpu0.num_idle_cycles 3683454681.836560 # Number of idle cycles -system.cpu0.num_busy_cycles 57196201.163440 # Number of busy cycles +system.cpu0.num_idle_cycles 3683454681.064560 # Number of idle cycles +system.cpu0.num_busy_cycles 57196201.935440 # Number of busy cycles system.cpu0.not_idle_fraction 0.015290 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.984710 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 2435d9264..178493c15 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -187,7 +187,7 @@ system.physmem.avgRdBW 0.00 # Av system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.00 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time @@ -302,8 +302,8 @@ system.cpu.num_fp_register_writes 166520 # nu system.cpu.num_mem_refs 16115688 # number of memory refs system.cpu.num_load_insts 9747503 # Number of load instructions system.cpu.num_store_insts 6368185 # Number of store instructions -system.cpu.num_idle_cycles 3598606250.520791 # Number of idle cycles -system.cpu.num_busy_cycles 60054827.479209 # Number of busy cycles +system.cpu.num_idle_cycles 3598606249.772791 # Number of idle cycles +system.cpu.num_busy_cycles 60054828.227209 # Number of busy cycles system.cpu.not_idle_fraction 0.016414 # Percentage of non-idle cycles system.cpu.idle_fraction 0.983586 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed @@ -608,5 +608,69 @@ system.cpu.dcache.cache_copies 0 # nu system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks system.cpu.dcache.writebacks::total 833491 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 2042707 # number of replacements +system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use +system.cpu.dcache.total_refs 14038405 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2043219 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 6.870729 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 7807769 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7807769 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5848199 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5848199 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183140 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183140 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199281 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199281 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13655968 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13655968 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13655968 # number of overall hits +system.cpu.dcache.overall_hits::total 13655968 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1721709 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1721709 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304365 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304365 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2026074 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2026074 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2026074 # number of overall misses +system.cpu.dcache.overall_misses::total 2026074 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 9529478 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9529478 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6152564 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6152564 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200302 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200302 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199281 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199281 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15682042 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15682042 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15682042 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15682042 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049470 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049470 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085681 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085681 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks +system.cpu.dcache.writebacks::total 833491 # number of writebacks +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 0e2cc710f..e93e66fed 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.950814 # Number of seconds simulated -sim_ticks 1950813955500 # Number of ticks simulated -final_tick 1950813955500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.952724 # Number of seconds simulated +sim_ticks 1952724269500 # Number of ticks simulated +final_tick 1952724269500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 720692 # Simulator instruction rate (inst/s) -host_op_rate 720692 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23054537293 # Simulator tick rate (ticks/s) -host_mem_usage 378432 # Number of bytes of host memory used -host_seconds 84.62 # Real time elapsed on the host -sim_insts 60983017 # Number of instructions simulated -sim_ops 60983017 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 827264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24727744 # Number of bytes read from this memory +host_inst_rate 1678586 # Simulator instruction rate (inst/s) +host_op_rate 1678585 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53851852439 # Simulator tick rate (ticks/s) +host_mem_usage 333452 # Number of bytes of host memory used +host_seconds 36.26 # Real time elapsed on the host +sim_insts 60867235 # Number of instructions simulated +sim_ops 60867235 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 830208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24725568 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 38464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 439872 # Number of bytes read from this memory -system.physmem.bytes_read::total 28684224 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 827264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 38464 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 865728 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7706496 # Number of bytes written to this memory -system.physmem.bytes_written::total 7706496 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12926 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 386371 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 35200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 438144 # Number of bytes read from this memory +system.physmem.bytes_read::total 28680000 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 830208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 35200 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 865408 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7698816 # Number of bytes written to this memory +system.physmem.bytes_written::total 7698816 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12972 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 386337 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 601 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6873 # Number of read requests responded to by this memory -system.physmem.num_reads::total 448191 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120414 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120414 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 424061 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12675603 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1358858 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 19717 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 225481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14703721 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 424061 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 19717 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 443778 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3950400 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3950400 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3950400 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 424061 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12675603 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1358858 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 19717 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 225481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18654121 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 448191 # Total number of read requests seen -system.physmem.writeReqs 120414 # Total number of write requests seen -system.physmem.cpureqs 599152 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28684224 # Total number of bytes read from memory -system.physmem.bytesWritten 7706496 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28684224 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7706496 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 57 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 7175 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28371 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27660 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28102 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27702 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 28190 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 28020 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27664 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27960 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28118 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28027 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27925 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 28196 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 28402 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28329 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27819 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27649 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7817 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7270 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7535 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7656 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7513 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7150 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7412 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7610 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7562 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7469 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7772 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 8034 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7948 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7345 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7159 # Track writes on a per bank basis +system.physmem.num_reads::cpu1.inst 550 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6846 # Number of read requests responded to by this memory +system.physmem.num_reads::total 448125 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120294 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120294 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 425154 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12662089 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1357529 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 18026 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 224376 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14687173 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 425154 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 18026 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 443180 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3942603 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3942603 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3942603 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 425154 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12662089 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1357529 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 18026 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 224376 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18629776 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 448125 # Total number of read requests seen +system.physmem.writeReqs 120294 # Total number of write requests seen +system.physmem.cpureqs 598443 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28680000 # Total number of bytes read from memory +system.physmem.bytesWritten 7698816 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28680000 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7698816 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 68 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 6945 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28344 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 28173 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28017 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27785 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 27951 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 27964 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 28022 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27886 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28437 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 28288 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28341 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 28051 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27575 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 27797 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27570 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27856 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7821 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7610 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7567 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7380 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7470 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7435 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7506 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7435 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7992 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7835 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7874 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7588 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7131 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7250 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7029 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7371 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 530 # Number of times wr buffer was full causing retry -system.physmem.totGap 1950760240000 # Total gap between requests +system.physmem.numWrRetry 1406 # Number of times wr buffer was full causing retry +system.physmem.totGap 1952670553500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 448191 # Categorize read packet sizes +system.physmem.readPktSize::6 448125 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -107,7 +107,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 120944 # categorize write packet sizes +system.physmem.writePktSize::6 121700 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -116,30 +116,30 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 7175 # categorize neither packet sizes +system.physmem.neitherpktsize::6 6945 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 409750 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7530 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5264 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2349 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2844 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2407 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1780 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2013 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1657 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1935 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1586 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1572 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1655 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1735 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1232 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1426 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 881 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 259 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 407346 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4785 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3654 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2222 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3126 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2960 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2681 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2639 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2601 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1535 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1459 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1410 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1370 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1401 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1629 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1508 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 906 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 771 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -152,225 +152,225 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 888 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1535 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 887 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 364 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 12 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2917085023 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10998617023 # Sum of mem lat for all requests -system.physmem.totBusLat 1792536000 # Total cycles spent in databus access -system.physmem.totBankLat 6288996000 # Total cycles spent in bank access -system.physmem.avgQLat 6509.40 # Average queueing delay per request -system.physmem.avgBankLat 14033.74 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24543.14 # Average memory access latency -system.physmem.avgRdBW 14.70 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 14.70 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 3.95 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.12 # Data bus utilization in percentage +system.physmem.totQLat 4798545467 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13448530467 # Sum of mem lat for all requests +system.physmem.totBusLat 2240285000 # Total cycles spent in databus access +system.physmem.totBankLat 6409700000 # Total cycles spent in bank access +system.physmem.avgQLat 10709.68 # Average queueing delay per request +system.physmem.avgBankLat 14305.55 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 30015.22 # Average memory access latency +system.physmem.avgRdBW 14.69 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 3.94 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 14.69 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 3.94 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 10.51 # Average write queue length over time -system.physmem.readRowHits 428061 # Number of row buffer hits during reads -system.physmem.writeRowHits 76773 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 63.76 # Row buffer hit rate for writes -system.physmem.avgGap 3430782.78 # Average gap between requests -system.l2c.replacements 341335 # number of replacements -system.l2c.tagsinuse 65247.035905 # Cycle average of tags in use -system.l2c.total_refs 2438054 # Total number of references to valid blocks. -system.l2c.sampled_refs 406311 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.000463 # Average number of references to valid blocks. -system.l2c.warmup_cycle 6891280002 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 55545.332470 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4807.217204 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4686.652945 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 164.376424 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 43.456861 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.847555 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.073352 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.071513 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.002508 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000663 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.995591 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 674205 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 658217 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 328581 # 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number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 706675500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 17206531500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 33342000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 443248500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 18389797500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 687131 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 929848 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 329193 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 113782 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2059954 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 791470 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 791470 # 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average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 50329.225948 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32268.229136 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 52474.220000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 44763.268318 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 33081.002138 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 50329.225948 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32268.229136 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 52474.220000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 44763.268318 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 33081.002138 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -503,14 +503,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41696 # number of replacements -system.iocache.tagsinuse 0.562950 # Cycle average of tags in use +system.iocache.tagsinuse 0.569993 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41712 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1745713328000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.562950 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.035184 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.035184 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1746698431000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 0.569993 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.035625 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.035625 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses system.iocache.ReadReq_misses::total 176 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -521,12 +521,12 @@ system.iocache.overall_misses::tsunami.ide 41728 # system.iocache.overall_misses::total 41728 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21268998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21268998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 9497531806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 9497531806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 9518800804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9518800804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 9518800804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9518800804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10634917806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10634917806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10656186804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10656186804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10656186804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10656186804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -545,17 +545,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120846.579545 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 120846.579545 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 228569.787399 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 228569.787399 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 228115.433378 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 228115.433378 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 228115.433378 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 228115.433378 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 188605 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 255942.380776 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 255942.380776 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 255372.574866 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 255372.574866 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 255372.574866 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 255372.574866 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 284837 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 22594 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27190 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.347570 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.475800 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -569,14 +569,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41728 system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12116000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12116000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7334778982 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7334778982 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 7346894982 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7346894982 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 7346894982 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7346894982 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12116250 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12116250 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8472911060 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8472911060 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8485027310 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8485027310 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8485027310 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8485027310 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -585,14 +585,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68840.909091 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68840.909091 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176520.479929 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 176520.479929 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176066.309960 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 176066.309960 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176066.309960 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 176066.309960 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68842.329545 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68842.329545 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203911.028591 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 203911.028591 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203341.336992 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 203341.336992 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203341.336992 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 203341.336992 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -610,22 +610,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7424685 # DTB read hits +system.cpu0.dtb.read_hits 7490982 # DTB read hits system.cpu0.dtb.read_misses 7443 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 490673 # DTB read accesses -system.cpu0.dtb.write_hits 5011105 # DTB write hits +system.cpu0.dtb.write_hits 5068153 # DTB write hits system.cpu0.dtb.write_misses 813 # DTB write misses system.cpu0.dtb.write_acv 134 # DTB write access violations system.cpu0.dtb.write_accesses 187452 # DTB write accesses -system.cpu0.dtb.data_hits 12435790 # DTB hits +system.cpu0.dtb.data_hits 12559135 # DTB hits system.cpu0.dtb.data_misses 8256 # DTB misses system.cpu0.dtb.data_acv 344 # DTB access violations system.cpu0.dtb.data_accesses 678125 # DTB accesses -system.cpu0.itb.fetch_hits 3481701 # ITB hits +system.cpu0.itb.fetch_hits 3503456 # ITB hits system.cpu0.itb.fetch_misses 3871 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3485572 # ITB accesses +system.cpu0.itb.fetch_accesses 3507327 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -638,55 +638,55 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3900399041 # number of cpu cycles simulated +system.cpu0.numCycles 3904305293 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 47350784 # Number of instructions committed -system.cpu0.committedOps 47350784 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 43919786 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 206365 # Number of float alu accesses -system.cpu0.num_func_calls 1188579 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5567614 # number of instructions that are conditional controls -system.cpu0.num_int_insts 43919786 # number of integer instructions -system.cpu0.num_fp_insts 206365 # number of float instructions -system.cpu0.num_int_register_reads 60378491 # number of times the integer registers were read -system.cpu0.num_int_register_writes 32741801 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 100221 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 101982 # number of times the floating registers were written -system.cpu0.num_mem_refs 12475691 # number of memory refs -system.cpu0.num_load_insts 7451626 # Number of load instructions -system.cpu0.num_store_insts 5024065 # Number of store instructions -system.cpu0.num_idle_cycles 3698902228.116945 # Number of idle cycles -system.cpu0.num_busy_cycles 201496812.883055 # Number of busy cycles -system.cpu0.not_idle_fraction 0.051661 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.948339 # Percentage of idle cycles +system.cpu0.committedInsts 47706703 # Number of instructions committed +system.cpu0.committedOps 47706703 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44241786 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 211423 # Number of float alu accesses +system.cpu0.num_func_calls 1201591 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5601417 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44241786 # number of integer instructions +system.cpu0.num_fp_insts 211423 # number of float instructions +system.cpu0.num_int_register_reads 60797943 # number of times the integer registers were read +system.cpu0.num_int_register_writes 32968604 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 102697 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 104564 # number of times the floating registers were written +system.cpu0.num_mem_refs 12599388 # number of memory refs +system.cpu0.num_load_insts 7518173 # Number of load instructions +system.cpu0.num_store_insts 5081215 # Number of store instructions +system.cpu0.num_idle_cycles 3700976170.173713 # Number of idle cycles +system.cpu0.num_busy_cycles 203329122.826288 # Number of busy cycles +system.cpu0.not_idle_fraction 0.052078 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.947922 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6813 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 162790 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 55943 40.16% 40.16% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.25% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1971 1.41% 41.66% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 443 0.32% 41.98% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 80829 58.02% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 139317 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 55450 49.07% 49.07% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1971 1.74% 50.93% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 443 0.39% 51.32% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 55007 48.68% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 113002 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1898623862000 97.36% 97.36% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 92984000 0.00% 97.36% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 759861500 0.04% 97.40% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 328899000 0.02% 97.42% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 50393884000 2.58% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1950199490500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.991187 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6787 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 165132 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 56916 40.19% 40.19% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1973 1.39% 41.67% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 418 0.30% 41.97% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 82194 58.03% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 141632 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 56372 49.08% 49.08% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 418 0.36% 51.28% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 55954 48.72% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 114848 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1900150859000 97.34% 97.34% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 92973000 0.00% 97.34% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 760723500 0.04% 97.38% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 310562000 0.02% 97.40% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 50837499000 2.60% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1952152616500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.990442 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.680535 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.811114 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.680755 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810890 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed @@ -718,37 +718,37 @@ system.cpu0.kern.syscall::144 2 0.90% 99.10% # nu system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 222 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 525 0.36% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3024 2.05% 2.41% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed -system.cpu0.kern.callpal::swpipl 132461 89.75% 92.20% # number of callpals executed -system.cpu0.kern.callpal::rdps 6674 4.52% 96.72% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.72% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.72% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.73% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.73% # number of callpals executed -system.cpu0.kern.callpal::rti 4310 2.92% 99.65% # number of callpals executed -system.cpu0.kern.callpal::callsys 381 0.26% 99.91% # number of callpals executed +system.cpu0.kern.callpal::wripir 500 0.33% 0.33% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.33% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3074 2.05% 2.39% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed +system.cpu0.kern.callpal::swpipl 134771 89.88% 92.30% # number of callpals executed +system.cpu0.kern.callpal::rdps 6676 4.45% 96.75% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.75% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.76% # number of callpals executed +system.cpu0.kern.callpal::rti 4338 2.89% 99.66% # number of callpals executed +system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 147588 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6865 # number of protection mode switches +system.cpu0.kern.callpal::total 149953 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6892 # number of protection mode switches system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches system.cpu0.kern.mode_good::kernel 1283 system.cpu0.kern.mode_good::user 1283 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.186890 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.186158 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.314924 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1946502716500 99.83% 99.83% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3403122000 0.17% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.313884 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1948377502000 99.82% 99.82% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3456174500 0.18% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3025 # number of times the context was actually changed +system.cpu0.kern.swap_context 3075 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -780,51 +780,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 686544 # number of replacements -system.cpu0.icache.tagsinuse 509.179305 # Cycle average of tags in use -system.cpu0.icache.total_refs 46672235 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 687056 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 67.930758 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 32409447000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.179305 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.994491 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.994491 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 46672235 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 46672235 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 46672235 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 46672235 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 46672235 # number of overall hits -system.cpu0.icache.overall_hits::total 46672235 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 687149 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 687149 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 687149 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 687149 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 687149 # number of overall misses -system.cpu0.icache.overall_misses::total 687149 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9571696500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 9571696500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 9571696500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 9571696500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 9571696500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 9571696500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47359384 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47359384 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47359384 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47359384 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47359384 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47359384 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014509 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014509 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014509 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014509 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014509 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014509 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13929.579320 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13929.579320 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13929.579320 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13929.579320 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13929.579320 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13929.579320 # average overall miss latency +system.cpu0.icache.replacements 699703 # number of replacements +system.cpu0.icache.tagsinuse 509.161264 # Cycle average of tags in use +system.cpu0.icache.total_refs 47014995 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 700215 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 67.143656 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 32599184000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.161264 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.994456 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.994456 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 47014995 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 47014995 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 47014995 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 47014995 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 47014995 # number of overall hits +system.cpu0.icache.overall_hits::total 47014995 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 700308 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 700308 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 700308 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 700308 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 700308 # number of overall misses +system.cpu0.icache.overall_misses::total 700308 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9851397000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 9851397000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 9851397000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 9851397000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 9851397000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 9851397000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47715303 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47715303 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47715303 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47715303 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47715303 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47715303 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014677 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014677 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014677 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014677 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014677 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014677 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14067.234702 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14067.234702 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14067.234702 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14067.234702 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14067.234702 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14067.234702 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -833,112 +833,112 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 687149 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 687149 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 687149 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 687149 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 687149 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 687149 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8197398500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 8197398500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8197398500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 8197398500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8197398500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 8197398500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014509 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014509 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014509 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014509 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014509 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014509 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11929.579320 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11929.579320 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11929.579320 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11929.579320 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11929.579320 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11929.579320 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 700308 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 700308 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 700308 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 700308 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 700308 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 700308 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8450781000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 8450781000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8450781000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 8450781000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8450781000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 8450781000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014677 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014677 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014677 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014677 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014677 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014677 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12067.234702 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12067.234702 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12067.234702 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12067.234702 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12067.234702 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12067.234702 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1171731 # number of replacements -system.cpu0.dcache.tagsinuse 505.264467 # Cycle average of tags in use -system.cpu0.dcache.total_refs 11253773 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1172148 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 9.600983 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 93429000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 505.264467 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.986845 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.986845 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6351999 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6351999 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4607371 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4607371 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138396 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 138396 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145569 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 145569 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10959370 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10959370 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10959370 # number of overall hits -system.cpu0.dcache.overall_hits::total 10959370 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 933038 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 933038 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 249274 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 249274 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13435 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13435 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5731 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5731 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1182312 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1182312 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1182312 # number of overall misses -system.cpu0.dcache.overall_misses::total 1182312 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 20824713000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 20824713000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7766651000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 7766651000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 144248500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 144248500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 43490500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 43490500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 28591364000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 28591364000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 28591364000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 28591364000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7285037 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7285037 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4856645 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4856645 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 151831 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 151831 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 151300 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 151300 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12141682 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12141682 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12141682 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12141682 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.128076 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.128076 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051326 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051326 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088487 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088487 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037878 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037878 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097376 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.097376 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097376 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097376 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22319.254950 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 22319.254950 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 31157.084172 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 31157.084172 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10736.769632 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10736.769632 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7588.640726 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7588.640726 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24182.588014 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 24182.588014 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24182.588014 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 24182.588014 # average overall miss latency +system.cpu0.dcache.replacements 1182211 # number of replacements +system.cpu0.dcache.tagsinuse 505.184188 # Cycle average of tags in use +system.cpu0.dcache.total_refs 11367781 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1182629 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 9.612297 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 93616000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 505.184188 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.986688 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.986688 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6409561 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6409561 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4659572 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4659572 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140562 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 140562 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148239 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 148239 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11069133 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11069133 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11069133 # number of overall hits +system.cpu0.dcache.overall_hits::total 11069133 # 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miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.097183 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097183 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.097183 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22477.794758 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 22477.794758 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30341.805420 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 30341.805420 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10928.895890 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10928.895890 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7610.926541 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7610.926541 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24140.225290 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 24140.225290 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24140.225290 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 24140.225290 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -947,62 +947,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 672345 # number of writebacks -system.cpu0.dcache.writebacks::total 672345 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 933038 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 933038 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249274 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 249274 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13435 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13435 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5731 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 5731 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1182312 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1182312 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1182312 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1182312 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 18958637000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 18958637000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7268103000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7268103000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 117378500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 117378500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 32028500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32028500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 26226740000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 26226740000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 26226740000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 26226740000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465462500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465462500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2285670500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2285670500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3751133000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3751133000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128076 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128076 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051326 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051326 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088487 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088487 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037878 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037878 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097376 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097376 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097376 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097376 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 20319.254950 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 20319.254950 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29157.084172 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29157.084172 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8736.769632 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8736.769632 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5588.640726 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5588.640726 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22182.588014 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22182.588014 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22182.588014 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22182.588014 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 680601 # number of writebacks +system.cpu0.dcache.writebacks::total 680601 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 939643 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 939643 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251886 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 251886 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13649 # 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number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 121870500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 121870500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30400000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30400000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 26380720500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 26380720500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 26380720500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 26380720500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465344500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465344500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2274931000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2274931000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3740275500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3740275500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127856 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127856 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051285 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051285 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088509 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088509 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035260 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035260 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097183 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097183 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097183 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097183 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 20477.794758 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 20477.794758 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28341.805420 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28341.805420 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8928.895890 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8928.895890 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5610.926541 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5610.926541 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22140.225290 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22140.225290 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22140.225290 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22140.225290 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1014,22 +1014,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2500361 # DTB read hits +system.cpu1.dtb.read_hits 2417694 # DTB read hits system.cpu1.dtb.read_misses 2992 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 239363 # DTB read accesses -system.cpu1.dtb.write_hits 1820984 # DTB write hits +system.cpu1.dtb.write_hits 1754404 # DTB write hits system.cpu1.dtb.write_misses 341 # DTB write misses system.cpu1.dtb.write_acv 29 # DTB write access violations system.cpu1.dtb.write_accesses 105247 # DTB write accesses -system.cpu1.dtb.data_hits 4321345 # DTB hits +system.cpu1.dtb.data_hits 4172098 # DTB hits system.cpu1.dtb.data_misses 3333 # DTB misses system.cpu1.dtb.data_acv 29 # DTB access violations system.cpu1.dtb.data_accesses 344610 # DTB accesses -system.cpu1.itb.fetch_hits 1990033 # ITB hits +system.cpu1.itb.fetch_hits 1961503 # ITB hits system.cpu1.itb.fetch_misses 1216 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1991249 # ITB accesses +system.cpu1.itb.fetch_accesses 1962719 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1042,51 +1042,51 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3901627911 # number of cpu cycles simulated +system.cpu1.numCycles 3905448539 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 13632233 # Number of instructions committed -system.cpu1.committedOps 13632233 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 12571690 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 180459 # Number of float alu accesses -system.cpu1.num_func_calls 426713 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1355142 # number of instructions that are conditional controls -system.cpu1.num_int_insts 12571690 # number of integer instructions -system.cpu1.num_fp_insts 180459 # number of float instructions -system.cpu1.num_int_register_reads 17311762 # number of times the integer registers were read -system.cpu1.num_int_register_writes 9221860 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 94168 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 96184 # number of times the floating registers were written -system.cpu1.num_mem_refs 4345653 # number of memory refs -system.cpu1.num_load_insts 2515108 # Number of load instructions -system.cpu1.num_store_insts 1830545 # Number of store instructions -system.cpu1.num_idle_cycles 3850258537.998026 # Number of idle cycles -system.cpu1.num_busy_cycles 51369373.001974 # Number of busy cycles -system.cpu1.not_idle_fraction 0.013166 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.986834 # Percentage of idle cycles +system.cpu1.committedInsts 13160532 # Number of instructions committed +system.cpu1.committedOps 13160532 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 12141335 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 171917 # Number of float alu accesses +system.cpu1.num_func_calls 411397 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1307333 # number of instructions that are conditional controls +system.cpu1.num_int_insts 12141335 # number of integer instructions +system.cpu1.num_fp_insts 171917 # number of float instructions +system.cpu1.num_int_register_reads 16724790 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8912820 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 89976 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 91834 # number of times the floating registers were written +system.cpu1.num_mem_refs 4195541 # number of memory refs +system.cpu1.num_load_insts 2431931 # Number of load instructions +system.cpu1.num_store_insts 1763610 # Number of store instructions +system.cpu1.num_idle_cycles 3855992964.998025 # Number of idle cycles +system.cpu1.num_busy_cycles 49455574.001975 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012663 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987337 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2717 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 80899 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 27499 38.50% 38.50% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1966 2.75% 41.25% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 525 0.74% 41.99% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 41433 58.01% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 71423 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 26615 48.22% 48.22% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1966 3.56% 51.78% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 525 0.95% 52.73% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 26090 47.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 55196 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1907137344500 97.76% 97.76% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 705261000 0.04% 97.80% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 364072500 0.02% 97.82% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 42606519500 2.18% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1950813197500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.967853 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2696 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 78331 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 26451 38.35% 38.35% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1967 2.85% 41.20% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 500 0.72% 41.92% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 40063 58.08% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 68981 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 25618 48.15% 48.15% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1967 3.70% 51.85% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 500 0.94% 52.79% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 25118 47.21% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 53203 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1909244973500 97.77% 97.77% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 705660500 0.04% 97.81% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 346600000 0.02% 97.83% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 42426277500 2.17% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1952723511500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.968508 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.629691 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.772804 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.626963 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.771270 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed @@ -1102,81 +1102,81 @@ system.cpu1.kern.syscall::74 10 9.62% 97.12% # nu system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 104 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 443 0.60% 0.60% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.60% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed -system.cpu1.kern.callpal::swpctx 2085 2.82% 3.43% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 3.43% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.44% # number of callpals executed -system.cpu1.kern.callpal::swpipl 65093 88.17% 91.61% # number of callpals executed -system.cpu1.kern.callpal::rdps 2167 2.94% 94.55% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.55% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 94.55% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.56% # number of callpals executed -system.cpu1.kern.callpal::rti 3838 5.20% 99.75% # number of callpals executed -system.cpu1.kern.callpal::callsys 136 0.18% 99.94% # number of callpals executed +system.cpu1.kern.callpal::wripir 418 0.59% 0.59% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1983 2.78% 3.37% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 3.38% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.39% # number of callpals executed +system.cpu1.kern.callpal::swpipl 62750 88.03% 91.41% # number of callpals executed +system.cpu1.kern.callpal::rdps 2168 3.04% 94.46% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.46% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 94.46% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.47% # number of callpals executed +system.cpu1.kern.callpal::rti 3763 5.28% 99.75% # number of callpals executed +system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 73828 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2125 # number of protection mode switches +system.cpu1.kern.callpal::total 71284 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2048 # number of protection mode switches system.cpu1.kern.mode_switch::user 465 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2925 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 915 +system.cpu1.kern.mode_switch::idle 2876 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 889 system.cpu1.kern.mode_good::user 465 -system.cpu1.kern.mode_good::idle 450 -system.cpu1.kern.mode_switch_good::kernel 0.430588 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::idle 424 +system.cpu1.kern.mode_switch_good::kernel 0.434082 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.153846 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.331822 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 18664257000 0.96% 0.96% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1710579000 0.09% 1.04% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1930438358000 98.96% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 2086 # number of times the context was actually changed -system.cpu1.icache.replacements 328646 # number of replacements -system.cpu1.icache.tagsinuse 446.257851 # Cycle average of tags in use -system.cpu1.icache.total_refs 13306402 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 329158 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 40.425577 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1948915489000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 446.257851 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.871597 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.871597 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 13306402 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 13306402 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 13306402 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 13306402 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 13306402 # number of overall hits -system.cpu1.icache.overall_hits::total 13306402 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 329194 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 329194 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 329194 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 329194 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 329194 # number of overall misses -system.cpu1.icache.overall_misses::total 329194 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4346536000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4346536000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4346536000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4346536000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4346536000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4346536000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13635596 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13635596 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13635596 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13635596 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13635596 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13635596 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024142 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024142 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024142 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024142 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024142 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024142 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13203.569931 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13203.569931 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13203.569931 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13203.569931 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13203.569931 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13203.569931 # average overall miss latency +system.cpu1.kern.mode_switch_good::idle 0.147427 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.329931 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 17784732000 0.91% 0.91% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1713538500 0.09% 1.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1933225237500 99.00% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1984 # number of times the context was actually changed +system.cpu1.icache.replacements 314891 # number of replacements +system.cpu1.icache.tagsinuse 448.025093 # Cycle average of tags in use +system.cpu1.icache.total_refs 12848456 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 315403 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 40.736632 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1950842738500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 448.025093 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.875049 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.875049 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 12848456 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 12848456 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 12848456 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 12848456 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 12848456 # number of overall hits +system.cpu1.icache.overall_hits::total 12848456 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 315439 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 315439 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 315439 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 315439 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 315439 # number of overall misses +system.cpu1.icache.overall_misses::total 315439 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4168917000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4168917000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4168917000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4168917000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4168917000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4168917000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 13163895 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13163895 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 13163895 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 13163895 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 13163895 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 13163895 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023962 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.023962 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023962 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.023962 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023962 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.023962 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13216.238322 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13216.238322 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13216.238322 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13216.238322 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13216.238322 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13216.238322 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1185,112 +1185,112 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # 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number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3538039000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3538039000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3538039000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3538039000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023962 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023962 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023962 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.023962 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023962 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.023962 # 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Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 165927 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 24.133384 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 60834829000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 486.567196 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.950327 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.950327 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 2254351 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2254351 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1637565 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1637565 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 47962 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 47962 # 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miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.155940 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103224 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103224 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044207 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.044207 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044207 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.044207 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12134.632708 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12134.632708 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17403.375365 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 17403.375365 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9185.644961 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9185.644961 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7253.223311 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7253.223311 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 13959.137473 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 13959.137473 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13959.137473 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 13959.137473 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1299,62 +1299,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 119125 # number of writebacks -system.cpu1.dcache.writebacks::total 119125 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 123241 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 123241 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 64769 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 64769 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9346 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9346 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6142 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 6142 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 188010 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 188010 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 188010 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 188010 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1247924500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1247924500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1037068000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1037068000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 66699000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 66699000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32308000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32308000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2284992500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2284992500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2284992500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2284992500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19381000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19381000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 723292500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 723292500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742673500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742673500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050252 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050252 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036717 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036717 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.156902 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.156902 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103980 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103980 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044590 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.044590 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044590 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.044590 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10125.887489 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10125.887489 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16011.795766 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16011.795766 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7136.635994 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7136.635994 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5260.175838 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5260.175838 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12153.568959 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12153.568959 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12153.568959 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12153.568959 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 113605 # number of writebacks +system.cpu1.dcache.writebacks::total 113605 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 117672 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 117672 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62334 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 62334 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8861 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8861 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5817 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 5817 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 180006 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 180006 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 180006 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 180006 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1192562500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1192562500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 960154000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 960154000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63672000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 63672000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30558000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30558000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2152716500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2152716500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2152716500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2152716500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19380500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19380500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 712390500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 712390500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 731771000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 731771000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049608 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049608 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036669 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036669 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155940 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155940 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103224 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103224 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044207 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.044207 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044207 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.044207 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10134.632708 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10134.632708 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15403.375365 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15403.375365 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7185.644961 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7185.644961 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5253.223311 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5253.223311 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11959.137473 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11959.137473 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11959.137473 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11959.137473 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index e3ca77030..37fa2c1e1 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,94 +1,94 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.910582 # Number of seconds simulated -sim_ticks 1910582068000 # Number of ticks simulated -final_tick 1910582068000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.910548 # Number of seconds simulated +sim_ticks 1910547559000 # Number of ticks simulated +final_tick 1910547559000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 951839 # Simulator instruction rate (inst/s) -host_op_rate 951839 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32401800424 # Simulator tick rate (ticks/s) -host_mem_usage 374212 # Number of bytes of host memory used -host_seconds 58.97 # Real time elapsed on the host -sim_insts 56125446 # Number of instructions simulated -sim_ops 56125446 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24847488 # Number of bytes read from this memory +host_inst_rate 1284259 # Simulator instruction rate (inst/s) +host_op_rate 1284258 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43720523895 # Simulator tick rate (ticks/s) +host_mem_usage 330356 # Number of bytes of host memory used +host_seconds 43.70 # Real time elapsed on the host +sim_insts 56120911 # Number of instructions simulated +sim_ops 56120911 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 850624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24858368 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28350400 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 850560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 850560 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7392192 # Number of bytes written to this memory -system.physmem.bytes_written::total 7392192 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13290 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388242 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28361344 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 850624 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 850624 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7404352 # Number of bytes written to this memory +system.physmem.bytes_written::total 7404352 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13291 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388412 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 442975 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115503 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115503 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 445184 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13005193 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1388243 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14838619 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 445184 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 445184 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3869078 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3869078 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3869078 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 445184 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13005193 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1388243 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18707698 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 442975 # Total number of read requests seen -system.physmem.writeReqs 115503 # Total number of write requests seen -system.physmem.cpureqs 559567 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28350400 # Total number of bytes read from memory -system.physmem.bytesWritten 7392192 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28350400 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7392192 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 51 # Number of read reqs serviced by write Q +system.physmem.num_reads::total 443146 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115693 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115693 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 445225 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13011122 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1388268 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14844616 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 445225 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 445225 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3875513 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3875513 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3875513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 445225 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13011122 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1388268 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18720129 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 443146 # Total number of read requests seen +system.physmem.writeReqs 115693 # Total number of write requests seen +system.physmem.cpureqs 561589 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28361344 # Total number of bytes read from memory +system.physmem.bytesWritten 7404352 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28361344 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7404352 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 45 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 130 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28021 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27576 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 27724 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27399 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 28096 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 27946 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27736 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27622 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 27577 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27238 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27723 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27886 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27600 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 27483 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27641 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27656 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7552 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7244 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7137 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6901 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7584 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7386 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7208 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7095 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7184 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6832 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7257 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7441 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7265 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7126 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7165 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7126 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 27901 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 27706 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 27556 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27375 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 27676 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 27765 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27827 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27615 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28008 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 27777 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 27792 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27562 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27598 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 27733 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27646 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27564 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7483 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7263 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7148 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7032 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7167 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7214 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7312 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7182 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7584 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7357 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7354 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7067 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7154 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7184 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7113 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7079 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 404 # Number of times wr buffer was full causing retry -system.physmem.totGap 1910570168000 # Total gap between requests +system.physmem.numWrRetry 2065 # Number of times wr buffer was full causing retry +system.physmem.totGap 1910535659000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 442975 # Categorize read packet sizes +system.physmem.readPktSize::6 443146 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -97,7 +97,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 115907 # categorize write packet sizes +system.physmem.writePktSize::6 117758 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -109,27 +109,27 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 130 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 404639 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7455 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5269 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2835 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2403 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1793 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2009 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1658 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1931 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1592 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1535 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1623 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1782 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1204 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1459 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 903 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 267 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 101 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 402456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4645 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3680 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3123 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2964 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2721 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2721 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2666 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2589 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1544 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1412 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1360 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1379 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1611 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1491 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 926 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 759 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -142,69 +142,69 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4893 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4987 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4653 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5001 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5012 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1521 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2804911869 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10779125869 # Sum of mem lat for all requests -system.physmem.totBusLat 1771696000 # Total cycles spent in databus access -system.physmem.totBankLat 6202518000 # Total cycles spent in bank access -system.physmem.avgQLat 6332.72 # Average queueing delay per request -system.physmem.avgBankLat 14003.57 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24336.29 # Average memory access latency +system.physmem.totQLat 4718066660 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13230246660 # Sum of mem lat for all requests +system.physmem.totBusLat 2215505000 # Total cycles spent in databus access +system.physmem.totBankLat 6296675000 # Total cycles spent in bank access +system.physmem.avgQLat 10647.84 # Average queueing delay per request +system.physmem.avgBankLat 14210.47 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 29858.31 # Average memory access latency system.physmem.avgRdBW 14.84 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 3.87 # Average achieved write bandwidth in MB/s +system.physmem.avgWrBW 3.88 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 14.84 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 3.87 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.12 # Data bus utilization in percentage +system.physmem.avgConsumedWrBW 3.88 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 14.48 # Average write queue length over time -system.physmem.readRowHits 423327 # Number of row buffer hits during reads -system.physmem.writeRowHits 74914 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.58 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 64.86 # Row buffer hit rate for writes -system.physmem.avgGap 3421030.31 # Average gap between requests +system.physmem.avgWrQLen 11.47 # Average write queue length over time +system.physmem.readRowHits 415807 # Number of row buffer hits during reads +system.physmem.writeRowHits 89941 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.84 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.74 # Row buffer hit rate for writes +system.physmem.avgGap 3418758.64 # Average gap between requests system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.342666 # Cycle average of tags in use +system.iocache.tagsinuse 1.342284 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1745691885000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.342666 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.083917 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.083917 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1745701071000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.342284 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.083893 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.083893 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -215,12 +215,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 9475235806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 9475235806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 9496163804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9496163804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 9496163804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9496163804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10644331806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10644331806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10665259804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10665259804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10665259804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10665259804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -239,17 +239,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 228033.206729 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 228033.206729 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 227589.306267 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 227589.306267 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 227589.306267 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 227589.306267 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 189601 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256168.940268 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 256168.940268 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 255608.383559 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 255608.383559 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 255608.383559 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 255608.383559 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 285028 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23064 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27152 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.220647 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.497496 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -263,14 +263,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11931000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7312468500 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7312468500 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 7324399500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7324399500 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 7324399500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7324399500 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931250 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11931250 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8482336109 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8482336109 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8494267359 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8494267359 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8494267359 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8494267359 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -279,14 +279,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68965.317919 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68965.317919 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 175983.550732 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 175983.550732 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 175539.832235 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 175539.832235 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 175539.832235 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 175539.832235 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.763006 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.763006 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204137.853990 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 204137.853990 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203577.408244 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 203577.408244 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203577.408244 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 203577.408244 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -304,22 +304,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9055970 # DTB read hits +system.cpu.dtb.read_hits 9055197 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations system.cpu.dtb.read_accesses 728856 # DTB read accesses -system.cpu.dtb.write_hits 6351685 # DTB write hits +system.cpu.dtb.write_hits 6350929 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 15407655 # DTB hits +system.cpu.dtb.data_hits 15406126 # DTB hits system.cpu.dtb.data_misses 11471 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations system.cpu.dtb.data_accesses 1020787 # DTB accesses -system.cpu.itb.fetch_hits 4974178 # ITB hits +system.cpu.itb.fetch_hits 4974131 # ITB hits system.cpu.itb.fetch_misses 5006 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979184 # ITB accesses +system.cpu.itb.fetch_accesses 4979137 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -332,51 +332,51 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3821164136 # number of cpu cycles simulated +system.cpu.numCycles 3821095118 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56125446 # Number of instructions committed -system.cpu.committedOps 56125446 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 51999916 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses -system.cpu.num_func_calls 1482010 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6463546 # number of instructions that are conditional controls -system.cpu.num_int_insts 51999916 # number of integer instructions -system.cpu.num_fp_insts 324393 # number of float instructions -system.cpu.num_int_register_reads 71242345 # number of times the integer registers were read -system.cpu.num_int_register_writes 38476410 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written -system.cpu.num_mem_refs 15460271 # number of memory refs -system.cpu.num_load_insts 9092827 # Number of load instructions -system.cpu.num_store_insts 6367444 # Number of store instructions -system.cpu.num_idle_cycles 3587332264.998123 # Number of idle cycles -system.cpu.num_busy_cycles 233831871.001878 # Number of busy cycles -system.cpu.not_idle_fraction 0.061194 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.938806 # Percentage of idle cycles +system.cpu.committedInsts 56120911 # Number of instructions committed +system.cpu.committedOps 56120911 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 51995405 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324259 # Number of float alu accesses +system.cpu.num_func_calls 1481756 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6462892 # number of instructions that are conditional controls +system.cpu.num_int_insts 51995405 # number of integer instructions +system.cpu.num_fp_insts 324259 # number of float instructions +system.cpu.num_int_register_reads 71234690 # number of times the integer registers were read +system.cpu.num_int_register_writes 38473511 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163543 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166418 # number of times the floating registers were written +system.cpu.num_mem_refs 15458726 # number of memory refs +system.cpu.num_load_insts 9092044 # Number of load instructions +system.cpu.num_store_insts 6366682 # Number of store instructions +system.cpu.num_idle_cycles 3587142255.998123 # Number of idle cycles +system.cpu.num_busy_cycles 233952862.001878 # Number of busy cycles +system.cpu.not_idle_fraction 0.061227 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.938773 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211969 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74892 40.89% 40.89% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6380 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211970 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74891 40.89% 40.89% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1930 1.05% 42.02% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106200 57.98% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183153 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73525 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1930 1.05% 42.01% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 106204 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183156 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73524 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1930 1.29% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73525 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149111 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1855918085500 97.14% 97.14% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 91164500 0.00% 97.14% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 736454000 0.04% 97.18% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 53835630000 2.82% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1910581334000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_good::31 73524 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149109 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1855675111500 97.13% 97.13% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 91586500 0.00% 97.13% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 735892500 0.04% 97.17% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 54044234500 2.83% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1910546825000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981747 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692326 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814134 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692290 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814109 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -412,10 +412,10 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed -system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed +system.cpu.kern.callpal::swpctx 4174 2.16% 2.17% # number of callpals executed +system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175936 91.22% 93.42% # number of callpals executed +system.cpu.kern.callpal::swpipl 175939 91.22% 93.42% # number of callpals executed system.cpu.kern.callpal::rdps 6831 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed @@ -424,21 +424,21 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu system.cpu.kern.callpal::rti 5155 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192878 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5901 # number of protection mode switches -system.cpu.kern.mode_switch::user 1741 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1911 -system.cpu.kern.mode_good::user 1741 -system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.323843 # fraction of useful protection mode switches +system.cpu.kern.callpal::total 192879 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5900 # number of protection mode switches +system.cpu.kern.mode_switch::user 1744 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1913 +system.cpu.kern.mode_good::user 1744 +system.cpu.kern.mode_good::idle 169 +system.cpu.kern.mode_switch_good::kernel 0.324237 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392483 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 45587423000 2.39% 2.39% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5075517000 0.27% 2.65% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1859918392000 97.35% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4177 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::idle 0.080668 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392853 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 45393996500 2.38% 2.38% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5132973000 0.27% 2.64% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1860019853500 97.36% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4175 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -470,51 +470,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 927460 # number of replacements -system.cpu.icache.tagsinuse 509.121498 # Cycle average of tags in use -system.cpu.icache.total_refs 55209154 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 927971 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 59.494482 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 32120759000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 509.121498 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.994378 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.994378 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 55209154 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55209154 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55209154 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55209154 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55209154 # number of overall hits -system.cpu.icache.overall_hits::total 55209154 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 928131 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 928131 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 928131 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 928131 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 928131 # number of overall misses -system.cpu.icache.overall_misses::total 928131 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12666318500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12666318500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12666318500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12666318500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12666318500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12666318500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56137285 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56137285 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56137285 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56137285 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 56137285 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56137285 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016533 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016533 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.016533 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.016533 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.016533 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.016533 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13647.123628 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13647.123628 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13647.123628 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13647.123628 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13647.123628 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13647.123628 # average overall miss latency +system.cpu.icache.replacements 927816 # number of replacements +system.cpu.icache.tagsinuse 509.100001 # Cycle average of tags in use +system.cpu.icache.total_refs 55204264 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 928327 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 59.466399 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 32331359000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 509.100001 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.994336 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.994336 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 55204264 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55204264 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55204264 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55204264 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55204264 # number of overall hits +system.cpu.icache.overall_hits::total 55204264 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 928486 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 928486 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 928486 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 928486 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 928486 # number of overall misses +system.cpu.icache.overall_misses::total 928486 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12769098000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12769098000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12769098000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12769098000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12769098000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12769098000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 56132750 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56132750 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 56132750 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 56132750 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 56132750 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 56132750 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016541 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016541 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016541 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016541 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016541 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016541 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13752.601547 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13752.601547 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13752.601547 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13752.601547 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13752.601547 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13752.601547 # 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number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 73991 # number of writebacks -system.cpu.l2cache.writebacks::total 73991 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13290 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271922 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 285212 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 74181 # number of writebacks +system.cpu.l2cache.writebacks::total 74181 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13291 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271961 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 285252 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # 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number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334146000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334146000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895221500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895221500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229367500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229367500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014319 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250366 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141600 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4162858124 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4162858124 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 666952085 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12539726199 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13206678284 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 666952085 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12539726199 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13206678284 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334145500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334145500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895221000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895221000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229366500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229366500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014315 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250431 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141604 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383643 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383643 # 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number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8388017500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8388017500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 229841000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 229841000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 31271663500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31271663500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31271663500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31271663500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8874336 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8874336 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6151362 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6151362 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200239 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200239 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199218 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199218 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15025698 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15025698 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15025698 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15025698 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120428 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120428 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049481 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049481 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086167 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086167 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091383 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091383 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091383 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091383 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21412.279782 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21412.279782 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27558.258918 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27558.258918 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13321.027008 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13321.027008 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22774.664079 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22774.664079 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22774.664079 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22774.664079 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -799,54 +799,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 834403 # number of writebacks -system.cpu.dcache.writebacks::total 834403 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1068876 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1068876 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304232 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304232 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17223 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17223 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1373108 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1373108 # 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number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28563427500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28563427500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424236000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424236000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2010997500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2010997500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435233500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435233500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120435 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120435 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049452 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049452 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086010 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086010 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091375 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091375 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091375 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091375 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19247.653610 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19247.653610 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26263.090339 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26263.090339 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11220.519073 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11220.519073 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20802.025405 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20802.025405 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20802.025405 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20802.025405 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 834499 # number of writebacks +system.cpu.dcache.writebacks::total 834499 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1068716 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1068716 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304374 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304374 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17254 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17254 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1373090 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1373090 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1373090 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1373090 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 20746214000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 20746214000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7779269500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7779269500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 195333000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 195333000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28525483500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28525483500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28525483500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28525483500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424235500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424235500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2010997000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2010997000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435232500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435232500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120428 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120428 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049481 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049481 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086167 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086167 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091383 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091383 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19412.279782 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19412.279782 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25558.258918 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25558.258918 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11321.027008 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11321.027008 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20774.664079 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20774.664079 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20774.664079 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20774.664079 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency |