diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha')
4 files changed, 2632 insertions, 2585 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 59ee1a74c..af5c79ab1 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -4,52 +4,52 @@ sim_seconds 1.869358 # Nu sim_ticks 1869358498000 # Number of ticks simulated final_tick 1869358498000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2397277 # Simulator instruction rate (inst/s) -host_op_rate 2397276 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 68943602925 # Simulator tick rate (ticks/s) -host_mem_usage 377676 # Number of bytes of host memory used -host_seconds 27.11 # Real time elapsed on the host +host_inst_rate 2198730 # Simulator instruction rate (inst/s) +host_op_rate 2198729 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63233555824 # Simulator tick rate (ticks/s) +host_mem_usage 377528 # Number of bytes of host memory used +host_seconds 29.56 # Real time elapsed on the host sim_insts 65000470 # Number of instructions simulated sim_ops 65000470 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 763776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 66536960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 106240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 766208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 758272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 66535616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 105984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 766336 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 68174144 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 763776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 106240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 870016 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7835712 # Number of bytes written to this memory -system.physmem.bytes_written::total 7835712 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11934 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 1039640 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1660 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 11972 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 68167168 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 758272 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 105984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 864256 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7836224 # Number of bytes written to this memory +system.physmem.bytes_written::total 7836224 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11848 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 1039619 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1656 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 11974 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1065221 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122433 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122433 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 408577 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 35593472 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 56832 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 409878 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 1065112 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122441 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122441 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 405632 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 35592753 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 56695 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 409946 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 514 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36469272 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 408577 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 56832 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 465409 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4191658 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4191658 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4191658 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 408577 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 35593472 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 56832 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 409878 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 36465540 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 405632 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 56695 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 462328 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4191932 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4191932 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4191932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 405632 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 35592753 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 56695 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 409946 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40660931 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 40657473 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses @@ -86,61 +86,6 @@ system.cpu0.itb.data_accesses 0 # DT system.cpu0.numCycles 3738723791 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 49478313 # Number of instructions committed -system.cpu0.committedOps 49478313 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 46202260 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 197598 # Number of float alu accesses -system.cpu0.num_func_calls 1124639 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 6043708 # number of instructions that are conditional controls -system.cpu0.num_int_insts 46202260 # number of integer instructions -system.cpu0.num_fp_insts 197598 # number of float instructions -system.cpu0.num_int_register_reads 64004164 # number of times the integer registers were read -system.cpu0.num_int_register_writes 34834852 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 97440 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 98967 # number of times the floating registers were written -system.cpu0.num_mem_refs 12536155 # number of memory refs -system.cpu0.num_load_insts 7783785 # Number of load instructions -system.cpu0.num_store_insts 4752370 # Number of store instructions -system.cpu0.num_idle_cycles 3689240240.665401 # Number of idle cycles -system.cpu0.num_busy_cycles 49483550.334599 # Number of busy cycles -system.cpu0.not_idle_fraction 0.013235 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.986765 # Percentage of idle cycles -system.cpu0.Branches 7530941 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2589824 5.23% 5.23% # Class of executed instruction -system.cpu0.op_class::IntAlu 33436514 67.57% 72.80% # Class of executed instruction -system.cpu0.op_class::IntMult 50547 0.10% 72.90% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 72.90% # Class of executed instruction -system.cpu0.op_class::FloatAdd 27840 0.06% 72.96% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::FloatDiv 2233 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::MemRead 7945621 16.06% 89.02% # Class of executed instruction -system.cpu0.op_class::MemWrite 4758309 9.62% 98.63% # Class of executed instruction -system.cpu0.op_class::IprAccess 675566 1.37% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 49486454 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed system.cpu0.kern.inst.hwrei 150436 # number of hwrei instructions executed @@ -231,6 +176,61 @@ system.cpu0.kern.mode_ticks::kernel 1868349657500 99.95% 99.95% # n system.cpu0.kern.mode_ticks::user 1008632000 0.05% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 2744 # number of times the context was actually changed +system.cpu0.committedInsts 49478313 # Number of instructions committed +system.cpu0.committedOps 49478313 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 46202260 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 197598 # Number of float alu accesses +system.cpu0.num_func_calls 1124639 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 6043708 # number of instructions that are conditional controls +system.cpu0.num_int_insts 46202260 # number of integer instructions +system.cpu0.num_fp_insts 197598 # number of float instructions +system.cpu0.num_int_register_reads 64004164 # number of times the integer registers were read +system.cpu0.num_int_register_writes 34834852 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 97440 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 98967 # number of times the floating registers were written +system.cpu0.num_mem_refs 12536155 # number of memory refs +system.cpu0.num_load_insts 7783785 # Number of load instructions +system.cpu0.num_store_insts 4752370 # Number of store instructions +system.cpu0.num_idle_cycles 3689240240.665401 # Number of idle cycles +system.cpu0.num_busy_cycles 49483550.334599 # Number of busy cycles +system.cpu0.not_idle_fraction 0.013235 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.986765 # Percentage of idle cycles +system.cpu0.Branches 7530941 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2589824 5.23% 5.23% # Class of executed instruction +system.cpu0.op_class::IntAlu 33436514 67.57% 72.80% # Class of executed instruction +system.cpu0.op_class::IntMult 50547 0.10% 72.90% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 72.90% # Class of executed instruction +system.cpu0.op_class::FloatAdd 27840 0.06% 72.96% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::FloatDiv 2233 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::MemRead 7945621 16.06% 89.02% # Class of executed instruction +system.cpu0.op_class::MemWrite 4758309 9.62% 98.63% # Class of executed instruction +system.cpu0.op_class::IprAccess 675566 1.37% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 49486454 # Class of executed instruction system.cpu0.dcache.tags.replacements 1781373 # number of replacements system.cpu0.dcache.tags.tagsinuse 506.187448 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 10705809 # Total number of references to valid blocks. @@ -303,8 +303,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 632989 # number of writebacks -system.cpu0.dcache.writebacks::total 632989 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 632988 # number of writebacks +system.cpu0.dcache.writebacks::total 632988 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 618298 # number of replacements system.cpu0.icache.tags.tagsinuse 511.240646 # Cycle average of tags in use @@ -354,6 +354,8 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.writebacks::writebacks 618298 # number of writebacks +system.cpu0.icache.writebacks::total 618298 # number of writebacks system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses @@ -390,61 +392,6 @@ system.cpu1.itb.data_accesses 0 # DT system.cpu1.numCycles 3738297607 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 15522157 # Number of instructions committed -system.cpu1.committedOps 15522157 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 14295542 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 198941 # Number of float alu accesses -system.cpu1.num_func_calls 493140 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1540067 # number of instructions that are conditional controls -system.cpu1.num_int_insts 14295542 # number of integer instructions -system.cpu1.num_fp_insts 198941 # number of float instructions -system.cpu1.num_int_register_reads 19514287 # number of times the integer registers were read -system.cpu1.num_int_register_writes 10457599 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 101734 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 104129 # number of times the floating registers were written -system.cpu1.num_mem_refs 4961785 # number of memory refs -system.cpu1.num_load_insts 2849089 # Number of load instructions -system.cpu1.num_store_insts 2112696 # Number of store instructions -system.cpu1.num_idle_cycles 3722774671.474094 # Number of idle cycles -system.cpu1.num_busy_cycles 15522935.525906 # Number of busy cycles -system.cpu1.not_idle_fraction 0.004152 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.995848 # Percentage of idle cycles -system.cpu1.Branches 2214162 # Number of branches fetched -system.cpu1.op_class::No_OpClass 856043 5.51% 5.51% # Class of executed instruction -system.cpu1.op_class::IntAlu 9156765 58.98% 64.49% # Class of executed instruction -system.cpu1.op_class::IntMult 25065 0.16% 64.65% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.65% # Class of executed instruction -system.cpu1.op_class::FloatAdd 12426 0.08% 64.73% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.73% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.73% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.73% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1409 0.01% 64.74% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::MemRead 2937015 18.92% 83.66% # Class of executed instruction -system.cpu1.op_class::MemWrite 2113897 13.62% 97.27% # Class of executed instruction -system.cpu1.op_class::IprAccess 423253 2.73% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 15525873 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 2704 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 92290 # number of hwrei instructions executed @@ -518,6 +465,61 @@ system.cpu1.kern.mode_ticks::kernel 5986367000 0.32% 0.32% # nu system.cpu1.kern.mode_ticks::user 456602000 0.02% 0.34% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 1862102855500 99.66% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 2507 # number of times the context was actually changed +system.cpu1.committedInsts 15522157 # Number of instructions committed +system.cpu1.committedOps 15522157 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 14295542 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 198941 # Number of float alu accesses +system.cpu1.num_func_calls 493140 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1540067 # number of instructions that are conditional controls +system.cpu1.num_int_insts 14295542 # number of integer instructions +system.cpu1.num_fp_insts 198941 # number of float instructions +system.cpu1.num_int_register_reads 19514287 # number of times the integer registers were read +system.cpu1.num_int_register_writes 10457599 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 101734 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 104129 # number of times the floating registers were written +system.cpu1.num_mem_refs 4961785 # number of memory refs +system.cpu1.num_load_insts 2849089 # Number of load instructions +system.cpu1.num_store_insts 2112696 # Number of store instructions +system.cpu1.num_idle_cycles 3722774671.474094 # Number of idle cycles +system.cpu1.num_busy_cycles 15522935.525906 # Number of busy cycles +system.cpu1.not_idle_fraction 0.004152 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.995848 # Percentage of idle cycles +system.cpu1.Branches 2214162 # Number of branches fetched +system.cpu1.op_class::No_OpClass 856043 5.51% 5.51% # Class of executed instruction +system.cpu1.op_class::IntAlu 9156765 58.98% 64.49% # Class of executed instruction +system.cpu1.op_class::IntMult 25065 0.16% 64.65% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.65% # Class of executed instruction +system.cpu1.op_class::FloatAdd 12426 0.08% 64.73% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.73% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.73% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.73% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1409 0.01% 64.74% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::MemRead 2937015 18.92% 83.66% # Class of executed instruction +system.cpu1.op_class::MemWrite 2113897 13.62% 97.27% # Class of executed instruction +system.cpu1.op_class::IprAccess 423253 2.73% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 15525873 # Class of executed instruction system.cpu1.dcache.tags.replacements 201756 # number of replacements system.cpu1.dcache.tags.tagsinuse 497.613037 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 4718402 # Total number of references to valid blocks. @@ -639,6 +641,8 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.writebacks::writebacks 380671 # number of writebacks +system.cpu1.icache.writebacks::total 380671 # number of writebacks system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -737,22 +741,22 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 999687 # number of replacements -system.l2c.tags.tagsinuse 65320.982503 # Cycle average of tags in use -system.l2c.tags.total_refs 4249853 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1064737 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.991458 # Average number of references to valid blocks. +system.l2c.tags.replacements 999918 # number of replacements +system.l2c.tags.tagsinuse 65320.982415 # Cycle average of tags in use +system.l2c.tags.total_refs 4249962 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1064968 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.990695 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55911.121944 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4939.470586 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4176.774738 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 179.034361 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 114.580874 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.853136 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.075370 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.063733 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002732 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.001748 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 55992.770808 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4860.291584 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4178.146657 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 175.172078 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 114.601288 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.854382 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.074162 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.063753 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.002673 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.001749 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.996719 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65050 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 768 # Occupied blocks per task id @@ -761,62 +765,66 @@ system.l2c.tags.age_task_id_blocks_1024::2 6123 # system.l2c.tags.age_task_id_blocks_1024::3 5943 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::4 48945 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.992584 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 46365678 # Number of tag accesses -system.l2c.tags.data_accesses 46365678 # Number of data accesses -system.l2c.Writeback_hits::writebacks 777520 # number of Writeback hits -system.l2c.Writeback_hits::total 777520 # number of Writeback hits +system.l2c.tags.tag_accesses 46365909 # Number of tag accesses +system.l2c.tags.data_accesses 46365909 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 777519 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 777519 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 719211 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 719211 # number of WritebackClean hits system.l2c.UpgradeReq_hits::cpu0.data 116 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 577 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 693 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 37 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 13 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 50 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 111476 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu0.data 111475 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu1.data 56603 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 168079 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 606990 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 379552 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 986542 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 626685 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 129013 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 755698 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 606990 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 738161 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 379552 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 185616 # number of demand (read+write) hits -system.l2c.demand_hits::total 1910319 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 606990 # number of overall hits -system.l2c.overall_hits::cpu0.data 738161 # number of overall hits -system.l2c.overall_hits::cpu1.inst 379552 # number of overall hits -system.l2c.overall_hits::cpu1.data 185616 # number of overall hits -system.l2c.overall_hits::total 1910319 # number of overall hits +system.l2c.ReadExReq_hits::total 168078 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 607076 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 379556 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 986632 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 626681 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 129011 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 755692 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.inst 607076 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 738156 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 379556 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 185614 # number of demand (read+write) hits +system.l2c.demand_hits::total 1910402 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 607076 # number of overall hits +system.l2c.overall_hits::cpu0.data 738156 # number of overall hits +system.l2c.overall_hits::cpu1.inst 379556 # number of overall hits +system.l2c.overall_hits::cpu1.data 185614 # number of overall hits +system.l2c.overall_hits::total 1910402 # number of overall hits system.l2c.UpgradeReq_misses::cpu0.data 3006 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 2174 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 5180 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu0.data 1175 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 1110 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2285 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 113873 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 113874 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 11069 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 124942 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 11934 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 1660 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 13594 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 926611 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 1033 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 927644 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.inst 11934 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 1040484 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1660 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 12102 # number of demand (read+write) misses -system.l2c.demand_misses::total 1066180 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 11934 # number of overall misses -system.l2c.overall_misses::cpu0.data 1040484 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1660 # number of overall misses -system.l2c.overall_misses::cpu1.data 12102 # number of overall misses -system.l2c.overall_misses::total 1066180 # number of overall misses -system.l2c.Writeback_accesses::writebacks 777520 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 777520 # number of Writeback accesses(hits+misses) +system.l2c.ReadExReq_misses::total 124943 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 11848 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 1656 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 13504 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 926615 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 1035 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 927650 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.inst 11848 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 1040489 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1656 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 12104 # number of demand (read+write) misses +system.l2c.demand_misses::total 1066097 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 11848 # number of overall misses +system.l2c.overall_misses::cpu0.data 1040489 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1656 # number of overall misses +system.l2c.overall_misses::cpu1.data 12104 # number of overall misses +system.l2c.overall_misses::total 1066097 # number of overall misses +system.l2c.WritebackDirty_accesses::writebacks 777519 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 777519 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 719211 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 719211 # number of WritebackClean accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 3122 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 2751 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 5873 # number of UpgradeReq accesses(hits+misses) @@ -848,25 +856,25 @@ system.l2c.UpgradeReq_miss_rate::total 0.882002 # mi system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.969472 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.988424 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 0.978587 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.505318 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.505323 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.163568 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.426393 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.019282 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004355 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.013592 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596545 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.007943 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.551073 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.019282 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.584987 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.004355 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.061208 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.358199 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.019282 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.584987 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.004355 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.061208 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.358199 # miss rate for overall accesses +system.l2c.ReadExReq_miss_rate::total 0.426396 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.019143 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004344 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.013502 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596548 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.007959 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.551076 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.019143 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.584990 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.004344 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.061219 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.358171 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.019143 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.584990 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.004344 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.061219 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.358171 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -875,47 +883,47 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 80913 # number of writebacks -system.l2c.writebacks::total 80913 # number of writebacks +system.l2c.writebacks::writebacks 80921 # number of writebacks +system.l2c.writebacks::total 80921 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 7449 # Transaction distribution -system.membus.trans_dist::ReadResp 948866 # Transaction distribution +system.membus.trans_dist::ReadResp 948782 # Transaction distribution system.membus.trans_dist::WriteReq 14588 # Transaction distribution system.membus.trans_dist::WriteResp 14588 # Transaction distribution -system.membus.trans_dist::Writeback 122433 # Transaction distribution -system.membus.trans_dist::CleanEvict 917961 # Transaction distribution -system.membus.trans_dist::UpgradeReq 19616 # Transaction distribution +system.membus.trans_dist::WritebackDirty 122441 # Transaction distribution +system.membus.trans_dist::CleanEvict 917844 # Transaction distribution +system.membus.trans_dist::UpgradeReq 19642 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 14180 # Transaction distribution -system.membus.trans_dist::UpgradeResp 8160 # Transaction distribution -system.membus.trans_dist::ReadExReq 126472 # Transaction distribution -system.membus.trans_dist::ReadExResp 124247 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 941417 # Transaction distribution +system.membus.trans_dist::UpgradeResp 8186 # Transaction distribution +system.membus.trans_dist::ReadExReq 126447 # Transaction distribution +system.membus.trans_dist::ReadExResp 124222 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 941333 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 44074 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3174012 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3218086 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3173737 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3217811 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124995 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124995 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3343081 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3342806 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 86162 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73369472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 73455634 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73363008 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 73449170 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2668736 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2668736 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 76124370 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 76117906 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2205834 # Request fanout histogram +system.membus.snoop_fanout::samples 2205642 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2205834 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2205642 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2205834 # Request fanout histogram +system.membus.snoop_fanout::total 2205642 # Request fanout histogram system.toL2Bus.snoop_filter.tot_requests 6035921 # Total number of requests made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_requests 3018741 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_requests 376832 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -926,8 +934,9 @@ system.toL2Bus.trans_dist::ReadReq 7449 # Tr system.toL2Bus.trans_dist::ReadResp 2732182 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 14588 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 777520 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1862622 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 777519 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 719211 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1143412 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 19614 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 14230 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 33844 # Transaction distribution @@ -940,17 +949,17 @@ system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5 system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1014431 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 661358 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count::total 8791862 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39612480 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155758075 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24397568 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 69513536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155758011 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 40526016 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23357975 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 243126098 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1083281 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 7141075 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.106201 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.308342 # Request fanout histogram +system.toL2Bus.pkt_size::total 289155538 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1083512 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 7141306 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.106198 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.308338 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 6383226 89.39% 89.39% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 6383457 89.39% 89.39% # Request fanout histogram system.toL2Bus.snoop_fanout::1 757309 10.60% 99.99% # Request fanout histogram system.toL2Bus.snoop_fanout::2 538 0.01% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram @@ -958,7 +967,7 @@ system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Re system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 7141075 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 7141306 # Request fanout histogram system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 34e6d6348..3a45545f2 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -4,42 +4,42 @@ sim_seconds 1.829332 # Nu sim_ticks 1829332273500 # Number of ticks simulated final_tick 1829332273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2390951 # Simulator instruction rate (inst/s) -host_op_rate 2390950 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 72850763127 # Simulator tick rate (ticks/s) -host_mem_usage 374092 # Number of bytes of host memory used -host_seconds 25.11 # Real time elapsed on the host +host_inst_rate 2238603 # Simulator instruction rate (inst/s) +host_op_rate 2238602 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68208828665 # Simulator tick rate (ticks/s) +host_mem_usage 373932 # Number of bytes of host memory used +host_seconds 26.82 # Real time elapsed on the host sim_insts 60038341 # Number of instructions simulated sim_ops 60038341 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 856000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 66836224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 850496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 66835456 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 67693184 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 856000 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 856000 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7414144 # Number of bytes written to this memory -system.physmem.bytes_written::total 7414144 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13375 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1044316 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 67686912 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 850496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 850496 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7416128 # Number of bytes written to this memory +system.physmem.bytes_written::total 7416128 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13289 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1044304 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1057706 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115846 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115846 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 467930 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 36535858 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 1057608 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115877 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115877 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 464922 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 36535438 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 37004313 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 467930 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 467930 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4052924 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4052924 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4052924 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 467930 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 36535858 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 37000884 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 464922 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 464922 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4054008 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4054008 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4054008 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 464922 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 36535438 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 525 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 41057237 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 41054893 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -76,61 +76,6 @@ system.cpu.itb.data_accesses 0 # DT system.cpu.numCycles 3658670905 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60038341 # Number of instructions committed -system.cpu.committedOps 60038341 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 55913563 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses -system.cpu.num_func_calls 1484182 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7110761 # number of instructions that are conditional controls -system.cpu.num_int_insts 55913563 # number of integer instructions -system.cpu.num_fp_insts 324460 # number of float instructions -system.cpu.num_int_register_reads 76954014 # number of times the integer registers were read -system.cpu.num_int_register_writes 41740254 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written -system.cpu.num_mem_refs 16115702 # number of memory refs -system.cpu.num_load_insts 9747508 # Number of load instructions -system.cpu.num_store_insts 6368194 # Number of store instructions -system.cpu.num_idle_cycles 3598621691.055137 # Number of idle cycles -system.cpu.num_busy_cycles 60049213.944863 # Number of busy cycles -system.cpu.not_idle_fraction 0.016413 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.983587 # Percentage of idle cycles -system.cpu.Branches 9064400 # Number of branches fetched -system.cpu.op_class::No_OpClass 3199098 5.33% 5.33% # Class of executed instruction -system.cpu.op_class::IntAlu 39448273 65.69% 71.02% # Class of executed instruction -system.cpu.op_class::IntMult 60677 0.10% 71.12% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction -system.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 71.18% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 71.18% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 71.18% # Class of executed instruction -system.cpu.op_class::FloatDiv 3636 0.01% 71.19% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::MemRead 9975076 16.61% 87.80% # Class of executed instruction -system.cpu.op_class::MemWrite 6374115 10.61% 98.42% # Class of executed instruction -system.cpu.op_class::IprAccess 951217 1.58% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 60050179 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed @@ -216,6 +161,61 @@ system.cpu.kern.mode_ticks::kernel 26833319500 1.47% 1.47% # nu system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode system.cpu.kern.mode_ticks::idle 1801033671500 98.45% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed +system.cpu.committedInsts 60038341 # Number of instructions committed +system.cpu.committedOps 60038341 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 55913563 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses +system.cpu.num_func_calls 1484182 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7110761 # number of instructions that are conditional controls +system.cpu.num_int_insts 55913563 # number of integer instructions +system.cpu.num_fp_insts 324460 # number of float instructions +system.cpu.num_int_register_reads 76954014 # number of times the integer registers were read +system.cpu.num_int_register_writes 41740254 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written +system.cpu.num_mem_refs 16115702 # number of memory refs +system.cpu.num_load_insts 9747508 # Number of load instructions +system.cpu.num_store_insts 6368194 # Number of store instructions +system.cpu.num_idle_cycles 3598621691.055137 # Number of idle cycles +system.cpu.num_busy_cycles 60049213.944863 # Number of busy cycles +system.cpu.not_idle_fraction 0.016413 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.983587 # Percentage of idle cycles +system.cpu.Branches 9064400 # Number of branches fetched +system.cpu.op_class::No_OpClass 3199098 5.33% 5.33% # Class of executed instruction +system.cpu.op_class::IntAlu 39448273 65.69% 71.02% # Class of executed instruction +system.cpu.op_class::IntMult 60677 0.10% 71.12% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction +system.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 71.18% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 71.18% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 71.18% # Class of executed instruction +system.cpu.op_class::FloatDiv 3636 0.01% 71.19% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::MemRead 9975076 16.61% 87.80% # Class of executed instruction +system.cpu.op_class::MemWrite 6374115 10.61% 98.42% # Class of executed instruction +system.cpu.op_class::IprAccess 951217 1.58% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 60050179 # Class of executed instruction system.cpu.dcache.tags.replacements 2042728 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 14038398 # Total number of references to valid blocks. @@ -284,8 +284,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 833493 # number of writebacks -system.cpu.dcache.writebacks::total 833493 # number of writebacks +system.cpu.dcache.writebacks::writebacks 833492 # number of writebacks +system.cpu.dcache.writebacks::total 833492 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 919605 # number of replacements system.cpu.icache.tags.tagsinuse 511.215260 # Cycle average of tags in use @@ -335,19 +335,21 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 919605 # number of writebacks +system.cpu.icache.writebacks::total 919605 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 992219 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65424.374112 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4560066 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1057382 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.312600 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 992425 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65424.374115 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4560164 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1057588 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.311853 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 56252.896873 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4923.444270 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4248.032969 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.858351 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.075126 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.064820 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 56331.555575 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4843.320500 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 4249.498040 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.859551 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073903 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.064842 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 781 # Occupied blocks per task id @@ -356,40 +358,44 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4024 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3053 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54045 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 48753828 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 48753828 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 833493 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 833493 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 48754034 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 48754034 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 833492 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 833492 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 919353 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 919353 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 187288 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 187288 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 906839 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 906839 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 811246 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 811246 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 906839 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 998534 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1905373 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 906839 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 998534 # number of overall hits -system.cpu.l2cache.overall_hits::total 1905373 # number of overall hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 906925 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 906925 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 811243 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 811243 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 906925 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 998531 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1905456 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 906925 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 998531 # number of overall hits +system.cpu.l2cache.overall_hits::total 1905456 # number of overall hits system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 117066 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 117066 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13375 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 13375 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 927641 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 927641 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 13375 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1044707 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1058082 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 13375 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1044707 # number of overall misses -system.cpu.l2cache.overall_misses::total 1058082 # number of overall misses -system.cpu.l2cache.Writeback_accesses::writebacks 833493 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 833493 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13289 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 13289 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 927644 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 927644 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 13289 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1044710 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1057999 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 13289 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1044710 # number of overall misses +system.cpu.l2cache.overall_misses::total 1057999 # number of overall misses +system.cpu.l2cache.WritebackDirty_accesses::writebacks 833492 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 833492 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 919353 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 919353 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 304354 # number of ReadExReq accesses(hits+misses) @@ -408,16 +414,16 @@ system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384638 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.384638 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014535 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014535 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.533468 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.533468 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014535 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.511299 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.357043 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014535 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.511299 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.357043 # miss rate for overall accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014441 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014441 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.533470 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.533470 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014441 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.511300 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.357015 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014441 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.511300 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.357015 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -426,8 +432,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 74334 # number of writebacks -system.cpu.l2cache.writebacks::total 74334 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 74365 # number of writebacks +system.cpu.l2cache.writebacks::total 74365 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 5925822 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2962455 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -439,8 +445,9 @@ system.cpu.toL2Bus.trans_dist::ReadReq 7184 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 2666303 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 833493 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2127019 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 833492 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 919353 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1207667 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 304354 # Transaction distribution @@ -450,21 +457,21 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 1738887 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2759817 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6161717 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 8921534 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58894848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184157102 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 243051950 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1075788 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 7018475 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 117733440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184157038 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 301890478 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1075994 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 7018681 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.000744 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.027269 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 7013252 99.93% 99.93% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 7013458 99.93% 99.93% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 5223 0.07% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 7018475 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 7018681 # Request fanout histogram system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -563,42 +570,42 @@ system.iocache.writebacks::writebacks 41512 # nu system.iocache.writebacks::total 41512 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 7184 # Transaction distribution -system.membus.trans_dist::ReadResp 948374 # Transaction distribution +system.membus.trans_dist::ReadResp 948291 # Transaction distribution system.membus.trans_dist::WriteReq 9838 # Transaction distribution system.membus.trans_dist::WriteResp 9838 # Transaction distribution -system.membus.trans_dist::Writeback 115846 # Transaction distribution -system.membus.trans_dist::CleanEvict 917156 # Transaction distribution -system.membus.trans_dist::UpgradeReq 132 # Transaction distribution -system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 116946 # Transaction distribution -system.membus.trans_dist::ReadExResp 116946 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 941190 # Transaction distribution +system.membus.trans_dist::WritebackDirty 115877 # Transaction distribution +system.membus.trans_dist::CleanEvict 917027 # Transaction distribution +system.membus.trans_dist::UpgradeReq 147 # Transaction distribution +system.membus.trans_dist::UpgradeResp 147 # Transaction distribution +system.membus.trans_dist::ReadExReq 116931 # Transaction distribution +system.membus.trans_dist::ReadExResp 116931 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 941107 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3107665 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3141709 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3107401 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3141445 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124977 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124977 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3266686 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3266422 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72466944 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72513070 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72462656 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72508782 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2667904 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2667904 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 75180974 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 75176686 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2150005 # Request fanout histogram +system.membus.snoop_fanout::samples 2149824 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2150005 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2149824 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2150005 # Request fanout histogram +system.membus.snoop_fanout::total 2149824 # Request fanout histogram system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 69fe46592..ce1bb41a0 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,118 +1,118 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.982585 # Number of seconds simulated -sim_ticks 1982585357000 # Number of ticks simulated -final_tick 1982585357000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.977709 # Number of seconds simulated +sim_ticks 1977709274000 # Number of ticks simulated +final_tick 1977709274000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1043358 # Simulator instruction rate (inst/s) -host_op_rate 1043358 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33918612914 # Simulator tick rate (ticks/s) -host_mem_usage 377952 # Number of bytes of host memory used -host_seconds 58.45 # Real time elapsed on the host -sim_insts 60985541 # Number of instructions simulated -sim_ops 60985541 # Number of ops (including micro ops) simulated +host_inst_rate 1549555 # Simulator instruction rate (inst/s) +host_op_rate 1549555 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51561372502 # Simulator tick rate (ticks/s) +host_mem_usage 334884 # Number of bytes of host memory used +host_seconds 38.36 # Real time elapsed on the host +sim_insts 59435338 # Number of instructions simulated +sim_ops 59435338 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 804544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24689088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 59456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 522432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 694336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 23907392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 165888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1310592 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26076480 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 804544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 59456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 864000 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7738240 # Number of bytes written to this memory -system.physmem.bytes_written::total 7738240 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12571 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 385767 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 929 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8163 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26079168 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 694336 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 165888 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 860224 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7747712 # Number of bytes written to this memory +system.physmem.bytes_written::total 7747712 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 10849 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 373553 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2592 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 20478 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 407445 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120910 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120910 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 405805 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12452976 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 29989 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 263510 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 484 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13152765 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 405805 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 29989 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 435795 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3903106 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3903106 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3903106 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 405805 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12452976 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 29989 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 263510 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 484 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17055871 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 407445 # Number of read requests accepted -system.physmem.writeReqs 120910 # Number of write requests accepted -system.physmem.readBursts 407445 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 120910 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26068672 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7808 # Total number of bytes read from write queue -system.physmem.bytesWritten 7736640 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26076480 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7738240 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 122 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 407487 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 121058 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121058 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 351081 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12088426 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 83879 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 662682 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 485 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13186553 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 351081 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 83879 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 434960 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3917518 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3917518 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3917518 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 351081 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12088426 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 83879 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 662682 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17104071 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 407487 # Number of read requests accepted +system.physmem.writeReqs 121058 # Number of write requests accepted +system.physmem.readBursts 407487 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 121058 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26071296 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7872 # Total number of bytes read from write queue +system.physmem.bytesWritten 7746112 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26079168 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7747712 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 123 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 48696 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25232 # Per bank write bursts -system.physmem.perBankRdBursts::1 25377 # Per bank write bursts -system.physmem.perBankRdBursts::2 25433 # Per bank write bursts -system.physmem.perBankRdBursts::3 24853 # Per bank write bursts -system.physmem.perBankRdBursts::4 25156 # Per bank write bursts -system.physmem.perBankRdBursts::5 25421 # Per bank write bursts -system.physmem.perBankRdBursts::6 25501 # Per bank write bursts -system.physmem.perBankRdBursts::7 25341 # Per bank write bursts -system.physmem.perBankRdBursts::8 25248 # Per bank write bursts -system.physmem.perBankRdBursts::9 25578 # Per bank write bursts -system.physmem.perBankRdBursts::10 25745 # Per bank write bursts -system.physmem.perBankRdBursts::11 25922 # Per bank write bursts -system.physmem.perBankRdBursts::12 25991 # Per bank write bursts -system.physmem.perBankRdBursts::13 25558 # Per bank write bursts -system.physmem.perBankRdBursts::14 25312 # Per bank write bursts -system.physmem.perBankRdBursts::15 25655 # Per bank write bursts -system.physmem.perBankWrBursts::0 7850 # Per bank write bursts -system.physmem.perBankWrBursts::1 7774 # Per bank write bursts -system.physmem.perBankWrBursts::2 7467 # Per bank write bursts -system.physmem.perBankWrBursts::3 6887 # Per bank write bursts -system.physmem.perBankWrBursts::4 7102 # Per bank write bursts -system.physmem.perBankWrBursts::5 7345 # Per bank write bursts -system.physmem.perBankWrBursts::6 7434 # Per bank write bursts -system.physmem.perBankWrBursts::7 7145 # Per bank write bursts -system.physmem.perBankWrBursts::8 7156 # Per bank write bursts -system.physmem.perBankWrBursts::9 7306 # Per bank write bursts -system.physmem.perBankWrBursts::10 7741 # Per bank write bursts -system.physmem.perBankWrBursts::11 8153 # Per bank write bursts -system.physmem.perBankWrBursts::12 8257 # Per bank write bursts -system.physmem.perBankWrBursts::13 7909 # Per bank write bursts -system.physmem.perBankWrBursts::14 7539 # Per bank write bursts -system.physmem.perBankWrBursts::15 7820 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 306935 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25840 # Per bank write bursts +system.physmem.perBankRdBursts::1 26009 # Per bank write bursts +system.physmem.perBankRdBursts::2 26271 # Per bank write bursts +system.physmem.perBankRdBursts::3 25739 # Per bank write bursts +system.physmem.perBankRdBursts::4 24904 # Per bank write bursts +system.physmem.perBankRdBursts::5 25588 # Per bank write bursts +system.physmem.perBankRdBursts::6 25282 # Per bank write bursts +system.physmem.perBankRdBursts::7 25179 # Per bank write bursts +system.physmem.perBankRdBursts::8 24919 # Per bank write bursts +system.physmem.perBankRdBursts::9 24911 # Per bank write bursts +system.physmem.perBankRdBursts::10 25224 # Per bank write bursts +system.physmem.perBankRdBursts::11 25266 # Per bank write bursts +system.physmem.perBankRdBursts::12 25817 # Per bank write bursts +system.physmem.perBankRdBursts::13 25627 # Per bank write bursts +system.physmem.perBankRdBursts::14 25517 # Per bank write bursts +system.physmem.perBankRdBursts::15 25271 # Per bank write bursts +system.physmem.perBankWrBursts::0 8076 # Per bank write bursts +system.physmem.perBankWrBursts::1 7966 # Per bank write bursts +system.physmem.perBankWrBursts::2 8289 # Per bank write bursts +system.physmem.perBankWrBursts::3 8035 # Per bank write bursts +system.physmem.perBankWrBursts::4 7145 # Per bank write bursts +system.physmem.perBankWrBursts::5 7755 # Per bank write bursts +system.physmem.perBankWrBursts::6 7349 # Per bank write bursts +system.physmem.perBankWrBursts::7 7181 # Per bank write bursts +system.physmem.perBankWrBursts::8 6971 # Per bank write bursts +system.physmem.perBankWrBursts::9 7004 # Per bank write bursts +system.physmem.perBankWrBursts::10 7220 # Per bank write bursts +system.physmem.perBankWrBursts::11 7086 # Per bank write bursts +system.physmem.perBankWrBursts::12 7863 # Per bank write bursts +system.physmem.perBankWrBursts::13 7891 # Per bank write bursts +system.physmem.perBankWrBursts::14 7798 # Per bank write bursts +system.physmem.perBankWrBursts::15 7404 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 21 # Number of times write queue was full causing retry -system.physmem.totGap 1982577992500 # Total gap between requests +system.physmem.numWrRetry 19 # Number of times write queue was full causing retry +system.physmem.totGap 1977655892500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 407445 # Read request sizes (log2) +system.physmem.readPktSize::6 407487 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 120910 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 407244 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66 # What read queue length does an incoming req see +system.physmem.writePktSize::6 121058 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 407280 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 71 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see @@ -158,177 +158,187 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5744 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6708 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7869 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7617 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5590 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 70 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 67564 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 500.345036 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 302.441164 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 405.330516 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16348 24.20% 24.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 12278 18.17% 42.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5298 7.84% 50.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3150 4.66% 54.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2433 3.60% 58.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4298 6.36% 64.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1531 2.27% 67.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2195 3.25% 70.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20033 29.65% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 67564 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5409 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 75.303198 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2854.593157 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5406 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1864 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8012 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5620 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 65 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 68003 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 497.292884 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 300.084252 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 405.105473 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16504 24.27% 24.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 12590 18.51% 42.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5294 7.78% 50.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3182 4.68% 55.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2479 3.65% 58.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4294 6.31% 65.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1483 2.18% 67.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2078 3.06% 70.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20099 29.56% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 68003 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5421 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 75.144069 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2865.262786 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5418 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5409 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5409 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.348863 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.981514 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.757339 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4806 88.85% 88.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 190 3.51% 92.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 24 0.44% 92.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 50 0.92% 93.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 37 0.68% 94.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 6 0.11% 94.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 18 0.33% 94.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 42 0.78% 95.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 29 0.54% 96.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 3 0.06% 96.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 162 3.00% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 1 0.02% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 4 0.07% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 3 0.06% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 2 0.04% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 2 0.04% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 4 0.07% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 6 0.11% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 10 0.18% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 2 0.04% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 2 0.04% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 4 0.07% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::312-319 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5409 # Writes before turning the bus around for reads -system.physmem.totQLat 2792890500 # Total ticks spent queuing -system.physmem.totMemAccLat 10430196750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2036615000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6856.70 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5421 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5421 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.326692 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.006479 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.134399 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4779 88.16% 88.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 22 0.41% 88.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 23 0.42% 88.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 175 3.23% 92.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 9 0.17% 92.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 25 0.46% 92.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 50 0.92% 93.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 2 0.04% 93.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 13 0.24% 94.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 19 0.35% 94.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.02% 94.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 6 0.11% 94.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 8 0.15% 94.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 2 0.04% 94.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 22 0.41% 95.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 20 0.37% 95.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 4 0.07% 95.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 34 0.63% 96.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.02% 96.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.04% 96.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 161 2.97% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.04% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.02% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 3 0.06% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.04% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.02% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 6 0.11% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 5 0.09% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 3 0.06% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.02% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 16 0.30% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::252-255 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5421 # Writes before turning the bus around for reads +system.physmem.totQLat 2796894000 # Total ticks spent queuing +system.physmem.totMemAccLat 10434969000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2036820000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6865.83 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25606.70 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.15 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.90 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.15 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.90 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 25615.83 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.18 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.92 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.19 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.92 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.13 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.01 # Average write queue length when enqueuing -system.physmem.readRowHits 363877 # Number of row buffer hits during reads -system.physmem.writeRowHits 96767 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.33 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.03 # Row buffer hit rate for writes -system.physmem.avgGap 3752359.67 # Average gap between requests -system.physmem.pageHitRate 87.20 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 243303480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 132754875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1578049200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 382345920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 129492598560 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 72929786580 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1125575674500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1330334513115 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.011108 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1872213779250 # Time in different power states -system.physmem_0.memoryStateTime::REF 66202760000 # Time in different power states +system.physmem.avgWrQLen 25.07 # Average write queue length when enqueuing +system.physmem.readRowHits 363824 # Number of row buffer hits during reads +system.physmem.writeRowHits 96570 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.31 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.77 # Row buffer hit rate for writes +system.physmem.avgGap 3741698.23 # Average gap between requests +system.physmem.pageHitRate 87.13 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 262483200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 143220000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1597533600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 400438080 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 129174240000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 73962048600 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1121745657750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1327285621230 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.123235 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1865834845500 # Time in different power states +system.physmem_0.memoryStateTime::REF 66040000000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 44165427000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 45832914500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 267480360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 145946625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1599070200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 400988880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 129492598560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 74043413820 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1124598800250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1330548298695 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.118945 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1870589115500 # Time in different power states -system.physmem_1.memoryStateTime::REF 66202760000 # Time in different power states +system.physmem_1.actEnergy 251619480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 137292375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1579905600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 383855760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 129174240000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 73584887580 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1122076500750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1327188301545 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.074027 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1866389529250 # Time in different power states +system.physmem_1.memoryStateTime::REF 66040000000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 45790077000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 45278230750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7416955 # DTB read hits +system.cpu0.dtb.read_hits 5727753 # DTB read hits system.cpu0.dtb.read_misses 7442 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 490672 # DTB read accesses -system.cpu0.dtb.write_hits 5004564 # DTB write hits +system.cpu0.dtb.write_hits 3981122 # DTB write hits system.cpu0.dtb.write_misses 812 # DTB write misses system.cpu0.dtb.write_acv 134 # DTB write access violations system.cpu0.dtb.write_accesses 187451 # DTB write accesses -system.cpu0.dtb.data_hits 12421519 # DTB hits +system.cpu0.dtb.data_hits 9708875 # DTB hits system.cpu0.dtb.data_misses 8254 # DTB misses system.cpu0.dtb.data_acv 344 # DTB access violations system.cpu0.dtb.data_accesses 678123 # DTB accesses -system.cpu0.itb.fetch_hits 3482641 # ITB hits +system.cpu0.itb.fetch_hits 3124468 # ITB hits system.cpu0.itb.fetch_misses 3871 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3486512 # ITB accesses +system.cpu0.itb.fetch_accesses 3128339 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -341,91 +351,36 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3964851833 # number of cpu cycles simulated +system.cpu0.numCycles 3955086246 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 47325532 # Number of instructions committed -system.cpu0.committedOps 47325532 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 43895499 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 207106 # Number of float alu accesses -system.cpu0.num_func_calls 1185742 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5567031 # number of instructions that are conditional controls -system.cpu0.num_int_insts 43895499 # number of integer instructions -system.cpu0.num_fp_insts 207106 # number of float instructions -system.cpu0.num_int_register_reads 60349527 # number of times the integer registers were read -system.cpu0.num_int_register_writes 32725613 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 100583 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 102386 # number of times the floating registers were written -system.cpu0.num_mem_refs 12461430 # number of memory refs -system.cpu0.num_load_insts 7443904 # Number of load instructions -system.cpu0.num_store_insts 5017526 # Number of store instructions -system.cpu0.num_idle_cycles 3700363584.987226 # Number of idle cycles -system.cpu0.num_busy_cycles 264488248.012774 # Number of busy cycles -system.cpu0.not_idle_fraction 0.066708 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.933292 # Percentage of idle cycles -system.cpu0.Branches 7135463 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2703242 5.71% 5.71% # Class of executed instruction -system.cpu0.op_class::IntAlu 31183402 65.88% 71.59% # Class of executed instruction -system.cpu0.op_class::IntMult 51823 0.11% 71.70% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.70% # Class of executed instruction -system.cpu0.op_class::FloatAdd 25571 0.05% 71.75% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1656 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::MemRead 7617030 16.09% 87.85% # Class of executed instruction -system.cpu0.op_class::MemWrite 5023630 10.61% 98.46% # Class of executed instruction -system.cpu0.op_class::IprAccess 727776 1.54% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 47334130 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6807 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 162813 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 55930 40.12% 40.12% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 133 0.10% 40.21% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1978 1.42% 41.63% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 435 0.31% 41.94% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 80947 58.06% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 139423 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 55420 49.07% 49.07% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 133 0.12% 49.18% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1978 1.75% 50.93% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 435 0.39% 51.32% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 54986 48.68% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 112952 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1904955657000 96.09% 96.09% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 92166000 0.00% 96.10% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 765642500 0.04% 96.14% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 319863500 0.02% 96.15% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 76292557500 3.85% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1982425886500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.990881 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 4843 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 129735 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 41337 38.33% 38.33% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.12% 38.45% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1972 1.83% 40.28% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 17 0.02% 40.29% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 64391 59.71% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 107848 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 40894 48.75% 48.75% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.16% 48.90% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1972 2.35% 51.25% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 17 0.02% 51.27% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 40877 48.73% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 83891 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1907093255000 96.44% 96.44% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 94033500 0.00% 96.44% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 783814000 0.04% 96.48% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 14262000 0.00% 96.48% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 69557728500 3.52% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1977543093000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.989283 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.679284 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810139 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.634825 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.777863 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed @@ -457,124 +412,179 @@ system.cpu0.kern.syscall::144 2 0.90% 99.10% # nu system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 222 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 523 0.35% 0.35% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3026 2.05% 2.41% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed -system.cpu0.kern.callpal::swpipl 132550 89.80% 92.24% # number of callpals executed -system.cpu0.kern.callpal::rdps 6593 4.47% 96.71% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.71% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.71% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.72% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.72% # number of callpals executed -system.cpu0.kern.callpal::rti 4327 2.93% 99.65% # number of callpals executed -system.cpu0.kern.callpal::callsys 381 0.26% 99.91% # number of callpals executed -system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 147613 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6866 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1281 # number of protection mode switches +system.cpu0.kern.callpal::wripir 93 0.08% 0.08% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.08% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.08% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.08% # number of callpals executed +system.cpu0.kern.callpal::swpctx 1998 1.74% 1.82% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.04% 1.87% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.01% 1.87% # number of callpals executed +system.cpu0.kern.callpal::swpipl 101884 88.63% 90.50% # number of callpals executed +system.cpu0.kern.callpal::rdps 6548 5.70% 96.19% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.20% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.20% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.21% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.21% # number of callpals executed +system.cpu0.kern.callpal::rti 3843 3.34% 99.55% # number of callpals executed +system.cpu0.kern.callpal::callsys 381 0.33% 99.88% # number of callpals executed +system.cpu0.kern.callpal::imb 136 0.12% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 114960 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 5413 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1282 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1281 -system.cpu0.kern.mode_good::user 1281 +system.cpu0.kern.mode_good::kernel 1282 +system.cpu0.kern.mode_good::user 1282 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.186572 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.236837 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.314472 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1977675856500 99.80% 99.80% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3900112000 0.20% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.382972 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1972827474000 99.80% 99.80% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3894173000 0.20% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3027 # number of times the context was actually changed -system.cpu0.dcache.tags.replacements 1172695 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.333942 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11237582 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1173114 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.579275 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 143226500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.333942 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986980 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986980 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 419 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 371 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.818359 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 50910847 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 50910847 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6343242 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6343242 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4601243 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4601243 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138155 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 138155 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145460 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 145460 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10944485 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10944485 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10944485 # number of overall hits -system.cpu0.dcache.overall_hits::total 10944485 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 934191 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 934191 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 249028 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 249028 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13578 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13578 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5734 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5734 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1183219 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1183219 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1183219 # number of overall misses -system.cpu0.dcache.overall_misses::total 1183219 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 42879044000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 42879044000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 16797420000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 16797420000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 151036000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 151036000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 96889000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 96889000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 59676464000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 59676464000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 59676464000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 59676464000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7277433 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7277433 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4850271 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4850271 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 151733 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 151733 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 151194 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 151194 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12127704 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12127704 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12127704 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12127704 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.128368 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.128368 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051343 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051343 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.089486 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.089486 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037925 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037925 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097563 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.097563 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097563 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097563 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 45899.654353 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 45899.654353 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 67451.933116 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 67451.933116 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11123.582265 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11123.582265 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 16897.279386 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16897.279386 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50435.687730 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 50435.687730 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50435.687730 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 50435.687730 # average overall miss latency +system.cpu0.kern.swap_context 1999 # number of times the context was actually changed +system.cpu0.committedInsts 36251265 # Number of instructions committed +system.cpu0.committedOps 36251265 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33727452 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 135758 # Number of float alu accesses +system.cpu0.num_func_calls 876834 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4248905 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33727452 # number of integer instructions +system.cpu0.num_fp_insts 135758 # number of float instructions +system.cpu0.num_int_register_reads 46333717 # number of times the integer registers were read +system.cpu0.num_int_register_writes 25193797 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 65701 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 66416 # number of times the floating registers were written +system.cpu0.num_mem_refs 9739707 # number of memory refs +system.cpu0.num_load_insts 5749561 # Number of load instructions +system.cpu0.num_store_insts 3990146 # Number of store instructions +system.cpu0.num_idle_cycles 3736968981.972937 # Number of idle cycles +system.cpu0.num_busy_cycles 218117264.027063 # Number of busy cycles +system.cpu0.not_idle_fraction 0.055149 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.944851 # Percentage of idle cycles +system.cpu0.Branches 5398761 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1979626 5.46% 5.46% # Class of executed instruction +system.cpu0.op_class::IntAlu 23753610 65.51% 70.97% # Class of executed instruction +system.cpu0.op_class::IntMult 36908 0.10% 71.07% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 71.07% # Class of executed instruction +system.cpu0.op_class::FloatAdd 22960 0.06% 71.13% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 71.13% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 71.13% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 71.13% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1656 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::MemRead 5882505 16.22% 87.36% # Class of executed instruction +system.cpu0.op_class::MemWrite 3995282 11.02% 98.38% # Class of executed instruction +system.cpu0.op_class::IprAccess 587316 1.62% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 36259863 # Class of executed instruction +system.cpu0.dcache.tags.replacements 822072 # number of replacements +system.cpu0.dcache.tags.tagsinuse 480.504845 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 8885001 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 822496 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 10.802485 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 144706500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.504845 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938486 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.938486 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 424 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 167 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 257 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.828125 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 39682070 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 39682070 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 5000163 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5000163 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3644006 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3644006 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117543 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 117543 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 123259 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 123259 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8644169 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8644169 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8644169 # number of overall hits +system.cpu0.dcache.overall_hits::total 8644169 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 612538 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 612538 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 209263 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 209263 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6851 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 6851 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 636 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 636 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 821801 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 821801 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 821801 # number of overall misses +system.cpu0.dcache.overall_misses::total 821801 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 38657814000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 38657814000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 14917066000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 14917066000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 93675500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 93675500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 8969500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 8969500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 53574880000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 53574880000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 53574880000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 53574880000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5612701 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 5612701 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 3853269 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 3853269 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 124394 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 124394 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 123895 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 123895 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 9465970 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 9465970 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 9465970 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 9465970 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.109134 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.109134 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.054308 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.054308 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055075 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055075 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.005133 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.005133 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.086816 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.086816 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.086816 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.086816 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 63110.882917 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 63110.882917 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 71283.819882 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 71283.819882 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13673.259378 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13673.259378 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 14102.987421 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14102.987421 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 65192.035541 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 65192.035541 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 65192.035541 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 65192.035541 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -583,126 +593,126 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 672708 # number of writebacks -system.cpu0.dcache.writebacks::total 672708 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 934191 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 934191 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249028 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 249028 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13578 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13578 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5734 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 5734 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1183219 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1183219 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1183219 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1183219 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7086 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7086 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10784 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10784 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17870 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17870 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 41944853000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 41944853000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 16548392000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 16548392000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 137458000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137458000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 91155000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 91155000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 58493245000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 58493245000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 58493245000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 58493245000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1488672000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1488672000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2316060500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2316060500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3804732500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3804732500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128368 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128368 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051343 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051343 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.089486 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.089486 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037925 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037925 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097563 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097563 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097563 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097563 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 44899.654353 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 44899.654353 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 66451.933116 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 66451.933116 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10123.582265 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10123.582265 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 15897.279386 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15897.279386 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 49435.687730 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 49435.687730 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 49435.687730 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 49435.687730 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210086.367485 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210086.367485 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 214768.221439 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 214768.221439 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 212911.723559 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 212911.723559 # average overall mshr uncacheable latency +system.cpu0.dcache.writebacks::writebacks 366665 # number of writebacks +system.cpu0.dcache.writebacks::total 366665 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 612538 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 612538 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 209263 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 209263 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6851 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6851 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 636 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 636 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 821801 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 821801 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 821801 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 821801 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 4814 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 4814 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 8193 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 8193 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 13007 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 13007 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 38045276000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 38045276000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 14707803000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 14707803000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 86824500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 86824500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 8333500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 8333500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 52753079000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 52753079000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 52753079000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 52753079000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1072338000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1072338000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1840159000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1840159000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2912497000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2912497000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.109134 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.109134 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.054308 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.054308 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055075 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.055075 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.005133 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.005133 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.086816 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.086816 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.086816 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.086816 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 62110.882917 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 62110.882917 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 70283.819882 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 70283.819882 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12673.259378 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12673.259378 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13102.987421 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13102.987421 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 64192.035541 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 64192.035541 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 64192.035541 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 64192.035541 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222754.050686 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222754.050686 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 224601.367021 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224601.367021 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 223917.659722 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 223917.659722 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 686863 # number of replacements -system.cpu0.icache.tags.tagsinuse 506.493433 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 46646633 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 687375 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.861987 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 58997592500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 506.493433 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.989245 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.989245 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 490042 # number of replacements +system.cpu0.icache.tags.tagsinuse 506.476572 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 35769214 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 490554 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 72.915956 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 58998281500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 506.476572 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.989212 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.989212 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 417 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 216 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 296 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 48021627 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 48021627 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 46646633 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 46646633 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 46646633 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 46646633 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 46646633 # number of overall hits -system.cpu0.icache.overall_hits::total 46646633 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 687497 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 687497 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 687497 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 687497 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 687497 # number of overall misses -system.cpu0.icache.overall_misses::total 687497 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10629492500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10629492500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10629492500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10629492500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10629492500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10629492500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47334130 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47334130 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47334130 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47334130 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47334130 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47334130 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014524 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014524 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014524 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014524 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014524 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014524 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15461.147467 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 15461.147467 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15461.147467 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 15461.147467 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15461.147467 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 15461.147467 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 36750512 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 36750512 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 35769214 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 35769214 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 35769214 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 35769214 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 35769214 # number of overall hits +system.cpu0.icache.overall_hits::total 35769214 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 490649 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 490649 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 490649 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 490649 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 490649 # number of overall misses +system.cpu0.icache.overall_misses::total 490649 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7808174000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 7808174000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 7808174000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 7808174000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7808174000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 7808174000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 36259863 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 36259863 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 36259863 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 36259863 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 36259863 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 36259863 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013531 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.013531 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013531 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.013531 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013531 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.013531 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15913.971087 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 15913.971087 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15913.971087 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 15913.971087 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15913.971087 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 15913.971087 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -711,51 +721,53 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 687497 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 687497 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 687497 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 687497 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 687497 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 687497 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9941995500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9941995500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9941995500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9941995500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9941995500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9941995500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014524 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014524 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014524 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14461.147467 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14461.147467 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14461.147467 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 14461.147467 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14461.147467 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 14461.147467 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 490042 # number of writebacks +system.cpu0.icache.writebacks::total 490042 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 490649 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 490649 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 490649 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 490649 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 490649 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 490649 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 7317525000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 7317525000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 7317525000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 7317525000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 7317525000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 7317525000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013531 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013531 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013531 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.013531 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013531 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.013531 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14913.971087 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14913.971087 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14913.971087 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 14913.971087 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14913.971087 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 14913.971087 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2508569 # DTB read hits +system.cpu1.dtb.read_hits 3965416 # DTB read hits system.cpu1.dtb.read_misses 2993 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 239364 # DTB read accesses -system.cpu1.dtb.write_hits 1828737 # DTB write hits +system.cpu1.dtb.write_hits 2725894 # DTB write hits system.cpu1.dtb.write_misses 342 # DTB write misses system.cpu1.dtb.write_acv 29 # DTB write access violations system.cpu1.dtb.write_accesses 105248 # DTB write accesses -system.cpu1.dtb.data_hits 4337306 # DTB hits +system.cpu1.dtb.data_hits 6691310 # DTB hits system.cpu1.dtb.data_misses 3335 # DTB misses system.cpu1.dtb.data_acv 29 # DTB access violations system.cpu1.dtb.data_accesses 344612 # DTB accesses -system.cpu1.itb.fetch_hits 1989876 # ITB hits +system.cpu1.itb.fetch_hits 2218092 # ITB hits system.cpu1.itb.fetch_misses 1216 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1991092 # ITB accesses +system.cpu1.itb.fetch_accesses 2219308 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -768,87 +780,32 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3965170714 # number of cpu cycles simulated +system.cpu1.numCycles 3955418548 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 13660009 # Number of instructions committed -system.cpu1.committedOps 13660009 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 12598388 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 178445 # Number of float alu accesses -system.cpu1.num_func_calls 429702 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1355296 # number of instructions that are conditional controls -system.cpu1.num_int_insts 12598388 # number of integer instructions -system.cpu1.num_fp_insts 178445 # number of float instructions -system.cpu1.num_int_register_reads 17340989 # number of times the integer registers were read -system.cpu1.num_int_register_writes 9240436 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 93179 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 95134 # number of times the floating registers were written -system.cpu1.num_mem_refs 4361445 # number of memory refs -system.cpu1.num_load_insts 2523214 # Number of load instructions -system.cpu1.num_store_insts 1838231 # Number of store instructions -system.cpu1.num_idle_cycles 3912374881.998026 # Number of idle cycles -system.cpu1.num_busy_cycles 52795832.001973 # Number of busy cycles -system.cpu1.not_idle_fraction 0.013315 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.986685 # Percentage of idle cycles -system.cpu1.Branches 1945174 # Number of branches fetched -system.cpu1.op_class::No_OpClass 733210 5.37% 5.37% # Class of executed instruction -system.cpu1.op_class::IntAlu 8079835 59.13% 64.50% # Class of executed instruction -system.cpu1.op_class::IntMult 22791 0.17% 64.67% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.67% # Class of executed instruction -system.cpu1.op_class::FloatAdd 14367 0.11% 64.77% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1986 0.01% 64.79% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::MemRead 2597857 19.01% 83.80% # Class of executed instruction -system.cpu1.op_class::MemWrite 1839254 13.46% 97.26% # Class of executed instruction -system.cpu1.op_class::IprAccess 374073 2.74% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 13663373 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2868 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 81018 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 27534 38.52% 38.52% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1971 2.76% 41.28% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 523 0.73% 42.01% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 41447 57.99% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 71475 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 26667 48.22% 48.22% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1971 3.56% 51.78% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 523 0.95% 52.73% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 26144 47.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 55305 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1912303307000 96.46% 96.46% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 705769500 0.04% 96.49% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 367699000 0.02% 96.51% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 69207844500 3.49% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1982584620000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.968512 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 3977 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 108865 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 40405 40.60% 40.60% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1966 1.98% 42.57% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 93 0.09% 42.67% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 57058 57.33% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 99522 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 39471 48.79% 48.79% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1966 2.43% 51.21% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 93 0.11% 51.33% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 39378 48.67% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 80908 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1902956585000 96.22% 96.22% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 734079500 0.04% 96.26% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 70449000 0.00% 96.26% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 73947425500 3.74% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1977708539000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.976884 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.630781 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.773767 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.690140 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.812966 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed @@ -864,124 +821,179 @@ system.cpu1.kern.syscall::74 10 9.62% 97.12% # nu system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 104 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 435 0.59% 0.59% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed -system.cpu1.kern.callpal::swpctx 2064 2.79% 3.38% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 3.39% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.40% # number of callpals executed -system.cpu1.kern.callpal::swpipl 65156 88.12% 91.51% # number of callpals executed -system.cpu1.kern.callpal::rdps 2261 3.06% 94.57% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.57% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 94.58% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.58% # number of callpals executed -system.cpu1.kern.callpal::rti 3824 5.17% 99.76% # number of callpals executed -system.cpu1.kern.callpal::callsys 136 0.18% 99.94% # number of callpals executed -system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 17 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed +system.cpu1.kern.callpal::swpctx 2247 2.20% 2.22% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 2.22% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.23% # number of callpals executed +system.cpu1.kern.callpal::swpipl 94014 91.97% 94.20% # number of callpals executed +system.cpu1.kern.callpal::rdps 2296 2.25% 96.44% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 96.44% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.00% 96.45% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 96.45% # number of callpals executed +system.cpu1.kern.callpal::rti 3448 3.37% 99.82% # number of callpals executed +system.cpu1.kern.callpal::callsys 136 0.13% 99.96% # number of callpals executed +system.cpu1.kern.callpal::imb 44 0.04% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 73942 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2112 # number of protection mode switches -system.cpu1.kern.mode_switch::user 464 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2921 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 911 -system.cpu1.kern.mode_good::user 464 -system.cpu1.kern.mode_good::idle 447 -system.cpu1.kern.mode_switch_good::kernel 0.431345 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 102224 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2738 # number of protection mode switches +system.cpu1.kern.mode_switch::user 463 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2043 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 518 +system.cpu1.kern.mode_good::user 463 +system.cpu1.kern.mode_good::idle 55 +system.cpu1.kern.mode_switch_good::kernel 0.189189 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.153030 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.331454 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 19415818500 0.98% 0.98% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1728972000 0.09% 1.07% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1961439827500 98.93% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 2065 # number of times the context was actually changed -system.cpu1.dcache.tags.replacements 173710 # number of replacements -system.cpu1.dcache.tags.tagsinuse 481.751289 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 4161033 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 174222 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 23.883511 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 90304766500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.751289 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.940920 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.940920 # Average percentage of cache occupancy +system.cpu1.kern.mode_switch_good::idle 0.026921 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.197559 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 70603027000 3.57% 3.57% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1708148000 0.09% 3.66% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1905397362000 96.34% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 2248 # number of times the context was actually changed +system.cpu1.committedInsts 23184073 # Number of instructions committed +system.cpu1.committedOps 23184073 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 21342235 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 193178 # Number of float alu accesses +system.cpu1.num_func_calls 708348 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2510657 # number of instructions that are conditional controls +system.cpu1.num_int_insts 21342235 # number of integer instructions +system.cpu1.num_fp_insts 193178 # number of float instructions +system.cpu1.num_int_register_reads 29195011 # number of times the integer registers were read +system.cpu1.num_int_register_writes 15673593 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 100176 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 102374 # number of times the floating registers were written +system.cpu1.num_mem_refs 6716060 # number of memory refs +system.cpu1.num_load_insts 3980976 # Number of load instructions +system.cpu1.num_store_insts 2735084 # Number of store instructions +system.cpu1.num_idle_cycles 3859200221.998049 # Number of idle cycles +system.cpu1.num_busy_cycles 96218326.001951 # Number of busy cycles +system.cpu1.not_idle_fraction 0.024326 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.975674 # Percentage of idle cycles +system.cpu1.Branches 3468812 # Number of branches fetched +system.cpu1.op_class::No_OpClass 1369332 5.91% 5.91% # Class of executed instruction +system.cpu1.op_class::IntAlu 14462485 62.37% 68.28% # Class of executed instruction +system.cpu1.op_class::IntMult 32790 0.14% 68.42% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 68.42% # Class of executed instruction +system.cpu1.op_class::FloatAdd 15288 0.07% 68.48% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 68.48% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 68.48% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 68.48% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1986 0.01% 68.49% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::MemRead 4085109 17.62% 86.11% # Class of executed instruction +system.cpu1.op_class::MemWrite 2736216 11.80% 97.91% # Class of executed instruction +system.cpu1.op_class::IprAccess 484231 2.09% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 23187437 # Class of executed instruction +system.cpu1.dcache.tags.replacements 637928 # number of replacements +system.cpu1.dcache.tags.tagsinuse 487.645459 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 6059697 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 638440 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 9.491412 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 77414441500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 487.645459 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.952433 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.952433 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 183 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 17592927 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 17592927 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2337017 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2337017 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1705874 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1705874 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 50407 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 50407 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 53062 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 53062 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 4042891 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 4042891 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 4042891 # number of overall hits -system.cpu1.dcache.overall_hits::total 4042891 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 123430 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 123430 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 65652 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 65652 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9249 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 9249 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6101 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 6101 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 189082 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 189082 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 189082 # number of overall misses -system.cpu1.dcache.overall_misses::total 189082 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1554368000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1554368000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1876323500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1876323500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 84244000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 84244000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 98989500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 98989500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 3430691500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 3430691500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 3430691500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 3430691500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2460447 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2460447 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1771526 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1771526 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 59656 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 59656 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 59163 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 59163 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4231973 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4231973 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4231973 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4231973 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050166 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.050166 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.037060 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.037060 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.155039 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.155039 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103122 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103122 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044679 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.044679 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044679 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.044679 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12593.113506 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12593.113506 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 28579.837629 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 28579.837629 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9108.444156 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9108.444156 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 16225.127028 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 16225.127028 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18143.934907 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 18143.934907 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18143.934907 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 18143.934907 # average overall miss latency +system.cpu1.dcache.tags.tag_accesses 27453473 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 27453473 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 3383453 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3383453 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 2527183 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 2527183 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 67642 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 67642 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79428 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 79428 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 5910636 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 5910636 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 5910636 # number of overall hits +system.cpu1.dcache.overall_hits::total 5910636 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 511536 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 511536 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 119772 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 119772 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 12967 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 12967 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 653 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 653 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 631308 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 631308 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 631308 # number of overall misses +system.cpu1.dcache.overall_misses::total 631308 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6625803500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 6625803500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3933748500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3933748500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 167428500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 167428500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 10386500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 10386500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 10559552000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 10559552000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 10559552000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 10559552000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3894989 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3894989 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 2646955 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 2646955 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 80609 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 80609 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 80081 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 80081 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 6541944 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 6541944 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 6541944 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 6541944 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.131332 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.131332 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.045249 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.045249 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.160863 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.160863 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.008154 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.008154 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.096502 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.096502 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.096502 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.096502 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12952.760901 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12952.760901 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32843.640417 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 32843.640417 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12911.891725 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12911.891725 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15905.819296 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 15905.819296 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16726.466321 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 16726.466321 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16726.466321 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16726.466321 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -990,128 +1002,128 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 119711 # number of writebacks -system.cpu1.dcache.writebacks::total 119711 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 123430 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 123430 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 65652 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 65652 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9249 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9249 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6101 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 6101 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 189082 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 189082 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 189082 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 189082 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 118 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 118 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3347 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3347 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3465 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3465 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1430938000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1430938000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1810671500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1810671500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74995000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74995000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 92888500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 92888500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3241609500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3241609500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3241609500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3241609500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 23714500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 23714500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 747400000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 747400000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 771114500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 771114500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050166 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050166 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.037060 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.037060 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155039 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155039 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103122 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103122 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044679 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.044679 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044679 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.044679 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11593.113506 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11593.113506 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27579.837629 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27579.837629 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8108.444156 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8108.444156 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15225.127028 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 15225.127028 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17143.934907 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17143.934907 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17143.934907 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17143.934907 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 200970.338983 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 200970.338983 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 223304.451748 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 223304.451748 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 222543.867244 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 222543.867244 # average overall mshr uncacheable latency +system.cpu1.dcache.writebacks::writebacks 496006 # number of writebacks +system.cpu1.dcache.writebacks::total 496006 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 511536 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 511536 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 119772 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 119772 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12967 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12967 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 653 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 653 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 631308 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 631308 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 631308 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 631308 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 2385 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 2385 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 4228 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 4228 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 6613 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 6613 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 6114267500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 6114267500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3813976500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3813976500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 154461500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 154461500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 9733500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 9733500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9928244000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 9928244000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9928244000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 9928244000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 520029500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 520029500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 992921500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 992921500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1512951000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1512951000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.131332 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.131332 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.045249 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.045249 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.160863 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.160863 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.008154 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.008154 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.096502 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.096502 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.096502 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.096502 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11952.760901 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11952.760901 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31843.640417 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31843.640417 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11911.891725 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11911.891725 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14905.819296 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14905.819296 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15726.466321 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15726.466321 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15726.466321 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15726.466321 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 218041.719078 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 218041.719078 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 234844.252602 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 234844.252602 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 228784.364131 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 228784.364131 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 331160 # number of replacements -system.cpu1.icache.tags.tagsinuse 442.919388 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 13331662 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 331672 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 40.195319 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1976558526500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 442.919388 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.865077 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.865077 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 510167 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.053321 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 22676720 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 510679 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 44.405037 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 117353975500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.053321 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.968854 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.968854 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 406 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 31 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 409 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 32 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 13995086 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 13995086 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 13331662 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 13331662 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 13331662 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 13331662 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 13331662 # number of overall hits -system.cpu1.icache.overall_hits::total 13331662 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 331712 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 331712 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 331712 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 331712 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 331712 # number of overall misses -system.cpu1.icache.overall_misses::total 331712 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4531331500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4531331500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4531331500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4531331500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4531331500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4531331500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13663374 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13663374 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13663374 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13663374 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13663374 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13663374 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024277 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024277 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024277 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024277 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024277 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024277 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13660.438875 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13660.438875 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13660.438875 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13660.438875 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13660.438875 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13660.438875 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 23698156 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 23698156 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 22676720 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 22676720 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 22676720 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 22676720 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 22676720 # number of overall hits +system.cpu1.icache.overall_hits::total 22676720 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 510718 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 510718 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 510718 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 510718 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 510718 # number of overall misses +system.cpu1.icache.overall_misses::total 510718 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7116614500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7116614500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7116614500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7116614500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7116614500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7116614500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 23187438 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 23187438 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 23187438 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 23187438 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 23187438 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 23187438 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022026 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.022026 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022026 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.022026 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022026 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.022026 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13934.528448 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13934.528448 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13934.528448 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13934.528448 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13934.528448 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13934.528448 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1120,30 +1132,32 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 331712 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 331712 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 331712 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 331712 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 331712 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 331712 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4199619500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4199619500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4199619500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4199619500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4199619500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4199619500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024277 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024277 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024277 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024277 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024277 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024277 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12660.438875 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12660.438875 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12660.438875 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12660.438875 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12660.438875 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12660.438875 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 510167 # number of writebacks +system.cpu1.icache.writebacks::total 510167 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 510718 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 510718 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 510718 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 510718 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 510718 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 510718 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6605896500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6605896500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6605896500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 6605896500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6605896500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 6605896500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022026 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022026 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022026 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.022026 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022026 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.022026 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12934.528448 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12934.528448 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12934.528448 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12934.528448 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12934.528448 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12934.528448 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1157,110 +1171,110 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 7379 # Transaction distribution -system.iobus.trans_dist::ReadResp 7379 # Transaction distribution -system.iobus.trans_dist::WriteReq 55683 # Transaction distribution -system.iobus.trans_dist::WriteResp 55683 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14064 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 7376 # Transaction distribution +system.iobus.trans_dist::ReadResp 7376 # Transaction distribution +system.iobus.trans_dist::WriteReq 53973 # Transaction distribution +system.iobus.trans_dist::WriteResp 53973 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10632 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2476 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 42670 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 126124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 56256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 39240 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83458 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83458 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 122698 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 42528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9884 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 82499 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2744123 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 13414000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 68786 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661640 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661640 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2730426 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 11275500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 391000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 174500 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 15840500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 2454000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 2460000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5167000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6042000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 211500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 82500 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 130500 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 215099489 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 215040242 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer30.occupancy 45000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28539000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 26819000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41950000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41954000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41695 # number of replacements -system.iocache.tags.tagsinuse 0.566806 # Cycle average of tags in use +system.iocache.tags.replacements 41699 # number of replacements +system.iocache.tags.tagsinuse 0.491123 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1775098751000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.566806 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035425 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035425 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1769281205000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.491123 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.030695 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.030695 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375543 # Number of tag accesses -system.iocache.tags.data_accesses 375543 # Number of data accesses -system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses -system.iocache.ReadReq_misses::total 175 # number of ReadReq misses +system.iocache.tags.tag_accesses 375561 # Number of tag accesses +system.iocache.tags.data_accesses 375561 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 177 # number of ReadReq misses +system.iocache.ReadReq_misses::total 177 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses -system.iocache.demand_misses::total 175 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 175 # number of overall misses -system.iocache.overall_misses::total 175 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 22127883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 22127883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5428057606 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5428057606 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 22127883 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 22127883 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 22127883 # number of overall miss cycles -system.iocache.overall_miss_latency::total 22127883 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 177 # number of demand (read+write) misses +system.iocache.demand_misses::total 177 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 177 # number of overall misses +system.iocache.overall_misses::total 177 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 22195883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22195883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5429420359 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5429420359 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 22195883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 22195883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 22195883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 22195883 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 177 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 177 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 177 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 177 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 177 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses @@ -1269,40 +1283,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126445.045714 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126445.045714 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130632.884241 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130632.884241 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 126445.045714 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126445.045714 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 126445.045714 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126445.045714 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 55 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125400.468927 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125400.468927 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130665.680569 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130665.680569 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 125400.468927 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125400.468927 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 125400.468927 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125400.468927 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 74 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 8 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 18.333333 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.250000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41520 # number of writebacks -system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 41522 # number of writebacks +system.iocache.writebacks::total 41522 # number of writebacks +system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 175 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 175 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13377883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13377883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3350457606 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3350457606 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 13377883 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 13377883 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 13377883 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 13377883 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 177 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 177 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 177 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 177 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13345883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13345883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3351820359 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3351820359 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 13345883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 13345883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 13345883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 13345883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1311,195 +1325,199 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76445.045714 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76445.045714 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80632.884241 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80632.884241 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76445.045714 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76445.045714 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76445.045714 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76445.045714 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75400.468927 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 75400.468927 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80665.680569 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80665.680569 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75400.468927 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75400.468927 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75400.468927 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 75400.468927 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 341926 # number of replacements -system.l2c.tags.tagsinuse 65167.982973 # Cycle average of tags in use -system.l2c.tags.total_refs 3685196 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 406932 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 9.056049 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 12918028000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54774.174056 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4860.572445 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5374.369214 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 120.511186 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 38.356073 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.835788 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.074166 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.082006 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.001839 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000585 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.994385 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65006 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 516 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5383 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6300 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52705 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.991913 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 35906123 # Number of tag accesses -system.l2c.tags.data_accesses 35906123 # Number of data accesses -system.l2c.Writeback_hits::writebacks 792419 # number of Writeback hits -system.l2c.Writeback_hits::total 792419 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 186 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 557 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 743 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 39 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 63 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 124095 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 48625 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 172720 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 674900 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 330771 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1005671 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 659420 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 113743 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 773163 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 674900 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 783515 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 330771 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 162368 # number of demand (read+write) hits -system.l2c.demand_hits::total 1951554 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 674900 # number of overall hits -system.l2c.overall_hits::cpu0.data 783515 # number of overall hits -system.l2c.overall_hits::cpu1.inst 330771 # number of overall hits -system.l2c.overall_hits::cpu1.data 162368 # number of overall hits -system.l2c.overall_hits::total 1951554 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 2967 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1808 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 4775 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 925 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 929 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1854 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 114970 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 7864 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 122834 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 12571 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 940 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 13511 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 271540 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 337 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 271877 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.inst 12571 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 386510 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 940 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 8201 # number of demand (read+write) misses -system.l2c.demand_misses::total 408222 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 12571 # number of overall misses -system.l2c.overall_misses::cpu0.data 386510 # number of overall misses -system.l2c.overall_misses::cpu1.inst 940 # number of overall misses -system.l2c.overall_misses::cpu1.data 8201 # number of overall misses -system.l2c.overall_misses::total 408222 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 3901500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 36480500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 40382000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 3643000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1056500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 4699500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 14617384500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1036956000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 15654340500 # number of ReadExReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1651627500 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu1.inst 124696500 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 1776324000 # number of ReadCleanReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 33670754500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 43654000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 33714408500 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1651627500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 48288139000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 124696500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1080610000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 51145073000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1651627500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 48288139000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 124696500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1080610000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 51145073000 # number of overall miss cycles -system.l2c.Writeback_accesses::writebacks 792419 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 792419 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 3153 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 2365 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 5518 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 964 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 953 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1917 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 239065 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 56489 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 295554 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 687471 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 331711 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1019182 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 930960 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 114080 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 1045040 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 687471 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1170025 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 331711 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 170569 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2359776 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 687471 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1170025 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 331711 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 170569 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2359776 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.941009 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.764482 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.865350 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.959544 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.974816 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.967136 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.480915 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.139213 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.415606 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.018286 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.002834 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.013257 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.291677 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.002954 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.260159 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.018286 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.330343 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.002834 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.048080 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.172992 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.018286 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.330343 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.002834 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.048080 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.172992 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1314.964611 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 20177.267699 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 8456.963351 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3938.378378 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1137.244349 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 2534.789644 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 127140.858485 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 131861.139369 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 127443.057297 # average ReadExReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 131383.939225 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 132655.851064 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::total 131472.429872 # average ReadCleanReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 123999.243205 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 129537.091988 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 124006.107541 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 131383.939225 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 124933.737808 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 132655.851064 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 131765.638337 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 125287.399993 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 131383.939225 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 124933.737808 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 132655.851064 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 131765.638337 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 125287.399993 # average overall miss latency +system.l2c.tags.replacements 342255 # number of replacements +system.l2c.tags.tagsinuse 65190.453062 # Cycle average of tags in use +system.l2c.tags.total_refs 3793407 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 407257 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 9.314529 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 12928623000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 54971.310995 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3771.999936 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4805.186829 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1123.175084 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 518.780218 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.838796 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.057556 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.073321 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.017138 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.007916 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.994727 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65002 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 176 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 1065 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 4849 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6325 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52587 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.991852 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 36989627 # Number of tag accesses +system.l2c.tags.data_accesses 36989627 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 862671 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 862671 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 732220 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 732220 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 141 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 87 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 228 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 25 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 26 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 51 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 102038 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 98486 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 200524 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 479778 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 508114 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 987892 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 344131 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 495524 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 839655 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.inst 479778 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 446169 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 508114 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 594010 # number of demand (read+write) hits +system.l2c.demand_hits::total 2028071 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 479778 # number of overall hits +system.l2c.overall_hits::cpu0.data 446169 # number of overall hits +system.l2c.overall_hits::cpu1.inst 508114 # number of overall hits +system.l2c.overall_hits::cpu1.data 594010 # number of overall hits +system.l2c.overall_hits::total 2028071 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 2602 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 483 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3085 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 77 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 94 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 171 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 103258 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 19364 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 122622 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 10849 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 2603 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 13452 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 270704 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 1159 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 271863 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.inst 10849 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 373962 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2603 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 20523 # number of demand (read+write) misses +system.l2c.demand_misses::total 407937 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 10849 # number of overall misses +system.l2c.overall_misses::cpu0.data 373962 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2603 # number of overall misses +system.l2c.overall_misses::cpu1.data 20523 # number of overall misses +system.l2c.overall_misses::total 407937 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 3090000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 2769500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 5859500 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 569500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 892000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 1461500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 13105172500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 2555486000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 15660658500 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1419877000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 342190500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 1762067500 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 33554759000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 151782000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 33706541000 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1419877000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 46659931500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 342190500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 2707268000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 51129267000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1419877000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 46659931500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 342190500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 2707268000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 51129267000 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 862671 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 862671 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 732220 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 732220 # number of WritebackClean accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2743 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 570 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3313 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 102 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 120 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 222 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 205296 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 117850 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 323146 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 490627 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 510717 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1001344 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 614835 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 496683 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 1111518 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 490627 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 820131 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 510717 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 614533 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2436008 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 490627 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 820131 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 510717 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 614533 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2436008 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.948596 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.847368 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.931180 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.754902 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.783333 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.770270 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.502971 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.164311 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.379463 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.022113 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.005097 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.013434 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.440287 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.002333 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.244587 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.022113 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.455978 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.005097 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.033396 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.167461 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.022113 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.455978 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.005097 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.033396 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.167461 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1187.548040 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5733.954451 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1899.351702 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 7396.103896 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 9489.361702 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 8546.783626 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 126916.776424 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 131970.977071 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 127714.916573 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 130876.301963 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 131460.046101 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 130989.258103 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 123953.687422 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 130959.447800 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 123983.554217 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 130876.301963 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 124771.852488 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 131460.046101 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 131913.852751 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 125336.184264 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 130876.301963 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 124771.852488 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 131460.046101 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 131913.852751 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 125336.184264 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1508,247 +1526,248 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 79390 # number of writebacks -system.l2c.writebacks::total 79390 # number of writebacks +system.l2c.writebacks::writebacks 79536 # number of writebacks +system.l2c.writebacks::total 79536 # number of writebacks system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 11 # number of ReadCleanReq MSHR hits system.l2c.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 324 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 324 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2967 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1808 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 4775 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 925 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 929 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1854 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 114970 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 7864 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 122834 # number of ReadExReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 12571 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 929 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::total 13500 # number of ReadCleanReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 271540 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 337 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 271877 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 12571 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 386510 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 929 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 8201 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 408211 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 12571 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 386510 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 929 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 8201 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 408211 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7086 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 118 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 7204 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 10784 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3347 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 14131 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 17870 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3465 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 21335 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 212307500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 129803000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 342110500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 65706500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 66436000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 132142500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 13467684500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 958316000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 14426000500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1525917500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 114051500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::total 1639969000 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 30955354500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 40284000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 30995638500 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1525917500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 44423039000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 114051500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 998600000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 47061608000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1525917500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 44423039000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 114051500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 998600000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 47061608000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1400094000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 22239000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1422333000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2192043000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 708908500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2900951500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3592137000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 731147500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4323284500 # number of overall MSHR uncacheable cycles +system.l2c.CleanEvict_mshr_misses::writebacks 9 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 9 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2602 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 483 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 3085 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 77 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 94 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 171 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 103258 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 19364 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 122622 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 10849 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 2592 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 13441 # number of ReadCleanReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 270704 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1159 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 271863 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 10849 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 373962 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2592 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 20523 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 407926 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 10849 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 373962 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2592 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 20523 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 407926 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 4814 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 2385 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 7199 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 8193 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 4228 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 12421 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 13007 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 6613 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 19620 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 186370500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 34557500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 220928000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5513500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 6719500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 12233000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 12072592500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2361846000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 14434438500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1311387000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 314915500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 1626302500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 30847719000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 140192000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 30987911000 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1311387000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 42920311500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 314915500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 2502038000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 47048652000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1311387000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 42920311500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 314915500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 2502038000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 47048652000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1012133000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 490208000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1502341000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1745847000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 944283500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2690130500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2757980000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1434491500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4192471500 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941009 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.764482 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.865350 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.959544 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.974816 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.967136 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.480915 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.139213 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.415606 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.018286 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.002801 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013246 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.291677 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.002954 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260159 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018286 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.330343 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002801 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.048080 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.172987 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018286 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.330343 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002801 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.048080 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.172987 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 71556.285811 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 71793.694690 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71646.178010 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71034.054054 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71513.455328 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71274.271845 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 117140.858485 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121861.139369 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 117443.057297 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 121383.939225 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122768.030140 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 121479.185185 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 113999.243205 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 119537.091988 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114006.107541 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121383.939225 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 114933.737808 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122768.030140 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121765.638337 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 115287.456732 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121383.939225 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 114933.737808 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122768.030140 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121765.638337 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 115287.456732 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197585.944115 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 188466.101695 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197436.563021 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 203268.082344 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 211804.152973 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 205289.894558 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 201014.941242 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 211009.379509 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 202638.129834 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.948596 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.847368 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.931180 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.754902 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.783333 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.770270 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.502971 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.164311 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.379463 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.022113 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005075 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013423 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.440287 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.002333 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.244587 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.022113 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.455978 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005075 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.033396 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.167457 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.022113 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.455978 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005075 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.033396 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.167457 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 71625.864719 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 71547.619048 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71613.614263 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71603.896104 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71484.042553 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71538.011696 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 116916.776424 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121970.977071 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 117714.916573 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 120876.301963 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121495.177469 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 120995.647645 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 113953.687422 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 120959.447800 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 113983.554217 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120876.301963 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 114771.852488 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121495.177469 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121913.852751 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 115336.242358 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120876.301963 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 114771.852488 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121495.177469 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121913.852751 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 115336.242358 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210247.818862 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 205537.945493 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208687.456591 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 213090.076895 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 223340.468307 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 216579.220675 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 212038.133313 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 216919.930440 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 213683.562691 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 7204 # Transaction distribution -system.membus.trans_dist::ReadResp 292756 # Transaction distribution -system.membus.trans_dist::WriteReq 14131 # Transaction distribution -system.membus.trans_dist::WriteResp 14131 # Transaction distribution -system.membus.trans_dist::Writeback 120910 # Transaction distribution -system.membus.trans_dist::CleanEvict 262059 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16821 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11772 # Transaction distribution -system.membus.trans_dist::UpgradeResp 7147 # Transaction distribution -system.membus.trans_dist::ReadExReq 123180 # Transaction distribution -system.membus.trans_dist::ReadExResp 122316 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 285552 # Transaction distribution +system.membus.trans_dist::ReadReq 7199 # Transaction distribution +system.membus.trans_dist::ReadResp 292680 # Transaction distribution +system.membus.trans_dist::WriteReq 12421 # Transaction distribution +system.membus.trans_dist::WriteResp 12421 # Transaction distribution +system.membus.trans_dist::WritebackDirty 121058 # Transaction distribution +system.membus.trans_dist::CleanEvict 261934 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4921 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1238 # Transaction distribution +system.membus.trans_dist::UpgradeResp 3449 # Transaction distribution +system.membus.trans_dist::ReadExReq 122558 # Transaction distribution +system.membus.trans_dist::ReadExResp 122429 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 285481 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42670 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1193160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1235830 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124827 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124827 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1360657 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82499 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31156480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31238979 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33897219 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 22736 # Total snoops (count) -system.membus.snoop_fanout::samples 883364 # Request fanout histogram +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39240 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1166399 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1205639 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124831 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124831 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1330470 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 68786 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31168512 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31237298 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658368 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2658368 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33895666 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3262 # Total snoops (count) +system.membus.snoop_fanout::samples 858545 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 883364 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 858545 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 883364 # Request fanout histogram -system.membus.reqLayer0.occupancy 40609000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 858545 # Request fanout histogram +system.membus.reqLayer0.occupancy 36672500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1325313892 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1323961648 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2193032106 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2184136804 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 69837727 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 69798217 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 4790600 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2395468 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 361643 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_requests 4935792 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2467069 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 374533 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 1240 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1180 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 60 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 7204 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2107021 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14131 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14131 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 913350 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1503335 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 17046 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11835 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 28881 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 297634 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 297634 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1019209 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1080623 # Transaction distribution +system.toL2Bus.snoop_filter.hit_single_snoops 1179 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 61 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 7199 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2152619 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 12421 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 12421 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 983748 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 732220 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 760785 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 4956 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 1289 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 6245 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 324079 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 324079 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1001367 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1144069 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1918193 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3544327 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 867106 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 539630 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6869256 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43998144 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118001405 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 21229504 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 18604166 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 201833219 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 484490 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 5237304 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.138719 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.345885 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1377223 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2478366 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1357708 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1834010 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7047307 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 56740736 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 76009449 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 54207360 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 71099081 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 258056626 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 461903 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2920905 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.131024 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.337667 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4511205 86.14% 86.14% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 725687 13.86% 99.99% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 408 0.01% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 4 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2538432 86.91% 86.91% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 382238 13.09% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 234 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 1 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5237304 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3205453497 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2920905 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4346798496 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 297883 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 299383 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1031366757 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1802104925 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 736191563 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1248608962 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 498533066 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 767009132 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 293884764 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 969915969 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 2decdfb20..350260732 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.941266 # Number of seconds simulated -sim_ticks 1941266487500 # Number of ticks simulated -final_tick 1941266487500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.941276 # Number of seconds simulated +sim_ticks 1941275996000 # Number of ticks simulated +final_tick 1941275996000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1056307 # Simulator instruction rate (inst/s) -host_op_rate 1056307 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36524098946 # Simulator tick rate (ticks/s) -host_mem_usage 374096 # Number of bytes of host memory used -host_seconds 53.15 # Real time elapsed on the host -sim_insts 56143021 # Number of instructions simulated -sim_ops 56143021 # Number of ops (including micro ops) simulated +host_inst_rate 1519860 # Simulator instruction rate (inst/s) +host_op_rate 1519860 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52515485940 # Simulator tick rate (ticks/s) +host_mem_usage 331552 # Number of bytes of host memory used +host_seconds 36.97 # Real time elapsed on the host +sim_insts 56182743 # Number of instructions simulated +sim_ops 56182743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 848832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24855488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 844800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24856512 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25705280 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 848832 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 848832 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7407552 # Number of bytes written to this memory -system.physmem.bytes_written::total 7407552 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13263 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388367 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25702272 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 844800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 844800 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7410752 # Number of bytes written to this memory +system.physmem.bytes_written::total 7410752 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13200 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388383 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 401645 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115743 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115743 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 437257 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12803749 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 401598 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115793 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115793 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 435178 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12804213 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 495 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13241500 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 437257 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 437257 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3815835 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3815835 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3815835 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 437257 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12803749 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13239886 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 435178 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 435178 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3817464 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3817464 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3817464 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 435178 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12804213 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 495 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17057335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 401645 # Number of read requests accepted -system.physmem.writeReqs 115743 # Number of write requests accepted -system.physmem.readBursts 401645 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 115743 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25697728 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7552 # Total number of bytes read from write queue -system.physmem.bytesWritten 7406016 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25705280 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7407552 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 118 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 17057350 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 401598 # Number of read requests accepted +system.physmem.writeReqs 115793 # Number of write requests accepted +system.physmem.readBursts 401598 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115793 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25694784 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7488 # Total number of bytes read from write queue +system.physmem.bytesWritten 7408704 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25702272 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7410752 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 117 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 41682 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25168 # Per bank write bursts -system.physmem.perBankRdBursts::1 25510 # Per bank write bursts -system.physmem.perBankRdBursts::2 25518 # Per bank write bursts -system.physmem.perBankRdBursts::3 25527 # Per bank write bursts -system.physmem.perBankRdBursts::4 25065 # Per bank write bursts -system.physmem.perBankRdBursts::5 24960 # Per bank write bursts -system.physmem.perBankRdBursts::6 24241 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 303100 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25225 # Per bank write bursts +system.physmem.perBankRdBursts::1 25628 # Per bank write bursts +system.physmem.perBankRdBursts::2 25541 # Per bank write bursts +system.physmem.perBankRdBursts::3 25494 # Per bank write bursts +system.physmem.perBankRdBursts::4 25069 # Per bank write bursts +system.physmem.perBankRdBursts::5 24955 # Per bank write bursts +system.physmem.perBankRdBursts::6 24242 # Per bank write bursts system.physmem.perBankRdBursts::7 24604 # Per bank write bursts -system.physmem.perBankRdBursts::8 25078 # Per bank write bursts -system.physmem.perBankRdBursts::9 24653 # Per bank write bursts -system.physmem.perBankRdBursts::10 25359 # Per bank write bursts -system.physmem.perBankRdBursts::11 24824 # Per bank write bursts -system.physmem.perBankRdBursts::12 24407 # Per bank write bursts -system.physmem.perBankRdBursts::13 25357 # Per bank write bursts -system.physmem.perBankRdBursts::14 25770 # Per bank write bursts -system.physmem.perBankRdBursts::15 25486 # Per bank write bursts -system.physmem.perBankWrBursts::0 7561 # Per bank write bursts -system.physmem.perBankWrBursts::1 7519 # Per bank write bursts -system.physmem.perBankWrBursts::2 7810 # Per bank write bursts -system.physmem.perBankWrBursts::3 7560 # Per bank write bursts -system.physmem.perBankWrBursts::4 7221 # Per bank write bursts -system.physmem.perBankWrBursts::5 6978 # Per bank write bursts -system.physmem.perBankWrBursts::6 6351 # Per bank write bursts -system.physmem.perBankWrBursts::7 6424 # Per bank write bursts +system.physmem.perBankRdBursts::8 25085 # Per bank write bursts +system.physmem.perBankRdBursts::9 24651 # Per bank write bursts +system.physmem.perBankRdBursts::10 25269 # Per bank write bursts +system.physmem.perBankRdBursts::11 24875 # Per bank write bursts +system.physmem.perBankRdBursts::12 24508 # Per bank write bursts +system.physmem.perBankRdBursts::13 25360 # Per bank write bursts +system.physmem.perBankRdBursts::14 25616 # Per bank write bursts +system.physmem.perBankRdBursts::15 25359 # Per bank write bursts +system.physmem.perBankWrBursts::0 7625 # Per bank write bursts +system.physmem.perBankWrBursts::1 7638 # Per bank write bursts +system.physmem.perBankWrBursts::2 7842 # Per bank write bursts +system.physmem.perBankWrBursts::3 7532 # Per bank write bursts +system.physmem.perBankWrBursts::4 7224 # Per bank write bursts +system.physmem.perBankWrBursts::5 6973 # Per bank write bursts +system.physmem.perBankWrBursts::6 6356 # Per bank write bursts +system.physmem.perBankWrBursts::7 6427 # Per bank write bursts system.physmem.perBankWrBursts::8 7248 # Per bank write bursts -system.physmem.perBankWrBursts::9 6410 # Per bank write bursts -system.physmem.perBankWrBursts::10 7207 # Per bank write bursts -system.physmem.perBankWrBursts::11 6855 # Per bank write bursts -system.physmem.perBankWrBursts::12 6980 # Per bank write bursts -system.physmem.perBankWrBursts::13 7819 # Per bank write bursts -system.physmem.perBankWrBursts::14 7982 # Per bank write bursts -system.physmem.perBankWrBursts::15 7794 # Per bank write bursts +system.physmem.perBankWrBursts::9 6409 # Per bank write bursts +system.physmem.perBankWrBursts::10 7117 # Per bank write bursts +system.physmem.perBankWrBursts::11 6905 # Per bank write bursts +system.physmem.perBankWrBursts::12 7093 # Per bank write bursts +system.physmem.perBankWrBursts::13 7822 # Per bank write bursts +system.physmem.perBankWrBursts::14 7863 # Per bank write bursts +system.physmem.perBankWrBursts::15 7687 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 23 # Number of times write queue was full causing retry -system.physmem.totGap 1941254508500 # Total gap between requests +system.physmem.numWrRetry 16 # Number of times write queue was full causing retry +system.physmem.totGap 1941264122500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 401645 # Read request sizes (log2) +system.physmem.readPktSize::6 401598 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 115743 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 401513 # What read queue length does an incoming req see +system.physmem.writePktSize::6 115793 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 401467 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see @@ -148,114 +148,123 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1824 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5414 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8014 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6616 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5487 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7624 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5554 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 134 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 146 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 176 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 87 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64921 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 509.908104 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 310.461658 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 406.215984 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15228 23.46% 23.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11644 17.94% 41.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4997 7.70% 49.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2980 4.59% 53.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2446 3.77% 57.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4228 6.51% 63.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1452 2.24% 66.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2063 3.18% 69.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19883 30.63% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64921 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5102 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 78.697570 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2954.645683 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5099 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::56 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 51 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64941 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 509.747124 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 310.189706 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 406.049901 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15359 23.65% 23.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11448 17.63% 41.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4958 7.63% 48.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3153 4.86% 53.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2453 3.78% 57.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4206 6.48% 64.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1429 2.20% 66.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2063 3.18% 69.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19872 30.60% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64941 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5113 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 78.517700 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2951.127642 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5110 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5102 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5102 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.681105 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.154688 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.203626 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4492 88.04% 88.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 201 3.94% 91.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 29 0.57% 92.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 48 0.94% 93.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 38 0.74% 94.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 6 0.12% 94.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 11 0.22% 94.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 38 0.74% 95.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 34 0.67% 95.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 1 0.02% 96.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 159 3.12% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 2 0.04% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 2 0.04% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 5 0.10% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 1 0.02% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 2 0.04% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 3 0.06% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 3 0.06% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 4 0.08% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 8 0.16% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 4 0.08% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 3 0.06% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 2 0.04% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 4 0.08% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5102 # Writes before turning the bus around for reads -system.physmem.totQLat 2705942000 # Total ticks spent queuing -system.physmem.totMemAccLat 10234573250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2007635000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6739.13 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5113 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5113 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.640524 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.158069 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.669047 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4483 87.68% 87.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 26 0.51% 88.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 11 0.22% 88.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 181 3.54% 91.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 5 0.10% 92.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 20 0.39% 92.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 39 0.76% 93.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 6 0.12% 93.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 12 0.23% 93.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 31 0.61% 94.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 3 0.06% 94.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 3 0.06% 94.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 9 0.18% 94.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 1 0.02% 94.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 22 0.43% 94.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 27 0.53% 95.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 2 0.04% 95.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 26 0.51% 95.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.06% 96.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 161 3.15% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 5 0.10% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.04% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 3 0.06% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.02% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 4 0.08% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 4 0.08% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 11 0.22% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 5 0.10% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5113 # Writes before turning the bus around for reads +system.physmem.totQLat 2717940750 # Total ticks spent queuing +system.physmem.totMemAccLat 10245709500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2007405000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6769.79 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25489.13 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25519.79 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.24 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.82 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.24 # Average system read bandwidth in MiByte/s @@ -265,62 +274,62 @@ system.physmem.busUtil 0.13 # Da system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.77 # Average write queue length when enqueuing -system.physmem.readRowHits 358859 # Number of row buffer hits during reads -system.physmem.writeRowHits 93466 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.37 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.75 # Row buffer hit rate for writes -system.physmem.avgGap 3752028.47 # Average gap between requests +system.physmem.avgWrQLen 22.09 # Average write queue length when enqueuing +system.physmem.readRowHits 358828 # Number of row buffer hits during reads +system.physmem.writeRowHits 93473 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.38 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.72 # Row buffer hit rate for writes +system.physmem.avgGap 3752025.30 # Average gap between requests system.physmem.pageHitRate 87.44 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 239349600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 130597500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1564625400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 372107520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 126793670640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 71640444015 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1101913691250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1302654485925 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.035450 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1832853481750 # Time in different power states -system.physmem_0.memoryStateTime::REF 64822940000 # Time in different power states +system.physmem_0.actEnergy 240362640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 131150250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1565912400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 373358160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 126794687760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 71531321220 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1102018756500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1302655548930 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.030615 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1833026995250 # Time in different power states +system.physmem_0.memoryStateTime::REF 64823460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 43583902000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 43425441000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 251453160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 137201625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1567285200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 377751600 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 126793670640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 72584952255 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1101085183500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1302797497980 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.109115 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1831469435000 # Time in different power states -system.physmem_1.memoryStateTime::REF 64822940000 # Time in different power states +system.physmem_1.actEnergy 250591320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 136731375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1565639400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 376773120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 126794687760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 72715172175 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1100980290750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1302819885900 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.115269 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1831298493250 # Time in different power states +system.physmem_1.memoryStateTime::REF 64823460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 44967962500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 45153943000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9058452 # DTB read hits -system.cpu.dtb.read_misses 10327 # DTB read misses +system.cpu.dtb.read_hits 9064657 # DTB read hits +system.cpu.dtb.read_misses 10324 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728858 # DTB read accesses -system.cpu.dtb.write_hits 6353129 # DTB write hits -system.cpu.dtb.write_misses 1143 # DTB write misses +system.cpu.dtb.read_accesses 728853 # DTB read accesses +system.cpu.dtb.write_hits 6356207 # DTB write hits +system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291932 # DTB write accesses -system.cpu.dtb.data_hits 15411581 # DTB hits -system.cpu.dtb.data_misses 11470 # DTB misses +system.cpu.dtb.write_accesses 291931 # DTB write accesses +system.cpu.dtb.data_hits 15420864 # DTB hits +system.cpu.dtb.data_misses 11466 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020790 # DTB accesses -system.cpu.itb.fetch_hits 4975133 # ITB hits +system.cpu.dtb.data_accesses 1020784 # DTB accesses +system.cpu.itb.fetch_hits 4975134 # ITB hits system.cpu.itb.fetch_misses 5010 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4980143 # ITB accesses +system.cpu.itb.fetch_accesses 4980144 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -333,87 +342,32 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3882532975 # number of cpu cycles simulated +system.cpu.numCycles 3882551992 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56143021 # Number of instructions committed -system.cpu.committedOps 56143021 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52016582 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses -system.cpu.num_func_calls 1482534 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6465507 # number of instructions that are conditional controls -system.cpu.num_int_insts 52016582 # number of integer instructions -system.cpu.num_fp_insts 324393 # number of float instructions -system.cpu.num_int_register_reads 71267420 # number of times the integer registers were read -system.cpu.num_int_register_writes 38489507 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written -system.cpu.num_mem_refs 15464199 # number of memory refs -system.cpu.num_load_insts 9095305 # Number of load instructions -system.cpu.num_store_insts 6368894 # Number of store instructions -system.cpu.num_idle_cycles 3584401371.998154 # Number of idle cycles -system.cpu.num_busy_cycles 298131603.001846 # Number of busy cycles -system.cpu.not_idle_fraction 0.076788 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.923212 # Percentage of idle cycles -system.cpu.Branches 8418668 # Number of branches fetched -system.cpu.op_class::No_OpClass 3199011 5.70% 5.70% # Class of executed instruction -system.cpu.op_class::IntAlu 36202225 64.47% 70.17% # Class of executed instruction -system.cpu.op_class::IntMult 61032 0.11% 70.27% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction -system.cpu.op_class::FloatAdd 38085 0.07% 70.34% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::FloatDiv 3636 0.01% 70.35% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::MemRead 9322424 16.60% 86.95% # Class of executed instruction -system.cpu.op_class::MemWrite 6374975 11.35% 98.30% # Class of executed instruction -system.cpu.op_class::IprAccess 953470 1.70% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 56154858 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6377 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 212043 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74906 40.88% 40.88% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 131 0.07% 40.95% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 212050 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74912 40.88% 40.88% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1935 1.06% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106248 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183220 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73539 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 106253 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183231 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73545 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1935 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73539 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149144 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1860736112500 95.85% 95.85% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 92522000 0.00% 95.86% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 746030500 0.04% 95.89% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 79691088500 4.11% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1941265753500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981750 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73545 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149156 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1860509644500 95.84% 95.84% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 94040000 0.00% 95.84% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 770515500 0.04% 95.88% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 79901062000 4.12% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1941275262000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981752 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692145 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814016 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692169 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814033 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -452,110 +406,165 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175993 91.21% 93.41% # number of callpals executed +system.cpu.kern.callpal::swpipl 176004 91.22% 93.41% # number of callpals executed system.cpu.kern.callpal::rdps 6835 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal::whami 2 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rti 5160 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192944 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5907 # number of protection mode switches -system.cpu.kern.mode_switch::user 1740 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1910 -system.cpu.kern.mode_good::user 1740 +system.cpu.kern.callpal::total 192955 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5908 # number of protection mode switches +system.cpu.kern.mode_switch::user 1739 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1909 +system.cpu.kern.mode_good::user 1739 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.323345 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.323121 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392117 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 48524962500 2.50% 2.50% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5595783500 0.29% 2.79% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1887145005500 97.21% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.081184 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.391952 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 48611852500 2.50% 2.50% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5602941000 0.29% 2.79% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1887060466500 97.21% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed -system.cpu.dcache.tags.replacements 1390004 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.973850 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14040102 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1390516 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 10.097045 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 143374500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.973850 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999949 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999949 # Average percentage of cache occupancy +system.cpu.committedInsts 56182743 # Number of instructions committed +system.cpu.committedOps 56182743 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52054633 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses +system.cpu.num_func_calls 1483394 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6468678 # number of instructions that are conditional controls +system.cpu.num_int_insts 52054633 # number of integer instructions +system.cpu.num_fp_insts 324393 # number of float instructions +system.cpu.num_int_register_reads 71322499 # number of times the integer registers were read +system.cpu.num_int_register_writes 38520900 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written +system.cpu.num_mem_refs 15473474 # number of memory refs +system.cpu.num_load_insts 9101503 # Number of load instructions +system.cpu.num_store_insts 6371971 # Number of store instructions +system.cpu.num_idle_cycles 3583834697.998154 # Number of idle cycles +system.cpu.num_busy_cycles 298717294.001846 # Number of busy cycles +system.cpu.not_idle_fraction 0.076938 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.923062 # Percentage of idle cycles +system.cpu.Branches 8422724 # Number of branches fetched +system.cpu.op_class::No_OpClass 3200638 5.70% 5.70% # Class of executed instruction +system.cpu.op_class::IntAlu 36231019 64.47% 70.17% # Class of executed instruction +system.cpu.op_class::IntMult 61043 0.11% 70.28% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 70.28% # Class of executed instruction +system.cpu.op_class::FloatAdd 38085 0.07% 70.35% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::FloatDiv 3636 0.01% 70.35% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::MemRead 9328633 16.60% 86.95% # Class of executed instruction +system.cpu.op_class::MemWrite 6378052 11.35% 98.30% # Class of executed instruction +system.cpu.op_class::IprAccess 953470 1.70% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 56194576 # Class of executed instruction +system.cpu.dcache.tags.replacements 1390387 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.973391 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 14048998 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1390899 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.100660 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 145150500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.973391 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999948 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999948 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63112993 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63112993 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7808536 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7808536 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5849272 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5849272 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183025 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183025 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199252 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199252 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13657808 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13657808 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13657808 # number of overall hits -system.cpu.dcache.overall_hits::total 13657808 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1069028 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1069028 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304257 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304257 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17249 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17249 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1373285 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1373285 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1373285 # number of overall misses -system.cpu.dcache.overall_misses::total 1373285 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 44750637500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 44750637500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 17613913000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 17613913000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232507000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 232507000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 62364550500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 62364550500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 62364550500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 62364550500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 8877564 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 8877564 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6153529 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6153529 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200274 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200274 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199252 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199252 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15031093 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15031093 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15031093 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15031093 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120419 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120419 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049444 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049444 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086127 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086127 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091363 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091363 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091363 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091363 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41861.052751 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41861.052751 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57891.562068 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 57891.562068 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13479.448084 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13479.448084 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45412.678723 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45412.678723 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45412.678723 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45412.678723 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63150492 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63150492 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7814415 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7814415 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5852271 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5852271 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183035 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183035 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199260 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199260 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13666686 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13666686 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13666686 # number of overall hits +system.cpu.dcache.overall_hits::total 13666686 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1069342 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1069342 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304328 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304328 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17247 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17247 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1373670 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1373670 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1373670 # number of overall misses +system.cpu.dcache.overall_misses::total 1373670 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 44770870500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 44770870500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 17634139000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 17634139000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232897500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 232897500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 62405009500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 62405009500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 62405009500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 62405009500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8883757 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8883757 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6156599 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6156599 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200282 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200282 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199260 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199260 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15040356 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15040356 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15040356 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15040356 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120370 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120370 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049431 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049431 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086114 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086114 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091332 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091332 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091332 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091332 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41867.681715 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41867.681715 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57944.517100 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 57944.517100 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13503.652809 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13503.652809 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45429.404078 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45429.404078 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45429.404078 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45429.404078 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -564,120 +573,120 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 834533 # number of writebacks -system.cpu.dcache.writebacks::total 834533 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069028 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069028 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304257 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304257 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17249 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17249 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1373285 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1373285 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1373285 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1373285 # number of overall MSHR misses +system.cpu.dcache.writebacks::writebacks 834936 # number of writebacks +system.cpu.dcache.writebacks::total 834936 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069342 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1069342 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304328 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304328 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17247 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17247 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1373670 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1373670 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1373670 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1373670 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9653 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 9653 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16583 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 16583 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43681609500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 43681609500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17309656000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 17309656000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 215258000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 215258000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 60991265500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 60991265500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 60991265500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 60991265500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1450109500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1450109500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2050243500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2050243500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3500353000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3500353000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120419 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120419 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049444 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049444 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086127 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086127 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091363 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091363 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091363 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091363 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40861.052751 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40861.052751 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56891.562068 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56891.562068 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12479.448084 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12479.448084 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44412.678723 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 44412.678723 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44412.678723 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44412.678723 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209251.010101 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209251.010101 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212394.436963 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212394.436963 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 211080.805644 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 211080.805644 # average overall mshr uncacheable latency +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43701528500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 43701528500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17329811000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 17329811000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 215650500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 215650500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61031339500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 61031339500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61031339500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 61031339500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1527878500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1527878500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2172467000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2172467000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3700345500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3700345500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120370 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120370 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049431 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049431 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086114 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086114 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091332 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091332 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091332 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091332 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40867.681715 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40867.681715 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56944.517100 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56944.517100 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12503.652809 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12503.652809 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44429.404078 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 44429.404078 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44429.404078 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44429.404078 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220473.088023 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220473.088023 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 225056.148348 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 225056.148348 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 223140.897304 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 223140.897304 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 928672 # number of replacements -system.cpu.icache.tags.tagsinuse 506.358595 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 55225516 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 929183 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 59.434488 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 58555927500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 506.358595 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.988982 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.988982 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 928920 # number of replacements +system.cpu.icache.tags.tagsinuse 506.355618 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 55264986 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 929431 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 59.461096 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 58592056500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 506.355618 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.988976 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.988976 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 57084202 # Number of tag accesses -system.cpu.icache.tags.data_accesses 57084202 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 55225516 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55225516 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55225516 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55225516 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55225516 # number of overall hits -system.cpu.icache.overall_hits::total 55225516 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 929343 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 929343 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 929343 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 929343 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 929343 # number of overall misses -system.cpu.icache.overall_misses::total 929343 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13682743000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13682743000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13682743000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13682743000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13682743000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13682743000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56154859 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56154859 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56154859 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56154859 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 56154859 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56154859 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016550 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016550 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.016550 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.016550 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.016550 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.016550 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14723.027989 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14723.027989 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14723.027989 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14723.027989 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14723.027989 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14723.027989 # average overall miss latency +system.cpu.icache.tags.tag_accesses 57124168 # Number of tag accesses +system.cpu.icache.tags.data_accesses 57124168 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 55264986 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55264986 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55264986 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55264986 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55264986 # number of overall hits +system.cpu.icache.overall_hits::total 55264986 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 929591 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 929591 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 929591 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 929591 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 929591 # number of overall misses +system.cpu.icache.overall_misses::total 929591 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13686380500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13686380500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13686380500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13686380500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13686380500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13686380500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 56194577 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56194577 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 56194577 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 56194577 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 56194577 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 56194577 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016542 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016542 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016542 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016542 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016542 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016542 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14723.013132 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14723.013132 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14723.013132 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14723.013132 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14723.013132 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14723.013132 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -686,141 +695,147 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929343 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 929343 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 929343 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 929343 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 929343 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 929343 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12753400000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12753400000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12753400000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12753400000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12753400000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12753400000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016550 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016550 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016550 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.016550 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016550 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.016550 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13723.027989 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13723.027989 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13723.027989 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13723.027989 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13723.027989 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13723.027989 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 928920 # number of writebacks +system.cpu.icache.writebacks::total 928920 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929591 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 929591 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 929591 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 929591 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 929591 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 929591 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12756789500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12756789500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12756789500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12756789500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12756789500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12756789500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016542 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.016542 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.016542 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13723.013132 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13723.013132 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13723.013132 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13723.013132 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13723.013132 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13723.013132 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 336158 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65233.633295 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3929109 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 401321 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 9.790440 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 10607812000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 54990.166282 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4743.088898 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 5500.378115 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.839083 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072374 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.083929 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.995386 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 336393 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65234.360025 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3930350 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 401556 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 9.787800 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 10619817000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 55072.826317 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4686.115204 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 5475.418504 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.840345 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.071504 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.083548 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.995397 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 718 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5223 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3222 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 722 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5220 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3221 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55822 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 37802165 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 37802165 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 834533 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 834533 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 37812565 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 37812565 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 834936 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 834936 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 928699 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 928699 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187442 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187442 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 916060 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 916060 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 814318 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 814318 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 916060 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1001760 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1917820 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 916060 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1001760 # number of overall hits -system.cpu.l2cache.overall_hits::total 1917820 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 187491 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187491 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 916371 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 916371 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 814618 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 814618 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 916371 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1002109 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1918480 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 916371 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1002109 # number of overall hits +system.cpu.l2cache.overall_hits::total 1918480 # number of overall hits system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 116798 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 116798 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13263 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 13263 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 271959 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 271959 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 13263 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 388757 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 402020 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 13263 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 388757 # number of overall misses -system.cpu.l2cache.overall_misses::total 402020 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 320000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 320000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14883886000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 14883886000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1737439000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 1737439000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33716172000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 33716172000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1737439000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 48600058000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 50337497000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1737439000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 48600058000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 50337497000 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 834533 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 834533 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 116820 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 116820 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13200 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 13200 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 271971 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 271971 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 13200 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 388791 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 401991 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 13200 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 388791 # number of overall misses +system.cpu.l2cache.overall_misses::total 401991 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 320500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 320500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14900273000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 14900273000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1727207500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 1727207500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33719775000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 33719775000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1727207500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 48620048000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 50347255500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1727207500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 48620048000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 50347255500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 834936 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 834936 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 928699 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 928699 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304240 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304240 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 929323 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 929323 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1086277 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1086277 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 929323 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1390517 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2319840 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 929323 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1390517 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2319840 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304311 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304311 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 929571 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 929571 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1086589 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1086589 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 929571 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1390900 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2320471 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 929571 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1390900 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2320471 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383901 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383901 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014272 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014272 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.250359 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.250359 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014272 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.279577 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.173296 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014272 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.279577 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.173296 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 24615.384615 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 24615.384615 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127432.712889 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127432.712889 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130998.944432 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130998.944432 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123975.202144 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123975.202144 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130998.944432 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 125013.975311 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 125211.424805 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130998.944432 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 125013.975311 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 125211.424805 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383884 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383884 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014200 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014200 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.250298 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.250298 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014200 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.279525 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.173237 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014200 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.279525 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.173237 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 24653.846154 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 24653.846154 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127548.989899 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127548.989899 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130849.053030 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130849.053030 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123982.979803 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123982.979803 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130849.053030 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 125054.458565 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 125244.733091 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130849.053030 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 125054.458565 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 125244.733091 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -829,131 +844,128 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 74231 # number of writebacks -system.cpu.l2cache.writebacks::total 74231 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 280 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 280 # number of CleanEvict MSHR misses +system.cpu.l2cache.writebacks::writebacks 74281 # number of writebacks +system.cpu.l2cache.writebacks::total 74281 # number of writebacks system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116798 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116798 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 13263 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 13263 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 271959 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 271959 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 13263 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 388757 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 402020 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 13263 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 388757 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 402020 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116820 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116820 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 13200 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 13200 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 271971 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 271971 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 13200 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 388791 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 401991 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 13200 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 388791 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 401991 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9653 # number of WriteReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9653 # number of WriteReq MSHR uncacheable system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16583 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16583 # number of overall MSHR uncacheable misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 922500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 922500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13715906000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13715906000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1604809000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1604809000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30996582000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30996582000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1604809000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44712488000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 46317297000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1604809000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44712488000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 46317297000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1363484500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1363484500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1939234000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1939234000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3302718500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3302718500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 924500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 924500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13732073000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13732073000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1595207500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1595207500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31000065000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31000065000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1595207500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44732138000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 46327345500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1595207500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44732138000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 46327345500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1441222500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1441222500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2061377000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2061377000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3502599500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3502599500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383901 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383901 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014272 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014272 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250359 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250359 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014272 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279577 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173296 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014272 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279577 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173296 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70961.538462 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70961.538462 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117432.712889 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117432.712889 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120998.944432 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120998.944432 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113975.202144 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113975.202144 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120998.944432 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 115013.975311 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115211.424805 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120998.944432 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 115013.975311 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115211.424805 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196751.010101 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196751.010101 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200894.436963 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200894.436963 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199162.907797 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199162.907797 # average overall mshr uncacheable latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383884 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383884 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014200 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014200 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250298 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250298 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014200 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279525 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.173237 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014200 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279525 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.173237 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71115.384615 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71115.384615 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117548.989899 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117548.989899 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120849.053030 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120849.053030 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113982.979803 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113982.979803 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120849.053030 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 115054.458565 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115244.733091 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120849.053030 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 115054.458565 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115244.733091 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 207968.614719 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 207968.614719 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213547.808971 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213547.808971 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211216.275704 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211216.275704 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 4638553 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2318842 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1502 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1135 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1135 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 4639815 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319473 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1501 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1136 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1136 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2022707 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2023267 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9653 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9653 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 950299 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1744757 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 950745 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 928699 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 816471 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304240 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304240 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 929343 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1086450 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304311 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304311 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 929591 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1086762 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2787117 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4203130 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6990247 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59476672 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142457836 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 201934508 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 419768 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5074727 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000845 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.029056 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2787861 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4204279 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6992140 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118929280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142508140 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 261437420 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 419996 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2756910 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001015 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.031841 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5070439 99.92% 99.92% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4288 0.08% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2754112 99.90% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2798 0.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5074727 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3166927500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2756910 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4096881500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 293383 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1394014500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1394386500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2097540500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2098115000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1003,45 +1015,45 @@ system.iobus.pkt_size_system.bridge.master::total 44588 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2706196 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 4773000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 5340500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 371000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 174000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 15817000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 1891500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6032000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 212000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 82500 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 131000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 215085744 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 215014002 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer30.occupancy 45000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23513000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.339381 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.339384 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1774103808000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.339381 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.083711 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.083711 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1774106672000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.339384 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.083712 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.083712 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1055,14 +1067,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21913883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21913883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5427871861 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5427871861 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21913883 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21913883 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21913883 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21913883 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21742883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21742883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5428926119 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5428926119 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21742883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21742883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21742883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21742883 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1079,19 +1091,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126669.843931 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126669.843931 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130628.414059 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130628.414059 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 126669.843931 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126669.843931 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 126669.843931 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126669.843931 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125681.404624 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125681.404624 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130653.786075 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130653.786075 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 125681.404624 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125681.404624 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 125681.404624 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125681.404624 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 32 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1105,14 +1117,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 173 system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13263883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13263883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3350271861 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3350271861 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 13263883 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 13263883 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 13263883 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 13263883 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13092883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13092883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3351326119 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3351326119 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 13092883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 13092883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 13092883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 13092883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1121,59 +1133,59 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76669.843931 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76669.843931 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80628.414059 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80628.414059 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76669.843931 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76669.843931 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76669.843931 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76669.843931 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75681.404624 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 75681.404624 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80653.786075 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80653.786075 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75681.404624 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75681.404624 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75681.404624 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 75681.404624 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 292325 # Transaction distribution +system.membus.trans_dist::ReadResp 292274 # Transaction distribution system.membus.trans_dist::WriteReq 9653 # Transaction distribution system.membus.trans_dist::WriteResp 9653 # Transaction distribution -system.membus.trans_dist::Writeback 115743 # Transaction distribution -system.membus.trans_dist::CleanEvict 261495 # Transaction distribution -system.membus.trans_dist::UpgradeReq 132 # Transaction distribution -system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 116679 # Transaction distribution -system.membus.trans_dist::ReadExResp 116679 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 285395 # Transaction distribution +system.membus.trans_dist::WritebackDirty 115793 # Transaction distribution +system.membus.trans_dist::CleanEvict 261400 # Transaction distribution +system.membus.trans_dist::UpgradeReq 150 # Transaction distribution +system.membus.trans_dist::UpgradeResp 150 # Transaction distribution +system.membus.trans_dist::ReadExReq 116683 # Transaction distribution +system.membus.trans_dist::ReadExResp 116683 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 285344 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33166 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139506 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172672 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139403 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172569 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1297489 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1297386 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44588 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30455104 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30499692 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30455296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30499884 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33157420 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33157612 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 431 # Total snoops (count) -system.membus.snoop_fanout::samples 837762 # Request fanout histogram +system.membus.snoop_fanout::samples 837681 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 837762 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 837681 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 837762 # Request fanout histogram -system.membus.reqLayer0.occupancy 30061000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 837681 # Request fanout histogram +system.membus.reqLayer0.occupancy 30116000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1285186893 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1287207146 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2143459620 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2143288852 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 69854947 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 69814679 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA |