diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha')
-rw-r--r-- | tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt | 2772 | ||||
-rw-r--r-- | tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt | 1511 |
2 files changed, 2146 insertions, 2137 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 7159169af..4c75131c1 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,118 +1,118 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.962843 # Number of seconds simulated -sim_ticks 1962842856000 # Number of ticks simulated -final_tick 1962842856000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.962613 # Number of seconds simulated +sim_ticks 1962612686500 # Number of ticks simulated +final_tick 1962612686500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1228880 # Simulator instruction rate (inst/s) -host_op_rate 1228880 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39594262798 # Simulator tick rate (ticks/s) -host_mem_usage 373652 # Number of bytes of host memory used -host_seconds 49.57 # Real time elapsed on the host -sim_insts 60920382 # Number of instructions simulated -sim_ops 60920382 # Number of ops (including micro ops) simulated +host_inst_rate 1121045 # Simulator instruction rate (inst/s) +host_op_rate 1121044 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36128483856 # Simulator tick rate (ticks/s) +host_mem_usage 373592 # Number of bytes of host memory used +host_seconds 54.32 # Real time elapsed on the host +sim_insts 60898638 # Number of instructions simulated +sim_ops 60898638 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 823232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24883392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 41664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 386496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 836288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24736704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 28736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 435776 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26135744 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 823232 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 41664 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 864896 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7759040 # Number of bytes written to this memory -system.physmem.bytes_written::total 7759040 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12863 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 388803 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 651 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6039 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26038464 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 836288 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 28736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 865024 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7702400 # Number of bytes written to this memory +system.physmem.bytes_written::total 7702400 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13067 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 386511 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 449 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6809 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 408371 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 121235 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121235 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 419408 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12677221 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 21226 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 196906 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 406851 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120350 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120350 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 426110 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12603966 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 14642 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 222039 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13315250 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 419408 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 21226 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 440634 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3952960 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3952960 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3952960 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 419408 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12677221 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 21226 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 196906 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13267245 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 426110 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 14642 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 440751 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3924564 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3924564 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3924564 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 426110 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12603966 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 14642 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 222039 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 489 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17268211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 408371 # Number of read requests accepted -system.physmem.writeReqs 162787 # Number of write requests accepted -system.physmem.readBursts 408371 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 162787 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26128640 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue -system.physmem.bytesWritten 10277440 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26135744 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10418368 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2175 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 7051 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25705 # Per bank write bursts -system.physmem.perBankRdBursts::1 25985 # Per bank write bursts -system.physmem.perBankRdBursts::2 25737 # Per bank write bursts -system.physmem.perBankRdBursts::3 25534 # Per bank write bursts -system.physmem.perBankRdBursts::4 24847 # Per bank write bursts -system.physmem.perBankRdBursts::5 24754 # Per bank write bursts -system.physmem.perBankRdBursts::6 25534 # Per bank write bursts -system.physmem.perBankRdBursts::7 25489 # Per bank write bursts -system.physmem.perBankRdBursts::8 25150 # Per bank write bursts -system.physmem.perBankRdBursts::9 25518 # Per bank write bursts -system.physmem.perBankRdBursts::10 25462 # Per bank write bursts -system.physmem.perBankRdBursts::11 25296 # Per bank write bursts -system.physmem.perBankRdBursts::12 25577 # Per bank write bursts -system.physmem.perBankRdBursts::13 25454 # Per bank write bursts -system.physmem.perBankRdBursts::14 26241 # Per bank write bursts -system.physmem.perBankRdBursts::15 25977 # Per bank write bursts -system.physmem.perBankWrBursts::0 10598 # Per bank write bursts -system.physmem.perBankWrBursts::1 10761 # Per bank write bursts -system.physmem.perBankWrBursts::2 9727 # Per bank write bursts -system.physmem.perBankWrBursts::3 9433 # Per bank write bursts -system.physmem.perBankWrBursts::4 8910 # Per bank write bursts -system.physmem.perBankWrBursts::5 9140 # Per bank write bursts -system.physmem.perBankWrBursts::6 9908 # Per bank write bursts -system.physmem.perBankWrBursts::7 9771 # Per bank write bursts -system.physmem.perBankWrBursts::8 9710 # Per bank write bursts -system.physmem.perBankWrBursts::9 9867 # Per bank write bursts -system.physmem.perBankWrBursts::10 9923 # Per bank write bursts -system.physmem.perBankWrBursts::11 10306 # Per bank write bursts -system.physmem.perBankWrBursts::12 10733 # Per bank write bursts -system.physmem.perBankWrBursts::13 10678 # Per bank write bursts -system.physmem.perBankWrBursts::14 10553 # Per bank write bursts -system.physmem.perBankWrBursts::15 10567 # Per bank write bursts +system.physmem.bw_total::total 17191810 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 406851 # Number of read requests accepted +system.physmem.writeReqs 161902 # Number of write requests accepted +system.physmem.readBursts 406851 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 161902 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26031872 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6592 # Total number of bytes read from write queue +system.physmem.bytesWritten 8721536 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26038464 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10361728 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 103 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 25609 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 6974 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25141 # Per bank write bursts +system.physmem.perBankRdBursts::1 25398 # Per bank write bursts +system.physmem.perBankRdBursts::2 25524 # Per bank write bursts +system.physmem.perBankRdBursts::3 24918 # Per bank write bursts +system.physmem.perBankRdBursts::4 25169 # Per bank write bursts +system.physmem.perBankRdBursts::5 25258 # Per bank write bursts +system.physmem.perBankRdBursts::6 25808 # Per bank write bursts +system.physmem.perBankRdBursts::7 25541 # Per bank write bursts +system.physmem.perBankRdBursts::8 25675 # Per bank write bursts +system.physmem.perBankRdBursts::9 25330 # Per bank write bursts +system.physmem.perBankRdBursts::10 25284 # Per bank write bursts +system.physmem.perBankRdBursts::11 25615 # Per bank write bursts +system.physmem.perBankRdBursts::12 25647 # Per bank write bursts +system.physmem.perBankRdBursts::13 25653 # Per bank write bursts +system.physmem.perBankRdBursts::14 25754 # Per bank write bursts +system.physmem.perBankRdBursts::15 25033 # Per bank write bursts +system.physmem.perBankWrBursts::0 8965 # Per bank write bursts +system.physmem.perBankWrBursts::1 8625 # Per bank write bursts +system.physmem.perBankWrBursts::2 8456 # Per bank write bursts +system.physmem.perBankWrBursts::3 7799 # Per bank write bursts +system.physmem.perBankWrBursts::4 8065 # Per bank write bursts +system.physmem.perBankWrBursts::5 8041 # Per bank write bursts +system.physmem.perBankWrBursts::6 8610 # Per bank write bursts +system.physmem.perBankWrBursts::7 8172 # Per bank write bursts +system.physmem.perBankWrBursts::8 8465 # Per bank write bursts +system.physmem.perBankWrBursts::9 8053 # Per bank write bursts +system.physmem.perBankWrBursts::10 8222 # Per bank write bursts +system.physmem.perBankWrBursts::11 8481 # Per bank write bursts +system.physmem.perBankWrBursts::12 8850 # Per bank write bursts +system.physmem.perBankWrBursts::13 9510 # Per bank write bursts +system.physmem.perBankWrBursts::14 9309 # Per bank write bursts +system.physmem.perBankWrBursts::15 8651 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1962837817500 # Total gap between requests +system.physmem.numWrRetry 56 # Number of times write queue was full causing retry +system.physmem.totGap 1962566141500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 408371 # Read request sizes (log2) +system.physmem.readPktSize::6 406851 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 162787 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 408177 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 70 # What read queue length does an incoming req see +system.physmem.writePktSize::6 161902 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 406672 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 63 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see @@ -158,185 +158,190 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4404 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 8320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 9433 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 10077 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10961 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11550 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11941 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 12017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8581 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6888 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 69318 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 525.203843 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 317.866807 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 416.347675 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16137 23.28% 23.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 12161 17.54% 40.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5284 7.62% 48.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3087 4.45% 52.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3309 4.77% 57.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1757 2.53% 60.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1519 2.19% 62.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1296 1.87% 64.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24768 35.73% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 69318 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5881 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 69.418466 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2107.784288 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 5876 99.91% 99.91% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-8191 1 0.02% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-45055 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::73728-77823 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::122880-126975 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5881 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5881 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.305730 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.811619 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 33.369719 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4828 82.09% 82.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 189 3.21% 85.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 283 4.81% 90.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 60 1.02% 91.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 106 1.80% 92.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 43 0.73% 93.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 17 0.29% 93.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 8 0.14% 94.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 22 0.37% 94.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 7 0.12% 94.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 14 0.24% 94.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 3 0.05% 94.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 16 0.27% 95.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 2 0.03% 95.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 15 0.26% 95.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 48 0.82% 96.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 18 0.31% 96.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 12 0.20% 96.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 85 1.45% 98.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 44 0.75% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 9 0.15% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 24 0.41% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 10 0.17% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 3 0.05% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 5 0.09% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 2 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 2 0.03% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 2 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 3 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5881 # Writes before turning the bus around for reads -system.physmem.totQLat 2189518000 # Total ticks spent queuing -system.physmem.totMemAccLat 9844393000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2041300000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5363.05 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 1460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6003 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5615 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7778 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5982 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 943 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1933 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1989 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 2372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 2742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 2945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 98 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 67633 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 513.852823 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 307.797069 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 417.051196 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16141 23.87% 23.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 12717 18.80% 42.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5311 7.85% 50.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2897 4.28% 54.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2115 3.13% 57.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1690 2.50% 60.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2144 3.17% 63.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1403 2.07% 65.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 23215 34.32% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 67633 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4988 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 81.544306 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2972.635603 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 4985 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4988 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4988 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.320369 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.529999 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 62.006905 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 4741 95.05% 95.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 52 1.04% 96.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 5 0.10% 96.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 6 0.12% 96.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 4 0.08% 96.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 12 0.24% 96.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 26 0.52% 97.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 19 0.38% 97.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 10 0.20% 97.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 13 0.26% 98.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 3 0.06% 98.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 4 0.08% 98.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 2 0.04% 98.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 1 0.02% 98.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 2 0.04% 98.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 5 0.10% 98.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 5 0.10% 98.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 12 0.24% 98.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 16 0.32% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 4 0.08% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 10 0.20% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 2 0.04% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::432-447 1 0.02% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 4 0.08% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 2 0.04% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 2 0.04% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 2 0.04% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 10 0.20% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 3 0.06% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-591 1 0.02% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-687 1 0.02% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 2 0.04% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-719 2 0.04% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::720-735 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::736-751 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::816-831 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::928-943 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4988 # Writes before turning the bus around for reads +system.physmem.totQLat 2137453500 # Total ticks spent queuing +system.physmem.totMemAccLat 9763978500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2033740000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5254.98 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24113.05 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.31 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 5.24 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.32 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 5.31 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 24004.98 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.26 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.44 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.27 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 5.28 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.78 # Average write queue length when enqueuing -system.physmem.readRowHits 365775 # Number of row buffer hits during reads -system.physmem.writeRowHits 133752 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.59 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.28 # Row buffer hit rate for writes -system.physmem.avgGap 3436593.41 # Average gap between requests -system.physmem.pageHitRate 87.81 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 258098400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 140827500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1587963000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 507047040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 128202890400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 65554579665 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1120197596250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1316449002255 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.687203 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1863305388500 # Time in different power states -system.physmem_0.memoryStateTime::REF 65543400000 # Time in different power states +system.physmem.avgWrQLen 25.00 # Average write queue length when enqueuing +system.physmem.readRowHits 364433 # Number of row buffer hits during reads +system.physmem.writeRowHits 110956 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.60 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.41 # Row buffer hit rate for writes +system.physmem.avgGap 3450647.54 # Average gap between requests +system.physmem.pageHitRate 87.54 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 253449000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 138290625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1581504600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 432429840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 128188142160 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 66287825100 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1119418909500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1316300550825 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.688732 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1862013795212 # Time in different power states +system.physmem_0.memoryStateTime::REF 65535860000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 33987247750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 35060566038 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 265945680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 145109250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1596465000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 533543760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 128202890400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 65970100260 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1119833096250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1316547150600 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.737211 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1862702158750 # Time in different power states -system.physmem_1.memoryStateTime::REF 65543400000 # Time in different power states +system.physmem_1.actEnergy 257856480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 140695500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1591129800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 450625680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 128188142160 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 66523569975 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1119212115750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1316364135345 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.721130 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1861673243216 # Time in different power states +system.physmem_1.memoryStateTime::REF 65535860000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 34590463750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 35401118034 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7535038 # DTB read hits -system.cpu0.dtb.read_misses 7765 # DTB read misses +system.cpu0.dtb.read_hits 7492205 # DTB read hits +system.cpu0.dtb.read_misses 7443 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations -system.cpu0.dtb.read_accesses 524069 # DTB read accesses -system.cpu0.dtb.write_hits 5127057 # DTB write hits -system.cpu0.dtb.write_misses 910 # DTB write misses -system.cpu0.dtb.write_acv 133 # DTB write access violations -system.cpu0.dtb.write_accesses 202595 # DTB write accesses -system.cpu0.dtb.data_hits 12662095 # DTB hits -system.cpu0.dtb.data_misses 8675 # DTB misses -system.cpu0.dtb.data_acv 343 # DTB access violations -system.cpu0.dtb.data_accesses 726664 # DTB accesses -system.cpu0.itb.fetch_hits 3654300 # ITB hits -system.cpu0.itb.fetch_misses 3984 # ITB misses +system.cpu0.dtb.read_accesses 490673 # DTB read accesses +system.cpu0.dtb.write_hits 5067323 # DTB write hits +system.cpu0.dtb.write_misses 813 # DTB write misses +system.cpu0.dtb.write_acv 134 # DTB write access violations +system.cpu0.dtb.write_accesses 187452 # DTB write accesses +system.cpu0.dtb.data_hits 12559528 # DTB hits +system.cpu0.dtb.data_misses 8256 # DTB misses +system.cpu0.dtb.data_acv 344 # DTB access violations +system.cpu0.dtb.data_accesses 678125 # DTB accesses +system.cpu0.itb.fetch_hits 3501951 # ITB hits +system.cpu0.itb.fetch_misses 3871 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3658284 # ITB accesses +system.cpu0.itb.fetch_accesses 3505822 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -349,241 +354,240 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3925685712 # number of cpu cycles simulated +system.cpu0.numCycles 3923838766 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 47981838 # Number of instructions committed -system.cpu0.committedOps 47981838 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 44508329 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 212945 # Number of float alu accesses -system.cpu0.num_func_calls 1202945 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5633344 # number of instructions that are conditional controls -system.cpu0.num_int_insts 44508329 # number of integer instructions -system.cpu0.num_fp_insts 212945 # number of float instructions -system.cpu0.num_int_register_reads 61205329 # number of times the integer registers were read -system.cpu0.num_int_register_writes 33143507 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 104073 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 105864 # number of times the floating registers were written -system.cpu0.num_mem_refs 12703139 # number of memory refs -system.cpu0.num_load_insts 7562835 # Number of load instructions -system.cpu0.num_store_insts 5140304 # Number of store instructions -system.cpu0.num_idle_cycles 3702094605.998114 # Number of idle cycles -system.cpu0.num_busy_cycles 223591106.001886 # Number of busy cycles -system.cpu0.not_idle_fraction 0.056956 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.943044 # Percentage of idle cycles -system.cpu0.Branches 7224625 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2734428 5.70% 5.70% # Class of executed instruction -system.cpu0.op_class::IntAlu 31547561 65.74% 71.43% # Class of executed instruction -system.cpu0.op_class::IntMult 52422 0.11% 71.54% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.54% # Class of executed instruction -system.cpu0.op_class::FloatAdd 26783 0.06% 71.60% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1883 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::MemRead 7738872 16.13% 87.73% # Class of executed instruction -system.cpu0.op_class::MemWrite 5146421 10.72% 98.45% # Class of executed instruction -system.cpu0.op_class::IprAccess 742486 1.55% 100.00% # Class of executed instruction +system.cpu0.committedInsts 47743384 # Number of instructions committed +system.cpu0.committedOps 47743384 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44279734 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 210698 # Number of float alu accesses +system.cpu0.num_func_calls 1202353 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5609016 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44279734 # number of integer instructions +system.cpu0.num_fp_insts 210698 # number of float instructions +system.cpu0.num_int_register_reads 60867436 # number of times the integer registers were read +system.cpu0.num_int_register_writes 32999466 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 102334 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 104190 # number of times the floating registers were written +system.cpu0.num_mem_refs 12599731 # number of memory refs +system.cpu0.num_load_insts 7519361 # Number of load instructions +system.cpu0.num_store_insts 5080370 # Number of store instructions +system.cpu0.num_idle_cycles 3698952400.393103 # Number of idle cycles +system.cpu0.num_busy_cycles 224886365.606898 # Number of busy cycles +system.cpu0.not_idle_fraction 0.057313 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.942687 # Percentage of idle cycles +system.cpu0.Branches 7198745 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2727567 5.71% 5.71% # Class of executed instruction +system.cpu0.op_class::IntAlu 31426598 65.81% 71.52% # Class of executed instruction +system.cpu0.op_class::IntMult 52886 0.11% 71.63% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 71.63% # Class of executed instruction +system.cpu0.op_class::FloatAdd 25715 0.05% 71.69% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1656 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::MemRead 7694830 16.11% 87.81% # Class of executed instruction +system.cpu0.op_class::MemWrite 5086464 10.65% 98.46% # Class of executed instruction +system.cpu0.op_class::IprAccess 736268 1.54% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 47990856 # Class of executed instruction +system.cpu0.op_class::total 47751984 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 165589 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 56925 40.22% 40.22% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.31% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1976 1.40% 41.70% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 424 0.30% 42.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 82092 58.00% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 141548 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 56392 49.08% 49.08% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.inst.quiesce 6802 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 164994 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 56858 40.19% 40.19% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1973 1.39% 41.68% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 421 0.30% 41.97% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 82092 58.03% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 141475 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 56322 49.08% 49.08% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1976 1.72% 50.92% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 424 0.37% 51.29% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 55969 48.71% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 114892 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1903333022000 96.97% 96.97% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 94388000 0.00% 96.97% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 768238500 0.04% 97.01% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 314332500 0.02% 97.03% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 58332103000 2.97% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1962842084000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.990637 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 421 0.37% 51.28% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 55901 48.72% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 114748 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1900658476000 96.88% 96.88% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 90840500 0.00% 96.88% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 754578500 0.04% 96.92% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 304090000 0.02% 96.94% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 60111368000 3.06% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1961919353000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.990573 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.681784 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.811682 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed -system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed -system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed -system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed -system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed -system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed -system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed -system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed -system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 234 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.680956 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.811083 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed +system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed +system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed +system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed +system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed +system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed +system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed +system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 222 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 512 0.34% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wripir 503 0.34% 0.34% # number of callpals executed system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3097 2.07% 2.41% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed -system.cpu0.kern.callpal::swpipl 134593 89.81% 92.26% # number of callpals executed -system.cpu0.kern.callpal::rdps 6634 4.43% 96.68% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.68% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 96.69% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.69% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.69% # number of callpals executed -system.cpu0.kern.callpal::rti 4424 2.95% 99.64% # number of callpals executed -system.cpu0.kern.callpal::callsys 394 0.26% 99.91% # number of callpals executed -system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 149871 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7013 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1370 # number of protection mode switches +system.cpu0.kern.callpal::swpctx 3067 2.05% 2.39% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed +system.cpu0.kern.callpal::swpipl 134616 89.86% 92.28% # number of callpals executed +system.cpu0.kern.callpal::rdps 6699 4.47% 96.75% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.76% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.76% # number of callpals executed +system.cpu0.kern.callpal::rti 4333 2.89% 99.65% # number of callpals executed +system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 149812 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6888 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1282 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1369 -system.cpu0.kern.mode_good::user 1370 +system.cpu0.kern.mode_good::kernel 1282 +system.cpu0.kern.mode_good::user 1282 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.195209 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.186121 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.326733 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1959061538500 99.81% 99.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3780541000 0.19% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.313831 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1958151397500 99.82% 99.82% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3535867500 0.18% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3098 # number of times the context was actually changed -system.cpu0.dcache.tags.replacements 1190069 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.197532 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11466522 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1190581 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.631031 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 108210250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.197532 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986714 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986714 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51892703 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51892703 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6451021 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6451021 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4712504 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4712504 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140772 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 140772 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148353 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 148353 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11163525 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11163525 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11163525 # number of overall hits -system.cpu0.dcache.overall_hits::total 11163525 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 942274 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 942274 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 257633 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 257633 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13709 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13709 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5579 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5579 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1199907 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1199907 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1199907 # number of overall misses -system.cpu0.dcache.overall_misses::total 1199907 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27224956000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 27224956000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10342084186 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 10342084186 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150000000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 150000000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 42703895 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 42703895 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 37567040186 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 37567040186 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 37567040186 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 37567040186 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7393295 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7393295 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4970137 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4970137 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154481 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 154481 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153932 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 153932 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12363432 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12363432 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12363432 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12363432 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127450 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.127450 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051836 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051836 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088742 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088742 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.036243 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.036243 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097053 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.097053 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097053 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097053 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28892.823107 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 28892.823107 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40142.699833 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 40142.699833 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10941.717120 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10941.717120 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7654.399534 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7654.399534 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31308.293214 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 31308.293214 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31308.293214 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 31308.293214 # average overall miss latency +system.cpu0.kern.swap_context 3068 # number of times the context was actually changed +system.cpu0.dcache.tags.replacements 1180939 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.262035 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11368359 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1181356 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.623144 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 112435250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.262035 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986840 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986840 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 417 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 372 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 45 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.814453 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 51471280 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 51471280 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6411907 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6411907 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4659091 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4659091 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140391 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 140391 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148074 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 148074 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11070998 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11070998 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11070998 # number of overall hits +system.cpu0.dcache.overall_hits::total 11070998 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 938638 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 938638 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 251661 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 251661 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13662 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13662 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5430 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 5430 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1190299 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1190299 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1190299 # number of overall misses +system.cpu0.dcache.overall_misses::total 1190299 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 29060390999 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 29060390999 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10906399185 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 10906399185 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150333500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 150333500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 48525392 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 48525392 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 39966790184 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 39966790184 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 39966790184 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 39966790184 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7350545 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7350545 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4910752 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4910752 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154053 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 154053 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153504 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 153504 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12261297 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12261297 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12261297 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12261297 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127696 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.127696 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051247 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051247 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088684 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088684 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035374 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035374 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097078 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.097078 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097078 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.097078 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30960.168882 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 30960.168882 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43337.661318 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 43337.661318 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11003.769580 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11003.769580 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8936.536280 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8936.536280 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33577.101370 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33577.101370 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33577.101370 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33577.101370 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -592,62 +596,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 685914 # number of writebacks -system.cpu0.dcache.writebacks::total 685914 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 942274 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 942274 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 257633 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 257633 # 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average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 679102 # number of writebacks +system.cpu0.dcache.writebacks::total 679102 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 938638 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 938638 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251661 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 251661 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13662 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13662 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5430 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5430 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1190299 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1190299 # 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number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38003531316 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 38003531316 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38003531316 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 38003531316 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1474416000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1474416000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2293895500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2293895500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3768311500 # 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Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 436 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 48691282 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 48691282 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 47290432 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 47290432 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 47290432 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 47290432 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 47290432 # number of overall hits -system.cpu0.icache.overall_hits::total 47290432 # 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number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47990857 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47990857 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47990857 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47990857 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47990857 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47990857 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014595 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014595 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014595 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014595 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014595 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014595 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14228.438085 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14228.438085 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14228.438085 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14228.438085 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14228.438085 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14228.438085 # average overall miss latency +system.cpu0.icache.tags.replacements 698758 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.155937 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 47052596 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 699270 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.288166 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 42435665250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.155937 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992492 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.992492 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 356 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 156 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 48451372 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 48451372 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 47052596 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 47052596 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 47052596 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 47052596 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 47052596 # number of overall hits +system.cpu0.icache.overall_hits::total 47052596 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 699388 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 699388 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 699388 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 699388 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 699388 # number of overall misses +system.cpu0.icache.overall_misses::total 699388 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10012837997 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10012837997 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10012837997 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10012837997 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10012837997 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10012837997 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47751984 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47751984 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47751984 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47751984 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47751984 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47751984 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014646 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014646 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014646 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014646 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014646 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014646 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14316.571055 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14316.571055 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14316.571055 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14316.571055 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14316.571055 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14316.571055 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -716,51 +718,51 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 700425 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 700425 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 700425 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 700425 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 700425 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 700425 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8560109254 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 8560109254 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8560109254 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 8560109254 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8560109254 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 8560109254 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014595 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014595 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014595 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12221.307426 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12221.307426 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12221.307426 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12221.307426 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12221.307426 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12221.307426 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 699388 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 699388 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 699388 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 699388 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 699388 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 699388 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8958710003 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 8958710003 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8958710003 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 8958710003 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8958710003 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 8958710003 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014646 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014646 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014646 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014646 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014646 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014646 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12809.356184 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12809.356184 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12809.356184 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12809.356184 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12809.356184 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12809.356184 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2381610 # DTB read hits -system.cpu1.dtb.read_misses 2620 # DTB read misses +system.cpu1.dtb.read_hits 2419579 # DTB read hits +system.cpu1.dtb.read_misses 2992 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations -system.cpu1.dtb.read_accesses 205337 # DTB read accesses -system.cpu1.dtb.write_hits 1701782 # DTB write hits -system.cpu1.dtb.write_misses 235 # DTB write misses -system.cpu1.dtb.write_acv 24 # DTB write access violations -system.cpu1.dtb.write_accesses 89739 # DTB write accesses -system.cpu1.dtb.data_hits 4083392 # DTB hits -system.cpu1.dtb.data_misses 2855 # DTB misses -system.cpu1.dtb.data_acv 24 # DTB access violations -system.cpu1.dtb.data_accesses 295076 # DTB accesses -system.cpu1.itb.fetch_hits 1808769 # ITB hits -system.cpu1.itb.fetch_misses 1064 # ITB misses +system.cpu1.dtb.read_accesses 239363 # DTB read accesses +system.cpu1.dtb.write_hits 1757217 # DTB write hits +system.cpu1.dtb.write_misses 341 # DTB write misses +system.cpu1.dtb.write_acv 29 # DTB write access violations +system.cpu1.dtb.write_accesses 105247 # DTB write accesses +system.cpu1.dtb.data_hits 4176796 # DTB hits +system.cpu1.dtb.data_misses 3333 # DTB misses +system.cpu1.dtb.data_acv 29 # DTB access violations +system.cpu1.dtb.data_accesses 344610 # DTB accesses +system.cpu1.itb.fetch_hits 1964101 # ITB hits +system.cpu1.itb.fetch_misses 1216 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1809833 # ITB accesses +system.cpu1.itb.fetch_accesses 1965317 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -773,219 +775,220 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3923834021 # number of cpu cycles simulated +system.cpu1.numCycles 3925225373 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 12938544 # Number of instructions committed -system.cpu1.committedOps 12938544 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 11924615 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 171199 # Number of float alu accesses -system.cpu1.num_func_calls 411382 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1282019 # number of instructions that are conditional controls -system.cpu1.num_int_insts 11924615 # number of integer instructions -system.cpu1.num_fp_insts 171199 # number of float instructions -system.cpu1.num_int_register_reads 16391744 # number of times the integer registers were read -system.cpu1.num_int_register_writes 8774012 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 88996 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 90942 # number of times the floating registers were written -system.cpu1.num_mem_refs 4106042 # number of memory refs -system.cpu1.num_load_insts 2395192 # Number of load instructions -system.cpu1.num_store_insts 1710850 # Number of store instructions -system.cpu1.num_idle_cycles 3874343491.006502 # Number of idle cycles -system.cpu1.num_busy_cycles 49490529.993498 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012613 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987387 # Percentage of idle cycles -system.cpu1.Branches 1847277 # Number of branches fetched -system.cpu1.op_class::No_OpClass 699299 5.40% 5.40% # Class of executed instruction -system.cpu1.op_class::IntAlu 7669413 59.26% 64.67% # Class of executed instruction -system.cpu1.op_class::IntMult 22263 0.17% 64.84% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.84% # Class of executed instruction -system.cpu1.op_class::FloatAdd 13113 0.10% 64.94% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1759 0.01% 64.95% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::MemRead 2466523 19.06% 84.01% # Class of executed instruction -system.cpu1.op_class::MemWrite 1711831 13.23% 97.24% # Class of executed instruction -system.cpu1.op_class::IprAccess 357222 2.76% 100.00% # Class of executed instruction +system.cpu1.committedInsts 13155254 # Number of instructions committed +system.cpu1.committedOps 13155254 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 12132982 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 173111 # Number of float alu accesses +system.cpu1.num_func_calls 411301 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1304865 # number of instructions that are conditional controls +system.cpu1.num_int_insts 12132982 # number of integer instructions +system.cpu1.num_fp_insts 173111 # number of float instructions +system.cpu1.num_int_register_reads 16703630 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8903954 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 90570 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 92446 # number of times the floating registers were written +system.cpu1.num_mem_refs 4200357 # number of memory refs +system.cpu1.num_load_insts 2433886 # Number of load instructions +system.cpu1.num_store_insts 1766471 # Number of store instructions +system.cpu1.num_idle_cycles 3876126897.998025 # Number of idle cycles +system.cpu1.num_busy_cycles 49098475.001975 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012508 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987492 # Percentage of idle cycles +system.cpu1.Branches 1871330 # Number of branches fetched +system.cpu1.op_class::No_OpClass 704516 5.35% 5.35% # Class of executed instruction +system.cpu1.op_class::IntAlu 7779367 59.12% 64.47% # Class of executed instruction +system.cpu1.op_class::IntMult 21509 0.16% 64.64% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.64% # Class of executed instruction +system.cpu1.op_class::FloatAdd 14171 0.11% 64.75% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.75% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.75% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.75% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1986 0.02% 64.76% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::MemRead 2505658 19.04% 83.80% # Class of executed instruction +system.cpu1.op_class::MemWrite 1767460 13.43% 97.23% # Class of executed instruction +system.cpu1.op_class::IprAccess 363949 2.77% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 12941423 # Class of executed instruction +system.cpu1.op_class::total 13158616 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2766 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 77895 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 26463 38.26% 38.26% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1970 2.85% 41.11% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 512 0.74% 41.85% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 40215 58.15% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 69160 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 25619 48.15% 48.15% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1970 3.70% 51.85% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 512 0.96% 52.81% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 25107 47.19% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 53208 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1910451046000 97.38% 97.38% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 701160000 0.04% 97.41% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 358891000 0.02% 97.43% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 50405883500 2.57% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1961916980500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.968106 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2740 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 78523 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 26526 38.34% 38.34% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1967 2.84% 41.19% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 503 0.73% 41.91% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 40183 58.09% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 69179 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 25685 48.16% 48.16% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1967 3.69% 51.84% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 503 0.94% 52.79% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 25182 47.21% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 53337 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1909492808500 97.29% 97.29% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 698045000 0.04% 97.33% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 344048000 0.02% 97.35% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 52077063000 2.65% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1962611964500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.968295 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.624319 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.769346 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed -system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed -system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed -system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed -system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed -system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed -system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed -system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed -system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed -system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed -system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed -system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed -system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 92 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.626683 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.771000 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed +system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed +system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed +system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed +system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed +system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed +system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed +system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 104 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 424 0.59% 0.59% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.60% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1967 2.75% 3.35% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 3.35% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.36% # number of callpals executed -system.cpu1.kern.callpal::swpipl 62985 88.13% 91.49% # number of callpals executed -system.cpu1.kern.callpal::rdps 2216 3.10% 94.59% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.60% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.00% 94.60% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.60% # number of callpals executed -system.cpu1.kern.callpal::rti 3692 5.17% 99.77% # number of callpals executed -system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 421 0.59% 0.59% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1997 2.79% 3.39% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 3.39% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.40% # number of callpals executed +system.cpu1.kern.callpal::swpipl 62934 88.05% 91.45% # number of callpals executed +system.cpu1.kern.callpal::rdps 2145 3.00% 94.46% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.46% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 94.46% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.47% # number of callpals executed +system.cpu1.kern.callpal::rti 3774 5.28% 99.75% # number of callpals executed +system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed +system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 71468 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1923 # number of protection mode switches -system.cpu1.kern.mode_switch::user 368 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2902 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 804 -system.cpu1.kern.mode_good::user 368 -system.cpu1.kern.mode_good::idle 436 -system.cpu1.kern.mode_switch_good::kernel 0.418097 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 71473 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2064 # number of protection mode switches +system.cpu1.kern.mode_switch::user 463 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2877 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 890 +system.cpu1.kern.mode_good::user 463 +system.cpu1.kern.mode_good::idle 427 +system.cpu1.kern.mode_switch_good::kernel 0.431202 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.150241 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.309648 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 17982324500 0.92% 0.92% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1495094500 0.08% 0.99% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1941563117500 99.01% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1968 # number of times the context was actually changed -system.cpu1.dcache.tags.replacements 157282 # number of replacements -system.cpu1.dcache.tags.tagsinuse 486.069018 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 3911225 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 157609 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 24.816000 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1048852201500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.069018 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949354 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.949354 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 327 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 295 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.638672 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 16556980 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 16556980 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2220683 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2220683 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1590246 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1590246 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 47776 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 47776 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50237 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 50237 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3810929 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3810929 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3810929 # number of overall hits -system.cpu1.dcache.overall_hits::total 3810929 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 115097 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 115097 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 57138 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 57138 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8903 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 8903 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5967 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 5967 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 172235 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 172235 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 172235 # number of overall misses -system.cpu1.dcache.overall_misses::total 172235 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1388298999 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1388298999 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1079375302 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1079375302 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 80583500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 80583500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 43835417 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 43835417 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 2467674301 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 2467674301 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 2467674301 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 2467674301 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2335780 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2335780 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1647384 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1647384 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 56679 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 56679 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56204 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 56204 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 3983164 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3983164 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 3983164 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3983164 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049276 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.049276 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034684 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.034684 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.157078 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.157078 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106167 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106167 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043241 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.043241 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043241 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.043241 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12061.991181 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12061.991181 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18890.673492 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18890.673492 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9051.274851 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9051.274851 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7346.307525 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7346.307525 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14327.368427 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14327.368427 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14327.368427 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14327.368427 # average overall miss latency +system.cpu1.kern.mode_switch_good::idle 0.148418 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.329386 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 17700699500 0.90% 0.90% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1706728000 0.09% 0.99% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1943204535000 99.01% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1998 # number of times the context was actually changed +system.cpu1.dcache.tags.replacements 166165 # number of replacements +system.cpu1.dcache.tags.tagsinuse 485.164459 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 4008469 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 166677 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 24.049323 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 79256927000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.164459 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.947587 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.947587 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 16941101 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 16941101 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 2255044 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2255044 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1640007 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1640007 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48683 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 48683 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50718 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 50718 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3895051 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3895051 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3895051 # number of overall hits +system.cpu1.dcache.overall_hits::total 3895051 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 118164 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 118164 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 62534 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 62534 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8914 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 8914 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5850 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 5850 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 180698 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 180698 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 180698 # number of overall misses +system.cpu1.dcache.overall_misses::total 180698 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1427964750 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1427964750 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1264688999 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1264688999 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 81194500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 81194500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 50099897 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 50099897 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 2692653749 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 2692653749 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 2692653749 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 2692653749 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2373208 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2373208 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1702541 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1702541 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57597 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 57597 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56568 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 56568 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4075749 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4075749 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4075749 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4075749 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049791 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.049791 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036730 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.036730 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.154765 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.154765 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103415 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103415 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044335 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.044335 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044335 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.044335 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12084.600640 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12084.600640 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20224.022116 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 20224.022116 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9108.649316 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9108.649316 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8564.084957 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8564.084957 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14901.403164 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14901.403164 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14901.403164 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14901.403164 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -994,62 +997,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 107942 # number of writebacks -system.cpu1.dcache.writebacks::total 107942 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 115097 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 115097 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 57138 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 57138 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8903 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8903 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5967 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 5967 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 172235 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 172235 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 172235 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 172235 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1158014001 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1158014001 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 962534698 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 962534698 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 62777500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 62777500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31899583 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31899583 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2120548699 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2120548699 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2120548699 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2120548699 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 22446500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 22446500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 726754500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 726754500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 749201000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 749201000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049276 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049276 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034684 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034684 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.157078 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.157078 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106167 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106167 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043241 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.043241 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043241 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.043241 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10061.200561 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10061.200561 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16845.789107 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16845.789107 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7051.274851 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7051.274851 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5346.000168 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5346.000168 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12311.949946 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12311.949946 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12311.949946 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12311.949946 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 114146 # number of writebacks +system.cpu1.dcache.writebacks::total 114146 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118164 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 118164 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62534 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 62534 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8914 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8914 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5850 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 5850 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 180698 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 180698 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 180698 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 180698 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1250643250 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1250643250 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1167915001 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1167915001 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67823500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 67823500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 41323103 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 41323103 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2418558251 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2418558251 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2418558251 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2418558251 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18864000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18864000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 716373000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 716373000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 735237000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 735237000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049791 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049791 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036730 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036730 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.154765 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.154765 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103415 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103415 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044335 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.044335 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044335 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.044335 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10583.961697 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10583.961697 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18676.480011 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18676.480011 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7608.649316 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7608.649316 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7063.778291 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7063.778291 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13384.532485 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13384.532485 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13384.532485 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13384.532485 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1057,58 +1060,59 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 318148 # number of replacements -system.cpu1.icache.tags.tagsinuse 446.541580 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 12622723 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 318660 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 39.611884 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1956986313500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.541580 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.872152 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.872152 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 315648 # number of replacements +system.cpu1.icache.tags.tagsinuse 445.931523 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 12842415 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 316160 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 40.619987 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1961765828000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.931523 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.870960 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.870960 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 72 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 439 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 13260123 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 13260123 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 12622723 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 12622723 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 12622723 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 12622723 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 12622723 # number of overall hits -system.cpu1.icache.overall_hits::total 12622723 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 318700 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 318700 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 318700 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 318700 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 318700 # number of overall misses -system.cpu1.icache.overall_misses::total 318700 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4202225742 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4202225742 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4202225742 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4202225742 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4202225742 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4202225742 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 12941423 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 12941423 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 12941423 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 12941423 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 12941423 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 12941423 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024626 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024626 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024626 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024626 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024626 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024626 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13185.521625 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13185.521625 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13185.521625 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13185.521625 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13185.521625 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13185.521625 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 13474819 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 13474819 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 12842415 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 12842415 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 12842415 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 12842415 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 12842415 # number of overall hits +system.cpu1.icache.overall_hits::total 12842415 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 316202 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 316202 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 316202 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 316202 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 316202 # number of overall misses +system.cpu1.icache.overall_misses::total 316202 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4145253739 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4145253739 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4145253739 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4145253739 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4145253739 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4145253739 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 13158617 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13158617 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 13158617 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 13158617 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 13158617 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 13158617 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024030 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024030 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024030 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024030 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024030 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024030 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13109.511448 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13109.511448 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13109.511448 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13109.511448 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13109.511448 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13109.511448 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1117,30 +1121,30 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 318700 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 318700 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 318700 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 318700 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 318700 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 318700 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3564575258 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3564575258 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3564575258 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3564575258 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3564575258 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3564575258 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024626 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024626 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024626 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024626 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024626 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024626 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11184.735670 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11184.735670 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11184.735670 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11184.735670 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11184.735670 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11184.735670 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 316202 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 316202 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 316202 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 316202 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 316202 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 316202 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3670775261 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3670775261 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3670775261 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3670775261 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3670775261 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3670775261 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024030 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024030 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024030 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024030 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024030 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024030 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11608.956493 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11608.956493 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11608.956493 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11608.956493 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11608.956493 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11608.956493 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1156,11 +1160,11 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 7373 # Transaction distribution system.iobus.trans_dist::ReadResp 7373 # Transaction distribution -system.iobus.trans_dist::WriteReq 55631 # Transaction distribution -system.iobus.trans_dist::WriteResp 14079 # Transaction distribution +system.iobus.trans_dist::WriteReq 55604 # Transaction distribution +system.iobus.trans_dist::WriteResp 14052 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13950 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13892 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1171,12 +1175,12 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 42552 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83456 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83456 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 126008 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55800 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 42502 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 125954 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) @@ -1187,13 +1191,13 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 82034 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661632 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661632 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2743666 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 13305000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 81834 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2743450 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 13247000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1213,52 +1217,52 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 406213784 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 242106937 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28473000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 28450000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42016500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42027500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41696 # number of replacements -system.iocache.tags.tagsinuse 0.577776 # Cycle average of tags in use +system.iocache.tags.replacements 41694 # number of replacements +system.iocache.tags.tagsinuse 0.567924 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41712 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1755504098000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.577776 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.036111 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.036111 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1756483552000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.567924 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035495 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035495 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375552 # Number of tag accesses -system.iocache.tags.data_accesses 375552 # Number of data accesses -system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses -system.iocache.ReadReq_misses::total 176 # number of ReadReq misses +system.iocache.tags.tag_accesses 375534 # Number of tag accesses +system.iocache.tags.data_accesses 375534 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses +system.iocache.ReadReq_misses::total 174 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses -system.iocache.demand_misses::tsunami.ide 176 # number of demand (read+write) misses -system.iocache.demand_misses::total 176 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 176 # number of overall misses -system.iocache.overall_misses::total 176 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21474383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21474383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13634467901 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 13634467901 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21474383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21474383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21474383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21474383 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses +system.iocache.demand_misses::total 174 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 174 # number of overall misses +system.iocache.overall_misses::total 174 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21822883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21822883 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8775454554 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 8775454554 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21822883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21822883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21822883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21822883 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 176 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 176 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 176 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 176 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 174 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 174 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses @@ -1267,40 +1271,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122013.539773 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122013.539773 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328130.244056 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 328130.244056 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 122013.539773 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 122013.539773 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 206274 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125418.867816 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125418.867816 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211192.109983 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 211192.109983 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 125418.867816 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125418.867816 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 125418.867816 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125418.867816 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 72753 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23554 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 9972 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.757493 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.295728 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 176 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 176 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 176 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12321383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12321383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11473763901 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11473763901 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12321383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12321383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12321383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12321383 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 174 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 174 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 174 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12615883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12615883 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6614750554 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6614750554 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12615883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12615883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12615883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12615883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1309,189 +1313,189 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70007.857955 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276130.244056 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276130.244056 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72505.074713 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72505.074713 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159192.109983 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159192.109983 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72505.074713 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72505.074713 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72505.074713 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72505.074713 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 342765 # number of replacements -system.l2c.tags.tagsinuse 65220.427494 # Cycle average of tags in use -system.l2c.tags.total_refs 2449404 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 407938 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.004354 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 8652068750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55273.007246 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4809.132503 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4932.058830 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 161.965185 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 44.263730 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.843399 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.073382 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.075257 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002471 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000675 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995185 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65173 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 767 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5220 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7222 # 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number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 23 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 66 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 129887 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 42518 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 172405 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 687538 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 798040 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 318040 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 147752 # number of demand (read+write) hits -system.l2c.demand_hits::total 1951370 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 687538 # number of overall hits -system.l2c.overall_hits::cpu0.data 798040 # number of overall hits -system.l2c.overall_hits::cpu1.inst 318040 # number of overall hits -system.l2c.overall_hits::cpu1.data 147752 # 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number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 21179000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 18676711000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 1101962 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 10166561 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 11268523 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 873463 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 278988 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 1152451 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 8137748269 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 426449979 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 8564198248 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 942533250 # 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number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 105527 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2064334 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 793856 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 793856 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 3137 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 2324 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 5461 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 938 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 940 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1878 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 247869 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 48299 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 296168 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 700404 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1187573 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 318699 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 153826 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2360502 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 700404 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1187573 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 318699 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 153826 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2360502 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.018369 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.288975 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.002068 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.002777 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.138238 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.942939 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.766781 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.867973 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.954158 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.975532 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.964856 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.475985 # 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average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 65053.255190 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72416.160850 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 72283.276451 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 65447.581903 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 372.536173 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5705.140853 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 2377.325527 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 975.936313 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 304.239913 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 636.010486 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 68974.489914 # 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number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 888765750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 16305067500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 31138500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 15561750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 17240533500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 51864446 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 30663235 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 82527681 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 15769892 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 15706897 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 31476789 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7347142739 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 457723764 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 7804866503 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 888765750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 23652210239 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 31138500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 473285514 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 25045400003 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 888765750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 23652210239 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 31138500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 473285514 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 25045400003 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1374876000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17618000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1392494000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2153053500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 674538500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2827592000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3527929500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 692156500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4220086000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018684 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.290186 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001420 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002148 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.138498 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941571 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.768142 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.868880 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.961207 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.973941 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.967550 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.477466 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.122420 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.412904 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018684 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.328679 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001420 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.041920 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.172964 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018684 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.328679 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001420 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.041920 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.172964 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68016.051886 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 60025.429251 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69350.779510 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66503.205128 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 60411.279811 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17587.129875 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17663.153802 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17615.300107 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17679.251121 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17510.476031 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17594.627725 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 63541.757020 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69467.865230 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 63861.249779 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68016.051886 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61075.316359 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69350.779510 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69366.189946 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 61445.724022 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68016.051886 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61075.316359 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69350.779510 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69366.189946 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 61445.724022 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1626,96 +1630,96 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 292731 # Transaction distribution -system.membus.trans_dist::ReadResp 292731 # Transaction distribution -system.membus.trans_dist::WriteReq 14079 # Transaction distribution -system.membus.trans_dist::WriteResp 14079 # Transaction distribution -system.membus.trans_dist::Writeback 121235 # Transaction distribution +system.membus.trans_dist::ReadReq 292759 # Transaction distribution +system.membus.trans_dist::ReadResp 292759 # Transaction distribution +system.membus.trans_dist::WriteReq 14052 # Transaction distribution +system.membus.trans_dist::WriteResp 14052 # Transaction distribution +system.membus.trans_dist::Writeback 120350 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16420 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11480 # Transaction distribution -system.membus.trans_dist::UpgradeResp 7054 # Transaction distribution -system.membus.trans_dist::ReadExReq 124107 # Transaction distribution -system.membus.trans_dist::ReadExResp 123261 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42552 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 932487 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 975039 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124815 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124815 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1099854 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82034 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31236544 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31318578 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 16060 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 11220 # Transaction distribution +system.membus.trans_dist::UpgradeResp 6977 # Transaction distribution +system.membus.trans_dist::ReadExReq 122543 # Transaction distribution +system.membus.trans_dist::ReadExResp 121713 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42502 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 927849 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 970351 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124813 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124813 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1095164 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 81834 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31082624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31164458 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36636146 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 22119 # Total snoops (count) -system.membus.snoop_fanout::samples 600328 # Request fanout histogram +system.membus.pkt_size::total 36482026 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 21558 # Total snoops (count) +system.membus.snoop_fanout::samples 597341 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 600328 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 597341 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 600328 # Request fanout histogram -system.membus.reqLayer0.occupancy 40794500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 597341 # Request fanout histogram +system.membus.reqLayer0.occupancy 40208500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1915022000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1232118814 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3840524699 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 43136500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2189522527 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 42501500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 2106481 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2106466 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14079 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14079 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 793856 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 16639 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11546 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 28185 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 298132 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 298132 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1400829 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3132611 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 637399 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 458996 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5629835 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44825856 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119969536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20396736 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16779122 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 201971250 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 99473 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3261009 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.012796 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.112394 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 2102341 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2102326 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 14052 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 14052 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 793248 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 41590 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 16264 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11280 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 27544 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 297931 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 297931 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1398755 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3106837 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 632403 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 482171 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5620166 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44759488 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118936680 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20236864 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17747522 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 201680554 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 98552 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3255455 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.012829 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.112536 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 3219281 98.72% 98.72% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 41728 1.28% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 3213691 98.72% 98.72% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 41764 1.28% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3261009 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4802800383 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3255455 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2417745499 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 238500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3154409746 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5532665081 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1434275242 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 787817718 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1051604997 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1901998576 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 474390739 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 282399146 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 5c3a9c7d0..d63246d54 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.920419 # Number of seconds simulated -sim_ticks 1920418772000 # Number of ticks simulated -final_tick 1920418772000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.922414 # Number of seconds simulated +sim_ticks 1922413663500 # Number of ticks simulated +final_tick 1922413663500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1235696 # Simulator instruction rate (inst/s) -host_op_rate 1235696 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42298287542 # Simulator tick rate (ticks/s) -host_mem_usage 370580 # Number of bytes of host memory used -host_seconds 45.40 # Real time elapsed on the host -sim_insts 56102800 # Number of instructions simulated -sim_ops 56102800 # Number of ops (including micro ops) simulated +host_inst_rate 1122927 # Simulator instruction rate (inst/s) +host_op_rate 1122927 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38428929684 # Simulator tick rate (ticks/s) +host_mem_usage 370248 # Number of bytes of host memory used +host_seconds 50.03 # Real time elapsed on the host +sim_insts 56174594 # Number of instructions simulated +sim_ops 56174594 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24857984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 850624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24859584 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25709504 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 850560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 850560 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7403648 # Number of bytes written to this memory -system.physmem.bytes_written::total 7403648 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13290 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388406 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25711168 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 850624 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 850624 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7404352 # Number of bytes written to this memory +system.physmem.bytes_written::total 7404352 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13291 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388431 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 401711 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115682 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115682 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 442903 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12944043 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 500 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13387447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 442903 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 442903 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3855226 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3855226 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3855226 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 442903 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12944043 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 500 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17242673 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 401711 # Number of read requests accepted -system.physmem.writeReqs 157234 # Number of write requests accepted -system.physmem.readBursts 401711 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 157234 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25703040 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6464 # Total number of bytes read from write queue -system.physmem.bytesWritten 9922432 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25709504 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10062976 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 101 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2169 # Number of DRAM write bursts merged with an existing one +system.physmem.num_reads::total 401737 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115693 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115693 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 442477 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12931444 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 499 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13374420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 442477 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 442477 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3851591 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3851591 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3851591 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 442477 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12931444 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 499 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17226012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 401737 # Number of read requests accepted +system.physmem.writeReqs 157245 # Number of write requests accepted +system.physmem.readBursts 401737 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 157245 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25705152 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6016 # Total number of bytes read from write queue +system.physmem.bytesWritten 8387264 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25711168 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10063680 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 94 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 26167 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 130 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25160 # Per bank write bursts -system.physmem.perBankRdBursts::1 25539 # Per bank write bursts -system.physmem.perBankRdBursts::2 25602 # Per bank write bursts +system.physmem.perBankRdBursts::0 25230 # Per bank write bursts +system.physmem.perBankRdBursts::1 25660 # Per bank write bursts +system.physmem.perBankRdBursts::2 25603 # Per bank write bursts system.physmem.perBankRdBursts::3 25523 # Per bank write bursts -system.physmem.perBankRdBursts::4 24974 # Per bank write bursts -system.physmem.perBankRdBursts::5 24969 # Per bank write bursts -system.physmem.perBankRdBursts::6 24210 # Per bank write bursts -system.physmem.perBankRdBursts::7 24487 # Per bank write bursts -system.physmem.perBankRdBursts::8 25140 # Per bank write bursts -system.physmem.perBankRdBursts::9 24800 # Per bank write bursts -system.physmem.perBankRdBursts::10 25360 # Per bank write bursts -system.physmem.perBankRdBursts::11 24834 # Per bank write bursts -system.physmem.perBankRdBursts::12 24395 # Per bank write bursts -system.physmem.perBankRdBursts::13 25368 # Per bank write bursts -system.physmem.perBankRdBursts::14 25772 # Per bank write bursts -system.physmem.perBankRdBursts::15 25477 # Per bank write bursts -system.physmem.perBankWrBursts::0 10048 # Per bank write bursts -system.physmem.perBankWrBursts::1 9910 # Per bank write bursts -system.physmem.perBankWrBursts::2 10442 # Per bank write bursts -system.physmem.perBankWrBursts::3 9959 # Per bank write bursts -system.physmem.perBankWrBursts::4 9552 # Per bank write bursts -system.physmem.perBankWrBursts::5 9342 # Per bank write bursts -system.physmem.perBankWrBursts::6 8789 # Per bank write bursts -system.physmem.perBankWrBursts::7 8561 # Per bank write bursts -system.physmem.perBankWrBursts::8 9905 # Per bank write bursts -system.physmem.perBankWrBursts::9 8742 # Per bank write bursts -system.physmem.perBankWrBursts::10 9526 # Per bank write bursts -system.physmem.perBankWrBursts::11 9262 # Per bank write bursts -system.physmem.perBankWrBursts::12 9811 # Per bank write bursts -system.physmem.perBankWrBursts::13 10568 # Per bank write bursts -system.physmem.perBankWrBursts::14 10305 # Per bank write bursts -system.physmem.perBankWrBursts::15 10316 # Per bank write bursts +system.physmem.perBankRdBursts::4 24970 # Per bank write bursts +system.physmem.perBankRdBursts::5 24976 # Per bank write bursts +system.physmem.perBankRdBursts::6 24206 # Per bank write bursts +system.physmem.perBankRdBursts::7 24492 # Per bank write bursts +system.physmem.perBankRdBursts::8 25173 # Per bank write bursts +system.physmem.perBankRdBursts::9 24777 # Per bank write bursts +system.physmem.perBankRdBursts::10 25267 # Per bank write bursts +system.physmem.perBankRdBursts::11 24875 # Per bank write bursts +system.physmem.perBankRdBursts::12 24505 # Per bank write bursts +system.physmem.perBankRdBursts::13 25378 # Per bank write bursts +system.physmem.perBankRdBursts::14 25651 # Per bank write bursts +system.physmem.perBankRdBursts::15 25357 # Per bank write bursts +system.physmem.perBankWrBursts::0 8677 # Per bank write bursts +system.physmem.perBankWrBursts::1 8490 # Per bank write bursts +system.physmem.perBankWrBursts::2 8972 # Per bank write bursts +system.physmem.perBankWrBursts::3 8549 # Per bank write bursts +system.physmem.perBankWrBursts::4 8030 # Per bank write bursts +system.physmem.perBankWrBursts::5 7962 # Per bank write bursts +system.physmem.perBankWrBursts::6 7256 # Per bank write bursts +system.physmem.perBankWrBursts::7 7133 # Per bank write bursts +system.physmem.perBankWrBursts::8 8241 # Per bank write bursts +system.physmem.perBankWrBursts::9 7447 # Per bank write bursts +system.physmem.perBankWrBursts::10 7887 # Per bank write bursts +system.physmem.perBankWrBursts::11 7738 # Per bank write bursts +system.physmem.perBankWrBursts::12 8187 # Per bank write bursts +system.physmem.perBankWrBursts::13 8962 # Per bank write bursts +system.physmem.perBankWrBursts::14 8876 # Per bank write bursts +system.physmem.perBankWrBursts::15 8644 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1920406851000 # Total gap between requests +system.physmem.numWrRetry 46 # Number of times write queue was full causing retry +system.physmem.totGap 1922401791500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 401711 # Read request sizes (log2) +system.physmem.readPktSize::6 401737 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 157234 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 401596 # What read queue length does an incoming req see +system.physmem.writePktSize::6 157245 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 401629 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see @@ -148,184 +148,189 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7978 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 9053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11559 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9597 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6479 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5940 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 361 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 66451 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 536.116417 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 326.833533 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 417.088244 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15015 22.60% 22.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11499 17.30% 39.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4712 7.09% 46.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3144 4.73% 51.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3072 4.62% 56.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1860 2.80% 59.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1297 1.95% 61.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1463 2.20% 63.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24389 36.70% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 66451 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5539 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 72.502618 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2835.834060 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5536 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6420 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1549 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 2468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 2834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 712 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 50 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64754 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 526.491275 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 319.634857 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 416.364161 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14682 22.67% 22.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11626 17.95% 40.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5040 7.78% 48.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3263 5.04% 53.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2595 4.01% 57.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1540 2.38% 59.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1251 1.93% 61.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1707 2.64% 64.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 23050 35.60% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64754 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4707 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 85.326110 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 3076.141166 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 4704 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5539 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5539 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.990251 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 21.086567 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 34.704660 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4497 81.19% 81.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 178 3.21% 84.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 301 5.43% 89.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 51 0.92% 90.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 99 1.79% 92.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 47 0.85% 93.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 17 0.31% 93.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 11 0.20% 93.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 12 0.22% 94.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 4 0.07% 94.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 17 0.31% 94.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 7 0.13% 94.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 14 0.25% 94.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 6 0.11% 94.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 9 0.16% 95.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 38 0.69% 95.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 16 0.29% 96.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 19 0.34% 96.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 88 1.59% 98.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 43 0.78% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 11 0.20% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 20 0.36% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 10 0.18% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 3 0.05% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 3 0.05% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 4 0.07% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 4 0.07% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 5 0.09% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 3 0.05% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5539 # Writes before turning the bus around for reads -system.physmem.totQLat 2115529750 # Total ticks spent queuing -system.physmem.totMemAccLat 9645717250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2008050000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5267.62 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4707 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4707 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.841725 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.684188 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 62.214453 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 4459 94.73% 94.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 47 1.00% 95.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 10 0.21% 95.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 2 0.04% 95.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 12 0.25% 96.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 3 0.06% 96.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 7 0.15% 96.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 17 0.36% 96.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 21 0.45% 97.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 12 0.25% 97.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 17 0.36% 97.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 2 0.04% 97.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 5 0.11% 98.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 3 0.06% 98.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 1 0.02% 98.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 2 0.04% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 4 0.08% 98.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 11 0.23% 98.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 21 0.45% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 6 0.13% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 6 0.13% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 6 0.13% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-463 1 0.02% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 8 0.17% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 2 0.04% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 2 0.04% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 5 0.11% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 2 0.04% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 3 0.06% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 1 0.02% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-655 1 0.02% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-687 3 0.06% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::720-735 2 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::800-815 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::832-847 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4707 # Writes before turning the bus around for reads +system.physmem.totQLat 2057087750 # Total ticks spent queuing +system.physmem.totMemAccLat 9587894000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2008215000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5121.68 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24017.62 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.38 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 5.17 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.39 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 5.24 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 23871.68 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.37 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.36 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.37 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 5.23 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.84 # Average write queue length when enqueuing -system.physmem.readRowHits 359951 # Number of row buffer hits during reads -system.physmem.writeRowHits 130246 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.63 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.99 # Row buffer hit rate for writes -system.physmem.avgGap 3435770.69 # Average gap between requests -system.physmem.pageHitRate 88.06 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 245601720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 134008875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1563619200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 496387440 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 125432255520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 64124070615 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1096000726500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1287996669870 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.686102 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1823056528000 # Time in different power states -system.physmem_0.memoryStateTime::REF 64126920000 # Time in different power states +system.physmem.avgWrQLen 25.61 # Average write queue length when enqueuing +system.physmem.readRowHits 360176 # Number of row buffer hits during reads +system.physmem.writeRowHits 107764 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.68 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 82.21 # Row buffer hit rate for writes +system.physmem.avgGap 3439112.16 # Average gap between requests +system.physmem.pageHitRate 87.84 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 240309720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 131121375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1565148000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 421647120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 125562446880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 64744742475 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1096652245500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1289317661070 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.677845 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1824141880650 # Time in different power states +system.physmem_0.memoryStateTime::REF 64193480000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 33233084500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 34074451850 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 256767840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 140101500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1568938800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 508258800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 125432255520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 64541926215 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1095634186500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1288082435175 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.730762 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1822448681750 # Time in different power states -system.physmem_1.memoryStateTime::REF 64126920000 # Time in different power states +system.physmem_1.actEnergy 249230520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 135988875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1567667400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 427563360 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 125562446880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 65411599725 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1096067283000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1289421779760 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.732006 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1823167298902 # Time in different power states +system.physmem_1.memoryStateTime::REF 64193480000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 33840930750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 35049033598 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9052701 # DTB read hits -system.cpu.dtb.read_misses 10312 # DTB read misses +system.cpu.dtb.read_hits 9063642 # DTB read hits +system.cpu.dtb.read_misses 10324 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728817 # DTB read accesses -system.cpu.dtb.write_hits 6349364 # DTB write hits -system.cpu.dtb.write_misses 1140 # DTB write misses +system.cpu.dtb.read_accesses 728853 # DTB read accesses +system.cpu.dtb.write_hits 6355525 # DTB write hits +system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291929 # DTB write accesses -system.cpu.dtb.data_hits 15402065 # DTB hits -system.cpu.dtb.data_misses 11452 # DTB misses +system.cpu.dtb.write_accesses 291931 # DTB write accesses +system.cpu.dtb.data_hits 15419167 # DTB hits +system.cpu.dtb.data_misses 11466 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020746 # DTB accesses -system.cpu.itb.fetch_hits 4973977 # ITB hits -system.cpu.itb.fetch_misses 4997 # ITB misses +system.cpu.dtb.data_accesses 1020784 # DTB accesses +system.cpu.itb.fetch_hits 4974414 # ITB hits +system.cpu.itb.fetch_misses 5010 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4978974 # ITB accesses +system.cpu.itb.fetch_accesses 4979424 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -338,87 +343,87 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3840837544 # number of cpu cycles simulated +system.cpu.numCycles 3844827327 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56102800 # Number of instructions committed -system.cpu.committedOps 56102800 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 51978055 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses -system.cpu.num_func_calls 1481300 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6461124 # number of instructions that are conditional controls -system.cpu.num_int_insts 51978055 # number of integer instructions -system.cpu.num_fp_insts 324393 # number of float instructions -system.cpu.num_int_register_reads 71208426 # number of times the integer registers were read -system.cpu.num_int_register_writes 38459690 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written -system.cpu.num_mem_refs 15454652 # number of memory refs -system.cpu.num_load_insts 9089529 # Number of load instructions -system.cpu.num_store_insts 6365123 # Number of store instructions -system.cpu.num_idle_cycles 3589204507.998131 # Number of idle cycles -system.cpu.num_busy_cycles 251633036.001869 # Number of busy cycles -system.cpu.not_idle_fraction 0.065515 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.934485 # Percentage of idle cycles -system.cpu.Branches 8412940 # Number of branches fetched -system.cpu.op_class::No_OpClass 3197536 5.70% 5.70% # Class of executed instruction -system.cpu.op_class::IntAlu 36173540 64.46% 70.16% # Class of executed instruction -system.cpu.op_class::IntMult 60992 0.11% 70.27% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction -system.cpu.op_class::FloatAdd 38085 0.07% 70.34% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::FloatDiv 3636 0.01% 70.34% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::MemRead 9316603 16.60% 86.95% # Class of executed instruction -system.cpu.op_class::MemWrite 6371197 11.35% 98.30% # Class of executed instruction -system.cpu.op_class::IprAccess 953030 1.70% 100.00% # Class of executed instruction +system.cpu.committedInsts 56174594 # Number of instructions committed +system.cpu.committedOps 56174594 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52047018 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses +system.cpu.num_func_calls 1483106 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6467546 # number of instructions that are conditional controls +system.cpu.num_int_insts 52047018 # number of integer instructions +system.cpu.num_fp_insts 324460 # number of float instructions +system.cpu.num_int_register_reads 71310653 # number of times the integer registers were read +system.cpu.num_int_register_writes 38515122 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written +system.cpu.num_mem_refs 15471782 # number of memory refs +system.cpu.num_load_insts 9100493 # Number of load instructions +system.cpu.num_store_insts 6371289 # Number of store instructions +system.cpu.num_idle_cycles 3587399919.998134 # Number of idle cycles +system.cpu.num_busy_cycles 257427407.001866 # Number of busy cycles +system.cpu.not_idle_fraction 0.066954 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.933046 # Percentage of idle cycles +system.cpu.Branches 8421188 # Number of branches fetched +system.cpu.op_class::No_OpClass 3200330 5.70% 5.70% # Class of executed instruction +system.cpu.op_class::IntAlu 36225212 64.47% 70.17% # Class of executed instruction +system.cpu.op_class::IntMult 61016 0.11% 70.28% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 70.28% # Class of executed instruction +system.cpu.op_class::FloatAdd 38087 0.07% 70.35% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::FloatDiv 3636 0.01% 70.35% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::MemRead 9327578 16.60% 86.95% # Class of executed instruction +system.cpu.op_class::MemWrite 6377363 11.35% 98.30% # Class of executed instruction +system.cpu.op_class::IprAccess 953205 1.70% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 56114619 # Class of executed instruction +system.cpu.op_class::total 56186427 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211965 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74895 40.89% 40.89% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211986 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74892 40.89% 40.89% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106217 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183175 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73528 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 106213 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183168 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73525 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73528 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149119 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1858230927500 96.76% 96.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 91348000 0.00% 96.77% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 737130000 0.04% 96.80% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 61358632500 3.20% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1920418038000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73525 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149113 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1857939859000 96.65% 96.65% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 91692000 0.00% 96.65% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 740049500 0.04% 96.69% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 63641329000 3.31% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1922412929500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981747 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692243 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814079 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692241 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814078 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -454,10 +459,10 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed -system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed +system.cpu.kern.callpal::swpctx 4177 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175954 91.22% 93.41% # number of callpals executed +system.cpu.kern.callpal::swpipl 175947 91.21% 93.41% # number of callpals executed system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed @@ -466,101 +471,101 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192900 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5901 # number of protection mode switches -system.cpu.kern.mode_switch::user 1743 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1913 -system.cpu.kern.mode_good::user 1743 +system.cpu.kern.callpal::total 192894 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5905 # number of protection mode switches +system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1910 +system.cpu.kern.mode_good::user 1740 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.324182 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.323455 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081030 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392732 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46109911500 2.40% 2.40% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5189208000 0.27% 2.67% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1869118916500 97.33% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4177 # number of times the context was actually changed -system.cpu.dcache.tags.replacements 1389979 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.978885 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14030604 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1390491 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 10.090395 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 107775250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.978885 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy +system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392197 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 46428613000 2.42% 2.42% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5237727500 0.27% 2.69% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1870746587000 97.31% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4178 # number of times the context was actually changed +system.cpu.dcache.tags.replacements 1391374 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.978196 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 14046325 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1391886 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.091577 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 112435250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.978196 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999957 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999957 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63074876 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63074876 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7802731 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7802731 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5845607 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5845607 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183026 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183026 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199223 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199223 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13648338 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13648338 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13648338 # number of overall hits -system.cpu.dcache.overall_hits::total 13648338 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1069103 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1069103 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304189 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304189 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17217 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17217 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1373292 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1373292 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1373292 # number of overall misses -system.cpu.dcache.overall_misses::total 1373292 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29000817500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 29000817500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10906930630 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10906930630 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228178000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 228178000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39907748130 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39907748130 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39907748130 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39907748130 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 8871834 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 8871834 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6149796 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6149796 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200243 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200243 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199223 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199223 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15021630 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15021630 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15021630 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15021630 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120505 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120505 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049463 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049463 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085981 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085981 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091421 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091421 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091421 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091421 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27126.308223 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 27126.308223 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35855.769374 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35855.769374 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13253.063832 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13253.063832 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29059.914519 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29059.914519 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 29059.914519 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29059.914519 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63144735 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63144735 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7812525 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7812525 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5851580 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5851580 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 182969 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 182969 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199234 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199234 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13664105 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13664105 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13664105 # number of overall hits +system.cpu.dcache.overall_hits::total 13664105 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1070248 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1070248 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304369 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304369 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17287 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17287 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1374617 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1374617 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1374617 # number of overall misses +system.cpu.dcache.overall_misses::total 1374617 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 30897353500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 30897353500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11699394130 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11699394130 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 229714500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 229714500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 42596747630 # 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miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091405 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091405 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091405 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28869.340097 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28869.340097 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38438.192227 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38438.192227 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13288.280211 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13288.280211 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30988.084412 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30988.084412 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30988.084412 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30988.084412 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -569,54 +574,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 834368 # number of writebacks -system.cpu.dcache.writebacks::total 834368 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069103 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069103 # 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number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10245884370 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 193732000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 193732000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36982839870 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 36982839870 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36982839870 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 36982839870 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424272500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424272500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2009399000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2009399000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3433671500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3433671500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120505 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120505 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049463 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049463 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085981 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085981 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091421 # 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average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26930.062849 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26930.062849 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26930.062849 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 835634 # number of writebacks +system.cpu.dcache.writebacks::total 835634 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1070248 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1070248 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304369 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304369 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17287 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17287 # 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number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40356234870 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 40356234870 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40356234870 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 40356234870 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1432759000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1432759000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2025445000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2025445000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3458204000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3458204000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120486 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120486 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049443 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049443 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086325 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086325 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091405 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091405 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091405 # 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average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29358.166580 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -624,59 +629,59 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 927664 # number of replacements -system.cpu.icache.tags.tagsinuse 508.305908 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 55186285 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 928175 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 59.456767 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 39853785250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 508.305908 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.992785 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.992785 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 928205 # number of replacements +system.cpu.icache.tags.tagsinuse 508.070911 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 55257552 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 928716 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 59.498869 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 42087191250 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17215992500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 327511 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 327511 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7455368119 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7455368119 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 897481500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23773879119 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 24671360619 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 897481500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23773879119 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 24671360619 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1335739000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1335739000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1899995000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1899995000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3235734000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3235734000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014309 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250074 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141468 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.384118 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.384118 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279610 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173402 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279610 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173402 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60415.180587 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52584.768604 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52949.595615 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56548.825031 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56548.825031 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60415.180587 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53776.016520 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53995.458357 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60415.180587 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53776.016520 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53995.458357 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383953 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383953 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014309 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279348 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.173269 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014309 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279348 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.173269 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67525.505981 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60002.467238 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60352.991183 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 25193.153846 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25193.153846 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63799.071677 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63799.071677 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67525.505981 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61143.505929 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61354.450051 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67525.505981 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61143.505929 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61354.450051 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -889,41 +894,41 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2021758 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2021741 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2023514 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2023497 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 834368 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 835634 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41588 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304172 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304172 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1856650 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3648702 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5505352 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59412160 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142445588 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 201857748 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 41901 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3194937 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.013060 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.113530 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 304352 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304352 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1857732 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3652758 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5510490 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59446784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142615892 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 202062676 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 41937 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3198175 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.013058 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.113522 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3153212 98.69% 98.69% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41725 1.31% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3156414 98.69% 98.69% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 41761 1.31% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3194937 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2424089000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3198175 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2426956000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1395084250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1395898500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2186669630 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2188894130 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -996,23 +1001,23 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 406198788 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 242042219 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42010500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42024000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.352284 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.342966 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1753525494000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.352284 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.084518 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.084518 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1756462668000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.342966 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.083935 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.083935 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1026,14 +1031,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 23338383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 23338383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13635239905 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 13635239905 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 23338383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 23338383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 23338383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 23338383 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21714383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21714383 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8755465836 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 8755465836 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21714383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21714383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21714383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21714383 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) @@ -1050,19 +1055,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 134903.947977 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 134903.947977 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328148.823282 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 328148.823282 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 134903.947977 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 134903.947977 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 134903.947977 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 134903.947977 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 206255 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125516.664740 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125516.664740 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 210711.056893 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 210711.056893 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125516.664740 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125516.664740 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 72960 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23561 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 9989 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.754085 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.304034 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1076,14 +1081,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 173 system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 14341383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 14341383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11474535905 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11474535905 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 14341383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 14341383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 14341383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 14341383 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12562383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12562383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6594761836 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6594761836 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12562383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12562383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12562383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12562383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1092,57 +1097,57 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82898.167630 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 82898.167630 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276148.823282 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276148.823282 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 82898.167630 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 82898.167630 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 82898.167630 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 82898.167630 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72614.930636 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 158711.056893 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 158711.056893 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 292351 # Transaction distribution -system.membus.trans_dist::ReadResp 292351 # Transaction distribution +system.membus.trans_dist::ReadReq 292358 # Transaction distribution +system.membus.trans_dist::ReadResp 292358 # Transaction distribution system.membus.trans_dist::WriteReq 9650 # Transaction distribution system.membus.trans_dist::WriteResp 9650 # Transaction distribution -system.membus.trans_dist::Writeback 115682 # Transaction distribution +system.membus.trans_dist::Writeback 115693 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution system.membus.trans_dist::UpgradeReq 132 # Transaction distribution system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 116719 # Transaction distribution -system.membus.trans_dist::ReadExResp 116719 # Transaction distribution +system.membus.trans_dist::ReadExReq 116738 # Transaction distribution +system.membus.trans_dist::ReadExResp 116738 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878095 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911255 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878158 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911318 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1036059 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1036122 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30455424 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30499988 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30457792 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30502356 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 35817044 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 35819412 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 431 # Total snoops (count) -system.membus.snoop_fanout::samples 559506 # Request fanout histogram +system.membus.snoop_fanout::samples 559589 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 559506 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 559589 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 559506 # Request fanout histogram -system.membus.reqLayer0.occupancy 30371500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 559589 # Request fanout histogram +system.membus.reqLayer0.occupancy 30034000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1824515500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1195840311 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3751827620 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 43109500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2144408870 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 42495000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA |