diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha')
4 files changed, 2420 insertions, 2432 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 44f9ef01c..87d1939f2 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -1,70 +1,73 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.870336 # Number of seconds simulated -sim_ticks 1870335522500 # Number of ticks simulated -final_tick 1870335522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.870335 # Number of seconds simulated +sim_ticks 1870335131500 # Number of ticks simulated +final_tick 1870335131500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2258331 # Simulator instruction rate (inst/s) -host_op_rate 2258329 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 66881420828 # Simulator tick rate (ticks/s) -host_mem_usage 346748 # Number of bytes of host memory used -host_seconds 27.97 # Real time elapsed on the host -sim_insts 63154034 # Number of instructions simulated -sim_ops 63154034 # Number of ops (including micro ops) simulated +host_inst_rate 1824221 # Simulator instruction rate (inst/s) +host_op_rate 1824220 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54024573563 # Simulator tick rate (ticks/s) +host_mem_usage 318368 # Number of bytes of host memory used +host_seconds 34.62 # Real time elapsed on the host +sim_insts 63154606 # Number of instructions simulated +sim_ops 63154606 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 761216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 66693056 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 761088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 66705472 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 110976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 668672 # Number of bytes read from this memory -system.physmem.bytes_read::total 70883520 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 761216 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.data 674112 # Number of bytes read from this memory +system.physmem.bytes_read::total 68252608 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 761088 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 110976 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 872192 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7861504 # Number of bytes written to this memory -system.physmem.bytes_written::total 7861504 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11894 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 1042079 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::total 872064 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5204096 # Number of bytes written to this memory +system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory +system.physmem.bytes_written::total 7863424 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11892 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 1042273 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 1734 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10448 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1107555 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122836 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122836 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 406994 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 35658338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1416644 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.data 10533 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1066447 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 81314 # Number of write requests responded to by this memory +system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122866 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 406926 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 35664984 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 513 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 59335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 357514 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 37898826 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 406994 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 360423 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 36492181 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 406926 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 59335 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 466329 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4203259 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4203259 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4203259 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 406994 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 35658338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1416644 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_inst_read::total 466261 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2782440 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::tsunami.ide 1421846 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4204286 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2782440 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 406926 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 35664984 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1422359 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 59335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 357514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42102084 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 42160248 # Throughput (bytes/s) -system.membus.data_through_bus 78853810 # Total data (bytes) +system.physmem.bw_total::cpu1.data 360423 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 40696467 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 40739369 # Throughput (bytes/s) +system.membus.data_through_bus 76196274 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 1000626 # number of replacements -system.l2c.tags.tagsinuse 65381.922680 # Cycle average of tags in use -system.l2c.tags.total_refs 2464737 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1065768 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.312639 # Average number of references to valid blocks. +system.l2c.tags.replacements 1000624 # number of replacements +system.l2c.tags.tagsinuse 65381.923240 # Cycle average of tags in use +system.l2c.tags.total_refs 2464778 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1065766 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.312682 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 56158.702580 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4894.236968 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4134.601551 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 174.423287 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 19.958294 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 56158.686870 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4894.230886 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4134.623273 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 174.423683 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 19.958527 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.856914 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.074680 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.063089 # Average percentage of cache occupancy @@ -75,42 +78,42 @@ system.l2c.tags.occ_task_id_blocks::1024 65142 # Oc system.l2c.tags.age_task_id_blocks_1024::0 769 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 3264 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 6912 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6232 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 47965 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6213 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 47984 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.993988 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 32109442 # Number of tag accesses -system.l2c.tags.data_accesses 32109442 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 873086 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 763077 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 101896 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 36734 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1774793 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 816653 # number of Writeback hits -system.l2c.Writeback_hits::total 816653 # number of Writeback hits +system.l2c.tags.tag_accesses 32109770 # Number of tag accesses +system.l2c.tags.data_accesses 32109770 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.inst 873092 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 763091 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 101902 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 36740 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1774825 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 816663 # number of Writeback hits +system.l2c.Writeback_hits::total 816663 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 135 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 37 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 172 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 14 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 9 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 23 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 166234 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 14285 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 180519 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 873086 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 929311 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 101896 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 51019 # number of demand (read+write) hits -system.l2c.demand_hits::total 1955312 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 873086 # number of overall hits -system.l2c.overall_hits::cpu0.data 929311 # number of overall hits -system.l2c.overall_hits::cpu1.inst 101896 # number of overall hits -system.l2c.overall_hits::cpu1.data 51019 # number of overall hits -system.l2c.overall_hits::total 1955312 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 11894 # number of ReadReq misses +system.l2c.ReadExReq_hits::cpu0.data 166232 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 14288 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 180520 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 873092 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 929323 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 101902 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 51028 # number of demand (read+write) hits +system.l2c.demand_hits::total 1955345 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 873092 # number of overall hits +system.l2c.overall_hits::cpu0.data 929323 # number of overall hits +system.l2c.overall_hits::cpu1.inst 101902 # number of overall hits +system.l2c.overall_hits::cpu1.data 51028 # number of overall hits +system.l2c.overall_hits::total 1955345 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 11892 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 926761 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 1734 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.data 908 # number of ReadReq misses -system.l2c.ReadReq_misses::total 941297 # number of ReadReq misses +system.l2c.ReadReq_misses::total 941295 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 2442 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 570 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 3012 # number of UpgradeReq misses @@ -120,66 +123,66 @@ system.l2c.SCUpgradeReq_misses::total 165 # nu system.l2c.ReadExReq_misses::cpu0.data 115706 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 9662 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 125368 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 11894 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 11892 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 1042467 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 1734 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 10570 # number of demand (read+write) misses -system.l2c.demand_misses::total 1066665 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 11894 # number of overall misses +system.l2c.demand_misses::total 1066663 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 11892 # number of overall misses system.l2c.overall_misses::cpu0.data 1042467 # number of overall misses system.l2c.overall_misses::cpu1.inst 1734 # number of overall misses system.l2c.overall_misses::cpu1.data 10570 # number of overall misses -system.l2c.overall_misses::total 1066665 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.inst 884980 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1689838 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 103630 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 37642 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2716090 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 816653 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 816653 # number of Writeback accesses(hits+misses) +system.l2c.overall_misses::total 1066663 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.inst 884984 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 1689852 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 103636 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 37648 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2716120 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 816663 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 816663 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 2577 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 607 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 3184 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu0.data 79 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 109 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 188 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 281940 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 23947 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 305887 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 884980 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1971778 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 103630 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 61589 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 3021977 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 884980 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1971778 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 103630 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 61589 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 3021977 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.013440 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.548432 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.016733 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.024122 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.346563 # miss rate for ReadReq accesses +system.l2c.ReadExReq_accesses::cpu0.data 281938 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 23950 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 305888 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 884984 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1971790 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 103636 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 61598 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 3022008 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 884984 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1971790 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 103636 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 61598 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 3022008 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.013438 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.548427 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.016732 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.024118 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.346559 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947614 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.939044 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.945980 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.822785 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.917431 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 0.877660 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.410392 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.403474 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.409851 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.013440 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.528694 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.016733 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.171622 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.352969 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.013440 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.528694 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.016733 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.171622 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.352969 # miss rate for overall accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.410395 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.403424 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.409849 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.013438 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.528691 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.016732 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.171596 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.352965 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.013438 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.528691 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.016732 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.171596 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.352965 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -188,16 +191,16 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 81316 # number of writebacks -system.l2c.writebacks::total 81316 # number of writebacks +system.l2c.writebacks::writebacks 81314 # number of writebacks +system.l2c.writebacks::total 81314 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.tags.replacements 41695 # number of replacements -system.iocache.tags.tagsinuse 0.435437 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.435433 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.435437 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::tsunami.ide 0.435433 # Average occupied blocks per requestor system.iocache.tags.occ_percent::tsunami.ide 0.027215 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.027215 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -205,26 +208,24 @@ system.iocache.tags.age_task_id_blocks_1023::2 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375543 # Number of tag accesses system.iocache.tags.data_accesses 375543 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses system.iocache.ReadReq_misses::total 175 # number of ReadReq misses -system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses -system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses -system.iocache.demand_misses::total 41727 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses -system.iocache.overall_misses::total 41727 # number of overall misses +system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses +system.iocache.demand_misses::total 175 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 175 # number of overall misses +system.iocache.overall_misses::total 175 # number of overall misses system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) -system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses +system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses @@ -235,10 +236,8 @@ system.iocache.blocked::no_mshrs 0 # nu system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.fast_writes 41552 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41520 # number of writebacks -system.iocache.writebacks::total 41520 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -256,22 +255,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9154530 # DTB read hits +system.cpu0.dtb.read_hits 9154569 # DTB read hits system.cpu0.dtb.read_misses 7079 # DTB read misses system.cpu0.dtb.read_acv 152 # DTB read access violations system.cpu0.dtb.read_accesses 508987 # DTB read accesses -system.cpu0.dtb.write_hits 5936899 # DTB write hits +system.cpu0.dtb.write_hits 5936918 # DTB write hits system.cpu0.dtb.write_misses 726 # DTB write misses system.cpu0.dtb.write_acv 99 # DTB write access violations system.cpu0.dtb.write_accesses 189050 # DTB write accesses -system.cpu0.dtb.data_hits 15091429 # DTB hits +system.cpu0.dtb.data_hits 15091487 # DTB hits system.cpu0.dtb.data_misses 7805 # DTB misses system.cpu0.dtb.data_acv 251 # DTB access violations system.cpu0.dtb.data_accesses 698037 # DTB accesses -system.cpu0.itb.fetch_hits 3855556 # ITB hits +system.cpu0.itb.fetch_hits 3855534 # ITB hits system.cpu0.itb.fetch_misses 3485 # ITB misses system.cpu0.itb.fetch_acv 127 # ITB acv -system.cpu0.itb.fetch_accesses 3859041 # ITB accesses +system.cpu0.itb.fetch_accesses 3859019 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -284,34 +283,34 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3740671046 # number of cpu cycles simulated +system.cpu0.numCycles 3740670264 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 57222076 # Number of instructions committed -system.cpu0.committedOps 57222076 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 53249924 # Number of integer alu accesses +system.cpu0.committedInsts 57222643 # Number of instructions committed +system.cpu0.committedOps 57222643 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 53250480 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 299810 # Number of float alu accesses -system.cpu0.num_func_calls 1399585 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 6808233 # number of instructions that are conditional controls -system.cpu0.num_int_insts 53249924 # number of integer instructions +system.cpu0.num_func_calls 1399593 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 6808341 # number of instructions that are conditional controls +system.cpu0.num_int_insts 53250480 # number of integer instructions system.cpu0.num_fp_insts 299810 # number of float instructions -system.cpu0.num_int_register_reads 73318596 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39827534 # number of times the integer registers were written +system.cpu0.num_int_register_reads 73319539 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39827957 # number of times the integer registers were written system.cpu0.num_fp_register_reads 147724 # number of times the floating registers were read system.cpu0.num_fp_register_writes 150835 # number of times the floating registers were written -system.cpu0.num_mem_refs 15135515 # number of memory refs -system.cpu0.num_load_insts 9184477 # Number of load instructions -system.cpu0.num_store_insts 5951038 # Number of store instructions -system.cpu0.num_idle_cycles 3683437200.584730 # Number of idle cycles -system.cpu0.num_busy_cycles 57233845.415270 # Number of busy cycles -system.cpu0.not_idle_fraction 0.015300 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.984700 # Percentage of idle cycles -system.cpu0.Branches 8650704 # Number of branches fetched -system.cpu0.op_class::No_OpClass 3102513 5.42% 5.42% # Class of executed instruction -system.cpu0.op_class::IntAlu 37823162 66.09% 71.51% # Class of executed instruction -system.cpu0.op_class::IntMult 59490 0.10% 71.61% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.61% # Class of executed instruction -system.cpu0.op_class::FloatAdd 18488 0.03% 71.65% # Class of executed instruction +system.cpu0.num_mem_refs 15135573 # number of memory refs +system.cpu0.num_load_insts 9184516 # Number of load instructions +system.cpu0.num_store_insts 5951057 # Number of store instructions +system.cpu0.num_idle_cycles 3683435851.584730 # Number of idle cycles +system.cpu0.num_busy_cycles 57234412.415270 # Number of busy cycles +system.cpu0.not_idle_fraction 0.015301 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.984699 # Percentage of idle cycles +system.cpu0.Branches 8650822 # Number of branches fetched +system.cpu0.op_class::No_OpClass 3102524 5.42% 5.42% # Class of executed instruction +system.cpu0.op_class::IntAlu 37811313 66.07% 71.49% # Class of executed instruction +system.cpu0.op_class::IntMult 59497 0.10% 71.59% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 71.59% # Class of executed instruction +system.cpu0.op_class::FloatAdd 30844 0.05% 71.65% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 71.65% # Class of executed instruction system.cpu0.op_class::FloatCvt 0 0.00% 71.65% # Class of executed instruction system.cpu0.op_class::FloatMult 0 0.00% 71.65% # Class of executed instruction @@ -337,38 +336,38 @@ system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.65% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 71.65% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.65% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::MemRead 9401052 16.43% 88.08% # Class of executed instruction -system.cpu0.op_class::MemWrite 5956984 10.41% 98.49% # Class of executed instruction -system.cpu0.op_class::IprAccess 866222 1.51% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 9401091 16.43% 88.08% # Class of executed instruction +system.cpu0.op_class::MemWrite 5957003 10.41% 98.49% # Class of executed instruction +system.cpu0.op_class::IprAccess 866206 1.51% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 57230132 # Class of executed instruction +system.cpu0.op_class::total 57230699 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 6283 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 197120 # number of hwrei instructions executed +system.cpu0.kern.inst.hwrei 197118 # number of hwrei instructions executed system.cpu0.kern.ipl_count::0 71004 40.60% 40.60% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 243 0.14% 40.74% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1908 1.09% 41.83% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 8 0.00% 41.84% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 101705 58.16% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 174868 # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 101703 58.16% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 174866 # number of times we switched to this ipl system.cpu0.kern.ipl_good::0 69637 49.24% 49.24% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 69629 49.23% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 141425 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1852989766500 99.07% 99.07% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1852989089000 99.07% 99.07% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.07% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::22 82044000 0.00% 99.08% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::30 949500 0.00% 99.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 17242445000 0.92% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1870335315000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 17242731500 0.92% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1870334924000 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.980748 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684617 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.808753 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.684631 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.808762 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 6 2.65% 2.65% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.41% 11.06% # number of syscalls executed system.cpu0.kern.syscall::4 2 0.88% 11.95% # number of syscalls executed @@ -408,7 +407,7 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # nu system.cpu0.kern.callpal::swpctx 3762 2.05% 2.11% # number of callpals executed system.cpu0.kern.callpal::tbi 38 0.02% 2.14% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.14% # number of callpals executed -system.cpu0.kern.callpal::swpipl 168035 91.68% 93.82% # number of callpals executed +system.cpu0.kern.callpal::swpipl 168033 91.68% 93.82% # number of callpals executed system.cpu0.kern.callpal::rdps 6150 3.36% 97.17% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 97.17% # number of callpals executed system.cpu0.kern.callpal::wrusp 3 0.00% 97.17% # number of callpals executed @@ -417,19 +416,19 @@ system.cpu0.kern.callpal::whami 2 0.00% 97.18% # nu system.cpu0.kern.callpal::rti 4673 2.55% 99.73% # number of callpals executed system.cpu0.kern.callpal::callsys 357 0.19% 99.92% # number of callpals executed system.cpu0.kern.callpal::imb 142 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 183291 # number of callpals executed +system.cpu0.kern.callpal::total 183289 # number of callpals executed system.cpu0.kern.mode_switch::kernel 7091 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1158 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1156 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1157 -system.cpu0.kern.mode_good::user 1158 +system.cpu0.kern.mode_good::kernel 1155 +system.cpu0.kern.mode_good::user 1156 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.163165 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.162883 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.280640 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1869378305000 99.95% 99.95% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 957009000 0.05% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.280223 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1869377924000 99.95% 99.95% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 956999000 0.05% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 3763 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA @@ -463,18 +462,18 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 131930255 # Throughput (bytes/s) -system.toL2Bus.data_through_bus 246743474 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 10368 # Total snoop data (bytes) +system.toL2Bus.throughput 133353257 # Throughput (bytes/s) +system.toL2Bus.data_through_bus 246745714 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 2669568 # Total snoop data (bytes) system.iobus.throughput 1460501 # Throughput (bytes/s) system.iobus.data_through_bus 2731626 # Total data (bytes) -system.cpu0.icache.tags.replacements 884404 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.244754 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 56345132 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 884916 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 63.672859 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 884408 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.244752 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 56345695 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 884920 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 63.673208 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.244754 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.244752 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998525 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.998525 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -482,26 +481,26 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::0 59 system.cpu0.icache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 345 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 58115132 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 58115132 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 56345132 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 56345132 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 56345132 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 56345132 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 56345132 # number of overall hits -system.cpu0.icache.overall_hits::total 56345132 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 885000 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 885000 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 885000 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 885000 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 885000 # number of overall misses -system.cpu0.icache.overall_misses::total 885000 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 57230132 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 57230132 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 57230132 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 57230132 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 57230132 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 57230132 # number of overall (read+write) accesses +system.cpu0.icache.tags.tag_accesses 58115703 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 58115703 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 56345695 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 56345695 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 56345695 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 56345695 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 56345695 # number of overall hits +system.cpu0.icache.overall_hits::total 56345695 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 885004 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 885004 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 885004 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 885004 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 885004 # number of overall misses +system.cpu0.icache.overall_misses::total 885004 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 57230699 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 57230699 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 57230699 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 57230699 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 57230699 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 57230699 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015464 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.015464 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015464 # miss rate for demand accesses @@ -517,13 +516,13 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1978686 # number of replacements -system.cpu0.dcache.tags.tagsinuse 507.129778 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13123753 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1979198 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 6.630844 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1978697 # number of replacements +system.cpu0.dcache.tags.tagsinuse 507.129647 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 13123800 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1979209 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 6.630831 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 507.129778 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu0.data 507.129647 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.990488 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.990488 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -531,44 +530,44 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 443 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 62404072 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 62404072 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 7298337 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7298337 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5462263 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5462263 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 62404315 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 62404315 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 7298365 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7298365 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5462282 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5462282 # number of WriteReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172144 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 172144 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.data 186624 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 186624 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12760600 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12760600 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12760600 # number of overall hits -system.cpu0.dcache.overall_hits::total 12760600 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1683332 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1683332 # number of ReadReq misses +system.cpu0.dcache.demand_hits::cpu0.data 12760647 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12760647 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12760647 # number of overall hits +system.cpu0.dcache.overall_hits::total 12760647 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1683343 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1683343 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 285998 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 285998 # number of WriteReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16153 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 16153 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 714 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 714 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1969330 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1969330 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1969330 # number of overall misses -system.cpu0.dcache.overall_misses::total 1969330 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8981669 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8981669 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5748261 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5748261 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 1969341 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1969341 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1969341 # number of overall misses +system.cpu0.dcache.overall_misses::total 1969341 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8981708 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8981708 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5748280 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5748280 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 188297 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 188297 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187338 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 187338 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14729930 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14729930 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14729930 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14729930 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 14729988 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14729988 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14729988 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14729988 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187419 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.187419 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049754 # miss rate for WriteReq accesses @@ -589,8 +588,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 775641 # number of writebacks -system.cpu0.dcache.writebacks::total 775641 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 775643 # number of writebacks +system.cpu0.dcache.writebacks::total 775643 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses @@ -624,34 +623,34 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3740248881 # number of cpu cycles simulated +system.cpu1.numCycles 3740248099 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 5931958 # Number of instructions committed -system.cpu1.committedOps 5931958 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 5550578 # Number of integer alu accesses +system.cpu1.committedInsts 5931963 # Number of instructions committed +system.cpu1.committedOps 5931963 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 5550581 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 28590 # Number of float alu accesses system.cpu1.num_func_calls 182742 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 577190 # number of instructions that are conditional controls -system.cpu1.num_int_insts 5550578 # number of integer instructions +system.cpu1.num_conditional_control_insts 577192 # number of instructions that are conditional controls +system.cpu1.num_int_insts 5550581 # number of integer instructions system.cpu1.num_fp_insts 28590 # number of float instructions -system.cpu1.num_int_register_reads 7657288 # number of times the integer registers were read -system.cpu1.num_int_register_writes 4163275 # number of times the integer registers were written +system.cpu1.num_int_register_reads 7657293 # number of times the integer registers were read +system.cpu1.num_int_register_writes 4163277 # number of times the integer registers were written system.cpu1.num_fp_register_reads 17889 # number of times the floating registers were read system.cpu1.num_fp_register_writes 17683 # number of times the floating registers were written system.cpu1.num_mem_refs 1926244 # number of memory refs system.cpu1.num_load_insts 1170888 # Number of load instructions system.cpu1.num_store_insts 755356 # Number of store instructions -system.cpu1.num_idle_cycles 3734312190.077655 # Number of idle cycles -system.cpu1.num_busy_cycles 5936690.922345 # Number of busy cycles +system.cpu1.num_idle_cycles 3734311403.078359 # Number of idle cycles +system.cpu1.num_busy_cycles 5936695.921641 # Number of busy cycles system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles -system.cpu1.Branches 836747 # Number of branches fetched +system.cpu1.Branches 836749 # Number of branches fetched system.cpu1.op_class::No_OpClass 239814 4.04% 4.04% # Class of executed instruction -system.cpu1.op_class::IntAlu 3533366 59.53% 63.57% # Class of executed instruction +system.cpu1.op_class::IntAlu 3533248 59.52% 63.56% # Class of executed instruction system.cpu1.op_class::IntMult 9651 0.16% 63.73% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 63.73% # Class of executed instruction -system.cpu1.op_class::FloatAdd 7265 0.12% 63.85% # Class of executed instruction +system.cpu1.op_class::FloatAdd 7388 0.12% 63.85% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 63.85% # Class of executed instruction system.cpu1.op_class::FloatCvt 0 0.00% 63.85% # Class of executed instruction system.cpu1.op_class::FloatMult 0 0.00% 63.85% # Class of executed instruction @@ -681,9 +680,9 @@ system.cpu1.op_class::MemRead 1191429 20.07% 83.95% # Cl system.cpu1.op_class::MemWrite 755540 12.73% 96.68% # Class of executed instruction system.cpu1.op_class::IprAccess 197280 3.32% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 5935766 # Class of executed instruction +system.cpu1.op_class::total 5935771 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2204 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 2205 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed system.cpu1.kern.ipl_count::0 10328 33.46% 33.46% # number of times we switched to this ipl system.cpu1.kern.ipl_count::22 1907 6.18% 39.64% # number of times we switched to this ipl @@ -695,11 +694,11 @@ system.cpu1.kern.ipl_good::22 1907 8.46% 54.23% # nu system.cpu1.kern.ipl_good::30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::total 22543 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1859123008500 99.41% 99.41% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::0 1859122617500 99.41% 99.41% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::22 82001000 0.00% 99.42% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::30 14064500 0.00% 99.42% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1870124427000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1870124036000 # number of cycles we spent at this ipl system.cpu1.kern.ipl_used::0 0.999032 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl @@ -751,48 +750,48 @@ system.cpu1.kern.mode_switch_good::kernel 0.592449 # f system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle 0.015640 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::total 0.334518 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 1373917500 0.07% 0.07% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::kernel 1373909000 0.07% 0.07% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::user 508289000 0.03% 0.10% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1868002549000 99.90% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1868002186500 99.90% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 471 # number of times the context was actually changed -system.cpu1.icache.tags.replacements 103091 # number of replacements -system.cpu1.icache.tags.tagsinuse 427.126317 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 5832136 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 103603 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 56.293119 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1868933059000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 427.126317 # Average occupied blocks per requestor +system.cpu1.icache.tags.replacements 103097 # number of replacements +system.cpu1.icache.tags.tagsinuse 427.126315 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 5832135 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 103609 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 56.289849 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1868932699000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 427.126315 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.834231 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.834231 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 6039396 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 6039396 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 5832136 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 5832136 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 5832136 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 5832136 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 5832136 # number of overall hits -system.cpu1.icache.overall_hits::total 5832136 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 103630 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 103630 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 103630 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 103630 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 103630 # number of overall misses -system.cpu1.icache.overall_misses::total 103630 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 5935766 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 5935766 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 5935766 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 5935766 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 5935766 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 5935766 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017459 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.017459 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.017459 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.017459 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.017459 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.017459 # miss rate for overall accesses +system.cpu1.icache.tags.tag_accesses 6039407 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 6039407 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 5832135 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 5832135 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 5832135 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 5832135 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 5832135 # number of overall hits +system.cpu1.icache.overall_hits::total 5832135 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 103636 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 103636 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 103636 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 103636 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 103636 # number of overall misses +system.cpu1.icache.overall_misses::total 103636 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 5935771 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 5935771 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 5935771 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 5935771 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 5935771 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 5935771 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017460 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.017460 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.017460 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.017460 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.017460 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.017460 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -802,45 +801,45 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 62044 # number of replacements -system.cpu1.dcache.tags.tagsinuse 421.562730 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 1836054 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 62382 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 29.432432 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1851115552500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 421.562730 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.823365 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.823365 # Average percentage of cache occupancy +system.cpu1.dcache.tags.replacements 62047 # number of replacements +system.cpu1.dcache.tags.tagsinuse 421.558473 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 1836050 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 62385 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 29.430953 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 1851115162500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 421.558473 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.823356 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.823356 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 338 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 337 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.660156 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 7735310 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 7735310 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 1109521 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1109521 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 707457 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 707457 # number of WriteReq hits +system.cpu1.dcache.tags.tag_accesses 7735314 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 7735314 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 1109520 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1109520 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 707454 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 707454 # number of WriteReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15133 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 15133 # number of LoadLockedReq hits system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15610 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 15610 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1816978 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1816978 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1816978 # number of overall hits -system.cpu1.dcache.overall_hits::total 1816978 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 41444 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 41444 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 25848 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 25848 # number of WriteReq misses +system.cpu1.dcache.demand_hits::cpu1.data 1816974 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 1816974 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 1816974 # number of overall hits +system.cpu1.dcache.overall_hits::total 1816974 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 41445 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 41445 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 25851 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 25851 # number of WriteReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1285 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 1285 # number of LoadLockedReq misses system.cpu1.dcache.StoreCondReq_misses::cpu1.data 735 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 735 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 67292 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 67292 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 67292 # number of overall misses -system.cpu1.dcache.overall_misses::total 67292 # number of overall misses +system.cpu1.dcache.demand_misses::cpu1.data 67296 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 67296 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 67296 # number of overall misses +system.cpu1.dcache.overall_misses::total 67296 # number of overall misses system.cpu1.dcache.ReadReq_accesses::cpu1.data 1150965 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 1150965 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 733305 # number of WriteReq accesses(hits+misses) @@ -853,18 +852,18 @@ system.cpu1.dcache.demand_accesses::cpu1.data 1884270 system.cpu1.dcache.demand_accesses::total 1884270 # number of demand (read+write) accesses system.cpu1.dcache.overall_accesses::cpu1.data 1884270 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036008 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.036008 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035249 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.035249 # miss rate for WriteReq accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036009 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.036009 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035253 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.035253 # miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078268 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.078268 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044968 # miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044968 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035713 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.035713 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035713 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.035713 # miss rate for overall accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035715 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.035715 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035715 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.035715 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -873,8 +872,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 41012 # number of writebacks -system.cpu1.dcache.writebacks::total 41012 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 41020 # number of writebacks +system.cpu1.dcache.writebacks::total 41020 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index d987ad3fa..8a7bfd4c1 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -1,55 +1,58 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.829332 # Number of seconds simulated -sim_ticks 1829332258000 # Number of ticks simulated -final_tick 1829332258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1829332049000 # Number of ticks simulated +final_tick 1829332049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2367650 # Simulator instruction rate (inst/s) -host_op_rate 2367648 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 72140813877 # Simulator tick rate (ticks/s) -host_mem_usage 343680 # Number of bytes of host memory used -host_seconds 25.36 # Real time elapsed on the host -sim_insts 60038305 # Number of instructions simulated -sim_ops 60038305 # Number of ops (including micro ops) simulated +host_inst_rate 2314619 # Simulator instruction rate (inst/s) +host_op_rate 2314617 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 70524837278 # Simulator tick rate (ticks/s) +host_mem_usage 315304 # Number of bytes of host memory used +host_seconds 25.94 # Real time elapsed on the host +sim_insts 60038433 # Number of instructions simulated +sim_ops 60038433 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 66839424 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::total 70349696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 66856384 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::total 67715328 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7411392 # Number of bytes written to this memory -system.physmem.bytes_written::total 7411392 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 4754240 # Number of bytes written to this memory +system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory +system.physmem.bytes_written::total 7413568 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 13406 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1044366 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1099214 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115803 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115803 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.data 1044631 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1058052 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 74285 # Number of write requests responded to by this memory +system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115837 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 469015 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 36537607 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1449867 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 38456489 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 36546883 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 37016422 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 469015 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 469015 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4051419 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4051419 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4051419 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 2598894 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::tsunami.ide 1453715 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4052609 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2598894 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 469015 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 36537607 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1449867 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42507908 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 42552540 # Throughput (bytes/s) -system.membus.data_through_bus 77842734 # Total data (bytes) +system.physmem.bw_total::cpu.data 36546883 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1454240 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 41069032 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 41099809 # Throughput (bytes/s) +system.membus.data_through_bus 75185198 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.iocache.tags.replacements 41686 # number of replacements -system.iocache.tags.tagsinuse 1.225570 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.225568 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.225570 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::tsunami.ide 1.225568 # Average occupied blocks per requestor system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -57,26 +60,24 @@ system.iocache.tags.age_task_id_blocks_1023::2 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375534 # Number of tag accesses system.iocache.tags.data_accesses 375534 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses system.iocache.ReadReq_misses::total 174 # number of ReadReq misses -system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses -system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses -system.iocache.demand_misses::total 41726 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses -system.iocache.overall_misses::total 41726 # number of overall misses +system.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses +system.iocache.demand_misses::total 174 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 174 # number of overall misses +system.iocache.overall_misses::total 174 # number of overall misses system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) -system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses +system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 174 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 174 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses @@ -87,10 +88,8 @@ system.iocache.blocked::no_mshrs 0 # nu system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.fast_writes 41552 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41512 # number of writebacks -system.iocache.writebacks::total 41512 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -109,7 +108,7 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9710427 # DTB read hits +system.cpu.dtb.read_hits 9710428 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations system.cpu.dtb.read_accesses 728856 # DTB read accesses @@ -117,14 +116,14 @@ system.cpu.dtb.write_hits 6352498 # DT system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 16062925 # DTB hits +system.cpu.dtb.data_hits 16062926 # DTB hits system.cpu.dtb.data_misses 11471 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations system.cpu.dtb.data_accesses 1020787 # DTB accesses -system.cpu.itb.fetch_hits 4974648 # ITB hits +system.cpu.itb.fetch_hits 4974637 # ITB hits system.cpu.itb.fetch_misses 5006 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979654 # ITB accesses +system.cpu.itb.fetch_accesses 4979643 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -137,34 +136,34 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3658664517 # number of cpu cycles simulated +system.cpu.numCycles 3658664099 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60038305 # Number of instructions committed -system.cpu.committedOps 60038305 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 55913521 # Number of integer alu accesses +system.cpu.committedInsts 60038433 # Number of instructions committed +system.cpu.committedOps 60038433 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 55913650 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses system.cpu.num_func_calls 1484182 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7110746 # number of instructions that are conditional controls -system.cpu.num_int_insts 55913521 # number of integer instructions +system.cpu.num_conditional_control_insts 7110776 # number of instructions that are conditional controls +system.cpu.num_int_insts 55913650 # number of integer instructions system.cpu.num_fp_insts 324460 # number of float instructions -system.cpu.num_int_register_reads 76953934 # number of times the integer registers were read -system.cpu.num_int_register_writes 41740225 # number of times the integer registers were written +system.cpu.num_int_register_reads 76954165 # number of times the integer registers were read +system.cpu.num_int_register_writes 41740323 # number of times the integer registers were written system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written -system.cpu.num_mem_refs 16115709 # number of memory refs -system.cpu.num_load_insts 9747513 # Number of load instructions +system.cpu.num_mem_refs 16115710 # number of memory refs +system.cpu.num_load_insts 9747514 # Number of load instructions system.cpu.num_store_insts 6368196 # Number of store instructions -system.cpu.num_idle_cycles 3598609086.391618 # Number of idle cycles -system.cpu.num_busy_cycles 60055430.608382 # Number of busy cycles +system.cpu.num_idle_cycles 3598608539.425618 # Number of idle cycles +system.cpu.num_busy_cycles 60055559.574382 # Number of busy cycles system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles system.cpu.idle_fraction 0.983585 # Percentage of idle cycles -system.cpu.Branches 9064385 # Number of branches fetched -system.cpu.op_class::No_OpClass 3199104 5.33% 5.33% # Class of executed instruction -system.cpu.op_class::IntAlu 39460699 65.71% 71.04% # Class of executed instruction -system.cpu.op_class::IntMult 60680 0.10% 71.14% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 71.14% # Class of executed instruction -system.cpu.op_class::FloatAdd 25609 0.04% 71.18% # Class of executed instruction +system.cpu.Branches 9064413 # Number of branches fetched +system.cpu.op_class::No_OpClass 3199106 5.33% 5.33% # Class of executed instruction +system.cpu.op_class::IntAlu 39448354 65.69% 71.02% # Class of executed instruction +system.cpu.op_class::IntMult 60680 0.10% 71.12% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction +system.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 71.18% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 71.18% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 71.18% # Class of executed instruction @@ -190,34 +189,34 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::MemRead 9975081 16.61% 87.80% # Class of executed instruction +system.cpu.op_class::MemRead 9975082 16.61% 87.80% # Class of executed instruction system.cpu.op_class::MemWrite 6374117 10.61% 98.42% # Class of executed instruction -system.cpu.op_class::IprAccess 951217 1.58% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 951209 1.58% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 60050143 # Class of executed instruction +system.cpu.op_class::total 60050271 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed +system.cpu.kern.inst.hwrei 211318 # number of hwrei instructions executed system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105623 57.86% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182562 # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105622 57.86% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182561 # number of times we switched to this ipl system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1811927407500 99.05% 99.05% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1811927133000 99.05% 99.05% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 17304295000 0.95% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1829332050500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 17304360500 0.95% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1829331841500 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.695521 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.816353 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.695527 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.816357 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -256,7 +255,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175249 91.19% 93.40% # number of callpals executed +system.cpu.kern.callpal::swpipl 175248 91.19% 93.40% # number of callpals executed system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed @@ -265,20 +264,20 @@ system.cpu.kern.callpal::whami 2 0.00% 96.93% # nu system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192180 # number of callpals executed +system.cpu.kern.callpal::total 192179 # number of callpals executed system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches -system.cpu.kern.mode_switch::user 1738 # number of protection mode switches +system.cpu.kern.mode_switch::user 1737 # number of protection mode switches system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1909 -system.cpu.kern.mode_good::user 1738 +system.cpu.kern.mode_good::kernel 1908 +system.cpu.kern.mode_good::user 1737 system.cpu.kern.mode_good::idle 171 -system.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.320726 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.390229 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 26834202500 1.47% 1.47% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1801032773000 98.45% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 0.390064 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 26834199500 1.47% 1.47% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 1465069000 0.08% 1.55% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1801032572000 98.45% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -313,13 +312,13 @@ system.tsunami.ethernet.postedInterrupts 0 # nu system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.iobus.throughput 1480181 # Throughput (bytes/s) system.iobus.data_through_bus 2707742 # Total data (bytes) -system.cpu.icache.tags.replacements 919594 # number of replacements -system.cpu.icache.tags.tagsinuse 511.215243 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 59129922 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 920106 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 64.264250 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 919591 # number of replacements +system.cpu.icache.tags.tagsinuse 511.215239 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 59130053 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 920103 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 64.264602 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.215243 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 511.215239 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -327,26 +326,26 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 63 system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 332 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 60970364 # Number of tag accesses -system.cpu.icache.tags.data_accesses 60970364 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 59129922 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 59129922 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 59129922 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 59129922 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 59129922 # number of overall hits -system.cpu.icache.overall_hits::total 59129922 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 920221 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 920221 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 920221 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 920221 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 920221 # number of overall misses -system.cpu.icache.overall_misses::total 920221 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 60050143 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 60050143 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 60050143 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 60050143 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 60050143 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 60050143 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 60970489 # Number of tag accesses +system.cpu.icache.tags.data_accesses 60970489 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 59130053 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 59130053 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 59130053 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 59130053 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 59130053 # number of overall hits +system.cpu.icache.overall_hits::total 59130053 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 920218 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 920218 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 920218 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 920218 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 920218 # number of overall misses +system.cpu.icache.overall_misses::total 920218 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 60050271 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 60050271 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 60050271 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 60050271 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 60050271 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 60050271 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses @@ -362,15 +361,15 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 992301 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65424.374305 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2433239 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1057464 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.301014 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 992295 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65424.374544 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2433214 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1057458 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.301003 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 56309.122439 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4867.329747 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4247.922119 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 56309.107765 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4867.336412 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 4247.930367 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy @@ -379,67 +378,67 @@ system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 781 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3260 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4024 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3055 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54043 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3048 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54050 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 31737437 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 31737437 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 906797 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 811229 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1718026 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 833491 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 833491 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 31737120 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 31737120 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 906794 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 811217 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1718011 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 833475 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 833475 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187229 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187229 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 906797 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 998458 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1905255 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 906797 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 998458 # number of overall hits -system.cpu.l2cache.overall_hits::total 1905255 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 187228 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187228 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 906794 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 998445 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1905239 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 906794 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 998445 # number of overall hits +system.cpu.l2cache.overall_hits::total 1905239 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 941046 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 117117 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 117117 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 117111 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 117111 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 13406 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1044757 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1058163 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1044751 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1058157 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 13406 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1044757 # number of overall misses -system.cpu.l2cache.overall_misses::total 1058163 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 920203 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1738869 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2659072 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 833491 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 833491 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 1044751 # number of overall misses +system.cpu.l2cache.overall_misses::total 1058157 # number of overall misses +system.cpu.l2cache.ReadReq_accesses::cpu.inst 920200 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1738857 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2659057 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 833475 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 833475 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304346 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 920203 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2043215 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2963418 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 920203 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2043215 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2963418 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304339 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304339 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 920200 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2043196 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2963396 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 920200 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2043196 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2963396 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014569 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533473 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.353900 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533477 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.353902 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384815 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.384815 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384804 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.384804 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014569 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.511330 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.357075 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.511332 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.357076 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014569 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.511330 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.357075 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.511332 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.357076 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -448,14 +447,14 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 74291 # number of writebacks -system.cpu.l2cache.writebacks::total 74291 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 74285 # number of writebacks +system.cpu.l2cache.writebacks::total 74285 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2042702 # number of replacements +system.cpu.dcache.tags.replacements 2042683 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14038431 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2043214 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 6.870759 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 14038451 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2043195 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 6.870833 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy @@ -465,52 +464,52 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 443 system.cpu.dcache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 66369799 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 66369799 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7807780 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7807780 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5848212 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5848212 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 66369784 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 66369784 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7807792 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7807792 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5848219 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5848219 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183142 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183142 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13655992 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13655992 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13655992 # number of overall hits -system.cpu.dcache.overall_hits::total 13655992 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1721707 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1721707 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304362 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2026069 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2026069 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2026069 # number of overall misses -system.cpu.dcache.overall_misses::total 2026069 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 9529487 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9529487 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 13656011 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13656011 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13656011 # number of overall hits +system.cpu.dcache.overall_hits::total 13656011 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1721696 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1721696 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304355 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304355 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17161 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17161 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2026051 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2026051 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2026051 # number of overall misses +system.cpu.dcache.overall_misses::total 2026051 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 9529488 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9529488 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6152574 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15682061 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15682061 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15682061 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15682061 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses +system.cpu.dcache.demand_accesses::cpu.data 15682062 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15682062 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15682062 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15682062 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180670 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.180670 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049468 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049468 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085675 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085675 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.129195 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.129195 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.129195 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.129195 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -519,11 +518,11 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks -system.cpu.dcache.writebacks::total 833491 # number of writebacks +system.cpu.dcache.writebacks::writebacks 833475 # number of writebacks +system.cpu.dcache.writebacks::total 833475 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 132867917 # Throughput (bytes/s) -system.cpu.toL2Bus.data_through_bus 243049454 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 10112 # Total snoop data (bytes) +system.cpu.toL2Bus.throughput 134320283 # Throughput (bytes/s) +system.cpu.toL2Bus.data_through_bus 243047022 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 2669376 # Total snoop data (bytes) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index a1c48ce35..034bdfed2 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,137 +1,140 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.962822 # Number of seconds simulated -sim_ticks 1962822184500 # Number of ticks simulated -final_tick 1962822184500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.962815 # Number of seconds simulated +sim_ticks 1962815218500 # Number of ticks simulated +final_tick 1962815218500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 916137 # Simulator instruction rate (inst/s) -host_op_rate 916137 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 30287148246 # Simulator tick rate (ticks/s) -host_mem_usage 346744 # Number of bytes of host memory used -host_seconds 64.81 # Real time elapsed on the host -sim_insts 59372170 # Number of instructions simulated -sim_ops 59372170 # Number of ops (including micro ops) simulated +host_inst_rate 1506000 # Simulator instruction rate (inst/s) +host_op_rate 1505999 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49787604582 # Simulator tick rate (ticks/s) +host_mem_usage 317424 # Number of bytes of host memory used +host_seconds 39.42 # Real time elapsed on the host +sim_insts 59372159 # Number of instructions simulated +sim_ops 59372159 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 724800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24150336 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2649344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 138496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1080640 # Number of bytes read from this memory -system.physmem.bytes_read::total 28743616 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 724800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 138496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 863296 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7747520 # Number of bytes written to this memory -system.physmem.bytes_written::total 7747520 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11325 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 377349 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41396 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2164 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16885 # Number of read requests responded to by this memory -system.physmem.num_reads::total 449119 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 121055 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121055 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 369264 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12303884 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1349763 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 70560 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 550554 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14644024 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 369264 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 70560 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 439824 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3947133 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3947133 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3947133 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 369264 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12303884 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1349763 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 70560 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 550554 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18591157 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 449119 # Number of read requests accepted -system.physmem.writeReqs 121055 # Number of write requests accepted -system.physmem.readBursts 449119 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 121055 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28736320 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7296 # Total number of bytes read from write queue -system.physmem.bytesWritten 7746176 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28743616 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7747520 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 114 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu0.inst 724992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24166912 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 138560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1080576 # Number of bytes read from this memory +system.physmem.bytes_read::total 26112000 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 724992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 138560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 863552 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5090112 # Number of bytes written to this memory +system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory +system.physmem.bytes_written::total 7749440 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11328 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 377608 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2165 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16884 # Number of read requests responded to by this memory +system.physmem.num_reads::total 408000 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 79533 # Number of write requests responded to by this memory +system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121085 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 369363 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12312372 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 70592 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 550524 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13303341 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 369363 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 70592 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 439956 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2593271 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::tsunami.ide 1354854 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3948125 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2593271 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 369363 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12312372 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1355343 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 70592 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 550524 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17251466 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 408000 # Number of read requests accepted +system.physmem.writeReqs 121085 # Number of write requests accepted +system.physmem.readBursts 408000 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 121085 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26099968 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 12032 # Total number of bytes read from write queue +system.physmem.bytesWritten 7747840 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26112000 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7749440 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 188 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 3360 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 28065 # Per bank write bursts -system.physmem.perBankRdBursts::1 28141 # Per bank write bursts -system.physmem.perBankRdBursts::2 27986 # Per bank write bursts -system.physmem.perBankRdBursts::3 28553 # Per bank write bursts -system.physmem.perBankRdBursts::4 28160 # Per bank write bursts -system.physmem.perBankRdBursts::5 27775 # Per bank write bursts -system.physmem.perBankRdBursts::6 27616 # Per bank write bursts -system.physmem.perBankRdBursts::7 27528 # Per bank write bursts -system.physmem.perBankRdBursts::8 27559 # Per bank write bursts -system.physmem.perBankRdBursts::9 27974 # Per bank write bursts -system.physmem.perBankRdBursts::10 27981 # Per bank write bursts -system.physmem.perBankRdBursts::11 28021 # Per bank write bursts -system.physmem.perBankRdBursts::12 28612 # Per bank write bursts -system.physmem.perBankRdBursts::13 28738 # Per bank write bursts -system.physmem.perBankRdBursts::14 28459 # Per bank write bursts -system.physmem.perBankRdBursts::15 27837 # Per bank write bursts +system.physmem.perBankRdBursts::0 25223 # Per bank write bursts +system.physmem.perBankRdBursts::1 25569 # Per bank write bursts +system.physmem.perBankRdBursts::2 25254 # Per bank write bursts +system.physmem.perBankRdBursts::3 25702 # Per bank write bursts +system.physmem.perBankRdBursts::4 25695 # Per bank write bursts +system.physmem.perBankRdBursts::5 25237 # Per bank write bursts +system.physmem.perBankRdBursts::6 25154 # Per bank write bursts +system.physmem.perBankRdBursts::7 25289 # Per bank write bursts +system.physmem.perBankRdBursts::8 25197 # Per bank write bursts +system.physmem.perBankRdBursts::9 25673 # Per bank write bursts +system.physmem.perBankRdBursts::10 25761 # Per bank write bursts +system.physmem.perBankRdBursts::11 25821 # Per bank write bursts +system.physmem.perBankRdBursts::12 25887 # Per bank write bursts +system.physmem.perBankRdBursts::13 25811 # Per bank write bursts +system.physmem.perBankRdBursts::14 25568 # Per bank write bursts +system.physmem.perBankRdBursts::15 24971 # Per bank write bursts system.physmem.perBankWrBursts::0 7862 # Per bank write bursts -system.physmem.perBankWrBursts::1 7636 # Per bank write bursts +system.physmem.perBankWrBursts::1 7635 # Per bank write bursts system.physmem.perBankWrBursts::2 7481 # Per bank write bursts -system.physmem.perBankWrBursts::3 8065 # Per bank write bursts -system.physmem.perBankWrBursts::4 7619 # Per bank write bursts +system.physmem.perBankWrBursts::3 8078 # Per bank write bursts +system.physmem.perBankWrBursts::4 7635 # Per bank write bursts system.physmem.perBankWrBursts::5 7244 # Per bank write bursts -system.physmem.perBankWrBursts::6 7159 # Per bank write bursts -system.physmem.perBankWrBursts::7 6941 # Per bank write bursts +system.physmem.perBankWrBursts::6 7160 # Per bank write bursts +system.physmem.perBankWrBursts::7 6937 # Per bank write bursts system.physmem.perBankWrBursts::8 6882 # Per bank write bursts system.physmem.perBankWrBursts::9 7297 # Per bank write bursts -system.physmem.perBankWrBursts::10 7427 # Per bank write bursts -system.physmem.perBankWrBursts::11 7400 # Per bank write bursts +system.physmem.perBankWrBursts::10 7429 # Per bank write bursts +system.physmem.perBankWrBursts::11 7398 # Per bank write bursts system.physmem.perBankWrBursts::12 8124 # Per bank write bursts system.physmem.perBankWrBursts::13 8265 # Per bank write bursts -system.physmem.perBankWrBursts::14 8168 # Per bank write bursts +system.physmem.perBankWrBursts::14 8169 # Per bank write bursts system.physmem.perBankWrBursts::15 7464 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 8 # Number of times write queue was full causing retry -system.physmem.totGap 1962815073500 # Total gap between requests +system.physmem.numWrRetry 6 # Number of times write queue was full causing retry +system.physmem.totGap 1962808109000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 449119 # Read request sizes (log2) +system.physmem.readPktSize::6 408000 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 121055 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 407912 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1721 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2712 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1995 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4350 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3947 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3971 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2533 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2190 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2091 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1633 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1613 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1890 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1879 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2087 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1205 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 975 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 896 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 121085 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 407738 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -158,356 +161,357 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1425 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4875 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4927 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4931 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4933 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5467 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 905 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 923 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 937 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 961 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1637 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1890 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1946 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1888 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 14 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 68642 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 531.489409 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 323.678439 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 416.279001 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15609 22.74% 22.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11929 17.38% 40.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5150 7.50% 47.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3087 4.50% 52.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3390 4.94% 57.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1779 2.59% 59.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1473 2.15% 61.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1315 1.92% 63.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24910 36.29% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 68642 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7087 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 63.355581 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 1920.089024 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 7082 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-8191 1 0.01% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-45055 1 0.01% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-61439 1 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::73728-77823 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::122880-126975 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7087 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7087 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.078312 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.846071 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 3.814192 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 5314 74.98% 74.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 115 1.62% 76.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1264 17.84% 94.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 37 0.52% 94.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 12 0.17% 95.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 12 0.17% 95.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 26 0.37% 95.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 96 1.35% 97.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 18 0.25% 97.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 39 0.55% 97.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 16 0.23% 98.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 10 0.14% 98.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 12 0.17% 98.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 8 0.11% 98.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 4 0.06% 98.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 15 0.21% 98.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 3 0.04% 98.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 4 0.06% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 2 0.03% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 1 0.01% 98.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 3 0.04% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38 2 0.03% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 10 0.14% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 6 0.08% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 6 0.08% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 2 0.03% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 2 0.03% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44 2 0.03% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::45 4 0.06% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46 1 0.01% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 10 0.14% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48 2 0.03% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 2 0.03% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::55 1 0.01% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56 9 0.13% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::57 14 0.20% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::58 3 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7087 # Writes before turning the bus around for reads -system.physmem.totQLat 7297703000 # Total ticks spent queuing -system.physmem.totMemAccLat 15716546750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2245025000 # Total ticks spent in databus transfers -system.physmem.avgQLat 16253.06 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 1952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6075 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8896 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8887 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8584 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5640 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 13 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 66023 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 512.666919 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 309.343673 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 413.043592 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15664 23.73% 23.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11865 17.97% 41.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5137 7.78% 49.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3080 4.67% 54.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3330 5.04% 59.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1778 2.69% 61.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1463 2.22% 64.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1306 1.98% 66.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22400 33.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 66023 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5447 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 74.865981 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2190.069327 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 5442 99.91% 99.91% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-8191 1 0.02% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-45055 1 0.02% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::73728-77823 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::122880-126975 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5447 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5447 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.225078 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.080270 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 19.855094 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4780 87.75% 87.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 19 0.35% 88.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 16 0.29% 88.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 235 4.31% 92.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 38 0.70% 93.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 9 0.17% 93.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 13 0.24% 93.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 10 0.18% 94.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 23 0.42% 94.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 3 0.06% 94.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 2 0.04% 94.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.02% 94.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 7 0.13% 94.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.09% 94.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.07% 94.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 29 0.53% 95.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 14 0.26% 95.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 6 0.11% 95.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 6 0.11% 95.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 182 3.34% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.04% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.04% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 10 0.18% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.04% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 5 0.09% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 5 0.09% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 8 0.15% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.04% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 2 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5447 # Writes before turning the bus around for reads +system.physmem.totQLat 2167934250 # Total ticks spent queuing +system.physmem.totMemAccLat 9814409250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2039060000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5316.01 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 35003.06 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 14.64 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24066.01 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.30 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 14.64 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.30 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.95 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.15 # Data bus utilization in percentage -system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.13 # Data bus utilization in percentage +system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.12 # Average write queue length when enqueuing -system.physmem.readRowHits 403892 # Number of row buffer hits during reads -system.physmem.writeRowHits 97505 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.95 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.55 # Row buffer hit rate for writes -system.physmem.avgGap 3442484.35 # Average gap between requests -system.physmem.pageHitRate 87.96 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1840580762750 # Time in different power states -system.physmem.memoryStateTime::REF 65542880000 # Time in different power states +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.06 # Average write queue length when enqueuing +system.physmem.readRowHits 365758 # Number of row buffer hits during reads +system.physmem.writeRowHits 97091 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.69 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.18 # Row buffer hit rate for writes +system.physmem.avgGap 3709816.21 # Average gap between requests +system.physmem.pageHitRate 87.51 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1840831671000 # Time in different power states +system.physmem.memoryStateTime::REF 65542620000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 56696821000 # Time in different power states +system.physmem.memoryStateTime::ACT 56438386500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 18645480 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 292657 # Transaction distribution -system.membus.trans_dist::ReadResp 292657 # Transaction distribution +system.membus.throughput 17291736 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 292660 # Transaction distribution +system.membus.trans_dist::ReadResp 292660 # Transaction distribution system.membus.trans_dist::WriteReq 12414 # Transaction distribution system.membus.trans_dist::WriteResp 12414 # Transaction distribution -system.membus.trans_dist::Writeback 121055 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4555 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1018 # Transaction distribution +system.membus.trans_dist::Writeback 79533 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4556 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1019 # Transaction distribution system.membus.trans_dist::UpgradeResp 3360 # Transaction distribution -system.membus.trans_dist::ReadExReq 164356 # Transaction distribution -system.membus.trans_dist::ReadExResp 164254 # Transaction distribution +system.membus.trans_dist::ReadExReq 122803 # Transaction distribution +system.membus.trans_dist::ReadExResp 122701 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39228 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 904273 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 943501 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124647 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124647 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1068148 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 904540 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 943768 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83295 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83295 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1027063 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68738 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31184320 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 31253058 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5306816 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5306816 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36559874 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36559874 # Total data (bytes) -system.membus.snoop_data_through_bus 37888 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 39221000 # Layer occupancy (ticks) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31201152 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 31269890 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 33930178 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 33930178 # Total data (bytes) +system.membus.snoop_data_through_bus 10304 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 39224500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1574833000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1533573250 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3826410374 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3826483141 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376647250 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 43139750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 342221 # number of replacements -system.l2c.tags.tagsinuse 65256.412579 # Cycle average of tags in use -system.l2c.tags.total_refs 2544259 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 407367 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.245619 # Average number of references to valid blocks. +system.l2c.tags.replacements 342222 # number of replacements +system.l2c.tags.tagsinuse 65256.426750 # Cycle average of tags in use +system.l2c.tags.total_refs 2542307 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 407368 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.240812 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 8652281750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55518.574788 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3744.543964 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4299.514442 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1171.756098 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 522.023286 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.847146 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.057137 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.065605 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.017880 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 55518.260732 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3744.767678 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4299.632317 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1171.746225 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 522.019798 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.847141 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.057141 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.065607 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.017879 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.007965 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.995734 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65146 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 752 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 748 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 5288 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7256 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 51736 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 7253 # 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mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60278.469280 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52492.993252 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61937.413395 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 52912.555559 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001.767960 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.650716 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56065.515243 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60544.909206 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 56643.410992 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60839.625077 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53504.540544 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61323.243993 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 60715.816579 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 54048.159692 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60839.625077 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53504.540544 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61323.243993 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 60715.816579 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 54048.159692 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56070.797953 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60481.716729 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 56639.797032 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60278.469280 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53506.457848 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61937.413395 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 60638.485413 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 54034.451306 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60278.469280 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53506.457848 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61937.413395 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 60638.485413 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 54034.451306 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -643,101 +647,93 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.tags.replacements 41699 # number of replacements -system.iocache.tags.tagsinuse 0.570023 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.569942 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1756486423000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.570023 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035626 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035626 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1756486320000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.569942 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035621 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035621 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375552 # Number of tag accesses system.iocache.tags.data_accesses 375552 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses system.iocache.ReadReq_misses::total 176 # number of ReadReq misses -system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses -system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41728 # number of demand (read+write) misses -system.iocache.demand_misses::total 41728 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41728 # number of overall misses -system.iocache.overall_misses::total 41728 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21474883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21474883 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 12370994210 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 12370994210 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 12392469093 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 12392469093 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 12392469093 # number of overall miss cycles -system.iocache.overall_miss_latency::total 12392469093 # number of overall miss cycles +system.iocache.demand_misses::tsunami.ide 176 # number of demand (read+write) misses +system.iocache.demand_misses::total 176 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 176 # number of overall misses +system.iocache.overall_misses::total 176 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21474383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21474383 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21474383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21474383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21474383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21474383 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) -system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41728 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41728 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41728 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41728 # number of overall (read+write) accesses +system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::tsunami.ide 176 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 176 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 176 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 176 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122016.380682 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122016.380682 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 297723.195273 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 297723.195273 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 296982.100580 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 296982.100580 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 296982.100580 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 296982.100580 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 362942 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122013.539773 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122013.539773 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 122013.539773 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 122013.539773 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 28216 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.862986 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.fast_writes 41552 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41523 # number of writebacks -system.iocache.writebacks::total 41523 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12321883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12321883 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10208100710 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 10208100710 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 10220422593 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10220422593 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 10220422593 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10220422593 # number of overall MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 176 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 176 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 176 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12321383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12321383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2504351556 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2504351556 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12321383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12321383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12321383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12321383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70010.698864 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70010.698864 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 245670.502262 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 245670.502262 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 244929.605852 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 244929.605852 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 244929.605852 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 244929.605852 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70007.857955 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60270.301213 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60270.301213 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -755,22 +751,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 6067358 # DTB read hits +system.cpu0.dtb.read_hits 6067147 # DTB read hits system.cpu0.dtb.read_misses 7765 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 524069 # DTB read accesses -system.cpu0.dtb.write_hits 4265662 # DTB write hits +system.cpu0.dtb.write_hits 4265547 # DTB write hits system.cpu0.dtb.write_misses 910 # DTB write misses system.cpu0.dtb.write_acv 133 # DTB write access violations system.cpu0.dtb.write_accesses 202595 # DTB write accesses -system.cpu0.dtb.data_hits 10333020 # DTB hits +system.cpu0.dtb.data_hits 10332694 # DTB hits system.cpu0.dtb.data_misses 8675 # DTB misses system.cpu0.dtb.data_acv 343 # DTB access violations system.cpu0.dtb.data_accesses 726664 # DTB accesses -system.cpu0.itb.fetch_hits 3354842 # ITB hits +system.cpu0.itb.fetch_hits 3354719 # ITB hits system.cpu0.itb.fetch_misses 3984 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3358826 # ITB accesses +system.cpu0.itb.fetch_accesses 3358703 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -783,34 +779,34 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3925644369 # number of cpu cycles simulated +system.cpu0.numCycles 3925630437 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 38276564 # Number of instructions committed -system.cpu0.committedOps 38276564 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 35596868 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 153627 # Number of float alu accesses -system.cpu0.num_func_calls 936507 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4464991 # number of instructions that are conditional controls -system.cpu0.num_int_insts 35596868 # number of integer instructions -system.cpu0.num_fp_insts 153627 # number of float instructions -system.cpu0.num_int_register_reads 48919002 # number of times the integer registers were read -system.cpu0.num_int_register_writes 26532177 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 75066 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 75978 # number of times the floating registers were written -system.cpu0.num_mem_refs 10366198 # number of memory refs -system.cpu0.num_load_insts 6090760 # Number of load instructions -system.cpu0.num_store_insts 4275438 # Number of store instructions -system.cpu0.num_idle_cycles 3742234246.498094 # Number of idle cycles -system.cpu0.num_busy_cycles 183410122.501907 # Number of busy cycles -system.cpu0.not_idle_fraction 0.046721 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.953279 # Percentage of idle cycles -system.cpu0.Branches 5694814 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2096369 5.48% 5.48% # Class of executed instruction -system.cpu0.op_class::IntAlu 24995370 65.29% 70.76% # Class of executed instruction -system.cpu0.op_class::IntMult 39322 0.10% 70.86% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 70.86% # Class of executed instruction -system.cpu0.op_class::FloatAdd 12602 0.03% 70.90% # Class of executed instruction +system.cpu0.committedInsts 38276405 # Number of instructions committed +system.cpu0.committedOps 38276405 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 35596815 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 153493 # Number of float alu accesses +system.cpu0.num_func_calls 936479 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4465105 # number of instructions that are conditional controls +system.cpu0.num_int_insts 35596815 # number of integer instructions +system.cpu0.num_fp_insts 153493 # number of float instructions +system.cpu0.num_int_register_reads 48919188 # number of times the integer registers were read +system.cpu0.num_int_register_writes 26532196 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 75000 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 75910 # number of times the floating registers were written +system.cpu0.num_mem_refs 10365856 # number of memory refs +system.cpu0.num_load_insts 6090539 # Number of load instructions +system.cpu0.num_store_insts 4275317 # Number of store instructions +system.cpu0.num_idle_cycles 3742236660.998093 # Number of idle cycles +system.cpu0.num_busy_cycles 183393776.001907 # Number of busy cycles +system.cpu0.not_idle_fraction 0.046717 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.953283 # Percentage of idle cycles +system.cpu0.Branches 5694884 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2096297 5.48% 5.48% # Class of executed instruction +system.cpu0.op_class::IntAlu 24983670 65.26% 70.73% # Class of executed instruction +system.cpu0.op_class::IntMult 39322 0.10% 70.83% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 70.83% # Class of executed instruction +system.cpu0.op_class::FloatAdd 24596 0.06% 70.90% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 70.90% # Class of executed instruction system.cpu0.op_class::FloatCvt 0 0.00% 70.90% # Class of executed instruction system.cpu0.op_class::FloatMult 0 0.00% 70.90% # Class of executed instruction @@ -836,37 +832,37 @@ system.cpu0.op_class::SimdFloatMisc 0 0.00% 70.90% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 70.90% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 70.90% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::MemRead 6233117 16.28% 87.18% # Class of executed instruction -system.cpu0.op_class::MemWrite 4280683 11.18% 98.36% # Class of executed instruction -system.cpu0.op_class::IprAccess 626236 1.64% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 6232893 16.28% 87.18% # Class of executed instruction +system.cpu0.op_class::MemWrite 4280562 11.18% 98.36% # Class of executed instruction +system.cpu0.op_class::IprAccess 626200 1.64% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 38285582 # Class of executed instruction +system.cpu0.op_class::total 38285423 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4866 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 138364 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 44810 38.76% 38.76% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 4863 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 138357 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 44808 38.76% 38.76% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 131 0.11% 38.88% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1975 1.71% 40.58% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 16 0.01% 40.60% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 68668 59.40% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 115600 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 44285 48.84% 48.84% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::31 68665 59.40% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 115595 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 44283 48.84% 48.84% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 131 0.14% 48.98% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1975 2.18% 51.16% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 16 0.02% 51.18% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 44269 48.82% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 90676 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1909704051500 97.29% 97.29% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 94854000 0.00% 97.30% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 764030500 0.04% 97.34% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_good::31 44267 48.82% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 90672 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1909699143000 97.29% 97.29% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 95243500 0.00% 97.30% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 764380500 0.04% 97.34% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::30 12585500 0.00% 97.34% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 52245891000 2.66% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1962821412500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.988284 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_ticks::31 52243094000 2.66% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1962814446500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.988283 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.644682 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.644681 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::total 0.784394 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed @@ -903,10 +899,10 @@ system.cpu0.kern.callpal::wripir 86 0.07% 0.07% # nu system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal::swpctx 2218 1.80% 1.88% # number of callpals executed +system.cpu0.kern.callpal::swpctx 2216 1.80% 1.87% # number of callpals executed system.cpu0.kern.callpal::tbi 51 0.04% 1.92% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.01% 1.92% # number of callpals executed -system.cpu0.kern.callpal::swpipl 109461 88.95% 90.88% # number of callpals executed +system.cpu0.kern.callpal::swpipl 109456 88.95% 90.88% # number of callpals executed system.cpu0.kern.callpal::rdps 6662 5.41% 96.29% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.29% # number of callpals executed system.cpu0.kern.callpal::wrusp 4 0.00% 96.29% # number of callpals executed @@ -915,21 +911,21 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.30% # nu system.cpu0.kern.callpal::rti 4016 3.26% 99.57% # number of callpals executed system.cpu0.kern.callpal::callsys 394 0.32% 99.89% # number of callpals executed system.cpu0.kern.callpal::imb 139 0.11% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 123054 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 5726 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1371 # number of protection mode switches +system.cpu0.kern.callpal::total 123047 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 5724 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1372 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1370 -system.cpu0.kern.mode_good::user 1371 +system.cpu0.kern.mode_good::kernel 1371 +system.cpu0.kern.mode_good::user 1372 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.239260 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.239518 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.386220 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1959031016000 99.81% 99.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3790392000 0.19% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.386556 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1959023925000 99.81% 99.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3790517000 0.19% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 2219 # number of times the context was actually changed +system.cpu0.kern.swap_context 2217 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -961,42 +957,43 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 108070579 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2148343 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2148328 # Transaction distribution +system.toL2Bus.throughput 109416622 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2148133 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2148118 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 12414 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 12414 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 850135 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 4614 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 1062 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 5676 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 363639 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 322090 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1078600 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2181406 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 927231 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1598323 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5785560 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 34514560 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 81611821 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 29671360 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 63815893 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 209613634 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 209603138 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 2520192 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 5075991989 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::Writeback 850078 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 41558 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 4615 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 1065 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 5680 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 322069 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 322069 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1078328 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2181300 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 927173 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1598235 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5785036 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 34505856 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 81606637 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 29669504 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 63812309 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 209594306 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 209584002 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 5180608 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 5075622491 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 738000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2429088500 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2428486244 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4030648808 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4030575545 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 2086694241 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 2086565739 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 2646669064 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 2646502814 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.1 # Layer utilization (%) -system.iobus.throughput 1391043 # Throughput (bytes/s) +system.iobus.throughput 1391048 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7376 # Transaction distribution system.iobus.trans_dist::ReadResp 7376 # Transaction distribution system.iobus.trans_dist::WriteReq 53966 # Transaction distribution @@ -1056,21 +1053,21 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 380139843 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 374413689 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 26814000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 43231750 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42018250 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 538677 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.393435 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 37746273 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 539189 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 70.005644 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 538541 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.393356 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 37746250 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 539053 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 70.023263 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 40276505250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.393435 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.393356 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992956 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.992956 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -1079,44 +1076,44 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 system.cpu0.icache.tags.age_task_id_blocks_1024::2 442 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 38824893 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 38824893 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 37746273 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 37746273 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 37746273 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 37746273 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 37746273 # number of overall hits -system.cpu0.icache.overall_hits::total 37746273 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 539310 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 539310 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 539310 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 539310 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 539310 # number of overall misses -system.cpu0.icache.overall_misses::total 539310 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7764312000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 7764312000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7764312000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 7764312000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7764312000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 7764312000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 38285583 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 38285583 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 38285583 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 38285583 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 38285583 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 38285583 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014087 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014087 # 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Number of tag accesses +system.cpu0.icache.tags.data_accesses 38824598 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 37746250 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 37746250 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 37746250 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 37746250 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 37746250 # number of overall hits +system.cpu0.icache.overall_hits::total 37746250 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 539174 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 539174 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 539174 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 539174 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 539174 # number of overall misses +system.cpu0.icache.overall_misses::total 539174 # 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average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14385.528130 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14385.528130 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1125,119 +1122,119 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 539310 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 539310 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 539310 # 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average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12377.355466 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12377.355466 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12377.355466 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12377.355466 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 871224 # number of replacements -system.cpu0.dcache.tags.tagsinuse 481.747613 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 9466123 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 871736 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 10.858933 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 871192 # 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Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 322 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 42234072 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 42234072 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 5299987 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5299987 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3905819 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3905819 # 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number of overall hits +system.cpu0.dcache.overall_hits::total 9205497 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 645318 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 645318 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 224183 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 224183 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7829 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 7829 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 497 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 497 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 869501 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 869501 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 869501 # number of overall misses +system.cpu0.dcache.overall_misses::total 869501 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 23374202500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 23374202500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9262527483 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 9262527483 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 102834500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 102834500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3584562 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 3584562 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 32636729983 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 32636729983 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 32636729983 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 32636729983 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5945097 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 5945097 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4129901 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4129901 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 132623 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 132623 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 132076 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 132076 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10074998 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10074998 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10074998 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10074998 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.108546 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.108546 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.054283 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.054283 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059032 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059032 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003763 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003763 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.086303 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.086303 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.086303 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.086303 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 36221.215742 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 36221.215742 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41316.814758 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 41316.814758 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13135.074722 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13135.074722 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7212.398390 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7212.398390 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37535.011441 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 37535.011441 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37535.011441 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 37535.011441 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1246,62 +1243,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 405192 # number of writebacks -system.cpu0.dcache.writebacks::total 405192 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 645326 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 645326 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 224198 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 224198 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 7833 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7833 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 495 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 495 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 869524 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 869524 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 869524 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 869524 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21958342736 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21958342736 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8764766768 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8764766768 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 87220250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 87220250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 2576938 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2576938 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 30723109504 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 30723109504 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 30723109504 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 30723109504 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1004924500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1004924500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1718153000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1718153000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2723077500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2723077500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.108544 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.108544 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.054285 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.054285 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059060 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059060 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003748 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.003748 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.086302 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.086302 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.086302 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.086302 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 34026.744213 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 34026.744213 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39093.866886 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39093.866886 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11134.973829 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11134.973829 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5205.935354 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5205.935354 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35333.250726 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35333.250726 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35333.250726 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35333.250726 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 405151 # number of writebacks +system.cpu0.dcache.writebacks::total 405151 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 645318 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 645318 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 224183 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 224183 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 7829 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7829 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 497 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 497 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 869501 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 869501 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 869501 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 869501 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21958327500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21958327500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8765186517 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8765186517 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 87163500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 87163500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 2590438 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2590438 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 30723514017 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 30723514017 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 30723514017 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 30723514017 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1004927000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1004927000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1718158000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1718158000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2723085000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2723085000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.108546 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.108546 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.054283 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.054283 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059032 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059032 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003763 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.003763 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.086303 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.086303 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.086303 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.086303 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 34027.142432 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 34027.142432 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39098.354991 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39098.354991 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11133.414229 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11133.414229 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5212.148893 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5212.148893 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35334.650583 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35334.650583 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35334.650583 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35334.650583 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1313,22 +1310,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 3617105 # DTB read hits +system.cpu1.dtb.read_hits 3617054 # DTB read hits system.cpu1.dtb.read_misses 2620 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 205337 # DTB read accesses -system.cpu1.dtb.write_hits 2433899 # DTB write hits +system.cpu1.dtb.write_hits 2433875 # DTB write hits system.cpu1.dtb.write_misses 235 # DTB write misses system.cpu1.dtb.write_acv 24 # DTB write access violations system.cpu1.dtb.write_accesses 89739 # DTB write accesses -system.cpu1.dtb.data_hits 6051004 # DTB hits +system.cpu1.dtb.data_hits 6050929 # DTB hits system.cpu1.dtb.data_misses 2855 # DTB misses system.cpu1.dtb.data_acv 24 # DTB access violations system.cpu1.dtb.data_accesses 295076 # DTB accesses -system.cpu1.itb.fetch_hits 1988116 # ITB hits +system.cpu1.itb.fetch_hits 1988100 # ITB hits system.cpu1.itb.fetch_misses 1064 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1989180 # ITB accesses +system.cpu1.itb.fetch_accesses 1989164 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1341,34 +1338,34 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3923841481 # number of cpu cycles simulated +system.cpu1.numCycles 3923841470 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 21095606 # Number of instructions committed -system.cpu1.committedOps 21095606 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 19410796 # Number of integer alu accesses +system.cpu1.committedInsts 21095754 # Number of instructions committed +system.cpu1.committedOps 21095754 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 19410964 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 175175 # Number of float alu accesses -system.cpu1.num_func_calls 648522 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2286515 # number of instructions that are conditional controls -system.cpu1.num_int_insts 19410796 # number of integer instructions +system.cpu1.num_func_calls 648514 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2286581 # number of instructions that are conditional controls +system.cpu1.num_int_insts 19410964 # number of integer instructions system.cpu1.num_fp_insts 175175 # number of float instructions -system.cpu1.num_int_register_reads 26519930 # number of times the integer registers were read -system.cpu1.num_int_register_writes 14289781 # number of times the integer registers were written +system.cpu1.num_int_register_reads 26520307 # number of times the integer registers were read +system.cpu1.num_int_register_writes 14289908 # number of times the integer registers were written system.cpu1.num_fp_register_reads 90745 # number of times the floating registers were read system.cpu1.num_fp_register_writes 92744 # number of times the floating registers were written -system.cpu1.num_mem_refs 6073244 # number of memory refs -system.cpu1.num_load_insts 3630952 # Number of load instructions -system.cpu1.num_store_insts 2442292 # Number of store instructions -system.cpu1.num_idle_cycles 3837671905.347151 # Number of idle cycles -system.cpu1.num_busy_cycles 86169575.652849 # Number of busy cycles -system.cpu1.not_idle_fraction 0.021961 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.978039 # Percentage of idle cycles -system.cpu1.Branches 3164985 # Number of branches fetched -system.cpu1.op_class::No_OpClass 1250072 5.92% 5.92% # Class of executed instruction -system.cpu1.op_class::IntAlu 13187049 62.50% 68.43% # Class of executed instruction -system.cpu1.op_class::IntMult 30193 0.14% 68.57% # Class of executed instruction +system.cpu1.num_mem_refs 6073169 # number of memory refs +system.cpu1.num_load_insts 3630901 # Number of load instructions +system.cpu1.num_store_insts 2442268 # Number of store instructions +system.cpu1.num_idle_cycles 3837673362.965370 # Number of idle cycles +system.cpu1.num_busy_cycles 86168107.034630 # Number of busy cycles +system.cpu1.not_idle_fraction 0.021960 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.978040 # Percentage of idle cycles +system.cpu1.Branches 3165037 # Number of branches fetched +system.cpu1.op_class::No_OpClass 1250062 5.92% 5.92% # Class of executed instruction +system.cpu1.op_class::IntAlu 13186802 62.50% 68.43% # Class of executed instruction +system.cpu1.op_class::IntMult 30198 0.14% 68.57% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 68.57% # Class of executed instruction -system.cpu1.op_class::FloatAdd 13163 0.06% 68.63% # Class of executed instruction +system.cpu1.op_class::FloatAdd 13644 0.06% 68.63% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 68.63% # Class of executed instruction system.cpu1.op_class::FloatCvt 0 0.00% 68.63% # Class of executed instruction system.cpu1.op_class::FloatMult 0 0.00% 68.63% # Class of executed instruction @@ -1394,34 +1391,34 @@ system.cpu1.op_class::SimdFloatMisc 0 0.00% 68.64% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 68.64% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.64% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::MemRead 3726131 17.66% 86.30% # Class of executed instruction -system.cpu1.op_class::MemWrite 2443312 11.58% 97.88% # Class of executed instruction -system.cpu1.op_class::IprAccess 446806 2.12% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 3726078 17.66% 86.30% # Class of executed instruction +system.cpu1.op_class::MemWrite 2443288 11.58% 97.88% # Class of executed instruction +system.cpu1.op_class::IprAccess 446802 2.12% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 21098485 # Class of executed instruction +system.cpu1.op_class::total 21098633 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 3863 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 100735 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 37219 40.29% 40.29% # number of times we switched to this ipl +system.cpu1.kern.inst.hwrei 100733 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 37218 40.29% 40.29% # number of times we switched to this ipl system.cpu1.kern.ipl_count::22 1970 2.13% 42.42% # number of times we switched to this ipl system.cpu1.kern.ipl_count::30 86 0.09% 42.51% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 53109 57.49% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 92384 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 36367 48.68% 48.68% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_count::31 53108 57.49% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 92382 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 36366 48.68% 48.68% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::22 1970 2.64% 51.32% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::30 86 0.12% 51.43% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 36281 48.57% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 74704 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1906656399000 97.18% 97.18% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 706249000 0.04% 97.22% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_good::31 36280 48.57% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 74702 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1906657223000 97.18% 97.18% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 706239500 0.04% 97.22% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::30 59367000 0.00% 97.22% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 54498695500 2.78% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1961920710500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 54497875500 2.78% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1961920705000 # number of cycles we spent at this ipl system.cpu1.kern.ipl_used::0 0.977108 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.683142 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.808625 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.683136 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.808621 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed @@ -1443,7 +1440,7 @@ system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # nu system.cpu1.kern.callpal::swpctx 2020 2.13% 2.15% # number of callpals executed system.cpu1.kern.callpal::tbi 3 0.00% 2.16% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 2.16% # number of callpals executed -system.cpu1.kern.callpal::swpipl 87061 91.90% 94.06% # number of callpals executed +system.cpu1.kern.callpal::swpipl 87059 91.90% 94.06% # number of callpals executed system.cpu1.kern.callpal::rdps 2187 2.31% 96.37% # number of callpals executed system.cpu1.kern.callpal::wrkgp 1 0.00% 96.37% # number of callpals executed system.cpu1.kern.callpal::wrusp 3 0.00% 96.38% # number of callpals executed @@ -1452,72 +1449,72 @@ system.cpu1.kern.callpal::rti 3266 3.45% 99.83% # nu system.cpu1.kern.callpal::callsys 121 0.13% 99.95% # number of callpals executed system.cpu1.kern.callpal::imb 42 0.04% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 94734 # number of callpals executed +system.cpu1.kern.callpal::total 94732 # number of callpals executed system.cpu1.kern.mode_switch::kernel 2415 # number of protection mode switches -system.cpu1.kern.mode_switch::user 366 # number of protection mode switches +system.cpu1.kern.mode_switch::user 367 # number of protection mode switches system.cpu1.kern.mode_switch::idle 2037 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 414 -system.cpu1.kern.mode_good::user 366 +system.cpu1.kern.mode_good::kernel 415 +system.cpu1.kern.mode_good::user 367 system.cpu1.kern.mode_good::idle 48 -system.cpu1.kern.mode_switch_good::kernel 0.171429 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.171843 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle 0.023564 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.171856 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 65780447000 3.35% 3.35% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1486717000 0.08% 3.43% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1893764152500 96.57% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_switch_good::total 0.172235 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 65779284000 3.35% 3.35% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1486343500 0.08% 3.43% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1893759051500 96.57% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 2021 # number of times the context was actually changed -system.cpu1.icache.tags.replacements 463064 # number of replacements -system.cpu1.icache.tags.tagsinuse 500.061225 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 20634869 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 463576 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 44.512376 # Average number of references to valid blocks. +system.cpu1.icache.tags.replacements 463035 # number of replacements +system.cpu1.icache.tags.tagsinuse 500.061178 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 20635046 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 463547 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 44.515542 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 97712638250 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 500.061225 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_blocks::cpu1.inst 500.061178 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.976682 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.976682 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 108 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 404 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 21562101 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 21562101 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 20634869 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 20634869 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 20634869 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 20634869 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 20634869 # number of overall hits -system.cpu1.icache.overall_hits::total 20634869 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 463616 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 463616 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 463616 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 463616 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 463616 # number of overall misses -system.cpu1.icache.overall_misses::total 463616 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6201828741 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6201828741 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6201828741 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6201828741 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6201828741 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6201828741 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 21098485 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 21098485 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 21098485 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 21098485 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 21098485 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 21098485 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.021974 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.021974 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.021974 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.021974 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.021974 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.021974 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13377.080905 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13377.080905 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13377.080905 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13377.080905 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13377.080905 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13377.080905 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 21562220 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 21562220 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 20635046 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 20635046 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 20635046 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 20635046 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 20635046 # number of overall hits +system.cpu1.icache.overall_hits::total 20635046 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 463587 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 463587 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 463587 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 463587 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 463587 # number of overall misses +system.cpu1.icache.overall_misses::total 463587 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6202855739 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 6202855739 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 6202855739 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6202855739 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6202855739 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6202855739 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 21098633 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 21098633 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 21098633 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 21098633 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 21098633 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 21098633 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.021972 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.021972 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.021972 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.021972 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.021972 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.021972 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13380.133047 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13380.133047 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13380.133047 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13380.133047 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13380.133047 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13380.133047 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1526,118 +1523,118 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 463616 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 463616 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 463616 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 463616 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 463616 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 463616 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5273752259 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5273752259 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5273752259 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5273752259 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5273752259 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5273752259 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.021974 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.021974 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.021974 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.021974 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.021974 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.021974 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11375.259394 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11375.259394 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11375.259394 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11375.259394 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11375.259394 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11375.259394 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 463587 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 463587 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 463587 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 463587 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 463587 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 463587 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5274833261 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5274833261 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5274833261 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5274833261 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5274833261 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5274833261 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.021972 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.021972 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.021972 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.021972 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.021972 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.021972 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11378.302802 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11378.302802 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11378.302802 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11378.302802 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11378.302802 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11378.302802 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 581734 # number of replacements -system.cpu1.dcache.tags.tagsinuse 492.027113 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 5462976 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 582077 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 9.385315 # Average number of references to valid blocks. +system.cpu1.dcache.tags.replacements 581700 # number of replacements +system.cpu1.dcache.tags.tagsinuse 492.027042 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 5462019 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 582040 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 9.384267 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 61159690250 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 492.027113 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_blocks::cpu1.data 492.027042 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.960990 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.960990 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 343 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 300 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.669922 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 24828652 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 24828652 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 3080166 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3080166 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 2260006 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 2260006 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 60928 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 60928 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71558 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 71558 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 5340172 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 5340172 # 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number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 8279020734 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 8279020734 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3553376 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3553376 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 2362509 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 2362509 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 72600 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 72600 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 72125 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 72125 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 5915885 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 5915885 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 5915885 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 5915885 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.133172 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.133172 # miss rate for ReadReq accesses +system.cpu1.dcache.tags.occ_task_id_blocks::1024 340 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 298 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.664062 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 24828314 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 24828314 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 3080149 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3080149 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 2259986 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 2259986 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 60927 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 60927 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71555 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 71555 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 5340135 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 5340135 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 5340135 # number of overall hits +system.cpu1.dcache.overall_hits::total 5340135 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 473178 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 473178 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 102501 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 102501 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11671 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 11671 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 568 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 568 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 575679 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 575679 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 575679 # number of overall misses +system.cpu1.dcache.overall_misses::total 575679 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5938208750 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 5938208750 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2338814234 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2338814234 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 149892750 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 149892750 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4181580 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4181580 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 8277022984 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8277022984 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8277022984 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8277022984 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3553327 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3553327 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 2362487 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 2362487 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 72598 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 72598 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 72123 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 72123 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 5915814 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 5915814 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 5915814 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 5915814 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.133165 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.133165 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.043387 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_miss_rate::total 0.043387 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.160771 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.160771 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.007861 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.007861 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.097316 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.097316 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.097316 # 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average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14380.465152 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14380.465152 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14380.465152 # average overall miss latency +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.160762 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.160762 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.007875 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.007875 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.097312 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.097312 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.097312 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.097312 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12549.629843 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12549.629843 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22817.477234 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 22817.477234 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12843.179676 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12843.179676 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7361.936620 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7361.936620 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14377.844222 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14377.844222 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14377.844222 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14377.844222 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1646,62 +1643,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 444943 # number of writebacks -system.cpu1.dcache.writebacks::total 444943 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 473210 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 473210 # 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number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 7120750266 # number of overall MSHR miss cycles +system.cpu1.dcache.writebacks::writebacks 444927 # number of writebacks +system.cpu1.dcache.writebacks::total 444927 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 473178 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 473178 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 102501 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 102501 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11671 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11671 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 568 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 568 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 575679 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 575679 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 575679 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 575679 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 4991497250 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 4991497250 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2127317766 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2127317766 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 126550250 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 126550250 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3045420 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3045420 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7118815016 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 7118815016 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7118815016 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 7118815016 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 479658500 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 479658500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 907861000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 907861000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1387519500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1387519500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.133172 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.133172 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 907862000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 907862000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1387520500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1387520500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.133165 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.133165 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.043387 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.043387 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.160771 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.160771 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.007861 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.007861 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.097316 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.097316 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.097316 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.097316 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10549.537203 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10549.537203 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 20766.258217 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 20766.258217 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10843.150274 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10843.150274 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5342.010582 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5342.010582 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12368.576471 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12368.576471 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12368.576471 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12368.576471 # average overall mshr miss latency +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.160762 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.160762 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.007875 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.007875 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.097312 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.097312 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.097312 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.097312 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10548.878540 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10548.878540 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 20754.117189 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 20754.117189 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10843.136835 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10843.136835 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5361.654930 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5361.654930 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12365.945285 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12365.945285 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12365.945285 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12365.945285 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 24f1d16b8..7916cb036 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,127 +1,130 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.919447 # Number of seconds simulated -sim_ticks 1919446558000 # Number of ticks simulated -final_tick 1919446558000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.919439 # Number of seconds simulated +sim_ticks 1919438772000 # Number of ticks simulated +final_tick 1919438772000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 885398 # Simulator instruction rate (inst/s) -host_op_rate 885398 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 30291378157 # Simulator tick rate (ticks/s) -host_mem_usage 344696 # Number of bytes of host memory used -host_seconds 63.37 # Real time elapsed on the host -sim_insts 56104177 # Number of instructions simulated -sim_ops 56104177 # Number of ops (including micro ops) simulated +host_inst_rate 1398299 # Simulator instruction rate (inst/s) +host_op_rate 1398299 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47840414078 # Simulator tick rate (ticks/s) +host_mem_usage 314348 # Number of bytes of host memory used +host_seconds 40.12 # Real time elapsed on the host +sim_insts 56102112 # Number of instructions simulated +sim_ops 56102112 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 850752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24858240 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28361344 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 850752 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 850752 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7404032 # Number of bytes written to this memory -system.physmem.bytes_written::total 7404032 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13293 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388410 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 443146 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115688 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115688 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 443228 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12950733 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1381832 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14775792 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 443228 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 443228 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3857379 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3857379 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3857379 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 443228 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12950733 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1381832 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18633171 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 443146 # Number of read requests accepted -system.physmem.writeReqs 115688 # Number of write requests accepted -system.physmem.readBursts 443146 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 115688 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28353856 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7488 # Total number of bytes read from write queue -system.physmem.bytesWritten 7402304 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28361344 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7404032 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 117 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 850816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24875968 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::total 25727744 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 850816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 850816 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4747712 # Number of bytes written to this memory +system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory +system.physmem.bytes_written::total 7407040 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13294 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388687 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::total 401996 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 74183 # Number of write requests responded to by this memory +system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115735 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 443263 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12960022 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 500 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13403785 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 443263 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 443263 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2473490 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::tsunami.ide 1385472 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3858961 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2473490 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 443263 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12960022 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1385972 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17262746 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 401996 # Number of read requests accepted +system.physmem.writeReqs 115735 # Number of write requests accepted +system.physmem.readBursts 401996 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115735 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25716224 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 11520 # Total number of bytes read from write queue +system.physmem.bytesWritten 7405312 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25727744 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7407040 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 180 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 130 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 27768 # Per bank write bursts -system.physmem.perBankRdBursts::1 28019 # Per bank write bursts -system.physmem.perBankRdBursts::2 28336 # Per bank write bursts -system.physmem.perBankRdBursts::3 28020 # Per bank write bursts -system.physmem.perBankRdBursts::4 27518 # Per bank write bursts -system.physmem.perBankRdBursts::5 27546 # Per bank write bursts -system.physmem.perBankRdBursts::6 26737 # Per bank write bursts -system.physmem.perBankRdBursts::7 26852 # Per bank write bursts -system.physmem.perBankRdBursts::8 27860 # Per bank write bursts -system.physmem.perBankRdBursts::9 27104 # Per bank write bursts -system.physmem.perBankRdBursts::10 27841 # Per bank write bursts -system.physmem.perBankRdBursts::11 27413 # Per bank write bursts -system.physmem.perBankRdBursts::12 27378 # Per bank write bursts -system.physmem.perBankRdBursts::13 28201 # Per bank write bursts -system.physmem.perBankRdBursts::14 28236 # Per bank write bursts -system.physmem.perBankRdBursts::15 28200 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 132 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25161 # Per bank write bursts +system.physmem.perBankRdBursts::1 25541 # Per bank write bursts +system.physmem.perBankRdBursts::2 25618 # Per bank write bursts +system.physmem.perBankRdBursts::3 25537 # Per bank write bursts +system.physmem.perBankRdBursts::4 24981 # Per bank write bursts +system.physmem.perBankRdBursts::5 24976 # Per bank write bursts +system.physmem.perBankRdBursts::6 24228 # Per bank write bursts +system.physmem.perBankRdBursts::7 24506 # Per bank write bursts +system.physmem.perBankRdBursts::8 25159 # Per bank write bursts +system.physmem.perBankRdBursts::9 24820 # Per bank write bursts +system.physmem.perBankRdBursts::10 25363 # Per bank write bursts +system.physmem.perBankRdBursts::11 24840 # Per bank write bursts +system.physmem.perBankRdBursts::12 24420 # Per bank write bursts +system.physmem.perBankRdBursts::13 25388 # Per bank write bursts +system.physmem.perBankRdBursts::14 25795 # Per bank write bursts +system.physmem.perBankRdBursts::15 25483 # Per bank write bursts system.physmem.perBankWrBursts::0 7550 # Per bank write bursts system.physmem.perBankWrBursts::1 7529 # Per bank write bursts -system.physmem.perBankWrBursts::2 7869 # Per bank write bursts -system.physmem.perBankWrBursts::3 7540 # Per bank write bursts +system.physmem.perBankWrBursts::2 7880 # Per bank write bursts +system.physmem.perBankWrBursts::3 7553 # Per bank write bursts system.physmem.perBankWrBursts::4 7115 # Per bank write bursts system.physmem.perBankWrBursts::5 6983 # Per bank write bursts system.physmem.perBankWrBursts::6 6321 # Per bank write bursts -system.physmem.perBankWrBursts::7 6313 # Per bank write bursts +system.physmem.perBankWrBursts::7 6319 # Per bank write bursts system.physmem.perBankWrBursts::8 7293 # Per bank write bursts -system.physmem.perBankWrBursts::9 6538 # Per bank write bursts +system.physmem.perBankWrBursts::9 6554 # Per bank write bursts system.physmem.perBankWrBursts::10 7205 # Per bank write bursts system.physmem.perBankWrBursts::11 6861 # Per bank write bursts system.physmem.perBankWrBursts::12 6964 # Per bank write bursts system.physmem.perBankWrBursts::13 7821 # Per bank write bursts -system.physmem.perBankWrBursts::14 7979 # Per bank write bursts +system.physmem.perBankWrBursts::14 7980 # Per bank write bursts system.physmem.perBankWrBursts::15 7780 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 11 # Number of times write queue was full causing retry -system.physmem.totGap 1919434637000 # Total gap between requests +system.physmem.totGap 1919426851000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 443146 # Read request sizes (log2) +system.physmem.readPktSize::6 401996 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 115688 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 401962 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1642 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2685 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1248 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1966 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4407 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3974 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3974 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2507 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2187 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1622 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1616 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1907 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1876 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1224 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 966 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 883 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 11 # What read queue length does an incoming req see +system.physmem.writePktSize::6 115735 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 401802 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -148,278 +151,267 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4579 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4946 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5540 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5621 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 915 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1033 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 949 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1625 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2098 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1878 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1629 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 18 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 66429 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 538.261302 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 328.855989 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 417.099114 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14887 22.41% 22.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11472 17.27% 39.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4684 7.05% 46.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3132 4.71% 51.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3072 4.62% 56.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1874 2.82% 58.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1342 2.02% 60.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1444 2.17% 63.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24522 36.91% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 66429 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6775 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 65.389077 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 16.529238 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2564.130292 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 6772 99.96% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6775 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6775 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.071734 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.848509 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 3.695111 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 5062 74.72% 74.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 127 1.87% 76.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1207 17.82% 94.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 25 0.37% 94.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 12 0.18% 94.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 16 0.24% 95.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 18 0.27% 95.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 98 1.45% 96.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 22 0.32% 97.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 41 0.61% 97.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 20 0.30% 98.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 8 0.12% 98.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 7 0.10% 98.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 8 0.12% 98.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 7 0.10% 98.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 15 0.22% 98.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 9 0.13% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 1 0.01% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 1 0.01% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 1 0.01% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 1 0.01% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38 1 0.01% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 4 0.06% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 9 0.13% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 8 0.12% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 2 0.03% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 2 0.03% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44 2 0.03% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::45 1 0.01% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46 1 0.01% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 8 0.12% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48 7 0.10% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::49 1 0.01% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 2 0.03% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::51 2 0.03% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52 1 0.01% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::54 1 0.01% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56 7 0.10% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::57 9 0.13% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::59 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6775 # Writes before turning the bus around for reads -system.physmem.totQLat 7315796250 # Total ticks spent queuing -system.physmem.totMemAccLat 15622590000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2215145000 # Total ticks spent in databus transfers -system.physmem.avgQLat 16513.13 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 1859 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2606 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5607 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5735 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5978 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6976 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6824 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 24 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 63869 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 518.585480 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 313.979775 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 413.923527 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14875 23.29% 23.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11515 18.03% 41.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4721 7.39% 48.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3142 4.92% 53.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3018 4.73% 58.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1863 2.92% 61.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1301 2.04% 63.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1404 2.20% 65.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22030 34.49% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63869 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5101 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 78.768477 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2955.016496 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5098 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5101 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5101 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.683395 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.235797 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.276820 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4452 87.28% 87.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 22 0.43% 87.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 15 0.29% 88.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 224 4.39% 92.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 41 0.80% 93.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 6 0.12% 93.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 9 0.18% 93.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 7 0.14% 93.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 19 0.37% 94.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 2 0.04% 94.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 4 0.08% 94.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.04% 94.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 11 0.22% 94.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 3 0.06% 94.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 7 0.14% 94.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 30 0.59% 95.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 13 0.25% 95.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.06% 95.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 95.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 166 3.25% 98.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 10 0.20% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.04% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 6 0.12% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 4 0.08% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.04% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 6 0.12% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 9 0.18% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 9 0.18% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.06% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.04% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 3 0.06% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 4 0.08% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5101 # Writes before turning the bus around for reads +system.physmem.totQLat 2117396500 # Total ticks spent queuing +system.physmem.totMemAccLat 9651446500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2009080000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5269.57 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 35263.13 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 14.77 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24019.57 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.40 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.86 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 14.78 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.40 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.86 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.15 # Data bus utilization in percentage -system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.13 # Data bus utilization in percentage +system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.40 # Average write queue length when enqueuing -system.physmem.readRowHits 398273 # Number of row buffer hits during reads -system.physmem.writeRowHits 93988 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.90 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.24 # Row buffer hit rate for writes -system.physmem.avgGap 3434713.42 # Average gap between requests -system.physmem.pageHitRate 88.11 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1800016178000 # Time in different power states -system.physmem.memoryStateTime::REF 64094420000 # Time in different power states +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.42 # Average write queue length when enqueuing +system.physmem.readRowHits 360116 # Number of row buffer hits during reads +system.physmem.writeRowHits 93539 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.62 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.82 # Row buffer hit rate for writes +system.physmem.avgGap 3707382.50 # Average gap between requests +system.physmem.pageHitRate 87.65 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1800046548500 # Time in different power states +system.physmem.memoryStateTime::REF 64094160000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 55332653250 # Time in different power states +system.physmem.memoryStateTime::ACT 55294756500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 18674823 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 292356 # Transaction distribution -system.membus.trans_dist::ReadResp 292356 # Transaction distribution +system.membus.throughput 17291227 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 292357 # Transaction distribution +system.membus.trans_dist::ReadResp 292357 # Transaction distribution system.membus.trans_dist::WriteReq 9649 # Transaction distribution system.membus.trans_dist::WriteResp 9649 # Transaction distribution -system.membus.trans_dist::Writeback 115688 # Transaction distribution +system.membus.trans_dist::Writeback 74183 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution system.membus.trans_dist::UpgradeReq 132 # Transaction distribution system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 158273 # Transaction distribution -system.membus.trans_dist::ReadExResp 158273 # Transaction distribution +system.membus.trans_dist::ReadExReq 116727 # Transaction distribution +system.membus.trans_dist::ReadExResp 116727 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33158 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878115 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911273 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124680 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124680 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1035953 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878409 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911567 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83292 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83292 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 994859 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30456256 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30500812 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309120 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5309120 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 35809932 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 35809932 # Total data (bytes) -system.membus.snoop_data_through_bus 35392 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 32376000 # Layer occupancy (ticks) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30474496 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30519052 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 33179340 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 33179340 # Total data (bytes) +system.membus.snoop_data_through_bus 10112 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 32375500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1491996000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1450892000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3751677600 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3751806368 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376660500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 43113000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.344872 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.344805 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1753525004000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.344872 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.084054 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.084054 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1753524887000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.344805 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.084050 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.084050 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375525 # Number of tag accesses system.iocache.tags.data_accesses 375525 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses -system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses -system.iocache.demand_misses::total 41725 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses -system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21253133 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21253133 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 12447285431 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 12447285431 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 12468538564 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 12468538564 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 12468538564 # number of overall miss cycles -system.iocache.overall_miss_latency::total 12468538564 # number of overall miss cycles +system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses +system.iocache.demand_misses::total 173 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 173 # number of overall misses +system.iocache.overall_misses::total 173 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses +system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122850.479769 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122850.479769 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 299559.237365 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 299559.237365 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 298826.568340 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 298826.568340 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 298826.568340 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 298826.568340 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 365803 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 28265 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.941907 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.fast_writes 41552 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41512 # number of writebacks -system.iocache.writebacks::total 41512 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12255133 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12255133 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10284312431 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 10284312431 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 10296567564 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10296567564 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 10296567564 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10296567564 # number of overall MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2506570306 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2506570306 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70838.919075 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70838.919075 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247504.631089 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 247504.631089 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 246772.140539 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 246772.140539 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 246772.140539 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 246772.140539 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60323.698161 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60323.698161 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -438,22 +430,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9052923 # DTB read hits -system.cpu.dtb.read_misses 10354 # DTB read misses +system.cpu.dtb.read_hits 9052614 # DTB read hits +system.cpu.dtb.read_misses 10356 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728911 # DTB read accesses -system.cpu.dtb.write_hits 6349403 # DTB write hits -system.cpu.dtb.write_misses 1143 # DTB write misses +system.cpu.dtb.read_accesses 728915 # DTB read accesses +system.cpu.dtb.write_hits 6349217 # DTB write hits +system.cpu.dtb.write_misses 1144 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291932 # DTB write accesses -system.cpu.dtb.data_hits 15402326 # DTB hits -system.cpu.dtb.data_misses 11497 # DTB misses +system.cpu.dtb.write_accesses 291933 # DTB write accesses +system.cpu.dtb.data_hits 15401831 # DTB hits +system.cpu.dtb.data_misses 11500 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020843 # DTB accesses -system.cpu.itb.fetch_hits 4974965 # ITB hits +system.cpu.dtb.data_accesses 1020848 # DTB accesses +system.cpu.itb.fetch_hits 4974960 # ITB hits system.cpu.itb.fetch_misses 5010 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979975 # ITB accesses +system.cpu.itb.fetch_accesses 4979970 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -466,34 +458,34 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3838893116 # number of cpu cycles simulated +system.cpu.numCycles 3838877544 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56104177 # Number of instructions committed -system.cpu.committedOps 56104177 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 51979169 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324594 # Number of float alu accesses -system.cpu.num_func_calls 1481286 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6461218 # number of instructions that are conditional controls -system.cpu.num_int_insts 51979169 # number of integer instructions -system.cpu.num_fp_insts 324594 # number of float instructions -system.cpu.num_int_register_reads 71209746 # number of times the integer registers were read -system.cpu.num_int_register_writes 38460532 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163708 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166588 # number of times the floating registers were written -system.cpu.num_mem_refs 15454993 # number of memory refs -system.cpu.num_load_insts 9089820 # Number of load instructions -system.cpu.num_store_insts 6365173 # Number of store instructions -system.cpu.num_idle_cycles 3587243859.498131 # Number of idle cycles -system.cpu.num_busy_cycles 251649256.501869 # Number of busy cycles -system.cpu.not_idle_fraction 0.065553 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.934447 # Percentage of idle cycles -system.cpu.Branches 8413035 # Number of branches fetched -system.cpu.op_class::No_OpClass 3197761 5.70% 5.70% # Class of executed instruction -system.cpu.op_class::IntAlu 36186344 64.48% 70.18% # Class of executed instruction -system.cpu.op_class::IntMult 61011 0.11% 70.29% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 70.29% # Class of executed instruction -system.cpu.op_class::FloatAdd 25613 0.05% 70.34% # Class of executed instruction +system.cpu.committedInsts 56102112 # Number of instructions committed +system.cpu.committedOps 56102112 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 51977185 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses +system.cpu.num_func_calls 1481236 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6460933 # number of instructions that are conditional controls +system.cpu.num_int_insts 51977185 # number of integer instructions +system.cpu.num_fp_insts 324460 # number of float instructions +system.cpu.num_int_register_reads 71206533 # number of times the integer registers were read +system.cpu.num_int_register_writes 38459103 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written +system.cpu.num_mem_refs 15454487 # number of memory refs +system.cpu.num_load_insts 9089505 # Number of load instructions +system.cpu.num_store_insts 6364982 # Number of store instructions +system.cpu.num_idle_cycles 3587234430.998131 # Number of idle cycles +system.cpu.num_busy_cycles 251643113.001869 # Number of busy cycles +system.cpu.not_idle_fraction 0.065551 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.934449 # Percentage of idle cycles +system.cpu.Branches 8412678 # Number of branches fetched +system.cpu.op_class::No_OpClass 3197715 5.70% 5.70% # Class of executed instruction +system.cpu.op_class::IntAlu 36172357 64.46% 70.16% # Class of executed instruction +system.cpu.op_class::IntMult 61004 0.11% 70.27% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction +system.cpu.op_class::FloatAdd 38087 0.07% 70.34% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction @@ -519,34 +511,34 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 70.34% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::MemRead 9316905 16.60% 86.95% # Class of executed instruction -system.cpu.op_class::MemWrite 6371245 11.35% 98.30% # Class of executed instruction -system.cpu.op_class::IprAccess 953526 1.70% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 9316582 16.60% 86.95% # Class of executed instruction +system.cpu.op_class::MemWrite 6371054 11.35% 98.30% # Class of executed instruction +system.cpu.op_class::IprAccess 953544 1.70% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 56116041 # Class of executed instruction +system.cpu.op_class::total 56113979 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 212017 # number of hwrei instructions executed +system.cpu.kern.inst.hwrei 212019 # number of hwrei instructions executed system.cpu.kern.ipl_count::0 74895 40.89% 40.89% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1931 1.05% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106210 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183167 # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 106211 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183168 # number of times we switched to this ipl system.cpu.kern.ipl_good::0 73528 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1931 1.29% 50.69% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73528 49.31% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 149118 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1857252195000 96.76% 96.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 91387500 0.00% 96.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 737178000 0.04% 96.80% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 61365063500 3.20% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1919445824000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1857248521000 96.76% 96.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 91287500 0.00% 96.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 737179000 0.04% 96.80% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 61361050500 3.20% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1919438038000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692289 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814110 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692282 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814105 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -582,10 +574,10 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4179 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal::swpctx 4177 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175948 91.21% 93.41% # number of callpals executed +system.cpu.kern.callpal::swpipl 175949 91.22% 93.41% # number of callpals executed system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed @@ -594,21 +586,21 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192895 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5904 # number of protection mode switches -system.cpu.kern.mode_switch::user 1741 # number of protection mode switches +system.cpu.kern.callpal::total 192894 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5902 # number of protection mode switches +system.cpu.kern.mode_switch::user 1742 # number of protection mode switches system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches system.cpu.kern.mode_good::kernel 1912 -system.cpu.kern.mode_good::user 1741 -system.cpu.kern.mode_good::idle 171 -system.cpu.kern.mode_switch_good::kernel 0.323848 # fraction of useful protection mode switches +system.cpu.kern.mode_good::user 1742 +system.cpu.kern.mode_good::idle 170 +system.cpu.kern.mode_switch_good::kernel 0.323958 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392527 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46108525500 2.40% 2.40% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5189217000 0.27% 2.67% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1868148079500 97.33% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4180 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392567 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 46116573000 2.40% 2.40% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5192895500 0.27% 2.67% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1868128567500 97.33% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -640,7 +632,7 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.throughput 1409867 # Throughput (bytes/s) +system.iobus.throughput 1409873 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution system.iobus.trans_dist::WriteReq 51201 # Transaction distribution @@ -700,21 +692,21 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 380199064 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 374407689 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23509000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 43233500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42014000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 927875 # number of replacements -system.cpu.icache.tags.tagsinuse 508.303976 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 55187496 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 928386 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 59.444559 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 927724 # number of replacements +system.cpu.icache.tags.tagsinuse 508.304001 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 55185585 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 928235 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 59.452170 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 39855277250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 508.303976 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 508.304001 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.992781 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.992781 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id @@ -723,44 +715,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 1 system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 57044588 # Number of tag accesses -system.cpu.icache.tags.data_accesses 57044588 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 55187496 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55187496 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55187496 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55187496 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55187496 # number of overall hits -system.cpu.icache.overall_hits::total 55187496 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 928546 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 928546 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 928546 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 928546 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 928546 # number of overall misses -system.cpu.icache.overall_misses::total 928546 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12910342260 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12910342260 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12910342260 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12910342260 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12910342260 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12910342260 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56116042 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56116042 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56116042 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56116042 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 56116042 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56116042 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016547 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016547 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.016547 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.016547 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.016547 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.016547 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13903.826262 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13903.826262 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13903.826262 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13903.826262 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13903.826262 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13903.826262 # average overall miss latency +system.cpu.icache.tags.tag_accesses 57042375 # Number of tag accesses +system.cpu.icache.tags.data_accesses 57042375 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 55185585 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55185585 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55185585 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55185585 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55185585 # number of overall hits +system.cpu.icache.overall_hits::total 55185585 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 928395 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 928395 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 928395 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 928395 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 928395 # number of overall misses +system.cpu.icache.overall_misses::total 928395 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12914246500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12914246500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12914246500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12914246500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12914246500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12914246500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 56113980 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56113980 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 56113980 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 56113980 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 56113980 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 56113980 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016545 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016545 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016545 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016545 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016545 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016545 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13910.293033 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13910.293033 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13910.293033 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13910.293033 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13910.293033 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13910.293033 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # 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average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69040.824085 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73195.238453 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66264.744837 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 66493.876849 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73195.238453 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66264.744837 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 66493.876849 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -906,66 +898,66 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 74176 # number of writebacks -system.cpu.l2cache.writebacks::total 74176 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13293 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 74183 # number of writebacks +system.cpu.l2cache.writebacks::total 74183 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13294 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271960 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 285253 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 285254 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116840 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116840 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 13293 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 388800 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 402093 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 13293 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 388800 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 402093 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 800656260 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14299493254 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15100149514 # 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number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334145500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334145500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895432500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895432500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229578000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229578000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250313 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141564 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116846 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116846 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 13294 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 388806 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 402100 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 13294 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 388806 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 402100 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 806506000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14297020250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15103526250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 130013 # 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number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334146000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895431500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895431500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229577500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229577500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014320 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250330 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141581 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.384060 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.384060 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279571 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173374 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279571 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173374 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60231.419544 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52579.398640 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52935.988452 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56549.489687 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56549.489687 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60231.419544 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53772.468182 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53985.997988 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60231.419544 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53772.468182 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53985.997988 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.384122 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.384122 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014320 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279596 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.173396 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014320 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279596 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.173396 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60666.917406 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52570.305376 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52947.640524 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56538.425526 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56538.425526 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60666.917406 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53762.825468 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53991.084603 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60666.917406 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53762.825468 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53991.084603 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -973,13 +965,13 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1390190 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.978877 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14030691 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1390702 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 10.088927 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1390084 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.978881 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 14030288 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1390596 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.089406 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 107775250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.978877 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.978881 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -987,72 +979,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63076279 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63076279 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7802806 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7802806 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5845593 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5845593 # 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number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15021903 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15021903 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15021903 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15021903 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120520 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120520 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049471 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049471 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085970 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085970 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091433 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091433 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091433 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091433 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27122.777447 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 27122.777447 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35852.292223 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35852.292223 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13255.881157 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13255.881157 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29056.421306 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29056.421306 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 29056.421306 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29056.421306 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63074137 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63074137 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7802568 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7802568 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5845442 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5845442 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183034 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183034 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199227 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199227 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13648010 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13648010 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13648010 # number of overall hits +system.cpu.dcache.overall_hits::total 13648010 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1069193 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1069193 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304207 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304207 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17214 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17214 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1373400 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1373400 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1373400 # number of overall misses +system.cpu.dcache.overall_misses::total 1373400 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 28998201750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 28998201750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10906246382 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10906246382 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228174000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 228174000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39904448132 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39904448132 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39904448132 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39904448132 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8871761 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8871761 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6149649 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6149649 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200248 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200248 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199227 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199227 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15021410 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15021410 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15021410 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15021410 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120516 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120516 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049467 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049467 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085963 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085963 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091429 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091429 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091429 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091429 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27121.578377 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 27121.578377 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35851.398495 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35851.398495 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13255.141164 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13255.141164 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29055.226541 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29055.226541 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 29055.226541 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29055.226541 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1061,54 +1053,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 834591 # number of writebacks -system.cpu.dcache.writebacks::total 834591 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069264 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069264 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304240 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304240 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17216 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17216 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1373504 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1373504 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1373504 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1373504 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26737269496 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26737269496 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10246531614 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10246531614 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 193767750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 193767750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36983801110 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 36983801110 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36983801110 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 36983801110 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424235500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424235500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011220500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011220500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435456000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435456000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120520 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120520 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049471 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049471 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085970 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085970 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091433 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091433 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091433 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091433 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25005.302242 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25005.302242 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33679.107330 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33679.107330 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11255.097003 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11255.097003 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26926.606046 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26926.606046 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26926.606046 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26926.606046 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 834526 # number of writebacks +system.cpu.dcache.writebacks::total 834526 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069193 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1069193 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304207 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304207 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17214 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17214 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1373400 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1373400 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1373400 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1373400 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26734131250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26734131250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10245126618 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10245126618 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 193732000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 193732000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36979257868 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 36979257868 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36979257868 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 36979257868 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424236000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424236000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011219500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011219500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435455500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435455500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120516 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120516 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049467 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049467 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085963 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085963 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091429 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091429 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091429 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091429 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25004.027570 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25004.027570 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33678.142245 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33678.142245 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11254.327873 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11254.327873 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26925.337023 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26925.337023 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26925.337023 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26925.337023 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1116,31 +1108,32 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 105186760 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2022129 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2022112 # Transaction distribution +system.cpu.toL2Bus.throughput 106562255 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2021905 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2021888 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9649 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9649 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 834591 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 834526 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41563 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 345775 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304224 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1857072 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3649346 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5506418 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59425664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142473420 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 201899084 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 201889036 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 11328 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2424633500 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::ReadExReq 304190 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304190 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1856770 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3649068 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5505838 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59416000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142462412 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 201878412 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 201868428 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 2671296 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2424407500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1395400760 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1395179500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2186975140 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2186860632 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |