diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt | 64 |
1 files changed, 32 insertions, 32 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt index 85c0f1360..a1b437e07 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783855 # Nu sim_ticks 2783854535000 # Number of ticks simulated final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1008697 # Simulator instruction rate (inst/s) -host_op_rate 1227927 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 19668230366 # Simulator tick rate (ticks/s) -host_mem_usage 576064 # Number of bytes of host memory used -host_seconds 141.54 # Real time elapsed on the host +host_inst_rate 787133 # Simulator instruction rate (inst/s) +host_op_rate 958208 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15348024787 # Simulator tick rate (ticks/s) +host_mem_usage 576068 # Number of bytes of host memory used +host_seconds 181.38 # Real time elapsed on the host sim_insts 142771651 # Number of instructions simulated sim_ops 173801592 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -119,9 +119,9 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7864 system.cpu.dtb.walker.walkRequestOrigin::total 17892 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 31525949 # DTB read hits +system.cpu.dtb.read_hits 31525950 # DTB read hits system.cpu.dtb.read_misses 8580 # DTB read misses -system.cpu.dtb.write_hits 23124104 # DTB write hits +system.cpu.dtb.write_hits 23124105 # DTB write hits system.cpu.dtb.write_misses 1448 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -132,12 +132,12 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 31534529 # DTB read accesses -system.cpu.dtb.write_accesses 23125552 # DTB write accesses +system.cpu.dtb.read_accesses 31534530 # DTB read accesses +system.cpu.dtb.write_accesses 23125553 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 54650053 # DTB hits +system.cpu.dtb.hits 54650055 # DTB hits system.cpu.dtb.misses 10028 # DTB misses -system.cpu.dtb.accesses 54660081 # DTB accesses +system.cpu.dtb.accesses 54660083 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -220,7 +220,7 @@ system.cpu.num_conditional_control_insts 18730275 # nu system.cpu.num_int_insts 153161279 # number of integer instructions system.cpu.num_fp_insts 11484 # number of float instructions system.cpu.num_int_register_reads 285057575 # number of times the integer registers were read -system.cpu.num_int_register_writes 107178464 # number of times the integer registers were written +system.cpu.num_int_register_writes 107178468 # number of times the integer registers were written system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written system.cpu.num_cc_register_reads 530849543 # number of times the CC registers were read @@ -270,9 +270,9 @@ system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class::total 177218432 # Class of executed instruction system.cpu.dcache.tags.replacements 819392 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 53783870 # Total number of references to valid blocks. +system.cpu.dcache.tags.total_refs 53783872 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 819904 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.597765 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.597768 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy @@ -282,22 +282,22 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 219235080 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 219235080 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 30128800 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 30128800 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 22339791 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 22339791 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 219235088 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 219235088 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 30128801 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 30128801 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 22339792 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 22339792 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 52468591 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 52468591 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 52863656 # number of overall hits -system.cpu.dcache.overall_hits::total 52863656 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 52468593 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 52468593 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 52863658 # number of overall hits +system.cpu.dcache.overall_hits::total 52863658 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 396281 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 396281 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 301663 # number of WriteReq misses @@ -312,20 +312,20 @@ system.cpu.dcache.demand_misses::cpu.data 697944 # n system.cpu.dcache.demand_misses::total 697944 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 814065 # number of overall misses system.cpu.dcache.overall_misses::total 814065 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 30525081 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 30525081 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 22641454 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 22641454 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 30525082 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 30525082 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 22641455 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 22641455 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 53166535 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 53166535 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 53677721 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 53677721 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 53166537 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 53166537 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 53677723 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 53677723 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013323 # miss rate for WriteReq accesses |