diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt | 538 |
1 files changed, 269 insertions, 269 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt index e4317ec15..f7d0d7b39 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.783867 # Number of seconds simulated -sim_ticks 2783867052000 # Number of ticks simulated -final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.783855 # Number of seconds simulated +sim_ticks 2783854535000 # Number of ticks simulated +final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 624684 # Simulator instruction rate (inst/s) -host_op_rate 760453 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12180447765 # Simulator tick rate (ticks/s) -host_mem_usage 563036 # Number of bytes of host memory used -host_seconds 228.55 # Real time elapsed on the host -sim_insts 142772879 # Number of instructions simulated -sim_ops 173803124 # Number of ops (including micro ops) simulated +host_inst_rate 1852974 # Simulator instruction rate (inst/s) +host_op_rate 2255698 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36130480826 # Simulator tick rate (ticks/s) +host_mem_usage 581484 # Number of bytes of host memory used +host_seconds 77.05 # Real time elapsed on the host +sim_insts 142771651 # Number of instructions simulated +sim_ops 173801592 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory @@ -21,36 +21,36 @@ system.physmem.bytes_read::realview.ide 960 # Nu system.physmem.bytes_read::total 11533384 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 1207012 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1207012 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8840896 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 8840960 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8858420 # Number of bytes written to this memory +system.physmem.bytes_written::total 8858484 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 27313 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 161845 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 189182 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 138139 # Number of write requests responded to by this memory +system.physmem.num_writes::writebacks 138140 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142520 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142521 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 433574 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3708811 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 433576 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3708827 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4142936 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 433574 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 433574 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3175761 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4142955 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 433576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 433576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3175798 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3182056 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3175761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3182093 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3175798 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 433574 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3715106 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 433576 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3715122 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7324992 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7325048 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -99,29 +99,29 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 10029 # Table walker walks requested -system.cpu.dtb.walker.walksShort 10029 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walkWaitTime::samples 10029 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 10029 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 10029 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walks 10028 # Table walker walks requested +system.cpu.dtb.walker.walksShort 10028 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walkWaitTime::samples 10028 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 10028 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 10028 # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6354 80.79% 80.79% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::4K 6353 80.79% 80.79% # Table walker page sizes translated system.cpu.dtb.walker.walkPageSizes::1M 1511 19.21% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7865 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 10029 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkPageSizes::total 7864 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 10028 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 10029 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7865 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 10028 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7864 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7865 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 17894 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7864 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 17892 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 31526223 # DTB read hits -system.cpu.dtb.read_misses 8581 # DTB read misses -system.cpu.dtb.write_hits 23124452 # DTB write hits +system.cpu.dtb.read_hits 31525949 # DTB read hits +system.cpu.dtb.read_misses 8580 # DTB read misses +system.cpu.dtb.write_hits 23124104 # DTB write hits system.cpu.dtb.write_misses 1448 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -132,12 +132,12 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 31534804 # DTB read accesses -system.cpu.dtb.write_accesses 23125900 # DTB write accesses +system.cpu.dtb.read_accesses 31534529 # DTB read accesses +system.cpu.dtb.write_accesses 23125552 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 54650675 # DTB hits -system.cpu.dtb.misses 10029 # DTB misses -system.cpu.dtb.accesses 54660704 # DTB accesses +system.cpu.dtb.hits 54650053 # DTB hits +system.cpu.dtb.misses 10028 # DTB misses +system.cpu.dtb.accesses 54660081 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -185,7 +185,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 147039346 # ITB inst hits +system.cpu.itb.inst_hits 147038166 # ITB inst hits system.cpu.itb.inst_misses 4762 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -202,40 +202,40 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 147044108 # ITB inst accesses -system.cpu.itb.hits 147039346 # DTB hits +system.cpu.itb.inst_accesses 147042928 # ITB inst accesses +system.cpu.itb.hits 147038166 # DTB hits system.cpu.itb.misses 4762 # DTB misses -system.cpu.itb.accesses 147044108 # DTB accesses -system.cpu.numCycles 5567737188 # number of cpu cycles simulated +system.cpu.itb.accesses 147042928 # DTB accesses +system.cpu.numCycles 5567712151 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed -system.cpu.committedInsts 142772879 # Number of instructions committed -system.cpu.committedOps 173803124 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 153162683 # Number of integer alu accesses +system.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed +system.cpu.committedInsts 142771651 # Number of instructions committed +system.cpu.committedOps 173801592 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 153161279 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses -system.cpu.num_func_calls 16873899 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18730330 # number of instructions that are conditional controls -system.cpu.num_int_insts 153162683 # number of integer instructions +system.cpu.num_func_calls 16873962 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 18730275 # number of instructions that are conditional controls +system.cpu.num_int_insts 153161279 # number of integer instructions system.cpu.num_fp_insts 11484 # number of float instructions -system.cpu.num_int_register_reads 285059803 # number of times the integer registers were read -system.cpu.num_int_register_writes 107179480 # number of times the integer registers were written +system.cpu.num_int_register_reads 285057575 # number of times the integer registers were read +system.cpu.num_int_register_writes 107178464 # number of times the integer registers were written system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 530854003 # number of times the CC registers were read -system.cpu.num_cc_register_writes 62364299 # number of times the CC registers were written -system.cpu.num_mem_refs 55939276 # number of memory refs -system.cpu.num_load_insts 31855884 # Number of load instructions -system.cpu.num_store_insts 24083392 # Number of store instructions -system.cpu.num_idle_cycles 5389653746.932674 # Number of idle cycles -system.cpu.num_busy_cycles 178083441.067325 # Number of busy cycles +system.cpu.num_cc_register_reads 530849543 # number of times the CC registers were read +system.cpu.num_cc_register_writes 62363904 # number of times the CC registers were written +system.cpu.num_mem_refs 55938616 # number of memory refs +system.cpu.num_load_insts 31855585 # Number of load instructions +system.cpu.num_store_insts 24083031 # Number of store instructions +system.cpu.num_idle_cycles 5389630193.939007 # Number of idle cycles +system.cpu.num_busy_cycles 178081957.060993 # Number of busy cycles system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles system.cpu.idle_fraction 0.968015 # Percentage of idle cycles -system.cpu.Branches 36396981 # Number of branches fetched +system.cpu.Branches 36396978 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 121152838 68.36% 68.36% # Class of executed instruction -system.cpu.op_class::IntMult 116892 0.07% 68.43% # Class of executed instruction +system.cpu.op_class::IntAlu 121152037 68.36% 68.36% # Class of executed instruction +system.cpu.op_class::IntMult 116873 0.07% 68.43% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction @@ -263,16 +263,16 @@ system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction -system.cpu.op_class::MemRead 31855884 17.98% 86.41% # Class of executed instruction -system.cpu.op_class::MemWrite 24083392 13.59% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 31855585 17.98% 86.41% # Class of executed instruction +system.cpu.op_class::MemWrite 24083031 13.59% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 177219912 # Class of executed instruction -system.cpu.dcache.tags.replacements 819402 # number of replacements +system.cpu.op_class::total 177218432 # Class of executed instruction +system.cpu.dcache.tags.replacements 819392 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 53784483 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 819914 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.597713 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 53783870 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 819904 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.597765 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy @@ -282,58 +282,58 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 219237582 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 219237582 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 30129052 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 30129052 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 22340110 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 22340110 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 395080 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 395080 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 457347 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 457347 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460136 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460136 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 52469162 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 52469162 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 52864242 # number of overall hits -system.cpu.dcache.overall_hits::total 52864242 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 396276 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 396276 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 301678 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 301678 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 116120 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 116120 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 8612 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 8612 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 219235080 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 219235080 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 30128800 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 30128800 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 22339791 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 22339791 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 52468591 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 52468591 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 52863656 # number of overall hits +system.cpu.dcache.overall_hits::total 52863656 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 396281 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 396281 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 301663 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 301663 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 116121 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 116121 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 8611 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 8611 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 697954 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 697954 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 814074 # number of overall misses -system.cpu.dcache.overall_misses::total 814074 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 30525328 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 30525328 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 22641788 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 22641788 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 511200 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 511200 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465959 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 465959 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460138 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460138 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 53167116 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 53167116 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 53678316 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 53678316 # number of overall (read+write) accesses +system.cpu.dcache.demand_misses::cpu.data 697944 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 697944 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 814065 # number of overall misses +system.cpu.dcache.overall_misses::total 814065 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 30525081 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 30525081 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 22641454 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 22641454 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 53166535 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 53166535 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 53677721 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 53677721 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227152 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.227152 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018482 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018482 # miss rate for LoadLockedReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013323 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013323 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227160 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.227160 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018481 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018481 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.013128 # miss rate for demand accesses @@ -348,16 +348,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 682040 # number of writebacks -system.cpu.dcache.writebacks::total 682040 # number of writebacks +system.cpu.dcache.writebacks::writebacks 682017 # number of writebacks +system.cpu.dcache.writebacks::total 682017 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1699214 # number of replacements -system.cpu.icache.tags.tagsinuse 511.663681 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 145342721 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1699726 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 85.509500 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 1698998 # number of replacements +system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 145341757 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1699510 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 85.519801 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.663681 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 511.663679 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -366,32 +366,32 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 77 system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 148742185 # Number of tag accesses -system.cpu.icache.tags.data_accesses 148742185 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 145342721 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 145342721 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 145342721 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 145342721 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 145342721 # number of overall hits -system.cpu.icache.overall_hits::total 145342721 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1699732 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1699732 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1699732 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1699732 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1699732 # number of overall misses -system.cpu.icache.overall_misses::total 1699732 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 147042453 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 147042453 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 147042453 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 147042453 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 147042453 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 147042453 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011559 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.011559 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.011559 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.011559 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.011559 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.011559 # miss rate for overall accesses +system.cpu.icache.tags.tag_accesses 148740789 # Number of tag accesses +system.cpu.icache.tags.data_accesses 148740789 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 145341757 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 145341757 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 145341757 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 145341757 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 145341757 # number of overall hits +system.cpu.icache.overall_hits::total 145341757 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1699516 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1699516 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1699516 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1699516 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1699516 # number of overall misses +system.cpu.icache.overall_misses::total 1699516 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 147041273 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 147041273 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 147041273 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 147041273 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 147041273 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 147041273 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011558 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.011558 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.011558 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.011558 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.011558 # miss rate for overall accesses system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -400,20 +400,20 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 1699214 # number of writebacks -system.cpu.icache.writebacks::total 1699214 # number of writebacks +system.cpu.icache.writebacks::writebacks 1698998 # number of writebacks +system.cpu.icache.writebacks::total 1698998 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 109913 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65155.309141 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4525282 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 65155.314985 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4524855 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 175194 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 25.830120 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 25.827682 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 48764.035583 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931998 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004345 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 9168.708883 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 7219.628332 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 48764.050695 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931995 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004344 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 9168.704513 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 7219.623437 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.744080 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy @@ -430,33 +430,33 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10699 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 40582495 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 40582495 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 40578944 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 40578944 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7597 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 11222 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 682040 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 682040 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1667206 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1667206 # number of WritebackClean hits +system.cpu.l2cache.ReadReq_hits::total 11218 # number of ReadReq hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 682017 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 682017 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1666999 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1666999 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 151146 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 151146 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681416 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1681416 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505440 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 505440 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 7601 # number of demand (read+write) hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 151131 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 151131 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681201 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1681201 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505445 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 505445 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 7597 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1681416 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 656586 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2349224 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 7601 # number of overall hits +system.cpu.l2cache.demand_hits::cpu.inst 1681201 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 656576 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2348995 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 7597 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1681416 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 656586 # number of overall hits -system.cpu.l2cache.overall_hits::total 2349224 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1681201 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 656576 # number of overall hits +system.cpu.l2cache.overall_hits::total 2348995 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses @@ -480,56 +480,56 @@ system.cpu.l2cache.overall_misses::cpu.itb.walker 2 system.cpu.l2cache.overall_misses::cpu.inst 18298 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 163344 # number of overall misses system.cpu.l2cache.overall_misses::total 181651 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7608 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7604 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 11231 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 682040 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 682040 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1667206 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1667206 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 11227 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 682017 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 682017 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1666999 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1666999 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 298922 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 298922 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699714 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1699714 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521008 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 521008 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7608 # number of demand (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 298907 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 298907 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699499 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1699499 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521013 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 521013 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7604 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1699714 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 819930 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2530875 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7608 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1699499 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 819920 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2530646 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7604 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1699714 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 819930 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2530875 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000920 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1699499 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 819920 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2530646 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000921 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000801 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000802 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494363 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.494363 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010765 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010765 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.029881 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029881 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000920 # miss rate for demand accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494388 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.494388 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010767 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010767 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.029880 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029880 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000921 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010765 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.199217 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.071774 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000920 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010767 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.199219 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.071780 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000921 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010765 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.199217 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.071774 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010767 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.199219 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.071780 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -538,51 +538,51 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 101949 # number of writebacks -system.cpu.l2cache.writebacks::total 101949 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 101950 # number of writebacks +system.cpu.l2cache.writebacks::total 101950 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5060356 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540713 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39274 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 420 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 420 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5059903 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540486 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39261 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 422 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 422 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 67802 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2288542 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 67800 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2288329 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 682040 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1667206 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 130096 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 682017 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1698998 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 137375 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 298922 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699732 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5084714 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2574734 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699516 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 521013 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116074 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2581970 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7714878 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 215520120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308833 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 36996 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7753470 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217540984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96306721 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 311939813 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 182974 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5319191 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.018482 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.134685 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 73992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 313958557 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 182975 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5318737 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.018478 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.134674 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5220884 98.15% 98.15% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 98307 1.85% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5220455 98.15% 98.15% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 98282 1.85% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5319191 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5318737 # Request fanout histogram system.iobus.trans_dist::ReadReq 30164 # Transaction distribution system.iobus.trans_dist::ReadResp 30164 # Transaction distribution system.iobus.trans_dist::WriteReq 59002 # Transaction distribution @@ -634,14 +634,14 @@ system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321 system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes) system.iocache.tags.replacements 36430 # number of replacements -system.iocache.tags.tagsinuse 0.909961 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.909893 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.909961 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.056873 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.056873 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ide 0.909893 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -686,8 +686,8 @@ system.membus.trans_dist::ReadReq 40087 # Tr system.membus.trans_dist::ReadResp 74202 # Transaction distribution system.membus.trans_dist::WriteReq 27546 # Transaction distribution system.membus.trans_dist::WriteResp 27546 # Transaction distribution -system.membus.trans_dist::WritebackDirty 138139 # Transaction distribution -system.membus.trans_dist::CleanEvict 7977 # Transaction distribution +system.membus.trans_dist::WritebackDirty 138140 # Transaction distribution +system.membus.trans_dist::CleanEvict 8203 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution @@ -701,17 +701,17 @@ system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 506581 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 613941 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109131 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 109131 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 723072 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 723299 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092412 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255385 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092476 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255449 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2331520 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2331520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20586905 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20586969 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 434821 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram |