diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini | 243 |
1 files changed, 189 insertions, 54 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini index 9cd433cc2..2198282f2 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini @@ -37,7 +37,7 @@ load_offset=0 machine_type=RealView_PBX mem_mode=atomic mem_ranges=0:134217727 -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem multi_proc=true num_work_ids=16 panic_on_oops=true @@ -99,7 +99,7 @@ voltage_domain=system.voltage_domain [system.cpu0] type=AtomicSimpleCPU -children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer branchPred=Null checker=Null clk_domain=system.cpu_clk_domain @@ -124,9 +124,6 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 -simpoint_interval=100000000 -simpoint_profile=false -simpoint_profile_file=simpoint.bb.gz simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false @@ -143,14 +140,14 @@ icache_port=system.cpu0.icache.cpu_side type=BaseCache children=tags addr_ranges=0:18446744073709551615 -assoc=4 +assoc=2 clk_domain=system.cpu_clk_domain eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=4 +mshrs=6 prefetch_on_access=false prefetcher=Null response_latency=2 @@ -158,15 +155,15 @@ sequential_access=false size=32768 system=system tags=system.cpu0.dcache.tags -tgts_per_mshr=20 +tgts_per_mshr=8 two_queue=false -write_buffers=8 +write_buffers=16 cpu_side=system.cpu0.dcache_port -mem_side=system.toL2Bus.slave[1] +mem_side=system.cpu0.toL2Bus.slave[1] [system.cpu0.dcache.tags] type=LRU -assoc=4 +assoc=2 block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 @@ -196,7 +193,7 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[5] +port=system.cpu0.toL2Bus.slave[5] [system.cpu0.dtb] type=ArmTLB @@ -213,40 +210,40 @@ eventq_index=0 is_stage2=false num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[3] +port=system.cpu0.toL2Bus.slave[3] [system.cpu0.icache] type=BaseCache children=tags addr_ranges=0:18446744073709551615 -assoc=1 +assoc=2 clk_domain=system.cpu_clk_domain eventq_index=0 forward_snoops=true -hit_latency=2 +hit_latency=1 is_top_level=true max_miss_count=0 -mshrs=4 +mshrs=2 prefetch_on_access=false prefetcher=Null -response_latency=2 +response_latency=1 sequential_access=false size=32768 system=system tags=system.cpu0.icache.tags -tgts_per_mshr=20 +tgts_per_mshr=8 two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port -mem_side=system.toL2Bus.slave[0] +mem_side=system.cpu0.toL2Bus.slave[0] [system.cpu0.icache.tags] type=LRU -assoc=1 +assoc=2 block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 -hit_latency=2 +hit_latency=1 sequential_access=false size=32768 @@ -305,7 +302,7 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[4] +port=system.cpu0.toL2Bus.slave[4] [system.cpu0.itb] type=ArmTLB @@ -322,7 +319,71 @@ eventq_index=0 is_stage2=false num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[2] +port=system.cpu0.toL2Bus.slave[2] + +[system.cpu0.l2cache] +type=BaseCache +children=prefetcher tags +addr_ranges=0:18446744073709551615 +assoc=16 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=12 +is_top_level=false +max_miss_count=0 +mshrs=16 +prefetch_on_access=true +prefetcher=system.cpu0.l2cache.prefetcher +response_latency=12 +sequential_access=false +size=1048576 +system=system +tags=system.cpu0.l2cache.tags +tgts_per_mshr=8 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.toL2Bus.master[0] +mem_side=system.toL2Bus.slave[0] + +[system.cpu0.l2cache.prefetcher] +type=StridePrefetcher +clk_domain=system.cpu_clk_domain +cross_pages=false +data_accesses_only=false +degree=8 +eventq_index=0 +inst_tagged=true +latency=1 +on_miss_only=false +on_prefetch=true +on_read_only=false +serial_squash=false +size=100 +sys=system +use_master_id=true + +[system.cpu0.l2cache.tags] +type=RandomRepl +assoc=16 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=12 +sequential_access=false +size=1048576 + +[system.cpu0.toL2Bus] +type=CoherentXBar +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=32 +master=system.cpu0.l2cache.cpu_side +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port [system.cpu0.tracer] type=ExeTracer @@ -330,7 +391,7 @@ eventq_index=0 [system.cpu1] type=AtomicSimpleCPU -children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer branchPred=Null checker=Null clk_domain=system.cpu_clk_domain @@ -355,9 +416,6 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 -simpoint_interval=100000000 -simpoint_profile=false -simpoint_profile_file=simpoint.bb.gz simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false @@ -374,14 +432,14 @@ icache_port=system.cpu1.icache.cpu_side type=BaseCache children=tags addr_ranges=0:18446744073709551615 -assoc=4 +assoc=2 clk_domain=system.cpu_clk_domain eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=4 +mshrs=6 prefetch_on_access=false prefetcher=Null response_latency=2 @@ -389,15 +447,15 @@ sequential_access=false size=32768 system=system tags=system.cpu1.dcache.tags -tgts_per_mshr=20 +tgts_per_mshr=8 two_queue=false -write_buffers=8 +write_buffers=16 cpu_side=system.cpu1.dcache_port -mem_side=system.toL2Bus.slave[7] +mem_side=system.cpu1.toL2Bus.slave[1] [system.cpu1.dcache.tags] type=LRU -assoc=4 +assoc=2 block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 @@ -427,7 +485,7 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[11] +port=system.cpu1.toL2Bus.slave[5] [system.cpu1.dtb] type=ArmTLB @@ -444,40 +502,40 @@ eventq_index=0 is_stage2=false num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[9] +port=system.cpu1.toL2Bus.slave[3] [system.cpu1.icache] type=BaseCache children=tags addr_ranges=0:18446744073709551615 -assoc=1 +assoc=2 clk_domain=system.cpu_clk_domain eventq_index=0 forward_snoops=true -hit_latency=2 +hit_latency=1 is_top_level=true max_miss_count=0 -mshrs=4 +mshrs=2 prefetch_on_access=false prefetcher=Null -response_latency=2 +response_latency=1 sequential_access=false size=32768 system=system tags=system.cpu1.icache.tags -tgts_per_mshr=20 +tgts_per_mshr=8 two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port -mem_side=system.toL2Bus.slave[6] +mem_side=system.cpu1.toL2Bus.slave[0] [system.cpu1.icache.tags] type=LRU -assoc=1 +assoc=2 block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 -hit_latency=2 +hit_latency=1 sequential_access=false size=32768 @@ -536,7 +594,7 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[10] +port=system.cpu1.toL2Bus.slave[4] [system.cpu1.itb] type=ArmTLB @@ -553,7 +611,71 @@ eventq_index=0 is_stage2=false num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[8] +port=system.cpu1.toL2Bus.slave[2] + +[system.cpu1.l2cache] +type=BaseCache +children=prefetcher tags +addr_ranges=0:18446744073709551615 +assoc=16 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=12 +is_top_level=false +max_miss_count=0 +mshrs=16 +prefetch_on_access=true +prefetcher=system.cpu1.l2cache.prefetcher +response_latency=12 +sequential_access=false +size=1048576 +system=system +tags=system.cpu1.l2cache.tags +tgts_per_mshr=8 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.toL2Bus.master[0] +mem_side=system.toL2Bus.slave[1] + +[system.cpu1.l2cache.prefetcher] +type=StridePrefetcher +clk_domain=system.cpu_clk_domain +cross_pages=false +data_accesses_only=false +degree=8 +eventq_index=0 +inst_tagged=true +latency=1 +on_miss_only=false +on_prefetch=true +on_read_only=false +serial_squash=false +size=100 +sys=system +use_master_id=true + +[system.cpu1.l2cache.tags] +type=RandomRepl +assoc=16 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=12 +sequential_access=false +size=1048576 + +[system.cpu1.toL2Bus] +type=CoherentXBar +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=32 +master=system.cpu1.l2cache.cpu_side +slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port [system.cpu1.tracer] type=ExeTracer @@ -581,13 +703,13 @@ eventq_index=0 sys=system [system.iobus] -type=NoncoherentBus +type=NoncoherentXBar clk_domain=system.clk_domain eventq_index=0 header_cycles=1 use_default_range=false width=8 -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] @@ -612,7 +734,7 @@ tags=system.iocache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 -cpu_side=system.iobus.master[25] +cpu_side=system.iobus.master[26] mem_side=system.membus.slave[2] [system.iocache.tags] @@ -661,11 +783,12 @@ sequential_access=false size=4194304 [system.membus] -type=CoherentBus +type=CoherentXBar children=badaddr_responder clk_domain=system.clk_domain eventq_index=0 header_cycles=1 +snoop_filter=Null system=system use_default_range=false width=8 @@ -706,12 +829,12 @@ port=system.membus.master[6] [system.realview] type=RealView -children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake eventq_index=0 intrctrl=system.intrctrl -max_mem_size=268435456 -mem_start_addr=0 pci_cfg_base=0 +pci_cfg_gen_offsets=false +pci_io_base=0 system=system [system.realview.a9scu] @@ -766,6 +889,7 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +LegacyIOBase=0 MSICAPBaseOffset=0 MSICAPCapId=0 MSICAPMaskBits=0 @@ -850,6 +974,16 @@ pio_latency=100000 system=system pio=system.iobus.master[9] +[system.realview.energy_ctrl] +type=EnergyCtrl +clk_domain=system.clk_domain +dvfs_handler=system.dvfs_handler +eventq_index=0 +pio_addr=268496896 +pio_latency=100000 +system=system +pio=system.iobus.master[25] + [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain @@ -1168,15 +1302,16 @@ output=true port=3456 [system.toL2Bus] -type=CoherentBus +type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 header_cycles=1 +snoop_filter=Null system=system use_default_range=false width=8 master=system.l2c.cpu_side -slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port +slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side [system.vncserver] type=VncServer |