diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt | 1772 |
1 files changed, 886 insertions, 886 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 560fdc0dc..1efe64b0a 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -1,76 +1,76 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.802883 # Number of seconds simulated -sim_ticks 2802882713500 # Number of ticks simulated -final_tick 2802882713500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2802882634000 # Number of ticks simulated +final_tick 2802882634000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1349319 # Simulator instruction rate (inst/s) -host_op_rate 1644123 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25757810314 # Simulator tick rate (ticks/s) -host_mem_usage 564420 # Number of bytes of host memory used -host_seconds 108.82 # Real time elapsed on the host -sim_insts 146828498 # Number of instructions simulated -sim_ops 178908222 # Number of ops (including micro ops) simulated +host_inst_rate 1078207 # Simulator instruction rate (inst/s) +host_op_rate 1313778 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20582448891 # Simulator tick rate (ticks/s) +host_mem_usage 574132 # Number of bytes of host memory used +host_seconds 136.18 # Real time elapsed on the host +sim_insts 146828350 # Number of instructions simulated +sim_ops 178908035 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1116900 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 9456508 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1117092 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 9456444 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 151892 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1081824 # Number of bytes read from this memory -system.physmem.bytes_read::total 11808788 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1116900 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 151892 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1268792 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6072384 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 151956 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1081888 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::total 11809044 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1117092 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 151956 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1269048 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6071744 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8408464 # Number of bytes written to this memory -system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory +system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory +system.physmem.bytes_written::total 8407824 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 25905 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 148283 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 25908 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 148282 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2528 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16927 # Number of read requests responded to by this memory -system.physmem.num_reads::total 193669 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 94881 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2529 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16928 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::total 193673 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 94871 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 135541 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory +system.physmem.num_writes::total 135531 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 398483 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3373851 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 398551 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3373828 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 54191 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 385968 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4213087 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 398483 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 54191 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 452674 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2166478 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 827126 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 54214 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 385991 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4213178 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 398551 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 54214 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 452765 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2166250 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6316 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2999934 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2166478 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 827468 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::realview.ide 827126 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2999706 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2166250 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 398483 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3380167 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 398551 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3380144 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 54191 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 385983 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7213021 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 54214 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 386005 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 827468 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7212884 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -89,356 +89,13 @@ system.realview.nvmem.bw_inst_read::total 24 # I system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 75957 # Transaction distribution -system.membus.trans_dist::ReadResp 75957 # Transaction distribution -system.membus.trans_dist::WriteReq 30905 # Transaction distribution -system.membus.trans_dist::WriteResp 30905 # Transaction distribution -system.membus.trans_dist::Writeback 94881 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 60384 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40930 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15620 # Transaction distribution -system.membus.trans_dist::ReadExReq 196326 # Transaction distribution -system.membus.trans_dist::ReadExResp 152193 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652128 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 773554 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72952 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72952 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 846506 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162808 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17897956 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18087780 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2334464 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2334464 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20422244 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 460689 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 460689 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 460689 # Request fanout histogram -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 107632 # number of replacements -system.l2c.tags.tagsinuse 62143.934871 # Cycle average of tags in use -system.l2c.tags.total_refs 207938 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 168025 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.237542 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48688.027343 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.972782 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030392 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7324.741121 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3758.950125 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.829103 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1656.363289 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 711.020717 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.742920 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.111767 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.057357 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000028 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.025274 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.010849 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.948241 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 60384 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1906 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 12994 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 45387 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000137 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.921387 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 4903910 # Number of tag accesses -system.l2c.tags.data_accesses 4903910 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 69 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 59 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 28044 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 76113 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 38 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 35 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 11456 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 11379 # number of ReadReq hits -system.l2c.ReadReq_hits::total 127193 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 225882 # number of Writeback hits -system.l2c.Writeback_hits::total 225882 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 506 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 65 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 571 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 65 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 6 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 71 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 13825 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 3137 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 16962 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 69 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 59 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 28044 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 89938 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 38 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 35 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 11456 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 14516 # number of demand (read+write) hits -system.l2c.demand_hits::total 144155 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 69 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 59 # number of overall hits -system.l2c.overall_hits::cpu0.inst 28044 # number of overall hits -system.l2c.overall_hits::cpu0.data 89938 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 38 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 35 # number of overall hits -system.l2c.overall_hits::cpu1.inst 11456 # number of overall hits -system.l2c.overall_hits::cpu1.data 14516 # number of overall hits -system.l2c.overall_hits::total 144155 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 7 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 16888 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 11308 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2363 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1122 # number of ReadReq misses -system.l2c.ReadReq_misses::total 31692 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 9982 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3290 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 13272 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 756 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1185 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1941 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 136781 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 15819 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 152600 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 16888 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 148089 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2363 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 16941 # number of demand (read+write) misses -system.l2c.demand_misses::total 184292 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 16888 # number of overall misses -system.l2c.overall_misses::cpu0.data 148089 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2363 # number of overall misses -system.l2c.overall_misses::cpu1.data 16941 # number of overall misses -system.l2c.overall_misses::total 184292 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 76 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 61 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 44932 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 87421 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 40 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 35 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 13819 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 12501 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 158885 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 225882 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 225882 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 10488 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 3355 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 13843 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 821 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1191 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2012 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 150606 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 18956 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 169562 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 76 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 61 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 44932 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 238027 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 40 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 35 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 13819 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 31457 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 328447 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 76 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 61 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 44932 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 238027 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 40 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 35 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 13819 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 31457 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 328447 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.092105 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.032787 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.375857 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.129351 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.050000 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.170996 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.089753 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.199465 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.951754 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.980626 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.958752 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.920828 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.994962 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.964712 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.908204 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.834512 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.899966 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.092105 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.032787 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.375857 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.622152 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.050000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.170996 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.538545 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.561101 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.092105 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.032787 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.375857 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.622152 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.050000 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.170996 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.538545 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.561101 # miss rate for overall accesses -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 94881 # number of writebacks -system.l2c.writebacks::total 94881 # number of writebacks -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 0 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 305223 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 305223 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30905 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30905 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 225882 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 60548 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 41001 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 101549 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 213695 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 213695 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1117774 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 410852 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1528626 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34664498 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10432626 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 45097124 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 36713 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 838812 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.043485 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.203947 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 802336 95.65% 95.65% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36476 4.35% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 838812 # Request fanout histogram -system.iobus.trans_dist::ReadReq 31002 # Transaction distribution -system.iobus.trans_dist::ReadResp 31002 # Transaction distribution -system.iobus.trans_dist::WriteReq 59433 # Transaction distribution -system.iobus.trans_dist::WriteResp 23209 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56624 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107918 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180870 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71568 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162808 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484056 # Cumulative packet size per connected master and slave (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -462,9 +119,9 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 20339791 # DTB read hits +system.cpu0.dtb.read_hits 20339775 # DTB read hits system.cpu0.dtb.read_misses 6871 # DTB read misses -system.cpu0.dtb.write_hits 16391007 # DTB write hits +system.cpu0.dtb.write_hits 16390998 # DTB write hits system.cpu0.dtb.write_misses 1093 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -475,12 +132,12 @@ system.cpu0.dtb.align_faults 0 # Nu system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 20346662 # DTB read accesses -system.cpu0.dtb.write_accesses 16392100 # DTB write accesses +system.cpu0.dtb.read_accesses 20346646 # DTB read accesses +system.cpu0.dtb.write_accesses 16392091 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 36730798 # DTB hits +system.cpu0.dtb.hits 36730773 # DTB hits system.cpu0.dtb.misses 7964 # DTB misses -system.cpu0.dtb.accesses 36738762 # DTB accesses +system.cpu0.dtb.accesses 36738737 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -502,7 +159,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 97439560 # ITB inst hits +system.cpu0.itb.inst_hits 97439484 # ITB inst hits system.cpu0.itb.inst_misses 3358 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -519,38 +176,38 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 97442918 # ITB inst accesses -system.cpu0.itb.hits 97439560 # DTB hits +system.cpu0.itb.inst_accesses 97442842 # ITB inst accesses +system.cpu0.itb.hits 97439484 # DTB hits system.cpu0.itb.misses 3358 # DTB misses -system.cpu0.itb.accesses 97442918 # DTB accesses -system.cpu0.numCycles 5605767393 # number of cpu cycles simulated +system.cpu0.itb.accesses 97442842 # DTB accesses +system.cpu0.numCycles 5605767234 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 95427097 # Number of instructions committed -system.cpu0.committedOps 115560530 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 100762762 # Number of integer alu accesses +system.cpu0.committedInsts 95427026 # Number of instructions committed +system.cpu0.committedOps 115560441 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 100762684 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses -system.cpu0.num_func_calls 8000275 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 13204265 # number of instructions that are conditional controls -system.cpu0.num_int_insts 100762762 # number of integer instructions +system.cpu0.num_func_calls 8000257 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 13204260 # number of instructions that are conditional controls +system.cpu0.num_int_insts 100762684 # number of integer instructions system.cpu0.num_fp_insts 9755 # number of float instructions -system.cpu0.num_int_register_reads 182457576 # number of times the integer registers were read -system.cpu0.num_int_register_writes 69135597 # number of times the integer registers were written +system.cpu0.num_int_register_reads 182457418 # number of times the integer registers were read +system.cpu0.num_int_register_writes 69135520 # number of times the integer registers were written system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 349971872 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 44907557 # number of times the CC registers were written -system.cpu0.num_mem_refs 37873781 # number of memory refs -system.cpu0.num_load_insts 20597370 # Number of load instructions -system.cpu0.num_store_insts 17276411 # Number of store instructions -system.cpu0.num_idle_cycles 5488182740.223901 # Number of idle cycles -system.cpu0.num_busy_cycles 117584652.776099 # Number of busy cycles +system.cpu0.num_cc_register_reads 349971578 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 44907537 # number of times the CC registers were written +system.cpu0.num_mem_refs 37873766 # number of memory refs +system.cpu0.num_load_insts 20597356 # Number of load instructions +system.cpu0.num_store_insts 17276410 # Number of store instructions +system.cpu0.num_idle_cycles 5488182675.223932 # Number of idle cycles +system.cpu0.num_busy_cycles 117584558.776067 # Number of busy cycles system.cpu0.not_idle_fraction 0.020976 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.979024 # Percentage of idle cycles -system.cpu0.Branches 21941666 # Number of branches fetched +system.cpu0.Branches 21941641 # Number of branches fetched system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 78887449 67.49% 67.50% # Class of executed instruction -system.cpu0.op_class::IntMult 110639 0.09% 67.59% # Class of executed instruction +system.cpu0.op_class::IntAlu 78887374 67.49% 67.50% # Class of executed instruction +system.cpu0.op_class::IntMult 110635 0.09% 67.59% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction @@ -578,18 +235,101 @@ system.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction -system.cpu0.op_class::MemRead 20597370 17.62% 85.22% # Class of executed instruction -system.cpu0.op_class::MemWrite 17276411 14.78% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 20597356 17.62% 85.22% # Class of executed instruction +system.cpu0.op_class::MemWrite 17276410 14.78% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 116882229 # Class of executed instruction +system.cpu0.op_class::total 116882135 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 1965 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 693468 # number of replacements +system.cpu0.dcache.tags.tagsinuse 494.853471 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 35932329 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 693980 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 51.777182 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 23661500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853471 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 74113668 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 74113668 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 19108613 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 19108613 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 15690292 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15690292 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346080 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 346080 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379619 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 379619 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363025 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 363025 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 34798905 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 34798905 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 35144985 # number of overall hits +system.cpu0.dcache.overall_hits::total 35144985 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 373094 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 373094 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 295766 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 295766 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100322 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 100322 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6740 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 6740 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18448 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 18448 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 668860 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 668860 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 769182 # number of overall misses +system.cpu0.dcache.overall_misses::total 769182 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481707 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 19481707 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986058 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 15986058 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446402 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 446402 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386359 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 386359 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381473 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381473 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 35467765 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 35467765 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 35914167 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 35914167 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019151 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.019151 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018501 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018501 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224735 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224735 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017445 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017445 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048360 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048360 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018858 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.018858 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021417 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.021417 # miss rate for overall accesses +system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.writebacks::writebacks 511566 # number of writebacks +system.cpu0.dcache.writebacks::total 511566 # number of writebacks +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 1109631 # number of replacements system.cpu0.icache.tags.tagsinuse 511.809991 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 96331750 # Total number of references to valid blocks. +system.cpu0.icache.tags.total_refs 96331674 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 1110143 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 86.774181 # Average number of references to valid blocks. +system.cpu0.icache.tags.avg_refs 86.774113 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809991 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy @@ -599,26 +339,26 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::0 212 system.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 195993956 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 195993956 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 96331750 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 96331750 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 96331750 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 96331750 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 96331750 # number of overall hits -system.cpu0.icache.overall_hits::total 96331750 # number of overall hits +system.cpu0.icache.tags.tag_accesses 195993804 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 195993804 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 96331674 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 96331674 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 96331674 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 96331674 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 96331674 # number of overall hits +system.cpu0.icache.overall_hits::total 96331674 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 1110152 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 1110152 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 1110152 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 1110152 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 1110152 # number of overall misses system.cpu0.icache.overall_misses::total 1110152 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 97441902 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 97441902 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 97441902 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 97441902 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 97441902 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 97441902 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 97441826 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 97441826 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 97441826 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 97441826 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 97441826 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 97441826 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011393 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.011393 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011393 # miss rate for demand accesses @@ -643,123 +383,123 @@ system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 252387 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16137.494570 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 1809761 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 268581 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.738232 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.replacements 252467 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16137.499100 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 1809671 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 268655 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.736041 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 1814550500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 8061.802195 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.197687 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.081095 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4773.849314 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3298.564278 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::writebacks 8061.791544 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.201142 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.081297 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4773.858530 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3298.566587 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_percent::writebacks 0.492053 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000195 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.291373 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.201328 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.201329 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::total 0.984955 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16188 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16181 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5625 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7524 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2662 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.988037 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 39447588 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 39447588 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7603 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3246 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1065220 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 351970 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 1428039 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 511617 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 511617 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 17 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 17 # number of UpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94214 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 94214 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7603 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3246 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1065220 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 446184 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1522253 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7603 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3246 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1065220 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 446184 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1522253 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 205 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 119 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 44932 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 128186 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 173442 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26232 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 26232 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18444 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 18444 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175300 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 175300 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 205 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 119 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 44932 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 303486 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 348742 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 205 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 119 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 44932 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 303486 # number of overall misses -system.cpu0.l2cache.overall_misses::total 348742 # number of overall misses -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7808 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3365 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 268 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5647 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7609 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2581 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000427 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.987610 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 39448657 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 39448657 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7673 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3273 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1065177 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 351940 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 1428063 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 511566 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 511566 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 16 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 16 # number of UpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94243 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 94243 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7673 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3273 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1065177 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 446183 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1522306 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7673 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3273 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1065177 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 446183 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1522306 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 211 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 123 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 44975 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 128216 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 173525 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26236 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 26236 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18448 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 18448 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175271 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 175271 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 211 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 123 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 44975 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 303487 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 348796 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 211 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 123 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 44975 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 303487 # number of overall misses +system.cpu0.l2cache.overall_misses::total 348796 # number of overall misses +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7884 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3396 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1110152 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::cpu0.data 480156 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 1601481 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 511617 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 511617 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26249 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 26249 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18444 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 18444 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 1601588 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 511566 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 511566 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26252 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 26252 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18448 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 18448 # number of SCUpgradeReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269514 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::total 269514 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7808 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3365 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7884 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3396 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.inst 1110152 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.data 749670 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1870995 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7808 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3365 # number of overall (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 1871102 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7884 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3396 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.inst 1110152 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.data 749670 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1870995 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.026255 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.035364 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040474 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.266967 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.108301 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999352 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999352 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.overall_accesses::total 1871102 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.026763 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.036219 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040512 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.267030 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.108346 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999391 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999391 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650430 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650430 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.026255 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.035364 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040474 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404826 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.186394 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.026255 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.035364 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040474 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404826 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.186394 # miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650322 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650322 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.026763 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.036219 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040512 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404827 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.186412 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.026763 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.036219 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040512 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404827 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.186412 # miss rate for overall accesses system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -768,128 +508,45 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 192916 # number of writebacks -system.cpu0.l2cache.writebacks::total 192916 # number of writebacks +system.cpu0.l2cache.writebacks::writebacks 192870 # number of writebacks +system.cpu0.l2cache.writebacks::total 192870 # number of writebacks system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 693468 # number of replacements -system.cpu0.dcache.tags.tagsinuse 494.853462 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 35932354 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 693980 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 51.777218 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 23661500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853462 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 74113718 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 74113718 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 19108629 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 19108629 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 15690304 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15690304 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346080 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 346080 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379619 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 379619 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363029 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 363029 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 34798933 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 34798933 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 35145013 # number of overall hits -system.cpu0.dcache.overall_hits::total 35145013 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 373094 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 373094 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 295763 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 295763 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100322 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 100322 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6740 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 6740 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18444 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 18444 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 668857 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 668857 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 769179 # number of overall misses -system.cpu0.dcache.overall_misses::total 769179 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481723 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 19481723 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986067 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 15986067 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446402 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 446402 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386359 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 386359 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381473 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381473 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 35467790 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 35467790 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 35914192 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 35914192 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019151 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.019151 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018501 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018501 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224735 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224735 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017445 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017445 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048349 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048349 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018858 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.018858 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021417 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.021417 # miss rate for overall accesses -system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 511617 # number of writebacks -system.cpu0.dcache.writebacks::total 511617 # number of writebacks -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.toL2Bus.trans_dist::ReadReq 1651731 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadResp 1651731 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteReq 28400 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteResp 28400 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 511617 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 26249 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18444 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 44693 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 511566 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 26252 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18448 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 44700 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExReq 269514 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExResp 269514 # Transaction distribution system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2238348 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2220321 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2220284 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28796 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 4500293 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 4500256 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71085816 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80913146 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80909882 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57592 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 152082210 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 322119 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 2656456 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.082633 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.275327 # Request fanout histogram +system.cpu0.toL2Bus.pkt_size::total 152078946 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 322137 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 2656435 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.082643 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.275341 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 2436944 91.74% 91.74% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 219512 8.26% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 2436900 91.74% 91.74% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 219535 8.26% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 2656456 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 2656435 # Request fanout histogram system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -913,9 +570,9 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 12173926 # DTB read hits +system.cpu1.dtb.read_hits 12173905 # DTB read hits system.cpu1.dtb.read_misses 2853 # DTB read misses -system.cpu1.dtb.write_hits 7587211 # DTB write hits +system.cpu1.dtb.write_hits 7587201 # DTB write hits system.cpu1.dtb.write_misses 506 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -926,12 +583,12 @@ system.cpu1.dtb.align_faults 0 # Nu system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12176779 # DTB read accesses -system.cpu1.dtb.write_accesses 7587717 # DTB write accesses +system.cpu1.dtb.read_accesses 12176758 # DTB read accesses +system.cpu1.dtb.write_accesses 7587707 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 19761137 # DTB hits +system.cpu1.dtb.hits 19761106 # DTB hits system.cpu1.dtb.misses 3359 # DTB misses -system.cpu1.dtb.accesses 19764496 # DTB accesses +system.cpu1.dtb.accesses 19764465 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -953,7 +610,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 53671662 # ITB inst hits +system.cpu1.itb.inst_hits 53671578 # ITB inst hits system.cpu1.itb.inst_misses 1734 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -970,38 +627,38 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 53673396 # ITB inst accesses -system.cpu1.itb.hits 53671662 # DTB hits +system.cpu1.itb.inst_accesses 53673312 # ITB inst accesses +system.cpu1.itb.hits 53671578 # DTB hits system.cpu1.itb.misses 1734 # DTB misses -system.cpu1.itb.accesses 53673396 # DTB accesses -system.cpu1.numCycles 5605296302 # number of cpu cycles simulated +system.cpu1.itb.accesses 53673312 # DTB accesses +system.cpu1.numCycles 5605296143 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 51401401 # Number of instructions committed -system.cpu1.committedOps 63347692 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 56984315 # Number of integer alu accesses +system.cpu1.committedInsts 51401324 # Number of instructions committed +system.cpu1.committedOps 63347594 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 56984226 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses -system.cpu1.num_func_calls 9170855 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 5967102 # number of instructions that are conditional controls -system.cpu1.num_int_insts 56984315 # number of integer instructions +system.cpu1.num_func_calls 9170833 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 5967095 # number of instructions that are conditional controls +system.cpu1.num_int_insts 56984226 # number of integer instructions system.cpu1.num_fp_insts 1792 # number of float instructions -system.cpu1.num_int_register_reads 110674840 # number of times the integer registers were read -system.cpu1.num_int_register_writes 41298430 # number of times the integer registers were written +system.cpu1.num_int_register_reads 110674651 # number of times the integer registers were read +system.cpu1.num_int_register_writes 41298354 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 196268898 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 18894414 # number of times the CC registers were written -system.cpu1.num_mem_refs 20026390 # number of memory refs -system.cpu1.num_load_insts 12289548 # Number of load instructions -system.cpu1.num_store_insts 7736842 # Number of store instructions -system.cpu1.num_idle_cycles 5539682707.595543 # Number of idle cycles -system.cpu1.num_busy_cycles 65613594.404457 # Number of busy cycles +system.cpu1.num_cc_register_reads 196268580 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 18894392 # number of times the CC registers were written +system.cpu1.num_mem_refs 20026364 # number of memory refs +system.cpu1.num_load_insts 12289528 # Number of load instructions +system.cpu1.num_store_insts 7736836 # Number of store instructions +system.cpu1.num_idle_cycles 5539682653.586912 # Number of idle cycles +system.cpu1.num_busy_cycles 65613489.413088 # Number of busy cycles system.cpu1.not_idle_fraction 0.011706 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.988294 # Percentage of idle cycles -system.cpu1.Branches 15217497 # Number of branches fetched +system.cpu1.Branches 15217468 # Number of branches fetched system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 45401373 69.36% 69.36% # Class of executed instruction -system.cpu1.op_class::IntMult 28395 0.04% 69.40% # Class of executed instruction +system.cpu1.op_class::IntAlu 45401296 69.36% 69.36% # Class of executed instruction +system.cpu1.op_class::IntMult 28394 0.04% 69.40% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction @@ -1029,18 +686,100 @@ system.cpu1.op_class::SimdFloatMisc 3319 0.01% 69.41% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::MemRead 12289548 18.77% 88.18% # Class of executed instruction -system.cpu1.op_class::MemWrite 7736842 11.82% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 12289528 18.77% 88.18% # Class of executed instruction +system.cpu1.op_class::MemWrite 7736836 11.82% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 65459543 # Class of executed instruction +system.cpu1.op_class::total 65459439 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed +system.cpu1.dcache.tags.replacements 191947 # number of replacements +system.cpu1.dcache.tags.tagsinuse 472.736020 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 19503484 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 192301 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 101.421646 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.736020 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923313 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.923313 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 39751950 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 39751950 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 11858675 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 11858675 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 7397476 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 7397476 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50100 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 50100 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72420 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 72420 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 19256151 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 19256151 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 19306251 # number of overall hits +system.cpu1.dcache.overall_hits::total 19306251 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 136639 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 136639 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 92478 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 92478 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30718 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30718 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22559 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 22559 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 229117 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 229117 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 259835 # number of overall misses +system.cpu1.dcache.overall_misses::total 259835 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995314 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 11995314 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489954 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 7489954 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80818 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 80818 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96765 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 96765 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94979 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 94979 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 19485268 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 19485268 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 19566086 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 19566086 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011391 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.011391 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012347 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.012347 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380089 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380089 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237516 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237516 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011758 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.011758 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013280 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.013280 # miss rate for overall accesses +system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.writebacks::writebacks 120692 # number of writebacks +system.cpu1.dcache.writebacks::total 120692 # number of writebacks +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 523402 # number of replacements system.cpu1.icache.tags.tagsinuse 499.711076 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 53148838 # Total number of references to valid blocks. +system.cpu1.icache.tags.total_refs 53148754 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 523914 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 101.445730 # Average number of references to valid blocks. +system.cpu1.icache.tags.avg_refs 101.445569 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit. system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711076 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy @@ -1049,26 +788,26 @@ system.cpu1.icache.tags.occ_task_id_blocks::1024 512 system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 107869418 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 107869418 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 53148838 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 53148838 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 53148838 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 53148838 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 53148838 # number of overall hits -system.cpu1.icache.overall_hits::total 53148838 # number of overall hits +system.cpu1.icache.tags.tag_accesses 107869250 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 107869250 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 53148754 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 53148754 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 53148754 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 53148754 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 53148754 # number of overall hits +system.cpu1.icache.overall_hits::total 53148754 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 523914 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 523914 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 523914 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 523914 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 523914 # number of overall misses system.cpu1.icache.overall_misses::total 523914 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 53672752 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 53672752 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 53672752 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 53672752 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 53672752 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 53672752 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 53672668 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 53672668 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 53672668 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 53672668 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 53672668 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 53672668 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009761 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_miss_rate::total 0.009761 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009761 # miss rate for demand accesses @@ -1093,121 +832,121 @@ system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 48605 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15302.416394 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 716648 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 63433 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 11.297716 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.replacements 48632 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15302.414906 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 716436 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 63462 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 11.289212 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 8289.635884 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 4.959660 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.032491 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3282.997092 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3722.791267 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.505959 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_blocks::writebacks 8289.533576 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 4.964027 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.029845 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3282.932073 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3722.955385 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.505953 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000303 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000124 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.200378 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.227221 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.200374 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.227231 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::total 0.933985 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 25 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14803 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 26 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14804 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 551 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9351 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4901 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001526 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903503 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 15213580 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 15213580 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3243 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1759 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 510095 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 99336 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 614433 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 120654 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 120654 # number of Writeback hits +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 19 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 554 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9309 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4941 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001587 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903564 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 15214590 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 15214590 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3250 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1767 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 510040 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 99338 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 614395 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 120692 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 120692 # number of Writeback hits system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 7 # number of UpgradeReq hits system.cpu1.l2cache.UpgradeReq_hits::total 7 # number of UpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19759 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 19759 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3243 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1759 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 510095 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 119095 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 634192 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3243 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1759 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 510095 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 119095 # number of overall hits -system.cpu1.l2cache.overall_hits::total 634192 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 343 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 267 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 13819 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 73339 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 87768 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28855 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 28855 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22557 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22557 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43856 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 43856 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 343 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 267 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 13819 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 117195 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 131624 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 343 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 267 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 13819 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 117195 # number of overall misses -system.cpu1.l2cache.overall_misses::total 131624 # number of overall misses -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3586 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2026 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19796 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 19796 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3250 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1767 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 510040 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 119134 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 634191 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3250 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1767 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 510040 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 119134 # number of overall hits +system.cpu1.l2cache.overall_hits::total 634191 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 345 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 269 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 13874 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 73337 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 87825 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28856 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 28856 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22559 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 22559 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43819 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 43819 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 345 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 269 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 13874 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 117156 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 131644 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 345 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 269 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 13874 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 117156 # number of overall misses +system.cpu1.l2cache.overall_misses::total 131644 # number of overall misses +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3595 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2036 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 523914 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::cpu1.data 172675 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 702201 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 120654 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 120654 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28862 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 28862 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22557 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 22557 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 702220 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 120692 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 120692 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28863 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 28863 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22559 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 22559 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63615 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::total 63615 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3586 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2026 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3595 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2036 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.inst 523914 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.data 236290 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 765816 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3586 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2026 # number of overall (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 765835 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3595 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2036 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.inst 523914 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.data 236290 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 765816 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.095650 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.131787 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026376 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.424723 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.124990 # miss rate for ReadReq accesses +system.cpu1.l2cache.overall_accesses::total 765835 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.095967 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.132122 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026481 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.424711 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.125068 # miss rate for ReadReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999757 # miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999757 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.689397 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.689397 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.095650 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.131787 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026376 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495980 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.171874 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.095650 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.131787 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026376 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495980 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.171874 # miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.688816 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.688816 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.095967 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.132122 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026481 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495814 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.171896 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.095967 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.132122 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026481 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495814 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.171896 # miss rate for overall accesses system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1216,134 +955,107 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 32966 # number of writebacks -system.cpu1.l2cache.writebacks::total 32966 # number of writebacks +system.cpu1.l2cache.writebacks::writebacks 32939 # number of writebacks +system.cpu1.l2cache.writebacks::total 32939 # number of writebacks system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 191947 # number of replacements -system.cpu1.dcache.tags.tagsinuse 472.736016 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 19503515 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 192301 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 101.421807 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.736016 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923313 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.923313 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 39752012 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 39752012 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 11858696 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 11858696 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 7397487 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 7397487 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50100 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 50100 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72422 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 72422 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 19256183 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 19256183 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 19306283 # number of overall hits -system.cpu1.dcache.overall_hits::total 19306283 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 136639 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 136639 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 92477 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 92477 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30718 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30718 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22557 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 22557 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 229116 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 229116 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 259834 # number of overall misses -system.cpu1.dcache.overall_misses::total 259834 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995335 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 11995335 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489964 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 7489964 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80818 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 80818 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96765 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 96765 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94979 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 94979 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 19485299 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 19485299 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 19566117 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 19566117 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011391 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.011391 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012347 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.012347 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380089 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380089 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237495 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237495 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011758 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.011758 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013280 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.013280 # miss rate for overall accesses -system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.fast_writes 0 # number of fast writes performed -system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 120654 # number of writebacks -system.cpu1.dcache.writebacks::total 120654 # number of writebacks -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.toL2Bus.trans_dist::ReadReq 709339 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadResp 709339 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 120654 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 28862 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22557 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 51419 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 120692 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 28863 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22559 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 51422 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExReq 63615 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExResp 63615 # Transaction distribution system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1048182 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707532 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707576 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12080 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 1774410 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 1774454 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33531204 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22863598 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22866030 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24160 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 56432194 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 499552 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1371519 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.313444 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.463893 # Request fanout histogram +system.cpu1.toL2Bus.pkt_size::total 56434626 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 499621 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1371622 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.313465 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.463902 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 941625 68.66% 68.66% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 429894 31.34% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 941666 68.65% 68.65% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 429956 31.35% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1371519 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 1371622 # Request fanout histogram +system.iobus.trans_dist::ReadReq 31002 # Transaction distribution +system.iobus.trans_dist::ReadResp 31002 # Transaction distribution +system.iobus.trans_dist::WriteReq 59433 # Transaction distribution +system.iobus.trans_dist::WriteResp 23209 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56624 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107918 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180870 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162808 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2484056 # Cumulative packet size per connected master and slave (bytes) system.iocache.tags.replacements 36442 # number of replacements -system.iocache.tags.tagsinuse 14.586085 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.586086 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 246641286009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.586085 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 14.586086 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.911630 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.911630 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -1382,5 +1094,293 @@ system.iocache.avg_blocked_cycles::no_targets nan system.iocache.fast_writes 36224 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.tags.replacements 107659 # number of replacements +system.l2c.tags.tagsinuse 62143.932416 # Cycle average of tags in use +system.l2c.tags.total_refs 208094 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 168104 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.237888 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 48688.063077 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.972782 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030392 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7324.743178 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3758.906335 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.829103 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1656.372339 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 711.015210 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.742921 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.111767 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.057356 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000028 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.025274 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.010849 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.948241 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 60436 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1910 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 13081 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 45354 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000137 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.922180 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 4903872 # Number of tag accesses +system.l2c.tags.data_accesses 4903872 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 74 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 63 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 28084 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 76119 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 40 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 38 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 11510 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 11381 # number of ReadReq hits +system.l2c.ReadReq_hits::total 127309 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 225809 # number of Writeback hits +system.l2c.Writeback_hits::total 225809 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 496 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 63 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 559 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 61 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 9 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 70 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 13793 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 3108 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 16901 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 74 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 63 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 28084 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 89912 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 40 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 38 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 11510 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 14489 # number of demand (read+write) hits +system.l2c.demand_hits::total 144210 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 74 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 63 # number of overall hits +system.l2c.overall_hits::cpu0.inst 28084 # number of overall hits +system.l2c.overall_hits::cpu0.data 89912 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 40 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 38 # number of overall hits +system.l2c.overall_hits::cpu1.inst 11510 # number of overall hits +system.l2c.overall_hits::cpu1.data 14489 # number of overall hits +system.l2c.overall_hits::total 144210 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 7 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 16891 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 11305 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 2364 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1123 # number of ReadReq misses +system.l2c.ReadReq_misses::total 31694 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 10009 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3295 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 13304 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 759 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1183 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1942 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 136769 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 15820 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 152589 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 16891 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 148074 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2364 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 16943 # number of demand (read+write) misses +system.l2c.demand_misses::total 184283 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses +system.l2c.overall_misses::cpu0.inst 16891 # number of overall misses +system.l2c.overall_misses::cpu0.data 148074 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2364 # number of overall misses +system.l2c.overall_misses::cpu1.data 16943 # number of overall misses +system.l2c.overall_misses::total 184283 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.dtb.walker 81 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 65 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 44975 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 87424 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 42 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 38 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 13874 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 12504 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 159003 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 225809 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 225809 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 10505 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 3358 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 13863 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 820 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1192 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2012 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 150562 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 18928 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 169490 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 81 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 65 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 44975 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 237986 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 42 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 38 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 13874 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 31432 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 328493 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 81 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 65 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 44975 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 237986 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 42 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 38 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 13874 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 31432 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 328493 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.086420 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.030769 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.375564 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.129312 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.047619 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.170391 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.089811 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.199330 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.952784 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.981239 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.959677 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.925610 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.992450 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.965209 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.908390 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.835799 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.900283 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.086420 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.030769 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.375564 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.622196 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.047619 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.170391 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.539037 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.560995 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.086420 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.030769 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.375564 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.622196 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.047619 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.170391 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.539037 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.560995 # miss rate for overall accesses +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.writebacks::writebacks 94871 # number of writebacks +system.l2c.writebacks::total 94871 # number of writebacks +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 75959 # Transaction distribution +system.membus.trans_dist::ReadResp 75959 # Transaction distribution +system.membus.trans_dist::WriteReq 30905 # Transaction distribution +system.membus.trans_dist::WriteResp 30905 # Transaction distribution +system.membus.trans_dist::Writeback 94871 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.membus.trans_dist::UpgradeReq 60398 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40937 # Transaction distribution +system.membus.trans_dist::UpgradeResp 15640 # Transaction distribution +system.membus.trans_dist::ReadExReq 196324 # Transaction distribution +system.membus.trans_dist::ReadExResp 152195 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652163 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 773589 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72952 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72952 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 846541 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162808 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17897572 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18087396 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2334464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2334464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20421860 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 460700 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 460700 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 460700 # Request fanout histogram +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 0 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.toL2Bus.trans_dist::ReadReq 305363 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 305363 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30905 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30905 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 225809 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 60563 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 41007 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 101570 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 213619 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 213619 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1117852 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 410871 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1528723 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34663730 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10432818 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 45096548 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 36713 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 838824 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.043485 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.203946 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 802348 95.65% 95.65% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36476 4.35% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 838824 # Request fanout histogram ---------- End Simulation Statistics ---------- |