diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt | 1862 |
1 files changed, 939 insertions, 923 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 999575681..396f5812c 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -1,71 +1,75 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.802883 # Number of seconds simulated -sim_ticks 2802882797500 # Number of ticks simulated -final_tick 2802882797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2802883274000 # Number of ticks simulated +final_tick 2802883274000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 808897 # Simulator instruction rate (inst/s) -host_op_rate 985629 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15441476365 # Simulator tick rate (ticks/s) -host_mem_usage 596572 # Number of bytes of host memory used -host_seconds 181.52 # Real time elapsed on the host -sim_insts 146828219 # Number of instructions simulated -sim_ops 178907974 # Number of ops (including micro ops) simulated +host_inst_rate 646295 # Simulator instruction rate (inst/s) +host_op_rate 787500 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12338508177 # Simulator tick rate (ticks/s) +host_mem_usage 590972 # Number of bytes of host memory used +host_seconds 227.17 # Real time elapsed on the host +sim_insts 146815798 # Number of instructions simulated +sim_ops 178892721 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1109284 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 9411812 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 153876 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1081872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1106276 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 9415076 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 154452 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1081616 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11758444 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1109284 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 153876 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1263160 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8475520 # Number of bytes written to this memory +system.physmem.bytes_read::total 11759020 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1106276 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 154452 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1260728 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8476800 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8493084 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8494364 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 25786 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 147579 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2559 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16924 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 25739 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 147630 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2568 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16920 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 192873 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 132430 # Number of write requests responded to by this memory +system.physmem.num_reads::total 192882 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 132450 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 136821 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 183 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 136841 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 395765 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3357904 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 54899 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 385985 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 394692 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3359068 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 55105 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 385894 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4195125 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 395765 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 54899 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 450665 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3023858 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4195330 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 394692 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 55105 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 449797 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3024314 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6252 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3030125 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3023858 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 183 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3030581 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3024314 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 395765 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3364156 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 54899 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 386000 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 394692 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3365320 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 55105 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 385908 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7225250 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states +system.physmem.bw_total::total 7225911 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -84,9 +88,9 @@ system.realview.nvmem.bw_inst_read::total 24 # I system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -94,7 +98,7 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -124,7 +128,7 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states system.cpu0.dtb.walker.walks 7964 # Table walker walks requested system.cpu0.dtb.walker.walksShort 7964 # Table walker walks initiated with short descriptors system.cpu0.dtb.walker.walkWaitTime::samples 7964 # Table walker wait (enqueue to first request) latency @@ -145,9 +149,9 @@ system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6570 system.cpu0.dtb.walker.walkRequestOrigin::total 14534 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 20339694 # DTB read hits +system.cpu0.dtb.read_hits 20338226 # DTB read hits system.cpu0.dtb.read_misses 6871 # DTB read misses -system.cpu0.dtb.write_hits 16391004 # DTB write hits +system.cpu0.dtb.write_hits 16389726 # DTB write hits system.cpu0.dtb.write_misses 1093 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -158,13 +162,13 @@ system.cpu0.dtb.align_faults 0 # Nu system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 20346565 # DTB read accesses -system.cpu0.dtb.write_accesses 16392097 # DTB write accesses +system.cpu0.dtb.read_accesses 20345097 # DTB read accesses +system.cpu0.dtb.write_accesses 16390819 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 36730698 # DTB hits +system.cpu0.dtb.hits 36727952 # DTB hits system.cpu0.dtb.misses 7964 # DTB misses -system.cpu0.dtb.accesses 36738662 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.accesses 36735916 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -194,7 +198,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states system.cpu0.itb.walker.walks 3358 # Table walker walks requested system.cpu0.itb.walker.walksShort 3358 # Table walker walks initiated with short descriptors system.cpu0.itb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency @@ -213,7 +217,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2342 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2342 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin::total 5700 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 97439155 # ITB inst hits +system.cpu0.itb.inst_hits 97433318 # ITB inst hits system.cpu0.itb.inst_misses 3358 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -230,54 +234,54 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 97442513 # ITB inst accesses -system.cpu0.itb.hits 97439155 # DTB hits +system.cpu0.itb.inst_accesses 97436676 # ITB inst accesses +system.cpu0.itb.hits 97433318 # DTB hits system.cpu0.itb.misses 3358 # DTB misses -system.cpu0.itb.accesses 97442513 # DTB accesses -system.cpu0.numPwrStateTransitions 3932 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 1966 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 1395773493.506104 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 23114974453.612934 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1154 58.70% 58.70% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 806 41.00% 99.69% # Distribution of time spent in the clock gated state +system.cpu0.itb.accesses 97436676 # DTB accesses +system.cpu0.numPwrStateTransitions 3946 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 1973 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 1390823508.162189 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 23082851772.246098 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1157 58.64% 58.64% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 810 41.05% 99.70% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.05% 99.75% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.80% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.20% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 499983242180 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 1966 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 58792109267 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2744090688233 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 5605767562 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 499983361388 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 1973 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 58788492396 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2744094781604 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 5605768522 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1966 # number of quiesce instructions executed -system.cpu0.committedInsts 95426725 # Number of instructions committed -system.cpu0.committedOps 115560170 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 100762477 # Number of integer alu accesses +system.cpu0.kern.inst.quiesce 1973 # number of quiesce instructions executed +system.cpu0.committedInsts 95420875 # Number of instructions committed +system.cpu0.committedOps 115552929 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 100755950 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses -system.cpu0.num_func_calls 8000241 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 13204192 # number of instructions that are conditional controls -system.cpu0.num_int_insts 100762477 # number of integer instructions +system.cpu0.num_func_calls 8000037 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 13203579 # number of instructions that are conditional controls +system.cpu0.num_int_insts 100755950 # number of integer instructions system.cpu0.num_fp_insts 9755 # number of float instructions -system.cpu0.num_int_register_reads 182433257 # number of times the integer registers were read -system.cpu0.num_int_register_writes 69135397 # number of times the integer registers were written +system.cpu0.num_int_register_reads 182421309 # number of times the integer registers were read +system.cpu0.num_int_register_writes 69130439 # number of times the integer registers were written system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 349970686 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 44907357 # number of times the CC registers were written -system.cpu0.num_mem_refs 37873679 # number of memory refs -system.cpu0.num_load_insts 20597264 # Number of load instructions -system.cpu0.num_store_insts 17276415 # Number of store instructions -system.cpu0.num_idle_cycles 5488183302.205065 # Number of idle cycles -system.cpu0.num_busy_cycles 117584259.794936 # Number of busy cycles -system.cpu0.not_idle_fraction 0.020976 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.979024 # Percentage of idle cycles -system.cpu0.Branches 21941548 # Number of branches fetched +system.cpu0.num_cc_register_reads 349948963 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 44904772 # number of times the CC registers were written +system.cpu0.num_mem_refs 37870790 # number of memory refs +system.cpu0.num_load_insts 20595754 # Number of load instructions +system.cpu0.num_store_insts 17275036 # Number of store instructions +system.cpu0.num_idle_cycles 5488191495.802790 # Number of idle cycles +system.cpu0.num_busy_cycles 117577026.197211 # Number of busy cycles +system.cpu0.not_idle_fraction 0.020974 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.979026 # Percentage of idle cycles +system.cpu0.Branches 21940702 # Number of branches fetched system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 78887162 67.49% 67.50% # Class of executed instruction -system.cpu0.op_class::IntMult 110635 0.09% 67.59% # Class of executed instruction +system.cpu0.op_class::IntAlu 78882840 67.49% 67.50% # Class of executed instruction +system.cpu0.op_class::IntMult 110618 0.09% 67.59% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction @@ -305,100 +309,100 @@ system.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction -system.cpu0.op_class::MemRead 20597264 17.62% 85.22% # Class of executed instruction -system.cpu0.op_class::MemWrite 17276415 14.78% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 20595754 17.62% 85.22% # Class of executed instruction +system.cpu0.op_class::MemWrite 17275036 14.78% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 116881836 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 693478 # number of replacements -system.cpu0.dcache.tags.tagsinuse 494.853458 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 35932315 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 693990 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 51.776416 # Average number of references to valid blocks. +system.cpu0.op_class::total 116874608 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 693483 # number of replacements +system.cpu0.dcache.tags.tagsinuse 494.728102 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 35929530 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 693995 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 51.772030 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853458 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.728102 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966266 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.966266 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 74113673 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 74113673 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 19108531 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 19108531 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 15690320 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15690320 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346085 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 346085 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379623 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 379623 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363046 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 363046 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 34798851 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 34798851 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 35144936 # number of overall hits -system.cpu0.dcache.overall_hits::total 35144936 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 373100 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 373100 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 295799 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 295799 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100321 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 100321 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6740 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 6740 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18431 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 18431 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 668899 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 668899 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 769220 # number of overall misses -system.cpu0.dcache.overall_misses::total 769220 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481631 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 19481631 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986119 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 15986119 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446406 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 446406 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386363 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 386363 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381477 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381477 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 35467750 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 35467750 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 35914156 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 35914156 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019151 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.019151 # miss rate for ReadReq accesses +system.cpu0.dcache.tags.tag_accesses 74108220 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 74108220 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 19107088 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 19107088 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 15689092 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15689092 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346042 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 346042 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379604 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 379604 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363038 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 363038 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 34796180 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 34796180 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 35142222 # number of overall hits +system.cpu0.dcache.overall_hits::total 35142222 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 373135 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 373135 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 295767 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 295767 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100322 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 100322 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6741 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 6741 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18421 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 18421 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 668902 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 668902 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 769224 # number of overall misses +system.cpu0.dcache.overall_misses::total 769224 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 19480223 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 19480223 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 15984859 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 15984859 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446364 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 446364 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386345 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 386345 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381459 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381459 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 35465082 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 35465082 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 35911446 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 35911446 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019155 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.019155 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018503 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.018503 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224730 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224730 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017445 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017445 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048315 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048315 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018859 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.018859 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021418 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.021418 # miss rate for overall accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224754 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224754 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017448 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017448 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048291 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048291 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018861 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.018861 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021420 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.021420 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 693478 # number of writebacks -system.cpu0.dcache.writebacks::total 693478 # number of writebacks -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1109639 # number of replacements +system.cpu0.dcache.writebacks::writebacks 693483 # number of writebacks +system.cpu0.dcache.writebacks::total 693483 # number of writebacks +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 1109362 # number of replacements system.cpu0.icache.tags.tagsinuse 511.809991 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 96331337 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1110151 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 86.773184 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.total_refs 96325777 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1109874 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 86.789831 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6345718500 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809991 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy @@ -407,224 +411,225 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::0 212 system.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 195993154 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 195993154 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 96331337 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 96331337 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 96331337 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 96331337 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 96331337 # number of overall hits -system.cpu0.icache.overall_hits::total 96331337 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1110160 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1110160 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1110160 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1110160 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1110160 # number of overall misses -system.cpu0.icache.overall_misses::total 1110160 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 97441497 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 97441497 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 97441497 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 97441497 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 97441497 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 97441497 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011393 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011393 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011393 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011393 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011393 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011393 # miss rate for overall accesses +system.cpu0.icache.tags.tag_accesses 195981203 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 195981203 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 96325777 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 96325777 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 96325777 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 96325777 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 96325777 # number of overall hits +system.cpu0.icache.overall_hits::total 96325777 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1109883 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1109883 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1109883 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1109883 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1109883 # number of overall misses +system.cpu0.icache.overall_misses::total 1109883 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 97435660 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 97435660 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 97435660 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 97435660 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 97435660 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 97435660 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011391 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011391 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011391 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011391 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011391 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011391 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1109639 # number of writebacks -system.cpu0.icache.writebacks::total 1109639 # number of writebacks -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.writebacks::writebacks 1109362 # number of writebacks +system.cpu0.icache.writebacks::total 1109362 # number of writebacks +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 249747 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16131.550435 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 2729892 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 265865 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 10.267963 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 249561 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16130.656320 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 2729360 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 265678 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 10.273188 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 1471234000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 16129.097151 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.376905 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.076379 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.984442 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000145 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_blocks::writebacks 16129.249413 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.326952 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.079954 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.984451 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000081 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.984592 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16110 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_percent::total 0.984537 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16104 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5562 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7431 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2624 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.983276 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 59696130 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 59696130 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10179 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4500 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 14679 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 510228 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 510228 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 1265023 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 1265023 # number of WritebackClean hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94248 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 94248 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1068491 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 1068491 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 352197 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 352197 # number of ReadSharedReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10179 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4500 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1068491 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 446445 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1529615 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10179 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4500 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1068491 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 446445 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1529615 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 212 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 127 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 339 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26279 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 26279 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18431 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 18431 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175272 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 175272 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 41669 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 41669 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 127964 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 127964 # number of ReadSharedReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 212 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 127 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 41669 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 303236 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 345244 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 212 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 127 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 41669 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 303236 # number of overall misses -system.cpu0.l2cache.overall_misses::total 345244 # number of overall misses -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10391 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 154 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 349 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5522 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7440 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2639 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.982910 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 59687833 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 59687833 # Number of data accesses +system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10176 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4489 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 14665 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 510613 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 510613 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 1264371 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 1264371 # number of WritebackClean hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94352 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 94352 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1067857 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 1067857 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 352287 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 352287 # number of ReadSharedReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10176 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4489 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1067857 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 446639 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1529161 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10176 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4489 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1067857 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 446639 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1529161 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 214 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 138 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 352 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26245 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 26245 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18421 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 18421 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175170 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 175170 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 42026 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 42026 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 127911 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 127911 # number of ReadSharedReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 214 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 138 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 42026 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 303081 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 345459 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 214 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 138 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 42026 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 303081 # number of overall misses +system.cpu0.l2cache.overall_misses::total 345459 # number of overall misses +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10390 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4627 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 15018 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 510228 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 510228 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 1265023 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 1265023 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26279 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 26279 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18431 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 18431 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269520 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 269520 # 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number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10390 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4627 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1110160 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 749681 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1874859 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10391 # number of overall (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1109883 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 749720 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 1874620 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10390 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4627 # 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miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.020402 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.027448 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.037534 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404487 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.184144 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.020402 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.027448 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.037534 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404487 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.184144 # miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.649928 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.649928 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.037865 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.037865 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.266371 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.266371 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.020597 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.029825 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.037865 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404259 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.184282 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.020597 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.029825 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.037865 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404259 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.184282 # miss rate for overall accesses system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l2cache.writebacks::writebacks 193031 # number of writebacks -system.cpu0.l2cache.writebacks::total 193031 # number of writebacks -system.cpu0.toL2Bus.snoop_filter.tot_requests 3720034 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1860217 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27866 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 218415 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 215401 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3014 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.writebacks::writebacks 192746 # number of writebacks +system.cpu0.l2cache.writebacks::total 192746 # number of writebacks +system.cpu0.toL2Bus.snoop_filter.tot_requests 3719480 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1859901 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27861 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 218561 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 215432 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3129 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states system.cpu0.toL2Bus.trans_dist::ReadReq 61410 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1651731 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28341 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28341 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 510228 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 1292889 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 26279 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18431 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 44710 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 269520 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 269520 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1110160 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 480161 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3348003 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2402094 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.trans_dist::ReadResp 1651491 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28340 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28340 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 510613 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1292232 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 26245 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18421 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 44666 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 269522 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 269522 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1109883 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 480198 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3347172 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2402087 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28796 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 5791721 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 142103224 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 92552708 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 5790883 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 142067768 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 92555520 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57592 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 234739180 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 623521 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 4318336 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.067052 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.252886 # Request fanout histogram +system.cpu0.toL2Bus.pkt_size::total 234706536 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 623474 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 12368448 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 4317750 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.067119 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.253107 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 4031799 93.36% 93.36% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 283523 6.57% 99.93% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 3014 0.07% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 4031077 93.36% 93.36% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 283544 6.57% 99.93% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 3129 0.07% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 4318336 # Request fanout histogram -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.snoop_fanout::total 4317750 # Request fanout histogram +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -654,15 +659,15 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states system.cpu1.dtb.walker.walks 3359 # Table walker walks requested system.cpu1.dtb.walker.walksShort 3359 # Table walker walks initiated with short descriptors system.cpu1.dtb.walker.walkWaitTime::samples 3359 # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::0 3359 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::total 3359 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walksPending::samples -1804206736 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -1804206736 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -1804206736 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::samples -1804201736 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1804201736 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1804201736 # Table walker pending requests distribution system.cpu1.dtb.walker.walkPageSizes::4K 1919 74.12% 74.12% # Table walker page sizes translated system.cpu1.dtb.walker.walkPageSizes::1M 670 25.88% 100.00% # Table walker page sizes translated system.cpu1.dtb.walker.walkPageSizes::total 2589 # Table walker page sizes translated @@ -675,9 +680,9 @@ system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2589 system.cpu1.dtb.walker.walkRequestOrigin::total 5948 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 12173945 # DTB read hits +system.cpu1.dtb.read_hits 12172373 # DTB read hits system.cpu1.dtb.read_misses 2853 # DTB read misses -system.cpu1.dtb.write_hits 7587221 # DTB write hits +system.cpu1.dtb.write_hits 7586083 # DTB write hits system.cpu1.dtb.write_misses 506 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -688,13 +693,13 @@ system.cpu1.dtb.align_faults 0 # Nu system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12176798 # DTB read accesses -system.cpu1.dtb.write_accesses 7587727 # DTB write accesses +system.cpu1.dtb.read_accesses 12175226 # DTB read accesses +system.cpu1.dtb.write_accesses 7586589 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 19761166 # DTB hits +system.cpu1.dtb.hits 19758456 # DTB hits system.cpu1.dtb.misses 3359 # DTB misses -system.cpu1.dtb.accesses 19764525 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.accesses 19761815 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -724,15 +729,15 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states system.cpu1.itb.walker.walks 1734 # Table walker walks requested system.cpu1.itb.walker.walksShort 1734 # Table walker walks initiated with short descriptors system.cpu1.itb.walker.walkWaitTime::samples 1734 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::0 1734 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::total 1734 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walksPending::samples -1804209236 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1804209236 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1804209236 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::samples -1804204236 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1804204236 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1804204236 # Table walker pending requests distribution system.cpu1.itb.walker.walkPageSizes::4K 935 85.39% 85.39% # Table walker page sizes translated system.cpu1.itb.walker.walkPageSizes::1M 160 14.61% 100.00% # Table walker page sizes translated system.cpu1.itb.walker.walkPageSizes::total 1095 # Table walker page sizes translated @@ -743,7 +748,7 @@ system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1095 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1095 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin::total 2829 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 53671758 # ITB inst hits +system.cpu1.itb.inst_hits 53665127 # ITB inst hits system.cpu1.itb.inst_misses 1734 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -760,55 +765,55 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 53673492 # ITB inst accesses -system.cpu1.itb.hits 53671758 # DTB hits +system.cpu1.itb.inst_accesses 53666861 # ITB inst accesses +system.cpu1.itb.hits 53665127 # DTB hits system.cpu1.itb.misses 1734 # DTB misses -system.cpu1.itb.accesses 53673492 # DTB accesses -system.cpu1.numPwrStateTransitions 5477 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2739 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 1011344723.290617 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 25846310002.973743 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 1957 71.45% 71.45% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 777 28.37% 99.82% # Distribution of time spent in the clock gated state +system.cpu1.itb.accesses 53666861 # DTB accesses +system.cpu1.numPwrStateTransitions 5467 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2734 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 1013195942.406364 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 25944771719.895676 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 1955 71.51% 71.51% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 774 28.31% 99.82% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.89% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.04% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 979984930372 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2739 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 32809600407 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 2770073197093 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 5605296470 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 979984970108 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 2734 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 32805567461 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 2770077706539 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 5605297416 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed -system.cpu1.committedInsts 51401494 # Number of instructions committed -system.cpu1.committedOps 63347804 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 56984416 # Number of integer alu accesses +system.cpu1.kern.inst.quiesce 2734 # number of quiesce instructions executed +system.cpu1.committedInsts 51394923 # Number of instructions committed +system.cpu1.committedOps 63339792 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 56977163 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses -system.cpu1.num_func_calls 9170873 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 5967115 # number of instructions that are conditional controls -system.cpu1.num_int_insts 56984416 # number of integer instructions +system.cpu1.num_func_calls 9170267 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 5966436 # number of instructions that are conditional controls +system.cpu1.num_int_insts 56977163 # number of integer instructions system.cpu1.num_fp_insts 1792 # number of float instructions -system.cpu1.num_int_register_reads 110669758 # number of times the integer registers were read -system.cpu1.num_int_register_writes 41298494 # number of times the integer registers were written +system.cpu1.num_int_register_reads 110656948 # number of times the integer registers were read +system.cpu1.num_int_register_writes 41293408 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 196269240 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 18894452 # number of times the CC registers were written -system.cpu1.num_mem_refs 20026424 # number of memory refs -system.cpu1.num_load_insts 12289568 # Number of load instructions -system.cpu1.num_store_insts 7736856 # Number of store instructions -system.cpu1.num_idle_cycles 5539682760.605002 # Number of idle cycles -system.cpu1.num_busy_cycles 65613709.394997 # Number of busy cycles -system.cpu1.not_idle_fraction 0.011706 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.988294 # Percentage of idle cycles -system.cpu1.Branches 15217528 # Number of branches fetched +system.cpu1.num_cc_register_reads 196244999 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 18891882 # number of times the CC registers were written +system.cpu1.num_mem_refs 20023552 # number of memory refs +system.cpu1.num_load_insts 12287954 # Number of load instructions +system.cpu1.num_store_insts 7735598 # Number of store instructions +system.cpu1.num_idle_cycles 5539691771.902995 # Number of idle cycles +system.cpu1.num_busy_cycles 65605644.097005 # Number of busy cycles +system.cpu1.not_idle_fraction 0.011704 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.988296 # Percentage of idle cycles +system.cpu1.Branches 15216243 # Number of branches fetched system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 45401456 69.36% 69.36% # Class of executed instruction -system.cpu1.op_class::IntMult 28394 0.04% 69.40% # Class of executed instruction +system.cpu1.op_class::IntAlu 45396317 69.36% 69.36% # Class of executed instruction +system.cpu1.op_class::IntMult 28337 0.04% 69.40% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction @@ -832,84 +837,84 @@ system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.40% # Cl system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 3319 0.01% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 3315 0.01% 69.41% # Class of executed instruction system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::MemRead 12289568 18.77% 88.18% # Class of executed instruction -system.cpu1.op_class::MemWrite 7736856 11.82% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 12287954 18.77% 88.18% # Class of executed instruction +system.cpu1.op_class::MemWrite 7735598 11.82% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 65459659 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 191946 # number of replacements -system.cpu1.dcache.tags.tagsinuse 472.736015 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 19503545 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 192300 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 101.422491 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.736015 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923313 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.923313 # Average percentage of cache occupancy +system.cpu1.op_class::total 65451587 # Class of executed instruction +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 191903 # number of replacements +system.cpu1.dcache.tags.tagsinuse 472.757938 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 19500903 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 192257 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 101.431433 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 105851556000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.757938 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923355 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.923355 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 39752069 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 39752069 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 11858716 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 11858716 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 7397520 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 7397520 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50100 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 50100 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72399 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 72399 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 19256236 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 19256236 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 19306336 # number of overall hits -system.cpu1.dcache.overall_hits::total 19306336 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 136638 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 136638 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 92454 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 92454 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30718 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30718 # number of SoftPFReq misses +system.cpu1.dcache.tags.tag_accesses 39746590 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 39746590 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 11857228 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 11857228 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 7396366 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 7396366 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50103 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 50103 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91426 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 91426 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72412 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 72412 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 19253594 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 19253594 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 19303697 # number of overall hits +system.cpu1.dcache.overall_hits::total 19303697 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 136574 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 136574 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 92490 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 92490 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30717 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30717 # number of SoftPFReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22580 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 22580 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 229092 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 229092 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 259810 # number of overall misses -system.cpu1.dcache.overall_misses::total 259810 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995354 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 11995354 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489974 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 7489974 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80818 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 80818 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96765 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 96765 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94979 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 94979 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 19485328 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 19485328 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 19566146 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 19566146 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011391 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.011391 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012344 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.012344 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380089 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380089 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237737 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237737 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22549 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 22549 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 229064 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 229064 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 259781 # number of overall misses +system.cpu1.dcache.overall_misses::total 259781 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 11993802 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 11993802 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 7488856 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 7488856 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80820 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 80820 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96744 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 96744 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94961 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 94961 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 19482658 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 19482658 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 19563478 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 19563478 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011387 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.011387 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012350 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.012350 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380067 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380067 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054970 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054970 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237455 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237455 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013279 # miss rate for overall accesses @@ -920,238 +925,239 @@ system.cpu1.dcache.blocked::no_mshrs 0 # nu system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 191946 # number of writebacks -system.cpu1.dcache.writebacks::total 191946 # number of writebacks -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 523401 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.711077 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 53148935 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 523913 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 101.446108 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711077 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.975998 # Average percentage of cache occupancy +system.cpu1.dcache.writebacks::writebacks 191903 # number of writebacks +system.cpu1.dcache.writebacks::total 191903 # number of writebacks +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 523286 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.709347 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 53142419 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 523798 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 101.455941 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 76931398500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.709347 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975995 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.975995 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 107869609 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 107869609 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 53148935 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 53148935 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 53148935 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 53148935 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 53148935 # number of overall hits -system.cpu1.icache.overall_hits::total 53148935 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 523913 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 523913 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 523913 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 523913 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 523913 # number of overall misses -system.cpu1.icache.overall_misses::total 523913 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 53672848 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 53672848 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 53672848 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 53672848 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 53672848 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 53672848 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009761 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.009761 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009761 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.009761 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009761 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.009761 # miss rate for overall accesses +system.cpu1.icache.tags.tag_accesses 107856232 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 107856232 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 53142419 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 53142419 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 53142419 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 53142419 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 53142419 # number of overall hits +system.cpu1.icache.overall_hits::total 53142419 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 523798 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 523798 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 523798 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 523798 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 523798 # number of overall misses +system.cpu1.icache.overall_misses::total 523798 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 53666217 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 53666217 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 53666217 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 53666217 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 53666217 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 53666217 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009760 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.009760 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009760 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.009760 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009760 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.009760 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 523401 # number of writebacks -system.cpu1.icache.writebacks::total 523401 # number of writebacks -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.writebacks::writebacks 523286 # number of writebacks +system.cpu1.icache.writebacks::total 523286 # number of writebacks +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 47503 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15229.973296 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1184897 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 62526 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 18.950469 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 47270 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15227.212087 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1184400 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 62319 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 19.005440 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 15227.338556 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 0.619660 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.015081 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.929403 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000038 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000123 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.929564 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 18 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15005 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 15223.147061 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.040750 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.024276 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.929147 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000125 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000124 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.929395 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 20 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15029 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 529 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9469 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5007 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001099 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.915833 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 24502168 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 24502168 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3621 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1918 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 5539 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 121092 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 121092 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 583097 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 583097 # number of WritebackClean hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19779 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 19779 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 510372 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 510372 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99144 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 99144 # number of ReadSharedReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3621 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1918 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 510372 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 118923 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 634834 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3621 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1918 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 510372 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 118923 # number of overall hits -system.cpu1.l2cache.overall_hits::total 634834 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 344 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 273 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 617 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28839 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 28839 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22580 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22580 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43836 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 43836 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13541 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 13541 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 73530 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 73530 # number of ReadSharedReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 344 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 273 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 13541 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 117366 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 131524 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 344 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 273 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 13541 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 117366 # number of overall misses -system.cpu1.l2cache.overall_misses::total 131524 # number of overall misses -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3965 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 528 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9407 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5094 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001221 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.917297 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 24496500 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 24496500 # Number of data accesses +system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3624 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1921 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 5545 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 120975 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 120975 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 583053 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 583053 # number of WritebackClean hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19849 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 19849 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 510459 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 510459 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99238 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 99238 # number of ReadSharedReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3624 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1921 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 510459 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 119087 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 635091 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3624 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1921 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 510459 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 119087 # number of overall hits +system.cpu1.l2cache.overall_hits::total 635091 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 336 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 270 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 606 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28875 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 28875 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22549 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 22549 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43766 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 43766 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13339 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 13339 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 73371 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 73371 # number of ReadSharedReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 336 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 270 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 13339 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 117137 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 131082 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 336 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 270 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 13339 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 117137 # number of overall misses +system.cpu1.l2cache.overall_misses::total 131082 # number of overall misses +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3960 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2191 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 6156 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 121092 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 121092 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 583097 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 583097 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28839 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 28839 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22580 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 22580 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 6151 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::writebacks 120975 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::total 120975 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::writebacks 583053 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::total 583053 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28875 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 28875 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22549 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 22549 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63615 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::total 63615 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 523913 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 523913 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 172674 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 172674 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3965 # number of demand (read+write) accesses +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 523798 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::total 523798 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 172609 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 172609 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3960 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2191 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 523913 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 236289 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 766358 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3965 # number of overall (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 523798 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 236224 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 766173 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3960 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2191 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 523913 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 236289 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 766358 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.086759 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.124601 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.100227 # miss rate for ReadReq accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 523798 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 236224 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 766173 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.084848 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.123231 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.098521 # miss rate for ReadReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.689083 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.689083 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.025846 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.025846 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.425831 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.425831 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.086759 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.124601 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.025846 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.496705 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.171622 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.086759 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.124601 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.025846 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.496705 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.171622 # miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.687982 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.687982 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.025466 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.025466 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.425071 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.425071 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.084848 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.123231 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.025466 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495873 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.171087 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.084848 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.123231 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.025466 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495873 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.171087 # miss rate for overall accesses system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l2cache.writebacks::writebacks 32790 # number of writebacks -system.cpu1.l2cache.writebacks::total 32790 # number of writebacks -system.cpu1.toL2Bus.snoop_filter.tot_requests 1533520 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773321 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11158 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 166202 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 164239 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1963 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 12750 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 709337 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 121092 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 594255 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 28839 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22580 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 51419 # Transaction distribution +system.cpu1.l2cache.writebacks::writebacks 32649 # number of writebacks +system.cpu1.l2cache.writebacks::total 32649 # number of writebacks +system.cpu1.toL2Bus.snoop_filter.tot_requests 1533187 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773168 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11161 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 166233 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 164289 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1944 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 12749 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 709156 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2504 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2504 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 120975 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 594214 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 28875 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22549 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 51424 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExReq 63615 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExResp 63615 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 523913 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 172674 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1571581 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 778822 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 523798 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 172609 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1571236 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 778655 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12080 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2369099 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 67028804 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 27426222 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2368587 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 67014084 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 27419302 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24160 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 94492418 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 347973 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1820541 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.108229 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.314122 # Request fanout histogram +system.cpu1.toL2Bus.pkt_size::total 94470778 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 347619 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 2342400 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 1819791 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.108284 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.314158 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 1625468 89.28% 89.28% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 193110 10.61% 99.89% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 1963 0.11% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1624681 89.28% 89.28% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 193166 10.61% 99.89% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 1944 0.11% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1820541 # Request fanout histogram -system.iobus.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.snoop_fanout::total 1819791 # Request fanout histogram +system.iobus.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 30995 # Transaction distribution system.iobus.trans_dist::ReadResp 30995 # Transaction distribution system.iobus.trans_dist::WriteReq 59419 # Transaction distribution @@ -1202,14 +1208,14 @@ system.iobus.pkt_size_system.bridge.master::total 162766 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2484014 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36442 # number of replacements -system.iocache.tags.tagsinuse 14.586085 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.586086 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 246641287009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.586085 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 246641129509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.586086 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.911630 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.911630 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -1217,7 +1223,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328284 # Number of tag accesses system.iocache.tags.data_accesses 328284 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses system.iocache.ReadReq_misses::total 252 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -1250,249 +1256,258 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 107745 # number of replacements -system.l2c.tags.tagsinuse 62386.756535 # Cycle average of tags in use -system.l2c.tags.total_refs 243993 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 168404 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.448855 # Average number of references to valid blocks. +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 107708 # number of replacements +system.l2c.tags.tagsinuse 62491.556145 # Cycle average of tags in use +system.l2c.tags.total_refs 243932 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 168376 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.448734 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48109.911781 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.010811 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030814 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7778.233869 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4058.534945 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1666.123091 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 768.911224 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.734099 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000076 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.118686 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.061928 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.025423 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.011733 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.951946 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 48154.057665 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.929229 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.998273 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7781.790625 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4106.660422 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.967503 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1678.829831 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 764.322598 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.734773 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000060 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.118741 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.062663 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.025617 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.011663 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.953545 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 60653 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 60662 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1824 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 13234 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 45523 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1796 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 13211 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 45580 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.925491 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5181909 # Number of tag accesses -system.l2c.tags.data_accesses 5181909 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 225821 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 225821 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 557 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 103 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 660 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 84 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 42 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 126 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 14022 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 3121 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 17143 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 71 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 67 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 24898 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 76097 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 46 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 38 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 11147 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 11696 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 124060 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 71 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 67 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 24898 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 90119 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 46 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 38 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 11147 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 14817 # number of demand (read+write) hits -system.l2c.demand_hits::total 141203 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 71 # 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miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.025000 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.397944 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.128708 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.024390 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.180148 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.087317 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.202390 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.087500 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.025000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.397944 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.621811 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.024390 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.180148 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.537000 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.566026 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.087500 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.025000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.397944 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.621811 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.024390 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.180148 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.537000 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.566026 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 96240 # number of writebacks -system.l2c.writebacks::total 96240 # number of writebacks -system.membus.snoop_filter.tot_requests 462691 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 248163 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2c.writebacks::writebacks 96260 # number of writebacks +system.l2c.writebacks::total 96260 # number of writebacks +system.membus.snoop_filter.tot_requests 462665 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 248104 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 501 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 43996 # Transaction distribution -system.membus.trans_dist::ReadResp 75748 # Transaction distribution -system.membus.trans_dist::WriteReq 30846 # Transaction distribution -system.membus.trans_dist::WriteResp 30846 # Transaction distribution -system.membus.trans_dist::WritebackDirty 132430 # Transaction distribution -system.membus.trans_dist::CleanEvict 8725 # Transaction distribution -system.membus.trans_dist::UpgradeReq 60386 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40885 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15565 # Transaction distribution -system.membus.trans_dist::ReadExReq 152277 # Transaction distribution -system.membus.trans_dist::ReadExResp 151876 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 31752 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 43995 # Transaction distribution +system.membus.trans_dist::ReadResp 75711 # Transaction distribution +system.membus.trans_dist::WriteReq 30844 # Transaction distribution +system.membus.trans_dist::WriteResp 30844 # Transaction distribution +system.membus.trans_dist::WritebackDirty 132450 # Transaction distribution +system.membus.trans_dist::CleanEvict 8737 # Transaction distribution +system.membus.trans_dist::UpgradeReq 60370 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40840 # Transaction distribution +system.membus.trans_dist::UpgradeResp 15528 # Transaction distribution +system.membus.trans_dist::ReadExReq 152316 # Transaction distribution +system.membus.trans_dist::ReadExResp 151921 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 31716 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 617002 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 738386 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13468 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 616948 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 738326 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109394 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 109394 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 847780 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 847720 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17952136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18141918 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26936 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17953992 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18143762 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2332288 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2332288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20474206 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20476050 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 537521 # Request fanout histogram -system.membus.snoop_fanout::mean 0.010364 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.101276 # Request fanout histogram +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 537492 # Request fanout histogram +system.membus.snoop_fanout::mean 0.010359 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.101252 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 531950 98.96% 98.96% # Request fanout histogram -system.membus.snoop_fanout::1 5571 1.04% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 531924 98.96% 98.96% # Request fanout histogram +system.membus.snoop_fanout::1 5568 1.04% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 537521 # Request fanout histogram -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states +system.membus.snoop_fanout::total 537492 # Request fanout histogram +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1524,65 +1539,66 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 863181 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 444499 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 128781 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 9832 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 9332 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 500 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 44000 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 301660 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30846 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30846 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 225821 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 64447 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 60576 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 41011 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 101587 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 213650 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 213650 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 257660 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1162060 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 423694 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1585754 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34449020 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10413874 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 44862894 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 113289 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1051063 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.300803 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.459644 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 862712 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 444233 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 128693 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 9862 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 9359 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 503 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 43999 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 301604 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30844 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30844 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 225395 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 64670 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 60630 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 40970 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 101600 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 213426 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 213426 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 257605 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1162374 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 422639 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1585013 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34441336 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10376426 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 44817762 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 113249 # Total snoops (count) +system.toL2Bus.snoopTraffic 6177216 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 1050551 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.300796 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.459647 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 735400 69.97% 69.97% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 315163 29.99% 99.95% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 500 0.05% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 735052 69.97% 69.97% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 314996 29.98% 99.95% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 503 0.05% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1051063 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 1050551 # Request fanout histogram ---------- End Simulation Statistics ---------- |