diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual')
4 files changed, 491 insertions, 267 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini index 894acecbc..b5633ad46 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini @@ -14,6 +14,7 @@ children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l atags_addr=256 boot_loader=/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain dtb_filename= @@ -22,9 +23,16 @@ enable_context_switch_stats_dump=false eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false init_param=0 kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 +load_offset=0 machine_type=RealView_PBX mem_mode=atomic mem_ranges=0:134217727 @@ -33,7 +41,9 @@ multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true +phys_addr_range_64=40 readfile=tests/halt.sh +reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -86,13 +96,14 @@ voltage_domain=system.voltage_domain [system.cpu0] type=AtomicSimpleCPU -children=dcache dtb icache interrupts isa itb tracer +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu0.dstage2_mmu dtb=system.cpu0.dtb eventq_index=0 fastmem=false @@ -100,6 +111,7 @@ function_trace=false function_trace_start=0 interrupts=system.cpu0.interrupts isa=system.cpu0.isa +istage2_mmu=system.cpu0.istage2_mmu itb=system.cpu0.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -157,10 +169,35 @@ hit_latency=2 sequential_access=false size=32768 +[system.cpu0.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb +tlb=system.cpu0.dtb + +[system.cpu0.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.dstage2_mmu.stage2_tlb.walker + +[system.cpu0.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[5] + [system.cpu0.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu0.dtb.walker @@ -168,6 +205,7 @@ walker=system.cpu0.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -215,24 +253,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu0.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb +tlb=system.cpu0.itb + +[system.cpu0.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.istage2_mmu.stage2_tlb.walker + +[system.cpu0.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[4] [system.cpu0.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu0.itb.walker @@ -240,6 +314,7 @@ walker=system.cpu0.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] @@ -250,13 +325,14 @@ eventq_index=0 [system.cpu1] type=AtomicSimpleCPU -children=dcache dtb icache interrupts isa itb tracer +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer checker=Null clk_domain=system.cpu_clk_domain cpu_id=1 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu1.dstage2_mmu dtb=system.cpu1.dtb eventq_index=0 fastmem=false @@ -264,6 +340,7 @@ function_trace=false function_trace_start=0 interrupts=system.cpu1.interrupts isa=system.cpu1.isa +istage2_mmu=system.cpu1.istage2_mmu itb=system.cpu1.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -309,7 +386,7 @@ tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.dcache_port -mem_side=system.toL2Bus.slave[5] +mem_side=system.toL2Bus.slave[7] [system.cpu1.dcache.tags] type=LRU @@ -321,10 +398,35 @@ hit_latency=2 sequential_access=false size=32768 +[system.cpu1.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb +tlb=system.cpu1.dtb + +[system.cpu1.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.dstage2_mmu.stage2_tlb.walker + +[system.cpu1.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[11] + [system.cpu1.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu1.dtb.walker @@ -332,9 +434,10 @@ walker=system.cpu1.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[7] +port=system.toL2Bus.slave[9] [system.cpu1.icache] type=BaseCache @@ -359,7 +462,7 @@ tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port -mem_side=system.toL2Bus.slave[4] +mem_side=system.toL2Bus.slave[6] [system.cpu1.icache.tags] type=LRU @@ -379,24 +482,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu1.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb +tlb=system.cpu1.itb + +[system.cpu1.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.istage2_mmu.stage2_tlb.walker + +[system.cpu1.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[10] [system.cpu1.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu1.itb.walker @@ -404,9 +543,10 @@ walker=system.cpu1.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[6] +port=system.toL2Bus.slave[8] [system.cpu1.tracer] type=ExeTracer @@ -1019,7 +1159,7 @@ system=system use_default_range=false width=8 master=system.l2c.cpu_side -slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port [system.vncserver] type=VncServer diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr index 5a43c8b18..9dee17aa2 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr @@ -10,7 +10,4 @@ warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented -warn: instruction 'mcr bpiallis' unimplemented warn: LCD dual screen mode not supported -warn: instruction 'mcr icialluis' unimplemented -warn: instruction 'mcr icialluis' unimplemented diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout index 1e2520995..bf118f1e9 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout @@ -1,12 +1,15 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 17:30:53 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:07:33 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 + 0: system.cpu0.isa: ISA system set to: 0x6a97800 0x6a97800 + 0: system.cpu1.isa: ISA system set to: 0x6a97800 0x6a97800 info: Using bootloader at address 0x80000000 +info: Using kernel entry physical address at 0x8000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 912096763500 because m5_exit instruction encountered +Exiting @ tick 912096767500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index eb8cedaf3..f0bd97b20 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -1,30 +1,30 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.912097 # Number of seconds simulated -sim_ticks 912096763500 # Number of ticks simulated -final_tick 912096763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 912096767500 # Number of ticks simulated +final_tick 912096767500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1859152 # Simulator instruction rate (inst/s) -host_op_rate 2393654 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27516397451 # Simulator tick rate (ticks/s) -host_mem_usage 399324 # Number of bytes of host memory used -host_seconds 33.15 # Real time elapsed on the host -sim_insts 61625970 # Number of instructions simulated -sim_ops 79343340 # Number of ops (including micro ops) simulated +host_inst_rate 1391627 # Simulator instruction rate (inst/s) +host_op_rate 1791703 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20594093924 # Simulator tick rate (ticks/s) +host_mem_usage 421260 # Number of bytes of host memory used +host_seconds 44.29 # Real time elapsed on the host +sim_insts 61634065 # Number of instructions simulated +sim_ops 79353129 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 502180 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6235188 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 502220 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6235196 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 214556 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 3364528 # Number of bytes read from this memory -system.physmem.bytes_read::total 49638500 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 502180 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 214556 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 716736 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.inst 214596 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 3364536 # Number of bytes read from this memory +system.physmem.bytes_read::total 49638596 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 502220 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 214596 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 716816 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4195776 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory @@ -32,12 +32,12 @@ system.physmem.bytes_written::total 7222864 # Nu system.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14065 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 97497 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14075 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 97499 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3434 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 52597 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5082800 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3444 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 52599 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5082824 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 65559 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory @@ -45,29 +45,29 @@ system.physmem.num_writes::total 822331 # Nu system.physmem.bw_read::realview.clcd 43111215 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 70 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 211 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 550578 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 6836104 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 550621 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 6836112 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 211 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 235234 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 3688784 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 54422406 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 550578 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 235234 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 785811 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4600144 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 235278 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 3688793 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 54422511 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 550621 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 235278 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 785899 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4600143 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 18638 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3300185 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 7918967 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4600144 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::writebacks 4600143 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.clcd 43111215 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 70 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 550578 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 6854742 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 550621 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 6854751 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 235234 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6988969 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 62341372 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 235278 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6988978 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 62341477 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -86,24 +86,24 @@ system.realview.nvmem.bw_inst_read::total 75 # I system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 64986577 # Throughput (bytes/s) -system.membus.data_through_bus 59274047 # Total data (bytes) +system.membus.throughput 64986682 # Throughput (bytes/s) +system.membus.data_through_bus 59274143 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks system.l2c.tags.replacements 70658 # number of replacements -system.l2c.tags.tagsinuse 51560.149653 # Cycle average of tags in use +system.l2c.tags.tagsinuse 51560.149479 # Cycle average of tags in use system.l2c.tags.total_refs 1623339 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 135810 # Sample count of references to valid blocks. system.l2c.tags.avg_refs 11.953015 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 39278.694978 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 39278.694836 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000049 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001108 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4358.955639 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2482.445004 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4358.955623 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2482.444990 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.678940 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2126.451282 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3310.922653 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2126.451280 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3310.922652 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.599345 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy @@ -124,8 +124,8 @@ system.l2c.tags.age_task_id_blocks_1024::3 12549 # system.l2c.tags.age_task_id_blocks_1024::4 48575 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.994080 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 16906854 # Number of tag accesses -system.l2c.tags.data_accesses 16906854 # Number of data accesses +system.l2c.tags.tag_accesses 16908094 # Number of tag accesses +system.l2c.tags.data_accesses 16908094 # Number of data accesses system.l2c.ReadReq_hits::cpu0.dtb.walker 3874 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 1919 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.inst 421038 # number of ReadReq hits @@ -172,9 +172,9 @@ system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # system.l2c.ReadReq_misses::cpu1.inst 3347 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.data 5276 # number of ReadReq misses system.l2c.ReadReq_misses::total 22454 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 4932 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4304 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 9236 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 4941 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 4450 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 9391 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu0.data 741 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 490 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 1231 # number of SCUpgradeReq misses @@ -208,9 +208,9 @@ system.l2c.ReadReq_accesses::cpu1.data 174787 # nu system.l2c.ReadReq_accesses::total 1231560 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 567807 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 567807 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 5543 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 4967 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 10510 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 5552 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 5113 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 10665 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu0.data 878 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 521 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 1399 # number of SCUpgradeReq accesses(hits+misses) @@ -243,9 +243,9 @@ system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000562 system.l2c.ReadReq_miss_rate::cpu1.inst 0.007715 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.030185 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.018232 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.889771 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.866519 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.878782 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.889950 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.870331 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.880544 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.843964 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.940499 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 0.879914 # miss rate for SCUpgradeReq accesses @@ -285,33 +285,75 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 154009014 # Throughput (bytes/s) -system.toL2Bus.data_through_bus 140471123 # Total data (bytes) +system.toL2Bus.throughput 154019994 # Throughput (bytes/s) +system.toL2Bus.data_through_bus 140481139 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.iobus.throughput 45730949 # Throughput (bytes/s) system.iobus.data_through_bus 41711051 # Total data (bytes) +system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7975768 # DTB read hits +system.cpu0.dtb.read_hits 7977216 # DTB read hits system.cpu0.dtb.read_misses 3611 # DTB read misses -system.cpu0.dtb.write_hits 5966574 # DTB write hits +system.cpu0.dtb.write_hits 5966960 # DTB write hits system.cpu0.dtb.write_misses 672 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1905 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 135 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7979379 # DTB read accesses -system.cpu0.dtb.write_accesses 5967246 # DTB write accesses +system.cpu0.dtb.read_accesses 7980827 # DTB read accesses +system.cpu0.dtb.write_accesses 5967632 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 13942342 # DTB hits +system.cpu0.dtb.hits 13944176 # DTB hits system.cpu0.dtb.misses 4283 # DTB misses -system.cpu0.dtb.accesses 13946625 # DTB accesses -system.cpu0.itb.inst_hits 30238804 # ITB inst hits +system.cpu0.dtb.accesses 13948459 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.inst_hits 30245736 # ITB inst hits system.cpu0.itb.inst_misses 2175 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -321,80 +363,80 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1499 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1280 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 30240979 # ITB inst accesses -system.cpu0.itb.hits 30238804 # DTB hits +system.cpu0.itb.inst_accesses 30247911 # ITB inst accesses +system.cpu0.itb.hits 30245736 # DTB hits system.cpu0.itb.misses 2175 # DTB misses -system.cpu0.itb.accesses 30240979 # DTB accesses -system.cpu0.numCycles 1823671407 # number of cpu cycles simulated +system.cpu0.itb.accesses 30247911 # DTB accesses +system.cpu0.numCycles 1823671415 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29750005 # Number of instructions committed -system.cpu0.committedOps 39129633 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 34471201 # Number of integer alu accesses +system.cpu0.committedInsts 29756754 # Number of instructions committed +system.cpu0.committedOps 39137733 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 34752271 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 5449 # Number of float alu accesses -system.cpu0.num_func_calls 1241903 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4044057 # number of instructions that are conditional controls -system.cpu0.num_int_insts 34471201 # number of integer instructions +system.cpu0.num_func_calls 1242676 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4045310 # number of instructions that are conditional controls +system.cpu0.num_int_insts 34752271 # number of integer instructions system.cpu0.num_fp_insts 5449 # number of float instructions -system.cpu0.num_int_register_reads 175121947 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36551788 # number of times the integer registers were written +system.cpu0.num_int_register_reads 179899233 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36833612 # number of times the integer registers were written system.cpu0.num_fp_register_reads 4535 # number of times the floating registers were read system.cpu0.num_fp_register_writes 916 # number of times the floating registers were written -system.cpu0.num_mem_refs 14626951 # number of memory refs -system.cpu0.num_load_insts 8357226 # Number of load instructions -system.cpu0.num_store_insts 6269725 # Number of store instructions -system.cpu0.num_idle_cycles 1784006336.868180 # Number of idle cycles -system.cpu0.num_busy_cycles 39665070.131821 # Number of busy cycles -system.cpu0.not_idle_fraction 0.021750 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.978250 # Percentage of idle cycles +system.cpu0.num_mem_refs 14629077 # number of memory refs +system.cpu0.num_load_insts 8358676 # Number of load instructions +system.cpu0.num_store_insts 6270401 # Number of store instructions +system.cpu0.num_idle_cycles 1783997907.577739 # Number of idle cycles +system.cpu0.num_busy_cycles 39673507.422261 # Number of busy cycles +system.cpu0.not_idle_fraction 0.021755 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.978245 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 49966 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 50449 # number of quiesce instructions executed system.cpu0.icache.tags.replacements 428546 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.015216 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 29811115 # Total number of references to valid blocks. +system.cpu0.icache.tags.tagsinuse 511.015213 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 29818047 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 429058 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 69.480385 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 64537139000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.015216 # Average occupied blocks per requestor +system.cpu0.icache.tags.avg_refs 69.496541 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 64537144000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.015213 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998077 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.998077 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 508 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 30669233 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 30669233 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 29811115 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29811115 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29811115 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29811115 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29811115 # number of overall hits -system.cpu0.icache.overall_hits::total 29811115 # number of overall hits +system.cpu0.icache.tags.tag_accesses 30676165 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 30676165 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 29818047 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 29818047 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29818047 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 29818047 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29818047 # number of overall hits +system.cpu0.icache.overall_hits::total 29818047 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 429059 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 429059 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 429059 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 429059 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 429059 # number of overall misses system.cpu0.icache.overall_misses::total 429059 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 30240174 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 30240174 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 30240174 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 30240174 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 30240174 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 30240174 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014188 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014188 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014188 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014188 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014188 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014188 # miss rate for overall accesses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 30247106 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 30247106 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 30247106 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 30247106 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 30247106 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 30247106 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014185 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014185 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014185 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014185 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014185 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014185 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -405,67 +447,67 @@ system.cpu0.icache.fast_writes 0 # nu system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.tags.replacements 323609 # number of replacements -system.cpu0.dcache.tags.tagsinuse 494.763091 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 12467604 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 494.763093 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 12469292 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 323981 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 38.482516 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 22115000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.763091 # Average occupied blocks per requestor +system.cpu0.dcache.tags.avg_refs 38.487726 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 22120000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.763093 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966334 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.966334 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 372 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 372 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.726562 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51675155 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51675155 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6512305 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6512305 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5630881 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5630881 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 151619 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 151619 # number of LoadLockedReq hits +system.cpu0.dcache.tags.tag_accesses 51682637 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 51682637 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6513463 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6513463 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5631258 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5631258 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 151763 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 151763 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.data 153180 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 153180 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12143186 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12143186 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12143186 # number of overall hits -system.cpu0.dcache.overall_hits::total 12143186 # number of overall hits +system.cpu0.dcache.demand_hits::cpu0.data 12144721 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12144721 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12144721 # number of overall hits +system.cpu0.dcache.overall_hits::total 12144721 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 197167 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 197167 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 167342 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 167342 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9062 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9062 # number of LoadLockedReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 167351 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 167351 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9208 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9208 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7466 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 7466 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 364509 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 364509 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 364509 # number of overall misses -system.cpu0.dcache.overall_misses::total 364509 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6709472 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6709472 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5798223 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5798223 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 160681 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 160681 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 364518 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 364518 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 364518 # number of overall misses +system.cpu0.dcache.overall_misses::total 364518 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6710630 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6710630 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5798609 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5798609 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 160971 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 160971 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 160646 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 160646 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12507695 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12507695 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12507695 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12507695 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029386 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.029386 # miss rate for ReadReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 12509239 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12509239 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12509239 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12509239 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029381 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.029381 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.028861 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.028861 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056397 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056397 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.057203 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.057203 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.046475 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.046475 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029143 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.029143 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029143 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.029143 # miss rate for overall accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029140 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.029140 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029140 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029140 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -477,28 +519,70 @@ system.cpu0.dcache.cache_copies 0 # nu system.cpu0.dcache.writebacks::writebacks 300958 # number of writebacks system.cpu0.dcache.writebacks::total 300958 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7364781 # DTB read hits +system.cpu1.dtb.read_hits 7365100 # DTB read hits system.cpu1.dtb.read_misses 3705 # DTB read misses -system.cpu1.dtb.write_hits 5489656 # DTB write hits +system.cpu1.dtb.write_hits 5489754 # DTB write hits system.cpu1.dtb.write_misses 1595 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1788 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1696 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 145 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7368486 # DTB read accesses -system.cpu1.dtb.write_accesses 5491251 # DTB write accesses +system.cpu1.dtb.read_accesses 7368805 # DTB read accesses +system.cpu1.dtb.write_accesses 5491349 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 12854437 # DTB hits +system.cpu1.dtb.hits 12854854 # DTB hits system.cpu1.dtb.misses 5300 # DTB misses -system.cpu1.dtb.accesses 12859737 # DTB accesses -system.cpu1.itb.inst_hits 32412306 # ITB inst hits +system.cpu1.dtb.accesses 12860154 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.inst_hits 32413691 # ITB inst hits system.cpu1.itb.inst_misses 2200 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -508,48 +592,48 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1327 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1176 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 32414506 # ITB inst accesses -system.cpu1.itb.hits 32412306 # DTB hits +system.cpu1.itb.inst_accesses 32415891 # ITB inst accesses +system.cpu1.itb.hits 32413691 # DTB hits system.cpu1.itb.misses 2200 # DTB misses -system.cpu1.itb.accesses 32414506 # DTB accesses -system.cpu1.numCycles 1824193528 # number of cpu cycles simulated +system.cpu1.itb.accesses 32415891 # DTB accesses +system.cpu1.numCycles 1824193536 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 31875965 # Number of instructions committed -system.cpu1.committedOps 40213707 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 35797832 # Number of integer alu accesses +system.cpu1.committedInsts 31877311 # Number of instructions committed +system.cpu1.committedOps 40215396 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 35862250 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 4436 # Number of float alu accesses -system.cpu1.num_func_calls 955227 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 4048022 # number of instructions that are conditional controls -system.cpu1.num_int_insts 35797832 # number of integer instructions +system.cpu1.num_func_calls 955425 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 4048275 # number of instructions that are conditional controls +system.cpu1.num_int_insts 35862250 # number of integer instructions system.cpu1.num_fp_insts 4436 # number of float instructions -system.cpu1.num_int_register_reads 181634271 # number of times the integer registers were read -system.cpu1.num_int_register_writes 39007898 # number of times the integer registers were written +system.cpu1.num_int_register_reads 183631460 # number of times the integer registers were read +system.cpu1.num_int_register_writes 39072446 # number of times the integer registers were written system.cpu1.num_fp_register_reads 3022 # number of times the floating registers were read system.cpu1.num_fp_register_writes 1416 # number of times the floating registers were written -system.cpu1.num_mem_refs 13370713 # number of memory refs -system.cpu1.num_load_insts 7642673 # Number of load instructions -system.cpu1.num_store_insts 5728040 # Number of store instructions -system.cpu1.num_idle_cycles 1783401357.733683 # Number of idle cycles -system.cpu1.num_busy_cycles 40792170.266317 # Number of busy cycles -system.cpu1.not_idle_fraction 0.022362 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.977638 # Percentage of idle cycles +system.cpu1.num_mem_refs 13371151 # number of memory refs +system.cpu1.num_load_insts 7642991 # Number of load instructions +system.cpu1.num_store_insts 5728160 # Number of store instructions +system.cpu1.num_idle_cycles 1783399616.755682 # Number of idle cycles +system.cpu1.num_busy_cycles 40793919.244318 # Number of busy cycles +system.cpu1.not_idle_fraction 0.022363 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.977637 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 40379 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 40450 # number of quiesce instructions executed system.cpu1.icache.tags.replacements 433942 # number of replacements -system.cpu1.icache.tags.tagsinuse 475.447912 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 31979125 # Total number of references to valid blocks. +system.cpu1.icache.tags.tagsinuse 475.447911 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 31980510 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 434454 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 73.607620 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 69967763000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 475.447912 # Average occupied blocks per requestor +system.cpu1.icache.tags.avg_refs 73.610808 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 69967761000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 475.447911 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.928609 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.928609 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -558,26 +642,26 @@ system.cpu1.icache.tags.age_task_id_blocks_1024::1 63 system.cpu1.icache.tags.age_task_id_blocks_1024::2 261 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 32848033 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 32848033 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 31979125 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 31979125 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 31979125 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 31979125 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 31979125 # number of overall hits -system.cpu1.icache.overall_hits::total 31979125 # number of overall hits +system.cpu1.icache.tags.tag_accesses 32849418 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 32849418 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 31980510 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 31980510 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 31980510 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 31980510 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 31980510 # number of overall hits +system.cpu1.icache.overall_hits::total 31980510 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 434454 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 434454 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 434454 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 434454 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 434454 # number of overall misses system.cpu1.icache.overall_misses::total 434454 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 32413579 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 32413579 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 32413579 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 32413579 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 32413579 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 32413579 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 32414964 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 32414964 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 32414964 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 32414964 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 32414964 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 32414964 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013403 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_miss_rate::total 0.013403 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013403 # miss rate for demand accesses @@ -595,10 +679,10 @@ system.cpu1.icache.cache_copies 0 # nu system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.tags.replacements 294289 # number of replacements system.cpu1.dcache.tags.tagsinuse 447.573682 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 11707745 # Total number of references to valid blocks. +system.cpu1.dcache.tags.total_refs 11708150 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 294801 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 39.714061 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 67293493000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.avg_refs 39.715435 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 67293491000 # Cycle when the warmup percentage was hit. system.cpu1.dcache.tags.occ_blocks::cpu1.data 447.573682 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.874167 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.874167 # Average percentage of cache occupancy @@ -608,56 +692,56 @@ system.cpu1.dcache.tags.age_task_id_blocks_1024::1 226 system.cpu1.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 48417680 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 48417680 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 7002209 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 7002209 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4520313 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4520313 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 77954 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 77954 # number of LoadLockedReq hits +system.cpu1.dcache.tags.tag_accesses 48419345 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 48419345 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 7002503 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 7002503 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4520265 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4520265 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 77967 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 77967 # number of LoadLockedReq hits system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79030 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 79030 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 11522522 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 11522522 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 11522522 # number of overall hits -system.cpu1.dcache.overall_hits::total 11522522 # number of overall hits +system.cpu1.dcache.demand_hits::cpu1.data 11522768 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 11522768 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 11522768 # number of overall hits +system.cpu1.dcache.overall_hits::total 11522768 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 198275 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 198275 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 125920 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 125920 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11251 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 11251 # number of LoadLockedReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 126066 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 126066 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11260 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 11260 # number of LoadLockedReq misses system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10133 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 10133 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 324195 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 324195 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 324195 # number of overall misses -system.cpu1.dcache.overall_misses::total 324195 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 7200484 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 7200484 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 4646233 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4646233 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 89205 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 89205 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.demand_misses::cpu1.data 324341 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 324341 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 324341 # number of overall misses +system.cpu1.dcache.overall_misses::total 324341 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 7200778 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 7200778 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4646331 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4646331 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 89227 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 89227 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 89163 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 89163 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 11846717 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 11846717 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 11846717 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 11846717 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027536 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.027536 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027102 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.027102 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.126125 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.126125 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.demand_accesses::cpu1.data 11847109 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 11847109 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 11847109 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 11847109 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027535 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.027535 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027132 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.027132 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.126195 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.126195 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.113646 # miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113646 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027366 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.027366 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027366 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.027366 # miss rate for overall accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027377 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.027377 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027377 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.027377 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked |