diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual')
3 files changed, 831 insertions, 830 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini index e4e3f0a2b..aaf42338c 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini @@ -37,13 +37,13 @@ load_offset=2147483648 machine_type=VExpress_EMM mem_mode=atomic mem_ranges=2147483648:2415919103 -memories=system.realview.nvmem system.physmem system.realview.vram +memories=system.physmem system.realview.vram system.realview.nvmem multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5.latest/tests/halt.sh +readfile=/work/gem5.ext/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout index c57bb127b..62e4f1a91 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout @@ -1,14 +1,14 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 29 2014 15:46:15 -gem5 started Oct 29 2014 15:58:03 +gem5 compiled Oct 31 2014 10:01:44 +gem5 started Oct 31 2014 11:25:21 gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 - 0: system.cpu0.isa: ISA system set to: 0x530db00 0x530db00 - 0: system.cpu1.isa: ISA system set to: 0x530db00 0x530db00 + 0: system.cpu0.isa: ISA system set to: 0x53ff680 0x53ff680 + 0: system.cpu1.isa: ISA system set to: 0x53ff680 0x53ff680 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80008000 info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000 @@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2802882496500 because m5_exit instruction encountered +Exiting @ tick 2802882713500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 53a29a0e7..560fdc0dc 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -1,312 +1,313 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.802882 # Number of seconds simulated -sim_ticks 2802882496500 # Number of ticks simulated -final_tick 2802882496500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.802883 # Number of seconds simulated +sim_ticks 2802882713500 # Number of ticks simulated +final_tick 2802882713500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1330236 # Simulator instruction rate (inst/s) -host_op_rate 1620871 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25395755903 # Simulator tick rate (ticks/s) -host_mem_usage 564312 # Number of bytes of host memory used -host_seconds 110.37 # Real time elapsed on the host -sim_insts 146815698 # Number of instructions simulated -sim_ops 178892459 # Number of ops (including micro ops) simulated +host_inst_rate 1349319 # Simulator instruction rate (inst/s) +host_op_rate 1644123 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25757810314 # Simulator tick rate (ticks/s) +host_mem_usage 564420 # Number of bytes of host memory used +host_seconds 108.82 # Real time elapsed on the host +sim_insts 146828498 # Number of instructions simulated +sim_ops 178908222 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.realview.nvmem.bytes_read::cpu0.inst 24 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 52 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 76 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 24 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 52 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 76 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 6 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 19 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 9 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 19 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 27 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 9 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 19 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 19 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1117476 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 9458684 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1116900 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 9456508 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 149780 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1082912 # Number of bytes read from this memory -system.physmem.bytes_read::total 11810580 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1117476 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 149780 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1267256 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6081216 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 151892 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1081824 # Number of bytes read from this memory +system.physmem.bytes_read::total 11808788 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1116900 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 151892 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1268792 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6072384 # Number of bytes written to this memory system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8417296 # Number of bytes written to this memory +system.physmem.bytes_written::total 8408464 # Number of bytes written to this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 25914 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 148317 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 25905 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 148283 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2495 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16944 # Number of read requests responded to by this memory -system.physmem.num_reads::total 193697 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 95019 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2528 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16927 # Number of read requests responded to by this memory +system.physmem.num_reads::total 193669 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 94881 # Number of write requests responded to by this memory system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 135679 # Number of write requests responded to by this memory +system.physmem.num_writes::total 135541 # Number of write requests responded to by this memory system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 183 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 398688 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3374627 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 398483 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3373851 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 53438 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 386357 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4213726 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 398688 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 53438 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 452126 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2169629 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 54191 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 385968 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4213087 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 398483 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 54191 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 452674 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2166478 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::realview.ide 827126 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6316 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3003086 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2169629 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2999934 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2166478 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 827468 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 183 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 398688 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3380944 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 398483 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3380167 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 53438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 386371 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7216812 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 75963 # Transaction distribution -system.membus.trans_dist::ReadResp 75963 # Transaction distribution -system.membus.trans_dist::WriteReq 30903 # Transaction distribution -system.membus.trans_dist::WriteResp 30903 # Transaction distribution -system.membus.trans_dist::Writeback 95019 # Transaction distribution +system.physmem.bw_total::cpu1.inst 54191 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 385983 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7213021 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 75957 # Transaction distribution +system.membus.trans_dist::ReadResp 75957 # Transaction distribution +system.membus.trans_dist::WriteReq 30905 # Transaction distribution +system.membus.trans_dist::WriteResp 30905 # Transaction distribution +system.membus.trans_dist::Writeback 94881 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 60332 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40886 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15607 # Transaction distribution -system.membus.trans_dist::ReadExReq 196321 # Transaction distribution -system.membus.trans_dist::ReadExResp 152216 # Transaction distribution +system.membus.trans_dist::UpgradeReq 60384 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40930 # Transaction distribution +system.membus.trans_dist::UpgradeResp 15620 # Transaction distribution +system.membus.trans_dist::ReadExReq 196326 # Transaction distribution +system.membus.trans_dist::ReadExResp 152193 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13468 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652185 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 773609 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652128 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 773554 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72952 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72952 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 846561 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 846506 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162808 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 76 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26936 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17908580 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18098400 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17897956 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18087780 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2334464 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2334464 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20432864 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20422244 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 460731 # Request fanout histogram +system.membus.snoop_fanout::samples 460689 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 460731 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 460689 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 460731 # Request fanout histogram +system.membus.snoop_fanout::total 460689 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 107723 # number of replacements -system.l2c.tags.tagsinuse 62123.921751 # Cycle average of tags in use -system.l2c.tags.total_refs 208051 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 168144 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.237338 # Average number of references to valid blocks. +system.l2c.tags.replacements 107632 # number of replacements +system.l2c.tags.tagsinuse 62143.934871 # Cycle average of tags in use +system.l2c.tags.total_refs 207938 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 168025 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.237542 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48622.171138 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.975943 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 48688.027343 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.972782 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030392 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7348.709599 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3778.182164 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.823425 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1628.255131 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 741.773959 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.741915 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 7324.741121 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3758.950125 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.829103 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1656.363289 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 711.020717 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.742920 # 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miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.540241 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.561073 # miss rate for overall accesses +system.l2c.overall_misses::cpu1.inst 2363 # number of overall misses +system.l2c.overall_misses::cpu1.data 16941 # number of overall misses +system.l2c.overall_misses::total 184292 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.dtb.walker 76 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 61 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 44932 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 87421 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 40 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 35 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 13819 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 12501 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 158885 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 225882 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 225882 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 10488 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 3355 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 13843 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 821 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1191 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2012 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 150606 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 18956 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 169562 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 76 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 61 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 44932 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 238027 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 40 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 35 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 13819 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 31457 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 328447 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 76 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 61 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 44932 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 238027 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 40 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 35 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 13819 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 31457 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 328447 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.092105 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.032787 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.375857 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.129351 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.050000 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.170996 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.089753 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.199465 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.951754 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.980626 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.958752 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.920828 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.994962 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.964712 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.908204 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.834512 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.899966 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.092105 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.032787 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.375857 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.622152 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.050000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.170996 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.538545 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.561101 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.092105 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.032787 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.375857 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.622152 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.050000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.170996 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.538545 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.561101 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -315,8 +316,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 95019 # number of writebacks -system.l2c.writebacks::total 95019 # number of writebacks +system.l2c.writebacks::writebacks 94881 # number of writebacks +system.l2c.writebacks::total 94881 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -355,34 +356,34 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 305028 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 305028 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30903 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30903 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 225966 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 60515 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 40953 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 101468 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 213769 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 213769 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1117772 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 410530 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1528302 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34667382 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10427306 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 45094688 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.trans_dist::ReadReq 305223 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 305223 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30905 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30905 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 225882 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 60548 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 41001 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 101549 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 213695 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 213695 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1117774 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 410852 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1528626 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34664498 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10432626 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 45097124 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 36713 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 838693 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.043491 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.203961 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 838812 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.043485 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.203947 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 802217 95.65% 95.65% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 802336 95.65% 95.65% # Request fanout histogram system.toL2Bus.snoop_fanout::2 36476 4.35% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 838693 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 838812 # Request fanout histogram system.iobus.trans_dist::ReadReq 31002 # Transaction distribution system.iobus.trans_dist::ReadResp 31002 # Transaction distribution system.iobus.trans_dist::WriteReq 59433 # Transaction distribution @@ -461,9 +462,9 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 20338466 # DTB read hits +system.cpu0.dtb.read_hits 20339791 # DTB read hits system.cpu0.dtb.read_misses 6871 # DTB read misses -system.cpu0.dtb.write_hits 16389914 # DTB write hits +system.cpu0.dtb.write_hits 16391007 # DTB write hits system.cpu0.dtb.write_misses 1093 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -474,12 +475,12 @@ system.cpu0.dtb.align_faults 0 # Nu system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 20345337 # DTB read accesses -system.cpu0.dtb.write_accesses 16391007 # DTB write accesses +system.cpu0.dtb.read_accesses 20346662 # DTB read accesses +system.cpu0.dtb.write_accesses 16392100 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 36728380 # DTB hits +system.cpu0.dtb.hits 36730798 # DTB hits system.cpu0.dtb.misses 7964 # DTB misses -system.cpu0.dtb.accesses 36736344 # DTB accesses +system.cpu0.dtb.accesses 36738762 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -501,7 +502,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 97433991 # ITB inst hits +system.cpu0.itb.inst_hits 97439560 # ITB inst hits system.cpu0.itb.inst_misses 3358 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -518,38 +519,38 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 97437349 # ITB inst accesses -system.cpu0.itb.hits 97433991 # DTB hits +system.cpu0.itb.inst_accesses 97442918 # ITB inst accesses +system.cpu0.itb.hits 97439560 # DTB hits system.cpu0.itb.misses 3358 # DTB misses -system.cpu0.itb.accesses 97437349 # DTB accesses -system.cpu0.numCycles 5605766965 # number of cpu cycles simulated +system.cpu0.itb.accesses 97442918 # DTB accesses +system.cpu0.numCycles 5605767393 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 95421538 # Number of instructions committed -system.cpu0.committedOps 115553717 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 100756647 # Number of integer alu accesses +system.cpu0.committedInsts 95427097 # Number of instructions committed +system.cpu0.committedOps 115560530 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 100762762 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses -system.cpu0.num_func_calls 7999979 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 13203645 # number of instructions that are conditional controls -system.cpu0.num_int_insts 100756647 # number of integer instructions +system.cpu0.num_func_calls 8000275 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 13204265 # number of instructions that are conditional controls +system.cpu0.num_int_insts 100762762 # number of integer instructions system.cpu0.num_fp_insts 9755 # number of float instructions -system.cpu0.num_int_register_reads 182446507 # number of times the integer registers were read -system.cpu0.num_int_register_writes 69131058 # number of times the integer registers were written +system.cpu0.num_int_register_reads 182457576 # number of times the integer registers were read +system.cpu0.num_int_register_writes 69135597 # number of times the integer registers were written system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 349951369 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 44905035 # number of times the CC registers were written -system.cpu0.num_mem_refs 37871263 # number of memory refs -system.cpu0.num_load_insts 20596038 # Number of load instructions -system.cpu0.num_store_insts 17275225 # Number of store instructions -system.cpu0.num_idle_cycles 5488189135.402444 # Number of idle cycles -system.cpu0.num_busy_cycles 117577829.597556 # Number of busy cycles -system.cpu0.not_idle_fraction 0.020974 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.979026 # Percentage of idle cycles -system.cpu0.Branches 21940727 # Number of branches fetched +system.cpu0.num_cc_register_reads 349971872 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 44907557 # number of times the CC registers were written +system.cpu0.num_mem_refs 37873781 # number of memory refs +system.cpu0.num_load_insts 20597370 # Number of load instructions +system.cpu0.num_store_insts 17276411 # Number of store instructions +system.cpu0.num_idle_cycles 5488182740.223901 # Number of idle cycles +system.cpu0.num_busy_cycles 117584652.776099 # Number of busy cycles +system.cpu0.not_idle_fraction 0.020976 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.979024 # Percentage of idle cycles +system.cpu0.Branches 21941666 # Number of branches fetched system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 78883166 67.49% 67.50% # Class of executed instruction -system.cpu0.op_class::IntMult 110618 0.09% 67.59% # Class of executed instruction +system.cpu0.op_class::IntAlu 78887449 67.49% 67.50% # Class of executed instruction +system.cpu0.op_class::IntMult 110639 0.09% 67.59% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction @@ -577,19 +578,19 @@ system.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction -system.cpu0.op_class::MemRead 20596038 17.62% 85.22% # Class of executed instruction -system.cpu0.op_class::MemWrite 17275225 14.78% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 20597370 17.62% 85.22% # Class of executed instruction +system.cpu0.op_class::MemWrite 17276411 14.78% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 116875407 # Class of executed instruction +system.cpu0.op_class::total 116882229 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1971 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 1109428 # number of replacements +system.cpu0.kern.inst.quiesce 1965 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 1109631 # number of replacements system.cpu0.icache.tags.tagsinuse 511.809991 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 96326384 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1109940 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 86.785217 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6345717500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.total_refs 96331750 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1110143 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 86.774181 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809991 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy @@ -598,32 +599,32 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::0 212 system.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 195982615 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 195982615 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 96326384 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 96326384 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 96326384 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 96326384 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 96326384 # number of overall hits -system.cpu0.icache.overall_hits::total 96326384 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1109949 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1109949 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1109949 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1109949 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1109949 # number of overall misses -system.cpu0.icache.overall_misses::total 1109949 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 97436333 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 97436333 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 97436333 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 97436333 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 97436333 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 97436333 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011392 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011392 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011392 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011392 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011392 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011392 # miss rate for overall accesses +system.cpu0.icache.tags.tag_accesses 195993956 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 195993956 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 96331750 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 96331750 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 96331750 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 96331750 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 96331750 # number of overall hits +system.cpu0.icache.overall_hits::total 96331750 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1110152 # 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miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011393 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011393 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011393 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011393 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011393 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -642,123 +643,123 @@ system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # 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Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.496271 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000086 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000006 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.285539 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.203261 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.985162 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16181 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # 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number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 511617 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 511617 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26249 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 26249 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18444 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 18444 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269514 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 269514 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7808 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3365 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1110152 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 749670 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 1870995 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7808 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3365 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1110152 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 749670 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 1870995 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.026255 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.035364 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040474 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.266967 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.108301 # miss rate for ReadReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999352 # miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999352 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650901 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650901 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.027936 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.040359 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040501 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404779 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.186434 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.027936 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.040359 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040501 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404779 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.186434 # miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650430 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650430 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.026255 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.035364 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040474 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404826 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.186394 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.026255 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.035364 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040474 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404826 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.186394 # miss rate for overall accesses system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -767,81 +768,81 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 192932 # number of writebacks -system.cpu0.l2cache.writebacks::total 192932 # number of writebacks +system.cpu0.l2cache.writebacks::writebacks 192916 # number of writebacks +system.cpu0.l2cache.writebacks::total 192916 # number of writebacks system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 693475 # number of replacements -system.cpu0.dcache.tags.tagsinuse 494.745909 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 35929913 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 693987 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 51.773179 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 23662000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.745909 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966301 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.966301 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 693468 # number of replacements +system.cpu0.dcache.tags.tagsinuse 494.853462 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 35932354 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 693980 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 51.777218 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 23661500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853462 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 74108905 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 74108905 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 19107323 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 19107323 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 15689235 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15689235 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346054 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 346054 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379605 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 379605 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363036 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 363036 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 34796558 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 34796558 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 35142612 # number of overall hits -system.cpu0.dcache.overall_hits::total 35142612 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 373110 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 373110 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 295751 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 295751 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100324 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 100324 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6742 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 6742 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18426 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 18426 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 668861 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 668861 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 769185 # number of overall misses -system.cpu0.dcache.overall_misses::total 769185 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 19480433 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 19480433 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 15984986 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 15984986 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446378 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 446378 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386347 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 386347 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381462 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381462 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 35465419 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 35465419 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 35911797 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 35911797 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019153 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.019153 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018502 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018502 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224751 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224751 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017451 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017451 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048304 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048304 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018860 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.018860 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021419 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.021419 # miss rate for overall accesses +system.cpu0.dcache.tags.tag_accesses 74113718 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 74113718 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 19108629 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 19108629 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 15690304 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15690304 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346080 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 346080 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379619 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 379619 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363029 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 363029 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 34798933 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 34798933 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 35145013 # number of overall hits +system.cpu0.dcache.overall_hits::total 35145013 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 373094 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 373094 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 295763 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 295763 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100322 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 100322 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6740 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 6740 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18444 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 18444 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 668857 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 668857 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 769179 # number of overall misses +system.cpu0.dcache.overall_misses::total 769179 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481723 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 19481723 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986067 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 15986067 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446402 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 446402 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386359 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 386359 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381473 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381473 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 35467790 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 35467790 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 35914192 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 35914192 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019151 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.019151 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018501 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018501 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224735 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224735 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017445 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017445 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048349 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048349 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018858 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.018858 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021417 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.021417 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -850,45 +851,45 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 511188 # number of writebacks -system.cpu0.dcache.writebacks::total 511188 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 511617 # number of writebacks +system.cpu0.dcache.writebacks::total 511617 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 1651550 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1651550 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28399 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28399 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 511188 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 26234 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18426 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 44660 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 269517 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 269517 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2237944 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2219872 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.trans_dist::ReadReq 1651731 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1651731 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28400 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28400 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 511617 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 26249 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18444 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 44693 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 269514 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 269514 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2238348 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2220321 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28796 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 4499440 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71072828 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80887162 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 4500293 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71085816 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80913146 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57592 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 152043238 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 321922 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 2655621 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.082587 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.275257 # Request fanout histogram +system.cpu0.toL2Bus.pkt_size::total 152082210 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 322119 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 2656456 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.082633 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.275327 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 2436302 91.74% 91.74% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 219319 8.26% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 2436944 91.74% 91.74% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 219512 8.26% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 2655621 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 2656456 # Request fanout histogram system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -912,9 +913,9 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 12172110 # DTB read hits +system.cpu1.dtb.read_hits 12173926 # DTB read hits system.cpu1.dtb.read_misses 2853 # DTB read misses -system.cpu1.dtb.write_hits 7585805 # DTB write hits +system.cpu1.dtb.write_hits 7587211 # DTB write hits system.cpu1.dtb.write_misses 506 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -925,12 +926,12 @@ system.cpu1.dtb.align_faults 0 # Nu system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12174963 # DTB read accesses -system.cpu1.dtb.write_accesses 7586311 # DTB write accesses +system.cpu1.dtb.read_accesses 12176779 # DTB read accesses +system.cpu1.dtb.write_accesses 7587717 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 19757915 # DTB hits +system.cpu1.dtb.hits 19761137 # DTB hits system.cpu1.dtb.misses 3359 # DTB misses -system.cpu1.dtb.accesses 19761274 # DTB accesses +system.cpu1.dtb.accesses 19764496 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -952,7 +953,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 53664371 # ITB inst hits +system.cpu1.itb.inst_hits 53671662 # ITB inst hits system.cpu1.itb.inst_misses 1734 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -969,38 +970,38 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 53666105 # ITB inst accesses -system.cpu1.itb.hits 53664371 # DTB hits +system.cpu1.itb.inst_accesses 53673396 # ITB inst accesses +system.cpu1.itb.hits 53671662 # DTB hits system.cpu1.itb.misses 1734 # DTB misses -system.cpu1.itb.accesses 53666105 # DTB accesses -system.cpu1.numCycles 5605295863 # number of cpu cycles simulated +system.cpu1.itb.accesses 53673396 # DTB accesses +system.cpu1.numCycles 5605296302 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 51394160 # Number of instructions committed -system.cpu1.committedOps 63338742 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 56976202 # Number of integer alu accesses +system.cpu1.committedInsts 51401401 # Number of instructions committed +system.cpu1.committedOps 63347692 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 56984315 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses -system.cpu1.num_func_calls 9170283 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 5966381 # number of instructions that are conditional controls -system.cpu1.num_int_insts 56976202 # number of integer instructions +system.cpu1.num_func_calls 9170855 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 5967102 # number of instructions that are conditional controls +system.cpu1.num_int_insts 56984315 # number of integer instructions system.cpu1.num_fp_insts 1792 # number of float instructions -system.cpu1.num_int_register_reads 110660301 # number of times the integer registers were read -system.cpu1.num_int_register_writes 41292600 # number of times the integer registers were written +system.cpu1.num_int_register_reads 110674840 # number of times the integer registers were read +system.cpu1.num_int_register_writes 41298430 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 196241872 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 18891627 # number of times the CC registers were written -system.cpu1.num_mem_refs 20022980 # number of memory refs -system.cpu1.num_load_insts 12287666 # Number of load instructions -system.cpu1.num_store_insts 7735314 # Number of store instructions -system.cpu1.num_idle_cycles 5539691262.121797 # Number of idle cycles -system.cpu1.num_busy_cycles 65604600.878203 # Number of busy cycles -system.cpu1.not_idle_fraction 0.011704 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.988296 # Percentage of idle cycles -system.cpu1.Branches 15216192 # Number of branches fetched +system.cpu1.num_cc_register_reads 196268898 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 18894414 # number of times the CC registers were written +system.cpu1.num_mem_refs 20026390 # number of memory refs +system.cpu1.num_load_insts 12289548 # Number of load instructions +system.cpu1.num_store_insts 7736842 # Number of store instructions +system.cpu1.num_idle_cycles 5539682707.595543 # Number of idle cycles +system.cpu1.num_busy_cycles 65613594.404457 # Number of busy cycles +system.cpu1.not_idle_fraction 0.011706 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.988294 # Percentage of idle cycles +system.cpu1.Branches 15217497 # Number of branches fetched system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 45395839 69.36% 69.36% # Class of executed instruction -system.cpu1.op_class::IntMult 28345 0.04% 69.40% # Class of executed instruction +system.cpu1.op_class::IntAlu 45401373 69.36% 69.36% # Class of executed instruction +system.cpu1.op_class::IntMult 28395 0.04% 69.40% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction @@ -1024,56 +1025,56 @@ system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.40% # Cl system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 3315 0.01% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 3319 0.01% 69.41% # Class of executed instruction system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::MemRead 12287666 18.77% 88.18% # Class of executed instruction -system.cpu1.op_class::MemWrite 7735314 11.82% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 12289548 18.77% 88.18% # Class of executed instruction +system.cpu1.op_class::MemWrite 7736842 11.82% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 65450545 # Class of executed instruction +system.cpu1.op_class::total 65459543 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2734 # number of quiesce instructions executed -system.cpu1.icache.tags.replacements 523179 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.711075 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 53141770 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 523691 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 101.475431 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 76931405000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711075 # Average occupied blocks per requestor +system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed +system.cpu1.icache.tags.replacements 523402 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.711076 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 53148838 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 523914 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 101.445730 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711076 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.975998 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 107854613 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 107854613 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 53141770 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 53141770 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 53141770 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 53141770 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 53141770 # number of overall hits -system.cpu1.icache.overall_hits::total 53141770 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 523691 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 523691 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 523691 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 523691 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 523691 # number of overall misses -system.cpu1.icache.overall_misses::total 523691 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 53665461 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 53665461 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 53665461 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 53665461 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 53665461 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 53665461 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009758 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.009758 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009758 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.009758 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009758 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.009758 # miss rate for overall accesses +system.cpu1.icache.tags.tag_accesses 107869418 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 107869418 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 53148838 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 53148838 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 53148838 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 53148838 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 53148838 # number of overall hits +system.cpu1.icache.overall_hits::total 53148838 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 523914 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 523914 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 523914 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 523914 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 523914 # number of overall misses +system.cpu1.icache.overall_misses::total 523914 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 53672752 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 53672752 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 53672752 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 53672752 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 53672752 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 53672752 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009761 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.009761 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009761 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.009761 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009761 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.009761 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1092,121 +1093,121 @@ system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 48552 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15311.760536 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 716558 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 63379 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 11.305922 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.replacements 48605 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15302.416394 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 716648 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 63433 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 11.297716 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 8243.045220 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.958358 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.015688 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3303.816337 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3759.924934 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.503116 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000181 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000123 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.201649 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.229488 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.934556 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 18 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14809 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 8289.635884 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 4.959660 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.032491 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3282.997092 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3722.791267 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.505959 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000303 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000124 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.200378 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.227221 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.933985 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 25 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14803 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 540 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9336 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4933 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001099 # 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number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 120654 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 120654 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28862 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 28862 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22557 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 22557 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63615 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 63615 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3586 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2026 # 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miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.424723 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.124990 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999757 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999757 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.688428 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.688428 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.099685 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.135772 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026432 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495310 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.171765 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.099685 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.135772 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026432 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495310 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.171765 # miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.689397 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.689397 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.095650 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.131787 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026376 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495980 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.171874 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.095650 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.131787 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026376 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495980 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.171874 # miss rate for overall accesses system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1215,80 +1216,80 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # 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Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.757627 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923355 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.923355 # Average percentage of cache occupancy +system.cpu1.dcache.tags.replacements 191947 # number of replacements +system.cpu1.dcache.tags.tagsinuse 472.736016 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 19503515 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 192301 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 101.421807 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.736016 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923313 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.923313 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 39745522 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 39745522 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 11856979 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 11856979 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 7396120 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 7396120 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50084 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 50084 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91418 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 91418 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72426 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 72426 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 19253099 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 19253099 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 19303183 # number of overall hits -system.cpu1.dcache.overall_hits::total 19303183 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 136590 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 136590 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 92466 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 92466 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30716 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30716 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5317 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 5317 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22527 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 22527 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 229056 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 229056 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 259772 # number of overall misses -system.cpu1.dcache.overall_misses::total 259772 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 11993569 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 11993569 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 7488586 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 7488586 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80800 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 80800 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96735 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 96735 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94953 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 94953 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 19482155 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 19482155 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 19562955 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 19562955 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011389 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.011389 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012348 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.012348 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380149 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380149 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054965 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054965 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237244 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237244 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013279 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.013279 # miss rate for overall accesses +system.cpu1.dcache.tags.tag_accesses 39752012 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 39752012 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 11858696 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 11858696 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 7397487 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 7397487 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50100 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 50100 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72422 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 72422 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 19256183 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 19256183 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 19306283 # number of overall hits +system.cpu1.dcache.overall_hits::total 19306283 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 136639 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 136639 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 92477 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 92477 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30718 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30718 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22557 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 22557 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 229116 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 229116 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 259834 # number of overall misses +system.cpu1.dcache.overall_misses::total 259834 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995335 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 11995335 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489964 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 7489964 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80818 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 80818 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96765 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 96765 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94979 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 94979 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 19485299 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 19485299 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 19566117 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 19566117 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011391 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.011391 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012347 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.012347 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380089 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380089 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237495 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237495 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011758 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.011758 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013280 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.013280 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1297,52 +1298,52 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 120669 # number of writebacks -system.cpu1.dcache.writebacks::total 120669 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 120654 # number of writebacks +system.cpu1.dcache.writebacks::total 120654 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 709063 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 709063 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2504 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2504 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 120669 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 28853 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22527 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 51380 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 63613 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 63613 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1047738 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707355 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.trans_dist::ReadReq 709339 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 709339 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 120654 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 28862 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22557 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 51419 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 63615 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 63615 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1048182 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707532 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12080 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 1773789 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33516936 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22861090 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 1774410 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33531204 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22863598 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24160 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 56415418 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 499577 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1371208 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.313508 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.463919 # Request fanout histogram +system.cpu1.toL2Bus.pkt_size::total 56432194 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 499552 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1371519 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.313444 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.463893 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 941324 68.65% 68.65% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 429884 31.35% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 941625 68.66% 68.66% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 429894 31.34% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1371208 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 1371519 # Request fanout histogram system.iocache.tags.replacements 36442 # number of replacements -system.iocache.tags.tagsinuse 14.586086 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.586085 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 246641119509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.586086 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 246641286009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.586085 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.911630 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.911630 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id |