diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt | 507 |
1 files changed, 254 insertions, 253 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 755cdf962..5c160a43e 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -1,59 +1,56 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.783854 # Number of seconds simulated -sim_ticks 2783854461500 # Number of ticks simulated -final_tick 2783854461500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.783867 # Number of seconds simulated +sim_ticks 2783867165000 # Number of ticks simulated +final_tick 2783867165000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1414038 # Simulator instruction rate (inst/s) -host_op_rate 1721363 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27571822204 # Simulator tick rate (ticks/s) -host_mem_usage 560116 # Number of bytes of host memory used -host_seconds 100.97 # Real time elapsed on the host -sim_insts 142771592 # Number of instructions simulated -sim_ops 173801445 # Number of ops (including micro ops) simulated +host_inst_rate 1064003 # Simulator instruction rate (inst/s) +host_op_rate 1295252 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20746494205 # Simulator tick rate (ticks/s) +host_mem_usage 558936 # Number of bytes of host memory used +host_seconds 134.19 # Real time elapsed on the host +sim_insts 142773109 # Number of instructions simulated +sim_ops 173803334 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1210980 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10345892 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1210852 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10328292 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11558408 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1210980 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1210980 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6521536 # Number of bytes written to this memory +system.physmem.bytes_read::total 11540680 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1210852 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1210852 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8837632 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory -system.physmem.bytes_written::total 8857396 # Number of bytes written to this memory +system.physmem.bytes_written::total 8855156 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 27375 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 162174 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 27373 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 161899 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 189573 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 101899 # Number of write requests responded to by this memory +system.physmem.num_reads::total 189296 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 138088 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142504 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142469 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 435001 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3716391 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 434953 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3710052 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4151944 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 435001 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 435001 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2342628 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4145557 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 434953 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 434953 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3174588 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 832779 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3181702 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2342628 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3180883 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3174588 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 435001 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3722686 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 833124 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7333646 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 434953 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3716347 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7326440 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -96,9 +93,9 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 31525959 # DTB read hits -system.cpu.dtb.read_misses 8580 # DTB read misses -system.cpu.dtb.write_hits 23124081 # DTB write hits +system.cpu.dtb.read_hits 31526301 # DTB read hits +system.cpu.dtb.read_misses 8581 # DTB read misses +system.cpu.dtb.write_hits 23124463 # DTB write hits system.cpu.dtb.write_misses 1448 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -109,12 +106,12 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 31534539 # DTB read accesses -system.cpu.dtb.write_accesses 23125529 # DTB write accesses +system.cpu.dtb.read_accesses 31534882 # DTB read accesses +system.cpu.dtb.write_accesses 23125911 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 54650040 # DTB hits -system.cpu.dtb.misses 10028 # DTB misses -system.cpu.dtb.accesses 54660068 # DTB accesses +system.cpu.dtb.hits 54650764 # DTB hits +system.cpu.dtb.misses 10029 # DTB misses +system.cpu.dtb.accesses 54660793 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -136,7 +133,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 147038107 # ITB inst hits +system.cpu.itb.inst_hits 147039592 # ITB inst hits system.cpu.itb.inst_misses 4762 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -153,38 +150,38 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 147042869 # ITB inst accesses -system.cpu.itb.hits 147038107 # DTB hits +system.cpu.itb.inst_accesses 147044354 # ITB inst accesses +system.cpu.itb.hits 147039592 # DTB hits system.cpu.itb.misses 4762 # DTB misses -system.cpu.itb.accesses 147042869 # DTB accesses -system.cpu.numCycles 5567712004 # number of cpu cycles simulated +system.cpu.itb.accesses 147044354 # DTB accesses +system.cpu.numCycles 5567737414 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 142771592 # Number of instructions committed -system.cpu.committedOps 173801445 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 153161099 # Number of integer alu accesses +system.cpu.committedInsts 142773109 # Number of instructions committed +system.cpu.committedOps 173803334 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 153162826 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses -system.cpu.num_func_calls 16873874 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18730301 # number of instructions that are conditional controls -system.cpu.num_int_insts 153161099 # number of integer instructions +system.cpu.num_func_calls 16873879 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 18730390 # number of instructions that are conditional controls +system.cpu.num_int_insts 153162826 # number of integer instructions system.cpu.num_fp_insts 11484 # number of float instructions -system.cpu.num_int_register_reads 285057250 # number of times the integer registers were read -system.cpu.num_int_register_writes 107178308 # number of times the integer registers were written +system.cpu.num_int_register_reads 285060124 # number of times the integer registers were read +system.cpu.num_int_register_writes 107179564 # number of times the integer registers were written system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 530849099 # number of times the CC registers were read -system.cpu.num_cc_register_writes 62363961 # number of times the CC registers were written -system.cpu.num_mem_refs 55938603 # number of memory refs -system.cpu.num_load_insts 31855595 # Number of load instructions -system.cpu.num_store_insts 24083008 # Number of store instructions -system.cpu.num_idle_cycles 5389630193.939086 # Number of idle cycles -system.cpu.num_busy_cycles 178081810.060914 # Number of busy cycles +system.cpu.num_cc_register_reads 530854681 # number of times the CC registers were read +system.cpu.num_cc_register_writes 62364458 # number of times the CC registers were written +system.cpu.num_mem_refs 55939365 # number of memory refs +system.cpu.num_load_insts 31855962 # Number of load instructions +system.cpu.num_store_insts 24083403 # Number of store instructions +system.cpu.num_idle_cycles 5389653746.932553 # Number of idle cycles +system.cpu.num_busy_cycles 178083667.067447 # Number of busy cycles system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles system.cpu.idle_fraction 0.968015 # Percentage of idle cycles -system.cpu.Branches 36396923 # Number of branches fetched +system.cpu.Branches 36397028 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 121151902 68.36% 68.36% # Class of executed instruction -system.cpu.op_class::IntMult 116873 0.07% 68.43% # Class of executed instruction +system.cpu.op_class::IntAlu 121152975 68.36% 68.36% # Class of executed instruction +system.cpu.op_class::IntMult 116892 0.07% 68.43% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction @@ -212,18 +209,18 @@ system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction -system.cpu.op_class::MemRead 31855595 17.98% 86.41% # Class of executed instruction -system.cpu.op_class::MemWrite 24083008 13.59% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 31855962 17.98% 86.41% # Class of executed instruction +system.cpu.op_class::MemWrite 24083403 13.59% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 177218284 # Class of executed instruction +system.cpu.op_class::total 177220138 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 819396 # number of replacements +system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed +system.cpu.dcache.tags.replacements 819403 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 53783832 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 819908 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.597399 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 53784550 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 819915 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.597714 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy @@ -233,58 +230,58 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 219234948 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 219234948 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 30128799 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 30128799 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 22339754 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 22339754 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 52468553 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 52468553 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 52863618 # number of overall hits -system.cpu.dcache.overall_hits::total 52863618 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 396285 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 396285 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 301663 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 301663 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 116121 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 116121 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 8611 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 8611 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 219237855 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 219237855 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 30129122 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 30129122 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 22340107 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 22340107 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 395080 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 395080 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 457347 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 457347 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460136 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460136 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 52469229 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 52469229 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 52864309 # number of overall hits +system.cpu.dcache.overall_hits::total 52864309 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 396277 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 396277 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 301678 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 301678 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 116120 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 116120 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 8612 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 8612 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 697948 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 697948 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 814069 # number of overall misses -system.cpu.dcache.overall_misses::total 814069 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 30525084 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 30525084 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 22641417 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 22641417 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 53166501 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 53166501 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 53677687 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 53677687 # number of overall (read+write) accesses +system.cpu.dcache.demand_misses::cpu.data 697955 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 697955 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 814075 # number of overall misses +system.cpu.dcache.overall_misses::total 814075 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 30525399 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 30525399 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 22641785 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 22641785 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 511200 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 511200 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465959 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 465959 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460138 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460138 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 53167184 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 53167184 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 53678384 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 53678384 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227160 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.227160 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018481 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018481 # miss rate for LoadLockedReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227152 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.227152 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018482 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018482 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.013128 # miss rate for demand accesses @@ -299,16 +296,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 682037 # number of writebacks -system.cpu.dcache.writebacks::total 682037 # number of writebacks +system.cpu.dcache.writebacks::writebacks 682060 # number of writebacks +system.cpu.dcache.writebacks::total 682060 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1699006 # number of replacements -system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 145341690 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1699518 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 85.519359 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 1699220 # number of replacements +system.cpu.icache.tags.tagsinuse 511.663681 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 145342961 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1699732 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 85.509340 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.663679 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 511.663681 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -317,32 +314,32 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 77 system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 148740738 # Number of tag accesses -system.cpu.icache.tags.data_accesses 148740738 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 145341690 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 145341690 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 145341690 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 145341690 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 145341690 # number of overall hits -system.cpu.icache.overall_hits::total 145341690 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1699524 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1699524 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1699524 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1699524 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1699524 # number of overall misses -system.cpu.icache.overall_misses::total 1699524 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 147041214 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 147041214 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 147041214 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 147041214 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 147041214 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 147041214 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011558 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.011558 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.011558 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.011558 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.011558 # miss rate for overall accesses +system.cpu.icache.tags.tag_accesses 148742437 # Number of tag accesses +system.cpu.icache.tags.data_accesses 148742437 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 145342961 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 145342961 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 145342961 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 145342961 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 145342961 # number of overall hits +system.cpu.icache.overall_hits::total 145342961 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1699738 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1699738 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1699738 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1699738 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1699738 # number of overall misses +system.cpu.icache.overall_misses::total 1699738 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 147042699 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 147042699 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 147042699 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 147042699 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 147042699 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 147042699 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011559 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.011559 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.011559 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.011559 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.011559 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.011559 # miss rate for overall accesses system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,21 +350,21 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 110027 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65155.314992 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2727662 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 65155.309065 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2727894 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 175308 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 15.559256 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 15.560579 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 48893.413815 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931995 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004344 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.654834 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.310003 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 48893.397928 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931998 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004345 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.659727 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.315067 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.746054 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.138316 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.109776 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.109777 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.994191 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 65276 # Occupied blocks per task id @@ -379,29 +376,29 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10700 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50640 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 26202418 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 26202418 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7597 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 26204409 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 26204409 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 1681149 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 505483 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2197850 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 682037 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 682037 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 1681362 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 505475 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2198059 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 682060 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 682060 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 151043 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 151043 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 7597 # number of demand (read+write) hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 151058 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 151058 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 7601 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1681149 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 656526 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2348893 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 7597 # number of overall hits +system.cpu.l2cache.demand_hits::cpu.inst 1681362 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 656533 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2349117 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 7601 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1681149 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 656526 # number of overall hits -system.cpu.l2cache.overall_hits::total 2348893 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1681362 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 656533 # number of overall hits +system.cpu.l2cache.overall_hits::total 2349117 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.inst 18358 # number of ReadReq misses @@ -423,50 +420,50 @@ system.cpu.l2cache.overall_misses::cpu.itb.walker 2 system.cpu.l2cache.overall_misses::cpu.inst 18358 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 163398 # number of overall misses system.cpu.l2cache.overall_misses::total 181765 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7604 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7608 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699507 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 521017 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2231751 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 682037 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 682037 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699720 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 521009 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2231960 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 682060 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 682060 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 298907 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 298907 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7604 # number of demand (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 298922 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 298922 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7608 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1699507 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 819924 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2530658 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7604 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1699720 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 819931 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2530882 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7608 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1699507 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 819924 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2530658 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000921 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1699720 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 819931 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2530882 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000920 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010802 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010801 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.029815 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.015190 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.015189 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494682 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.494682 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000921 # miss rate for demand accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494657 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.494657 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000920 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010802 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.199284 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.071825 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000921 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010801 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.199283 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.071819 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000920 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010802 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.199284 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.071825 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010801 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.199283 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.071819 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -475,45 +472,45 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 101899 # number of writebacks -system.cpu.l2cache.writebacks::total 101899 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 101898 # number of writebacks +system.cpu.l2cache.writebacks::total 101898 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2288348 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2288348 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2288556 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2288556 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27560 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27560 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 682037 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 682060 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417092 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444665 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 298922 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417520 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444702 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 36996 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5917183 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108805624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308299 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5917652 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108819320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96310219 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 73992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205224775 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 36632 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3268420 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205240399 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 36631 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3268666 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 5.011156 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.105033 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.105029 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 3231956 98.88% 98.88% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 3232202 98.88% 98.88% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::6 36464 1.12% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3268420 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3268666 # Request fanout histogram system.iobus.trans_dist::ReadReq 30171 # Transaction distribution system.iobus.trans_dist::ReadResp 30171 # Transaction distribution system.iobus.trans_dist::WriteReq 59016 # Transaction distribution @@ -570,23 +567,23 @@ system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321 system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480255 # Cumulative packet size per connected master and slave (bytes) system.iocache.tags.replacements 36430 # number of replacements -system.iocache.tags.tagsinuse 0.909893 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.909962 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.909893 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ide 0.909962 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.056873 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.056873 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328176 # Number of tag accesses system.iocache.tags.data_accesses 328176 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses system.iocache.ReadReq_misses::total 240 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ide 240 # number of demand (read+write) misses system.iocache.demand_misses::total 240 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 240 # number of overall misses @@ -601,6 +598,8 @@ system.iocache.overall_accesses::realview.ide 240 system.iocache.overall_accesses::total 240 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses @@ -611,14 +610,16 @@ system.iocache.blocked::no_mshrs 0 # nu system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 36224 # number of fast writes performed +system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 36190 # number of writebacks +system.iocache.writebacks::total 36190 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 74235 # Transaction distribution system.membus.trans_dist::ReadResp 74235 # Transaction distribution system.membus.trans_dist::WriteReq 27560 # Transaction distribution system.membus.trans_dist::WriteResp 27560 # Transaction distribution -system.membus.trans_dist::Writeback 101899 # Transaction distribution +system.membus.trans_dist::Writeback 138088 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution @@ -629,31 +630,31 @@ system.membus.trans_dist::ReadExResp 146085 # Tr system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498795 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606197 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72928 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72928 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 679125 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498794 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606196 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109118 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 109118 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 715314 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096508 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259523 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2333696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2333696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20593219 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096444 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259459 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4649856 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 4649856 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22909315 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 322858 # Request fanout histogram +system.membus.snoop_fanout::samples 359047 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 322858 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 359047 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 322858 # Request fanout histogram +system.membus.snoop_fanout::total 359047 # Request fanout histogram system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA |