diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt | 627 |
1 files changed, 315 insertions, 312 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index aefcf2796..cc1e1b968 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -1,58 +1,58 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.783855 # Number of seconds simulated -sim_ticks 2783855034000 # Number of ticks simulated -final_tick 2783855034000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2783854715000 # Number of ticks simulated +final_tick 2783854715000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 704767 # Simulator instruction rate (inst/s) -host_op_rate 857940 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 13741971204 # Simulator tick rate (ticks/s) -host_mem_usage 573692 # Number of bytes of host memory used -host_seconds 202.58 # Real time elapsed on the host -sim_insts 142771937 # Number of instructions simulated -sim_ops 173801895 # Number of ops (including micro ops) simulated +host_inst_rate 812904 # Simulator instruction rate (inst/s) +host_op_rate 989581 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15850589349 # Simulator tick rate (ticks/s) +host_mem_usage 583016 # Number of bytes of host memory used +host_seconds 175.63 # Real time elapsed on the host +sim_insts 142771202 # Number of instructions simulated +sim_ops 173801044 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 1207012 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10324900 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10324772 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11533448 # Number of bytes read from this memory +system.physmem.bytes_read::total 11533320 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 1207012 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1207012 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8840960 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 8840896 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8858484 # Number of bytes written to this memory +system.physmem.bytes_written::total 8858420 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 27313 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 161846 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 161844 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 189183 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 138140 # Number of write requests responded to by this memory +system.physmem.num_reads::total 189181 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 138139 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142521 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142520 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 433576 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3708850 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3708804 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4142977 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4142932 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 433576 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 433576 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3175798 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3175775 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3182092 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3175798 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3182070 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3175775 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 433576 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3715145 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3715099 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7325070 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.physmem.bw_total::total 7325002 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -65,9 +65,9 @@ system.realview.nvmem.bw_inst_read::cpu.inst 7 system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -75,7 +75,7 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -105,7 +105,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 10028 # Table walker walks requested system.cpu.dtb.walker.walksShort 10028 # Table walker walks initiated with short descriptors system.cpu.dtb.walker.walkWaitTime::samples 10028 # Table walker wait (enqueue to first request) latency @@ -126,9 +126,9 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7864 system.cpu.dtb.walker.walkRequestOrigin::total 17892 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 31526014 # DTB read hits +system.cpu.dtb.read_hits 31525882 # DTB read hits system.cpu.dtb.read_misses 8580 # DTB read misses -system.cpu.dtb.write_hits 23124171 # DTB write hits +system.cpu.dtb.write_hits 23124079 # DTB write hits system.cpu.dtb.write_misses 1448 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -139,13 +139,13 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 31534594 # DTB read accesses -system.cpu.dtb.write_accesses 23125619 # DTB write accesses +system.cpu.dtb.read_accesses 31534462 # DTB read accesses +system.cpu.dtb.write_accesses 23125527 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 54650185 # DTB hits +system.cpu.dtb.hits 54649961 # DTB hits system.cpu.dtb.misses 10028 # DTB misses -system.cpu.dtb.accesses 54660213 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.accesses 54659989 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -175,7 +175,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 4762 # Table walker walks requested system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency @@ -194,7 +194,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 147038452 # ITB inst hits +system.cpu.itb.inst_hits 147037694 # ITB inst hits system.cpu.itb.inst_misses 4762 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -211,14 +211,14 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 147043214 # ITB inst accesses -system.cpu.itb.hits 147038452 # DTB hits +system.cpu.itb.inst_accesses 147042456 # ITB inst accesses +system.cpu.itb.hits 147037694 # DTB hits system.cpu.itb.misses 4762 # DTB misses -system.cpu.itb.accesses 147043214 # DTB accesses +system.cpu.itb.accesses 147042456 # DTB accesses system.cpu.numPwrStateTransitions 6160 # Number of power state transitions system.cpu.pwrStateClkGateDist::samples 3080 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 874939595.358117 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 17329944407.298908 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 874939633.669805 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 17329944405.377167 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::underflows 3002 97.47% 97.47% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1000-5e+10 72 2.34% 99.81% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state @@ -228,38 +228,38 @@ system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 499984036900 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::total 3080 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 89041080297 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 2694813953703 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 5567713149 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 89040643297 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 2694814071703 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 5567712511 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed -system.cpu.committedInsts 142771937 # Number of instructions committed -system.cpu.committedOps 173801895 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 153161571 # Number of integer alu accesses +system.cpu.committedInsts 142771202 # Number of instructions committed +system.cpu.committedOps 173801044 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 153160791 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses -system.cpu.num_func_calls 16873976 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18730294 # number of instructions that are conditional controls -system.cpu.num_int_insts 153161571 # number of integer instructions +system.cpu.num_func_calls 16873864 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 18730220 # number of instructions that are conditional controls +system.cpu.num_int_insts 153160791 # number of integer instructions system.cpu.num_fp_insts 11484 # number of float instructions -system.cpu.num_int_register_reads 285044694 # number of times the integer registers were read -system.cpu.num_int_register_writes 107178579 # number of times the integer registers were written +system.cpu.num_int_register_reads 285043206 # number of times the integer registers were read +system.cpu.num_int_register_writes 107178068 # number of times the integer registers were written system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 530850452 # number of times the CC registers were read -system.cpu.num_cc_register_writes 62364047 # number of times the CC registers were written -system.cpu.num_mem_refs 55938751 # number of memory refs -system.cpu.num_load_insts 31855653 # Number of load instructions -system.cpu.num_store_insts 24083098 # Number of store instructions -system.cpu.num_idle_cycles 5389630889.858858 # Number of idle cycles -system.cpu.num_busy_cycles 178082259.141142 # Number of busy cycles +system.cpu.num_cc_register_reads 530847827 # number of times the CC registers were read +system.cpu.num_cc_register_writes 62363707 # number of times the CC registers were written +system.cpu.num_mem_refs 55938510 # number of memory refs +system.cpu.num_load_insts 31855508 # Number of load instructions +system.cpu.num_store_insts 24083002 # Number of store instructions +system.cpu.num_idle_cycles 5389631125.859330 # Number of idle cycles +system.cpu.num_busy_cycles 178081385.140670 # Number of busy cycles system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles system.cpu.idle_fraction 0.968015 # Percentage of idle cycles -system.cpu.Branches 36397005 # Number of branches fetched +system.cpu.Branches 36396820 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 121152199 68.36% 68.36% # Class of executed instruction -system.cpu.op_class::IntMult 116879 0.07% 68.43% # Class of executed instruction +system.cpu.op_class::IntAlu 121151571 68.36% 68.36% # Class of executed instruction +system.cpu.op_class::IntMult 116873 0.07% 68.43% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction @@ -287,17 +287,17 @@ system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction -system.cpu.op_class::MemRead 31855653 17.98% 86.41% # Class of executed instruction -system.cpu.op_class::MemWrite 24083098 13.59% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 31855508 17.98% 86.41% # Class of executed instruction +system.cpu.op_class::MemWrite 24083002 13.59% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 177218735 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 819389 # number of replacements +system.cpu.op_class::total 177217860 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 819387 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 53784005 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 819901 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.598170 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 53783783 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 819899 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.598059 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy @@ -307,51 +307,51 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 219235605 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 219235605 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 30128867 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 30128867 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 22339858 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 22339858 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 219234707 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 219234707 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 30128737 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 30128737 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 22339767 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 22339767 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 395067 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 395067 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 457333 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 457333 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 52468725 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 52468725 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 52863792 # number of overall hits -system.cpu.dcache.overall_hits::total 52863792 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 396279 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 396279 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 301663 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 301663 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 52468504 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 52468504 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 52863571 # number of overall hits +system.cpu.dcache.overall_hits::total 52863571 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 396277 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 396277 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 301662 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 301662 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 116119 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 116119 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 8612 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 8612 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 697942 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 697942 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 814061 # number of overall misses -system.cpu.dcache.overall_misses::total 814061 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 30525146 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 30525146 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 22641521 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 22641521 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 697939 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 697939 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 814058 # number of overall misses +system.cpu.dcache.overall_misses::total 814058 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 30525014 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 30525014 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 22641429 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 22641429 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 53166667 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 53166667 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 53677853 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 53677853 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 53166443 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 53166443 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 53677629 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 53677629 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013323 # miss rate for WriteReq accesses @@ -372,14 +372,14 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 682017 # number of writebacks -system.cpu.dcache.writebacks::total 682017 # number of writebacks -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1698989 # number of replacements +system.cpu.dcache.writebacks::writebacks 682138 # number of writebacks +system.cpu.dcache.writebacks::total 682138 # number of writebacks +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 1698988 # number of replacements system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 145342052 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1699501 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 85.520427 # Average number of references to valid blocks. +system.cpu.icache.tags.total_refs 145341295 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1699500 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 85.520032 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 7831497000 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.663679 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy @@ -390,27 +390,27 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 77 system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 148741066 # Number of tag accesses -system.cpu.icache.tags.data_accesses 148741066 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 145342052 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 145342052 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 145342052 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 145342052 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 145342052 # number of overall hits -system.cpu.icache.overall_hits::total 145342052 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1699507 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1699507 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1699507 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1699507 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1699507 # number of overall misses -system.cpu.icache.overall_misses::total 1699507 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 147041559 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 147041559 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 147041559 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 147041559 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 147041559 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 147041559 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 148740307 # Number of tag accesses +system.cpu.icache.tags.data_accesses 148740307 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 145341295 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 145341295 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 145341295 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 145341295 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 145341295 # number of overall hits +system.cpu.icache.overall_hits::total 145341295 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1699506 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1699506 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1699506 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1699506 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1699506 # number of overall misses +system.cpu.icache.overall_misses::total 1699506 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 147040801 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 147040801 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 147040801 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 147040801 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 147040801 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 147040801 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011558 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.011558 # miss rate for demand accesses @@ -423,73 +423,70 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1698989 # number of writebacks -system.cpu.icache.writebacks::total 1698989 # number of writebacks -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 109914 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65155.312641 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4524828 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 175195 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 25.827381 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 48764.064013 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931994 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004344 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 9168.693007 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 7219.619283 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.744081 # Average percentage of cache occupancy +system.cpu.icache.writebacks::writebacks 1698988 # number of writebacks +system.cpu.icache.writebacks::total 1698988 # number of writebacks +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 109912 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65246.862245 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4827688 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 175338 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 27.533609 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 71491095000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.971735 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.023390 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 9170.132693 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56073.734427 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.139903 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.110163 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.994191 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.139925 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.855617 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.995588 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65276 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65421 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3716 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10699 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 195 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9745 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55480 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 40578737 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 40578737 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7597 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 11218 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 682017 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 682017 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1666988 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1666988 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 151130 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 151130 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681192 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1681192 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505442 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 505442 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 7597 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1681192 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 656572 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2348982 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 7597 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1681192 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 656572 # number of overall hits -system.cpu.l2cache.overall_hits::total 2348982 # number of overall hits +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998245 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 40257223 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 40257223 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 5671 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2714 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 8385 # number of ReadReq hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 682138 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 682138 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1666989 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1666989 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 2746 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 2746 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 152790 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 152790 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681191 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1681191 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505440 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 505440 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 5671 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 2714 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1681191 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 658230 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2347806 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 5671 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 2714 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1681191 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 658230 # number of overall hits +system.cpu.l2cache.overall_hits::total 2347806 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2728 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2728 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 9 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 9 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 147777 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 147777 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 146117 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 146117 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 18298 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 18298 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 15568 # number of ReadSharedReq misses @@ -497,116 +494,116 @@ system.cpu.l2cache.ReadSharedReq_misses::total 15568 system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.inst 18298 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 163345 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 181652 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 161685 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 179992 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 18298 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 163345 # number of overall misses -system.cpu.l2cache.overall_misses::total 181652 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7604 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 11227 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 682017 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 682017 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1666988 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1666988 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 161685 # number of overall misses +system.cpu.l2cache.overall_misses::total 179992 # number of overall misses +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 5678 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2716 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 8394 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 682138 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 682138 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1666989 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1666989 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2755 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2755 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 298907 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 298907 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699490 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1699490 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521010 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 521010 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7604 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1699490 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 819917 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2530634 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7604 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1699490 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 819917 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2530634 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000921 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000802 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699489 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1699489 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521008 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 521008 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 5678 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 2716 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1699489 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 819915 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2527798 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 5678 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 2716 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1699489 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 819915 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2527798 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001233 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000736 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.001072 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.003267 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.003267 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494391 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.494391 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.488838 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.488838 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010767 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010767 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.029880 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029880 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000921 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.029881 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029881 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001233 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000736 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010767 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.199221 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.071781 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000921 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.197197 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.071205 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001233 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000736 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010767 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.199221 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.071781 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.197197 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.071205 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 101950 # number of writebacks -system.cpu.l2cache.writebacks::total 101950 # number of writebacks -system.cpu.toL2Bus.snoop_filter.tot_requests 5059879 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540474 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39263 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.l2cache.writebacks::writebacks 101949 # number of writebacks +system.cpu.l2cache.writebacks::total 101949 # number of writebacks +system.cpu.toL2Bus.snoop_filter.tot_requests 5059872 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540470 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39261 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 422 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 422 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 67800 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2288317 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2288314 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 682017 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1698989 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 137372 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 682138 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1698988 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 137249 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2755 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2757 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699507 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 521010 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116047 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2581961 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699506 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116044 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2581953 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 36996 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7753434 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217539832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96306529 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7753423 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217539704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96314145 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 73992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 313957213 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 182976 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 8840960 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 5318714 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.018479 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.134677 # Request fanout histogram +system.cpu.toL2Bus.pkt_size::total 313964701 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 115326 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 6541312 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 5251057 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.018717 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.135522 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5220428 98.15% 98.15% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 98286 1.85% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5152775 98.13% 98.13% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 98282 1.87% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5318714 # Request fanout histogram -system.iobus.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.snoop_fanout::total 5251057 # Request fanout histogram +system.iobus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 30164 # Transaction distribution system.iobus.trans_dist::ReadResp 30164 # Transaction distribution system.iobus.trans_dist::WriteReq 59002 # Transaction distribution @@ -657,14 +654,14 @@ system.iobus.pkt_size_system.bridge.master::total 159061 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36430 # number of replacements -system.iocache.tags.tagsinuse 0.909892 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.909890 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 227410175509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.909892 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 227410176509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 0.909890 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -672,7 +669,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328176 # Number of tag accesses system.iocache.tags.data_accesses 328176 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses system.iocache.ReadReq_misses::total 240 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -705,65 +702,71 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.membus.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 362809 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 151023 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 488 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 40087 # Transaction distribution system.membus.trans_dist::ReadResp 74202 # Transaction distribution system.membus.trans_dist::WriteReq 27546 # Transaction distribution system.membus.trans_dist::WriteResp 27546 # Transaction distribution -system.membus.trans_dist::WritebackDirty 138140 # Transaction distribution -system.membus.trans_dist::CleanEvict 8204 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution +system.membus.trans_dist::WritebackDirty 138139 # Transaction distribution +system.membus.trans_dist::CleanEvict 8203 # Transaction distribution +system.membus.trans_dist::UpgradeReq 130 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution -system.membus.trans_dist::ReadExReq 145998 # Transaction distribution -system.membus.trans_dist::ReadExResp 145998 # Transaction distribution +system.membus.trans_dist::UpgradeResp 132 # Transaction distribution +system.membus.trans_dist::ReadExReq 145996 # Transaction distribution +system.membus.trans_dist::ReadExResp 145996 # Transaction distribution system.membus.trans_dist::ReadSharedReq 34115 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 506584 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 613944 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 497824 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 605184 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 723302 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 714542 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092540 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255513 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092348 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255321 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2331520 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2331520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20587033 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20586841 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 434823 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::samples 430442 # Request fanout histogram +system.membus.snoop_fanout::mean 0.012836 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.112565 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 434823 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 424917 98.72% 98.72% # Request fanout histogram +system.membus.snoop_fanout::1 5525 1.28% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 434823 # Request fanout histogram -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.membus.snoop_fanout::total 430442 # Request fanout histogram +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -795,28 +798,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- |