diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic')
3 files changed, 76 insertions, 34 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini index 720edf3cb..99dc32f6e 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini @@ -12,6 +12,7 @@ children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview termi atags_addr=256 boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +early_kernel_symbols=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 @@ -184,9 +185,8 @@ type=IntrControl sys=system [system.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -245,10 +245,9 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] [system.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false @@ -660,9 +659,8 @@ output=true port=3456 [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout index 4b3b38463..f08c091ef 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 10 2012 12:36:36 -gem5 started May 10 2012 12:36:42 -gem5 executing on u200540-lin +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:24:24 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 2332330037000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index e1058fc4f..154c8ff44 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,32 +4,63 @@ sim_seconds 2.332330 # Nu sim_ticks 2332330037000 # Number of ticks simulated final_tick 2332330037000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1538399 # Simulator instruction rate (inst/s) -host_op_rate 1985816 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60412799239 # Simulator tick rate (ticks/s) -host_mem_usage 379756 # Number of bytes of host memory used -host_seconds 38.61 # Real time elapsed on the host +host_inst_rate 1412842 # Simulator instruction rate (inst/s) +host_op_rate 1823742 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55482154888 # Simulator tick rate (ticks/s) +host_mem_usage 382804 # Number of bytes of host memory used +host_seconds 42.04 # Real time elapsed on the host sim_insts 59392246 # Number of instructions simulated sim_ops 76665494 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 122661296 # Number of bytes read from this memory -system.physmem.bytes_inst_read 941920 # Number of instructions bytes read from this memory -system.physmem.bytes_written 9590216 # Number of bytes written to this memory -system.physmem.num_reads 14137091 # Number of read requests responded to by this memory -system.physmem.num_writes 856679 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 52591740 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 403854 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 4111861 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 56703601 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bytes_read 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory -system.realview.nvmem.num_reads 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory -system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory -system.realview.nvmem.bw_read 9 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read 9 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total 9 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 1536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 941920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10043536 # Number of bytes read from this memory +system.physmem.bytes_read::total 122661296 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 941920 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 941920 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6574400 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 3015816 # Number of bytes written to this memory +system.physmem.bytes_written::total 9590216 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 24 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 20920 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 156964 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14137091 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 102725 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory +system.physmem.num_writes::total 856679 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47880592 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 659 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 412 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 403854 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4306224 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52591740 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 403854 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 403854 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2818812 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1293049 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4111861 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2818812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47880592 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 659 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 412 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 403854 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5599273 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 56703601 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 9 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 9 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 117012 # number of replacements system.l2c.tagsinuse 24288.656748 # Cycle average of tags in use system.l2c.total_refs 1527554 # Total number of references to valid blocks. @@ -112,16 +143,21 @@ system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.003183 system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.004756 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.inst 0.016837 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.data 0.046592 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.025753 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu.data 0.991168 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.991168 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu.data 0.570577 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.570577 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu.dtb.walker 0.003183 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.itb.walker 0.004756 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.inst 0.016837 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.data 0.254824 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.116613 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu.dtb.walker 0.003183 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.itb.walker 0.004756 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.inst 0.016837 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.data 0.254824 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.116613 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -233,8 +269,11 @@ system.cpu.icache.demand_accesses::total 60406063 # nu system.cpu.icache.overall_accesses::cpu.inst 60406063 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 60406063 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014090 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014090 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.014090 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014090 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.014090 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014090 # miss rate for overall accesses system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -290,10 +329,15 @@ system.cpu.dcache.demand_accesses::total 23757776 # nu system.cpu.dcache.overall_accesses::cpu.data 23757776 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 23757776 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026980 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.026980 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045255 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045255 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.025912 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025912 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.025912 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025912 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked |