diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini | 170 |
1 files changed, 155 insertions, 15 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini index da0c44ae8..9fa392075 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini @@ -14,6 +14,7 @@ children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l atags_addr=256 boot_loader=/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain dtb_filename= @@ -22,9 +23,16 @@ enable_context_switch_stats_dump=false eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false init_param=0 kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 +load_offset=0 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 @@ -33,7 +41,9 @@ multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true +phys_addr_range_64=40 readfile=tests/halt.sh +reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -86,19 +96,21 @@ voltage_domain=system.voltage_domain [system.cpu0] type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb tracer +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu0.dstage2_mmu dtb=system.cpu0.dtb eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu0.interrupts isa=system.cpu0.isa +istage2_mmu=system.cpu0.istage2_mmu itb=system.cpu0.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -150,10 +162,35 @@ hit_latency=2 sequential_access=false size=32768 +[system.cpu0.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb +tlb=system.cpu0.dtb + +[system.cpu0.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.dstage2_mmu.stage2_tlb.walker + +[system.cpu0.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[5] + [system.cpu0.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu0.dtb.walker @@ -161,6 +198,7 @@ walker=system.cpu0.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -208,24 +246,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu0.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb +tlb=system.cpu0.itb + +[system.cpu0.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.istage2_mmu.stage2_tlb.walker + +[system.cpu0.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[4] [system.cpu0.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu0.itb.walker @@ -233,6 +307,7 @@ walker=system.cpu0.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] @@ -243,19 +318,21 @@ eventq_index=0 [system.cpu1] type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb tracer +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer checker=Null clk_domain=system.cpu_clk_domain cpu_id=1 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu1.dstage2_mmu dtb=system.cpu1.dtb eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu1.interrupts isa=system.cpu1.isa +istage2_mmu=system.cpu1.istage2_mmu itb=system.cpu1.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -295,7 +372,7 @@ tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.dcache_port -mem_side=system.toL2Bus.slave[5] +mem_side=system.toL2Bus.slave[7] [system.cpu1.dcache.tags] type=LRU @@ -307,10 +384,35 @@ hit_latency=2 sequential_access=false size=32768 +[system.cpu1.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb +tlb=system.cpu1.dtb + +[system.cpu1.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.dstage2_mmu.stage2_tlb.walker + +[system.cpu1.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[11] + [system.cpu1.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu1.dtb.walker @@ -318,9 +420,10 @@ walker=system.cpu1.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[7] +port=system.toL2Bus.slave[9] [system.cpu1.icache] type=BaseCache @@ -345,7 +448,7 @@ tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port -mem_side=system.toL2Bus.slave[4] +mem_side=system.toL2Bus.slave[6] [system.cpu1.icache.tags] type=LRU @@ -365,24 +468,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu1.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb +tlb=system.cpu1.itb + +[system.cpu1.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.istage2_mmu.stage2_tlb.walker + +[system.cpu1.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[10] [system.cpu1.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu1.itb.walker @@ -390,9 +529,10 @@ walker=system.cpu1.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[6] +port=system.toL2Bus.slave[8] [system.cpu1.tracer] type=ExeTracer @@ -1029,7 +1169,7 @@ system=system use_default_range=false width=8 master=system.l2c.cpu_side -slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port [system.vncserver] type=VncServer |