diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt | 1880 |
1 files changed, 927 insertions, 953 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 0ffcacbe4..0a013f420 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,75 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.207291 # Number of seconds simulated -sim_ticks 1207290627000 # Number of ticks simulated -final_tick 1207290627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.203695 # Number of seconds simulated +sim_ticks 1203694548000 # Number of ticks simulated +final_tick 1203694548000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 648322 # Simulator instruction rate (inst/s) -host_op_rate 826248 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12731770448 # Simulator tick rate (ticks/s) -host_mem_usage 380152 # Number of bytes of host memory used -host_seconds 94.83 # Real time elapsed on the host -sim_insts 61477134 # Number of instructions simulated -sim_ops 78349023 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 52642784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 394084 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4718772 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 323100 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4791152 # Number of bytes read from this memory -system.physmem.bytes_read::total 62870404 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 394084 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 323100 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 717184 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4105920 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7133264 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 6580348 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12376 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73803 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5130 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 74888 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6746553 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 64155 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 820991 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43604069 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 106 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 326420 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3908563 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 212 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 267624 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 3968516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52075617 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 326420 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 267624 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 594044 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3400938 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 14081 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2493471 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5908490 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3400938 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43604069 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 106 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 326420 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3922645 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 212 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 267624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6461987 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 57984106 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 610810 # Simulator instruction rate (inst/s) +host_op_rate 778429 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11963163223 # Simulator tick rate (ticks/s) +host_mem_usage 383784 # Number of bytes of host memory used +host_seconds 100.62 # Real time elapsed on the host +sim_insts 61457649 # Number of instructions simulated +sim_ops 78322983 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -88,251 +29,292 @@ system.realview.nvmem.bw_inst_read::total 56 # I system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 56 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 69267 # number of replacements -system.l2c.tagsinuse 52917.687101 # Cycle average of tags in use -system.l2c.total_refs 1645693 # Total number of references to valid blocks. -system.l2c.sampled_refs 134464 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.238912 # Average number of references to valid blocks. +system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 354404 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4259252 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 364636 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5307760 # Number of bytes read from this memory +system.physmem.bytes_read::total 62191012 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 354404 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 364636 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 719040 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4163840 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory +system.physmem.bytes_written::total 7191184 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 11756 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 66623 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5779 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82960 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6655189 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 65060 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory +system.physmem.num_writes::total 821896 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43120999 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 53 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 294430 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3538482 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 302931 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4409557 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51666772 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 294430 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 302931 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 597361 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3459216 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 14123 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2500920 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5974260 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3459216 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43120999 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 53 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 294430 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3552606 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 302931 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6910477 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 57641032 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 70187 # number of replacements +system.l2c.tagsinuse 53228.642974 # Cycle average of tags in use +system.l2c.total_refs 1643789 # Total number of references to valid blocks. +system.l2c.sampled_refs 135350 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.144728 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 40124.661917 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 0.000403 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.001466 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3720.854167 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4213.259554 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 2.746626 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.itb.walker 0.001732 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2800.295591 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2055.865645 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.612254 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 40454.040636 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 0.000402 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.003088 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 3394.914064 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2735.381228 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 2.669984 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 3118.851455 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 3522.782116 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.617280 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.056776 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.064289 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.042729 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.031370 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.807460 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 4114 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1841 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 402307 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 205875 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5723 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1959 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 449970 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 144091 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1215880 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 572580 # number of Writeback hits -system.l2c.Writeback_hits::total 572580 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1130 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 572 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1702 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 212 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 104 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 316 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 56723 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 53017 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 109740 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4114 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1841 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 402307 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 262598 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5723 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1959 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 449970 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 197108 # number of demand (read+write) hits -system.l2c.demand_hits::total 1325620 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4114 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 1841 # number of overall hits -system.l2c.overall_hits::cpu0.inst 402307 # number of overall hits -system.l2c.overall_hits::cpu0.data 262598 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5723 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1959 # number of overall hits -system.l2c.overall_hits::cpu1.inst 449970 # number of overall hits -system.l2c.overall_hits::cpu1.data 197108 # number of overall hits -system.l2c.overall_hits::total 1325620 # number of overall hits +system.l2c.occ_percent::cpu0.inst 0.051802 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.041739 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.047590 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.053753 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.812205 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 2523 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 1490 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 278283 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 124654 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 5208 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1502 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 576279 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 223386 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1213325 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 571443 # number of Writeback hits +system.l2c.Writeback_hits::total 571443 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 992 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 888 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1880 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 191 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 95 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 286 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 39230 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 70245 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 109475 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 2523 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 1490 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 278283 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 163884 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 5208 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 1502 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 576279 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 293631 # number of demand (read+write) hits +system.l2c.demand_hits::total 1322800 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 2523 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 1490 # number of overall hits +system.l2c.overall_hits::cpu0.inst 278283 # number of overall hits +system.l2c.overall_hits::cpu0.data 163884 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 5208 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 1502 # number of overall hits +system.l2c.overall_hits::cpu1.inst 576279 # number of overall hits +system.l2c.overall_hits::cpu1.data 293631 # number of overall hits +system.l2c.overall_hits::total 1322800 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 5744 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 7874 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 5043 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 3639 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40184.810629 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40043.288277 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40031.815373 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40014.444661 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40010.696679 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 41333.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40164.441321 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40143.499941 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40085.138012 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -528,27 +498,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7076084 # DTB read hits -system.cpu0.dtb.read_misses 3743 # DTB read misses -system.cpu0.dtb.write_hits 5660386 # DTB write hits -system.cpu0.dtb.write_misses 804 # DTB write misses +system.cpu0.dtb.read_hits 4800541 # DTB read hits +system.cpu0.dtb.read_misses 2116 # DTB read misses +system.cpu0.dtb.write_hits 4101169 # DTB write hits +system.cpu0.dtb.write_misses 405 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1791 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1539 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 91 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7079827 # DTB read accesses -system.cpu0.dtb.write_accesses 5661190 # DTB write accesses +system.cpu0.dtb.perms_faults 203 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 4802657 # DTB read accesses +system.cpu0.dtb.write_accesses 4101574 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12736470 # DTB hits -system.cpu0.dtb.misses 4547 # DTB misses -system.cpu0.dtb.accesses 12741017 # DTB accesses -system.cpu0.itb.inst_hits 29574655 # ITB inst hits -system.cpu0.itb.inst_misses 2205 # ITB inst misses +system.cpu0.dtb.hits 8901710 # DTB hits +system.cpu0.dtb.misses 2521 # DTB misses +system.cpu0.dtb.accesses 8904231 # DTB accesses +system.cpu0.itb.inst_hits 19425295 # ITB inst hits +system.cpu0.itb.inst_misses 1350 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -557,86 +527,86 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1347 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 29576860 # ITB inst accesses -system.cpu0.itb.hits 29574655 # DTB hits -system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 29576860 # DTB accesses -system.cpu0.numCycles 2414581254 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 19426645 # ITB inst accesses +system.cpu0.itb.hits 19425295 # DTB hits +system.cpu0.itb.misses 1350 # DTB misses +system.cpu0.itb.accesses 19426645 # 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number of times the integer registers were written -system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 13404188 # number of memory refs -system.cpu0.num_load_insts 7413537 # Number of load instructions -system.cpu0.num_store_insts 5990651 # Number of store instructions -system.cpu0.num_idle_cycles 2267023582.330122 # Number of idle cycles -system.cpu0.num_busy_cycles 147557671.669878 # Number of busy cycles -system.cpu0.not_idle_fraction 0.061111 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.938889 # Percentage of idle cycles +system.cpu0.committedInsts 19048182 # Number of instructions committed +system.cpu0.committedOps 25051772 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 22684080 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4364 # Number of float alu accesses +system.cpu0.num_func_calls 868675 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 2620305 # number of instructions that are conditional controls +system.cpu0.num_int_insts 22684080 # number of integer instructions +system.cpu0.num_fp_insts 4364 # number of float instructions +system.cpu0.num_int_register_reads 128950966 # number of times the integer registers were read +system.cpu0.num_int_register_writes 23731370 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3980 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 384 # number of times the floating registers were written +system.cpu0.num_mem_refs 9388163 # number of memory refs +system.cpu0.num_load_insts 5047859 # Number of load instructions +system.cpu0.num_store_insts 4340304 # Number of store instructions +system.cpu0.num_idle_cycles 2301502404.823749 # Number of idle cycles +system.cpu0.num_busy_cycles 104459206.176251 # Number of busy cycles +system.cpu0.not_idle_fraction 0.043417 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.956583 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 46683 # number of quiesce instructions executed -system.cpu0.icache.replacements 408135 # number of replacements -system.cpu0.icache.tagsinuse 509.469782 # Cycle average of tags in use -system.cpu0.icache.total_refs 29165991 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 408647 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 71.372091 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 75845657000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.469782 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.995058 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.995058 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 29165991 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29165991 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29165991 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29165991 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29165991 # number of overall hits -system.cpu0.icache.overall_hits::total 29165991 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 408647 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 408647 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 408647 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 408647 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 408647 # number of overall misses -system.cpu0.icache.overall_misses::total 408647 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6096279000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6096279000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 6096279000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6096279000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 6096279000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6096279000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 29574638 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 29574638 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 29574638 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 29574638 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 29574638 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 29574638 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013817 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.013817 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013817 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.013817 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013817 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.013817 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14918.203241 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14918.203241 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14918.203241 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14918.203241 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14918.203241 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14918.203241 # average overall miss latency +system.cpu0.kern.inst.quiesce 34020 # number of quiesce instructions executed +system.cpu0.icache.replacements 283184 # number of replacements +system.cpu0.icache.tagsinuse 509.502628 # Cycle average of tags in use +system.cpu0.icache.total_refs 19141582 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 283696 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 67.472160 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 75588601000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.502628 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.995122 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.995122 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 19141582 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 19141582 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 19141582 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 19141582 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 19141582 # number of overall hits +system.cpu0.icache.overall_hits::total 19141582 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 283696 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 283696 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 283696 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 283696 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 283696 # number of overall misses +system.cpu0.icache.overall_misses::total 283696 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 3929923500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 3929923500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 3929923500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 3929923500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 3929923500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 3929923500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 19425278 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 19425278 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 19425278 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 19425278 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 19425278 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 19425278 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014604 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014604 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014604 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014604 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014604 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014604 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13852.586924 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13852.586924 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13852.586924 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13852.586924 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13852.586924 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13852.586924 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -645,120 +615,120 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 408647 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 408647 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 408647 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 408647 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 408647 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 408647 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4869493500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4869493500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4869493500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4869493500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4869493500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4869493500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 351814000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 351814000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013817 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013817 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013817 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.013817 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013817 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.013817 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11916.136666 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11916.136666 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11916.136666 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11916.136666 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11916.136666 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11916.136666 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 283696 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 283696 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 283696 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 283696 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 283696 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 283696 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 3362531500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 3362531500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 3362531500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 3362531500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 3362531500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 3362531500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 353907000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 353907000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 353907000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 353907000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014604 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014604 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014604 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014604 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014604 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014604 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11852.586924 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11852.586924 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11852.586924 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11852.586924 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11852.586924 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11852.586924 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 330734 # number of replacements -system.cpu0.dcache.tagsinuse 459.649702 # Cycle average of tags in use -system.cpu0.dcache.total_refs 12280871 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 331246 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 37.074775 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 664264000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 459.649702 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.897753 # 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Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.891650 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 4452407 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 4452407 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3852535 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3852535 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117731 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 117731 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 117849 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 117849 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8304942 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8304942 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8304942 # number of overall hits +system.cpu0.dcache.overall_hits::total 8304942 # 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average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23502.313804 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 23502.313804 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23502.313804 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 23502.313804 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -767,66 +737,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 306480 # 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number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 50946500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 50946500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5664118000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 5664118000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5664118000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 5664118000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12130688000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12130688000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1193496500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1193496500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13324184500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13324184500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031847 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031847 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029464 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029464 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062733 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062733 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.061292 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.061292 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030743 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.030743 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030743 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.030743 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11596.209913 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11596.209913 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33907.261581 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33907.261581 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 6916.687817 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6916.687817 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6620.727745 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6620.727745 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19611.032961 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19611.032961 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19611.032961 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19611.032961 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21502.313804 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21502.313804 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21502.313804 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21502.313804 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -836,27 +806,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 8318170 # DTB read hits -system.cpu1.dtb.read_misses 3663 # DTB read misses -system.cpu1.dtb.write_hits 5832653 # DTB write hits -system.cpu1.dtb.write_misses 1435 # DTB write misses +system.cpu1.dtb.read_hits 10590618 # DTB read hits +system.cpu1.dtb.read_misses 5230 # DTB read misses +system.cpu1.dtb.write_hits 7384755 # DTB write hits +system.cpu1.dtb.write_misses 1835 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1968 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 2257 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 142 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 194 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 8321833 # DTB read accesses -system.cpu1.dtb.write_accesses 5834088 # DTB write accesses +system.cpu1.dtb.perms_faults 249 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 10595848 # DTB read accesses +system.cpu1.dtb.write_accesses 7386590 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 14150823 # DTB hits -system.cpu1.dtb.misses 5098 # DTB misses -system.cpu1.dtb.accesses 14155921 # DTB accesses -system.cpu1.itb.inst_hits 33211066 # ITB inst hits -system.cpu1.itb.inst_misses 2171 # ITB inst misses +system.cpu1.dtb.hits 17975373 # DTB hits +system.cpu1.dtb.misses 7065 # DTB misses +system.cpu1.dtb.accesses 17982438 # DTB accesses +system.cpu1.itb.inst_hits 43340388 # ITB inst hits +system.cpu1.itb.inst_misses 3017 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -865,86 +835,86 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1458 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 33213237 # ITB inst accesses -system.cpu1.itb.hits 33211066 # DTB hits -system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 33213237 # DTB accesses -system.cpu1.numCycles 2413083038 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 43343405 # ITB inst accesses +system.cpu1.itb.hits 43340388 # DTB hits +system.cpu1.itb.misses 3017 # DTB misses +system.cpu1.itb.accesses 43343405 # DTB accesses +system.cpu1.numCycles 2407389096 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 32600335 # Number of instructions committed -system.cpu1.committedOps 41120048 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 37342001 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 963082 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3735102 # number of instructions that are conditional controls -system.cpu1.num_int_insts 37342001 # number of integer instructions -system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 213831809 # number of times the integer registers were read -system.cpu1.num_int_register_writes 39482622 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 14689113 # number of memory refs -system.cpu1.num_load_insts 8640454 # Number of load instructions -system.cpu1.num_store_insts 6048659 # Number of store instructions -system.cpu1.num_idle_cycles 1863361359.722463 # Number of idle cycles -system.cpu1.num_busy_cycles 549721678.277537 # Number of busy cycles -system.cpu1.not_idle_fraction 0.227809 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.772191 # Percentage of idle cycles +system.cpu1.committedInsts 42409467 # Number of instructions committed +system.cpu1.committedOps 53271211 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 47739499 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5457 # Number of float alu accesses +system.cpu1.num_func_calls 1335008 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 5483103 # number of instructions that are conditional controls +system.cpu1.num_int_insts 47739499 # number of integer instructions +system.cpu1.num_fp_insts 5457 # number of float instructions +system.cpu1.num_int_register_reads 274842107 # number of times the integer registers were read +system.cpu1.num_int_register_writes 51975033 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3577 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1884 # number of times the floating registers were written +system.cpu1.num_mem_refs 18684058 # number of memory refs +system.cpu1.num_load_insts 11000639 # Number of load instructions +system.cpu1.num_store_insts 7683419 # Number of store instructions +system.cpu1.num_idle_cycles 1827105047.254482 # Number of idle cycles +system.cpu1.num_busy_cycles 580284048.745518 # Number of busy cycles +system.cpu1.not_idle_fraction 0.241043 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.758957 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 43948 # number of quiesce instructions executed -system.cpu1.icache.replacements 455071 # number of replacements -system.cpu1.icache.tagsinuse 479.019014 # Cycle average of tags in use -system.cpu1.icache.total_refs 32755479 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 455583 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 71.897940 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 94151388000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 479.019014 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.935584 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.935584 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 32755479 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 32755479 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 32755479 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 32755479 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 32755479 # number of overall hits -system.cpu1.icache.overall_hits::total 32755479 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 455583 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 455583 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 455583 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 455583 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 455583 # number of overall misses -system.cpu1.icache.overall_misses::total 455583 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6728250000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6728250000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6728250000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6728250000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6728250000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6728250000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 33211062 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 33211062 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 33211062 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 33211062 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 33211062 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 33211062 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013718 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.013718 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013718 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.013718 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013718 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.013718 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14768.439560 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14768.439560 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14768.439560 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14768.439560 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14768.439560 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14768.439560 # average overall miss latency +system.cpu1.kern.inst.quiesce 56706 # number of quiesce instructions executed +system.cpu1.icache.replacements 582628 # number of replacements +system.cpu1.icache.tagsinuse 479.068937 # Cycle average of tags in use +system.cpu1.icache.total_refs 42757244 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 583140 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 73.322434 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 92849627500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 479.068937 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.935682 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.935682 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 42757244 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 42757244 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 42757244 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 42757244 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 42757244 # number of overall hits +system.cpu1.icache.overall_hits::total 42757244 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 583140 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 583140 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 583140 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 583140 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 583140 # number of overall misses +system.cpu1.icache.overall_misses::total 583140 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7853505000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7853505000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7853505000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7853505000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7853505000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7853505000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 43340384 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 43340384 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 43340384 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 43340384 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 43340384 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 43340384 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013455 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.013455 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013455 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.013455 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013455 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.013455 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13467.614981 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13467.614981 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13467.614981 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13467.614981 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13467.614981 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13467.614981 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -953,120 +923,120 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 455583 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 455583 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 455583 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 455583 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 455583 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 455583 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5360597500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5360597500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5360597500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5360597500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5360597500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5360597500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5250000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 5250000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013718 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013718 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013718 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.013718 # 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number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024002 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.024002 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030142 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030142 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119518 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119518 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108316 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108316 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026529 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026529 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026529 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026529 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10882.580134 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10882.580134 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31210.760999 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31210.760999 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6562.629710 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6562.629710 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5722.146077 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5722.146077 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20387.850884 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20387.850884 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20387.850884 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20387.850884 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 366483 # number of writebacks +system.cpu1.dcache.writebacks::total 366483 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 253200 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 253200 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 178129 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 178129 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13100 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13100 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10399 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10399 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 431329 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 431329 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 431329 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 431329 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2771848500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2771848500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5304406500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5304406500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89559000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89559000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 42226500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 42226500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8076255000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 8076255000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8076255000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 8076255000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 170163530000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 170163530000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40377042500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40377042500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 210540572500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 210540572500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027065 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.027065 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027397 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027397 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.104839 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.104839 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.083274 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.083274 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027201 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027201 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027201 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.027201 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10947.268957 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10947.268957 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29778.455501 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 29778.455501 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6836.564885 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6836.564885 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4060.630830 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4060.630830 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18724.117785 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18724.117785 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18724.117785 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18724.117785 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1152,10 +1126,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 574279130811 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 574279130811 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 574279130811 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 574279130811 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 567076826640 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 567076826640 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 567076826640 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 567076826640 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |