diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt | 2909 |
1 files changed, 1454 insertions, 1455 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index dfe5d9e95..786f029ca 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.196139 # Number of seconds simulated -sim_ticks 1196139241000 # Number of ticks simulated -final_tick 1196139241000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.196143 # Number of seconds simulated +sim_ticks 1196142873000 # Number of ticks simulated +final_tick 1196142873000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 363491 # Simulator instruction rate (inst/s) -host_op_rate 463152 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7074263356 # Simulator tick rate (ticks/s) -host_mem_usage 480032 # Number of bytes of host memory used -host_seconds 169.08 # Real time elapsed on the host -sim_insts 61460236 # Number of instructions simulated -sim_ops 78311148 # Number of ops (including micro ops) simulated +host_inst_rate 497666 # Simulator instruction rate (inst/s) +host_op_rate 634118 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9685782626 # Simulator tick rate (ticks/s) +host_mem_usage 425428 # Number of bytes of host memory used +host_seconds 123.49 # Real time elapsed on the host +sim_insts 61459155 # Number of instructions simulated +sim_ops 78310163 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory @@ -34,141 +34,141 @@ system.realview.nvmem.bw_total::total 57 # To system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 393164 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4714556 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 393356 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4724988 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 324676 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4804536 # Number of bytes read from this memory -system.physmem.bytes_read::total 62141956 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 393164 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 324676 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 717840 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4110528 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 324292 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4798584 # Number of bytes read from this memory +system.physmem.bytes_read::total 62146244 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 393356 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 324292 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 717648 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4113152 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7137872 # Number of bytes written to this memory +system.physmem.bytes_written::total 7140496 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12371 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73739 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 12374 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73902 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5164 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 75099 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6654445 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 64227 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5158 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 75006 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6654512 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 64268 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 821063 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43393369 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 821104 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43393238 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 328694 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3941478 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 328854 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3950187 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 214 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 271437 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4016703 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51952109 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 328694 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 271437 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 600131 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3436496 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 271115 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4011715 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51955536 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 328854 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 271115 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 599968 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3438680 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 14212 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2516717 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5967426 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3436496 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43393369 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2516709 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5969601 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3438680 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43393238 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 328694 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3955690 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 328854 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3964399 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 271437 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6533420 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 57919534 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6654445 # Number of read requests accepted -system.physmem.writeReqs 821063 # Number of write requests accepted -system.physmem.readBursts 6654445 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 821063 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 425854976 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 29504 # Total number of bytes read from write queue -system.physmem.bytesWritten 7264576 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 62141956 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7137872 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 461 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 707541 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 12043 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 415328 # Per bank write bursts -system.physmem.perBankRdBursts::1 415204 # Per bank write bursts -system.physmem.perBankRdBursts::2 415403 # Per bank write bursts -system.physmem.perBankRdBursts::3 415627 # Per bank write bursts -system.physmem.perBankRdBursts::4 422407 # Per bank write bursts -system.physmem.perBankRdBursts::5 415617 # Per bank write bursts -system.physmem.perBankRdBursts::6 415785 # Per bank write bursts -system.physmem.perBankRdBursts::7 415500 # Per bank write bursts -system.physmem.perBankRdBursts::8 416027 # Per bank write bursts -system.physmem.perBankRdBursts::9 415632 # Per bank write bursts -system.physmem.perBankRdBursts::10 415316 # Per bank write bursts -system.physmem.perBankRdBursts::11 414840 # Per bank write bursts -system.physmem.perBankRdBursts::12 415044 # Per bank write bursts -system.physmem.perBankRdBursts::13 415557 # Per bank write bursts -system.physmem.perBankRdBursts::14 415554 # Per bank write bursts -system.physmem.perBankRdBursts::15 415143 # Per bank write bursts -system.physmem.perBankWrBursts::0 6946 # Per bank write bursts -system.physmem.perBankWrBursts::1 6844 # Per bank write bursts -system.physmem.perBankWrBursts::2 7080 # Per bank write bursts -system.physmem.perBankWrBursts::3 7140 # Per bank write bursts -system.physmem.perBankWrBursts::4 7438 # Per bank write bursts -system.physmem.perBankWrBursts::5 7223 # Per bank write bursts -system.physmem.perBankWrBursts::6 7431 # Per bank write bursts -system.physmem.perBankWrBursts::7 7190 # Per bank write bursts -system.physmem.perBankWrBursts::8 7575 # Per bank write bursts -system.physmem.perBankWrBursts::9 7264 # Per bank write bursts -system.physmem.perBankWrBursts::10 7139 # Per bank write bursts -system.physmem.perBankWrBursts::11 6649 # Per bank write bursts -system.physmem.perBankWrBursts::12 6729 # Per bank write bursts -system.physmem.perBankWrBursts::13 7011 # Per bank write bursts -system.physmem.perBankWrBursts::14 7090 # Per bank write bursts -system.physmem.perBankWrBursts::15 6760 # Per bank write bursts +system.physmem.bw_total::cpu1.inst 271115 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6528424 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 57925137 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6654512 # Number of read requests accepted +system.physmem.writeReqs 821104 # Number of write requests accepted +system.physmem.readBursts 6654512 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 821104 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 425857728 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 31040 # Total number of bytes read from write queue +system.physmem.bytesWritten 7268800 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 62146244 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7140496 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 485 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 707525 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 12040 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 415388 # Per bank write bursts +system.physmem.perBankRdBursts::1 415219 # Per bank write bursts +system.physmem.perBankRdBursts::2 415339 # Per bank write bursts +system.physmem.perBankRdBursts::3 415675 # Per bank write bursts +system.physmem.perBankRdBursts::4 422392 # Per bank write bursts +system.physmem.perBankRdBursts::5 415542 # Per bank write bursts +system.physmem.perBankRdBursts::6 415783 # Per bank write bursts +system.physmem.perBankRdBursts::7 415483 # Per bank write bursts +system.physmem.perBankRdBursts::8 416074 # Per bank write bursts +system.physmem.perBankRdBursts::9 415577 # Per bank write bursts +system.physmem.perBankRdBursts::10 415249 # Per bank write bursts +system.physmem.perBankRdBursts::11 414844 # Per bank write bursts +system.physmem.perBankRdBursts::12 415143 # Per bank write bursts +system.physmem.perBankRdBursts::13 415555 # Per bank write bursts +system.physmem.perBankRdBursts::14 415561 # Per bank write bursts +system.physmem.perBankRdBursts::15 415203 # Per bank write bursts +system.physmem.perBankWrBursts::0 6999 # Per bank write bursts +system.physmem.perBankWrBursts::1 6843 # Per bank write bursts +system.physmem.perBankWrBursts::2 7018 # Per bank write bursts +system.physmem.perBankWrBursts::3 7170 # Per bank write bursts +system.physmem.perBankWrBursts::4 7419 # Per bank write bursts +system.physmem.perBankWrBursts::5 7182 # Per bank write bursts +system.physmem.perBankWrBursts::6 7433 # Per bank write bursts +system.physmem.perBankWrBursts::7 7180 # Per bank write bursts +system.physmem.perBankWrBursts::8 7611 # Per bank write bursts +system.physmem.perBankWrBursts::9 7217 # Per bank write bursts +system.physmem.perBankWrBursts::10 7107 # Per bank write bursts +system.physmem.perBankWrBursts::11 6660 # Per bank write bursts +system.physmem.perBankWrBursts::12 6804 # Per bank write bursts +system.physmem.perBankWrBursts::13 7009 # Per bank write bursts +system.physmem.perBankWrBursts::14 7096 # Per bank write bursts +system.physmem.perBankWrBursts::15 6827 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1196134740000 # Total gap between requests +system.physmem.totGap 1196138285000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 6849 # Read request sizes (log2) system.physmem.readPktSize::3 6488064 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 159532 # Read request sizes (log2) +system.physmem.readPktSize::6 159599 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 756836 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 64227 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 627903 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 474579 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 475456 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1579907 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1133019 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1127067 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1123495 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 24904 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 24218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 9367 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 9281 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 9166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 8936 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8867 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8833 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 8794 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 186 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 6 # What read queue length does an incoming req see +system.physmem.writePktSize::6 64268 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 628282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 475071 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 476093 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1580129 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1132007 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1126499 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1123122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 25082 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 24371 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 9325 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 9268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 9185 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 8944 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8860 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 8817 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 8783 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 173 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -183,29 +183,29 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5161 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 5161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5163 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 5163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see @@ -215,727 +215,726 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 74432 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 5818.973345 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 397.615709 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 13075.139994 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 25664 34.48% 34.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 15269 20.51% 54.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 3288 4.42% 59.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2378 3.19% 62.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1591 2.14% 64.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1326 1.78% 66.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 1035 1.39% 67.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1141 1.53% 69.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 724 0.97% 70.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 588 0.79% 71.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 595 0.80% 72.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 643 0.86% 72.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 322 0.43% 73.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 287 0.39% 73.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 216 0.29% 73.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 358 0.48% 74.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 180 0.24% 74.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 137 0.18% 74.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 142 0.19% 75.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 152 0.20% 75.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 122 0.16% 75.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 2272 3.05% 78.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 131 0.18% 78.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 156 0.21% 78.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 73 0.10% 78.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 70 0.09% 79.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 46 0.06% 79.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 130 0.17% 79.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 52 0.07% 79.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 26 0.03% 79.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 15 0.02% 79.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 134 0.18% 79.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 21 0.03% 79.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 20 0.03% 79.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 27 0.04% 79.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 25 0.03% 79.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 14 0.02% 79.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 24 0.03% 79.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 22 0.03% 79.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 90 0.12% 79.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 23 0.03% 79.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 8 0.01% 79.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 25 0.03% 80.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 35 0.05% 80.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 11 0.01% 80.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 26 0.03% 80.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 8 0.01% 80.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 105 0.14% 80.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 21 0.03% 80.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 6 0.01% 80.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 7 0.01% 80.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 41 0.06% 80.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 7 0.01% 80.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 9 0.01% 80.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 26 0.03% 80.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 85 0.11% 80.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 5 0.01% 80.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 20 0.03% 80.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 29 0.04% 80.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 86 0.12% 80.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 19 0.03% 80.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 4 0.01% 80.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 4 0.01% 80.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 202 0.27% 81.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 3 0.00% 81.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 6 0.01% 81.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 17 0.02% 81.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 18 0.02% 81.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 2 0.00% 81.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 18 0.02% 81.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 2 0.00% 81.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 20 0.03% 81.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 17 0.02% 81.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 3 0.00% 81.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 2 0.00% 81.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 92 0.12% 81.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 4 0.01% 81.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 6 0.01% 81.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 17 0.02% 81.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 96 0.13% 81.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 3 0.00% 81.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 19 0.03% 81.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 30 0.04% 81.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 172 0.23% 81.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 59 0.08% 81.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 8 0.01% 81.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 1 0.00% 81.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 88 0.12% 81.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 2 0.00% 81.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 223 0.30% 82.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 1 0.00% 82.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 29 0.04% 82.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 2 0.00% 82.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 1 0.00% 82.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 24 0.03% 82.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 22 0.03% 82.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 74541 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 5810.577695 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 397.196541 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 13066.067638 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 25758 34.56% 34.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 15237 20.44% 55.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 3243 4.35% 59.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2416 3.24% 62.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1619 2.17% 64.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1307 1.75% 66.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 1041 1.40% 67.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1103 1.48% 69.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 718 0.96% 70.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 614 0.82% 71.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 577 0.77% 71.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 705 0.95% 72.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 343 0.46% 73.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 280 0.38% 73.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 211 0.28% 74.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 365 0.49% 74.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 178 0.24% 74.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 141 0.19% 74.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 142 0.19% 75.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 160 0.21% 75.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 121 0.16% 75.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 2248 3.02% 78.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 145 0.19% 78.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 165 0.22% 78.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 59 0.08% 79.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 66 0.09% 79.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 46 0.06% 79.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 116 0.16% 79.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 53 0.07% 79.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 27 0.04% 79.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 17 0.02% 79.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 120 0.16% 79.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 17 0.02% 79.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 20 0.03% 79.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 29 0.04% 79.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 31 0.04% 79.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 12 0.02% 79.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 26 0.03% 79.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 23 0.03% 79.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 90 0.12% 79.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 24 0.03% 79.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 12 0.02% 79.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 29 0.04% 80.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 36 0.05% 80.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 10 0.01% 80.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 25 0.03% 80.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 10 0.01% 80.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 133 0.18% 80.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 21 0.03% 80.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 12 0.02% 80.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 14 0.02% 80.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 45 0.06% 80.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 4 0.01% 80.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 9 0.01% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 21 0.03% 80.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 88 0.12% 80.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 4 0.01% 80.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 17 0.02% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 31 0.04% 80.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 79 0.11% 80.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 18 0.02% 80.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 3 0.00% 80.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 4 0.01% 80.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 183 0.25% 81.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 2 0.00% 81.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 2 0.00% 81.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 17 0.02% 81.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 24 0.03% 81.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 3 0.00% 81.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 18 0.02% 81.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 3 0.00% 81.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 17 0.02% 81.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 18 0.02% 81.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 2 0.00% 81.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 4 0.01% 81.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 95 0.13% 81.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 11 0.01% 81.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 5 0.01% 81.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 15 0.02% 81.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 100 0.13% 81.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 3 0.00% 81.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 19 0.03% 81.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 4 0.01% 81.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 16 0.02% 81.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 174 0.23% 81.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 59 0.08% 81.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 9 0.01% 81.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 1 0.00% 81.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 93 0.12% 82.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 3 0.00% 82.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 214 0.29% 82.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 32 0.04% 82.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 2 0.00% 82.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 2 0.00% 82.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 12 0.02% 82.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 17 0.02% 82.39% # Bytes accessed per row activation system.physmem.bytesPerActivate::7040-7047 1 0.00% 82.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 1 0.00% 82.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 158 0.21% 82.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 160 0.21% 82.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7239 1 0.00% 82.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::7360-7367 1 0.00% 82.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 33 0.04% 82.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7623 1 0.00% 82.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 14 0.02% 82.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7751 1 0.00% 82.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7815 1 0.00% 82.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 10 0.01% 82.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 260 0.35% 83.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8391 1 0.00% 83.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 7 0.01% 83.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 14 0.02% 83.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 33 0.04% 83.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9095 1 0.00% 83.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9159 1 0.00% 83.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 155 0.21% 83.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9280-9287 2 0.00% 83.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 19 0.03% 83.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9671 1 0.00% 83.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 22 0.03% 83.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 27 0.04% 83.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 223 0.30% 83.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10368-10375 1 0.00% 83.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 89 0.12% 83.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 6 0.01% 83.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 22 0.03% 83.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11072-11079 1 0.00% 83.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11136-11143 2 0.00% 83.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11200-11207 1 0.00% 83.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 98 0.13% 84.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 76 0.10% 84.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11648-11655 1 0.00% 84.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 19 0.03% 84.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11904-11911 1 0.00% 84.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 15 0.02% 84.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 169 0.23% 84.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12359 1 0.00% 84.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12423 1 0.00% 84.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12480-12487 1 0.00% 84.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 85 0.11% 84.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 80 0.11% 84.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 20 0.03% 84.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13191 1 0.00% 84.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 90 0.12% 84.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13504-13511 1 0.00% 84.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 22 0.03% 84.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 82 0.11% 84.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14016-14023 1 0.00% 84.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 7 0.01% 84.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14215 2 0.00% 84.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14279 1 0.00% 84.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 95 0.13% 85.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 100 0.13% 85.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14663 2 0.00% 85.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 74 0.10% 85.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15047 1 0.00% 85.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 18 0.02% 85.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 105 0.14% 85.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15495 1 0.00% 85.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 76 0.10% 85.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 18 0.02% 85.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16007 1 0.00% 85.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16071 1 0.00% 85.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 76 0.10% 85.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16263 1 0.00% 85.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 161 0.22% 85.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16519 2 0.00% 85.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 77 0.10% 86.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16768-16775 1 0.00% 86.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 23 0.03% 86.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17031 2 0.00% 86.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 72 0.10% 86.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 107 0.14% 86.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17536-17543 1 0.00% 86.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 15 0.02% 86.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 76 0.10% 86.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18112-18119 1 0.00% 86.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 97 0.13% 86.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 102 0.14% 86.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18624-18631 2 0.00% 86.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 4 0.01% 86.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18752-18759 1 0.00% 86.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 78 0.10% 86.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 26 0.03% 86.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19328-19335 2 0.00% 86.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19392-19399 1 0.00% 86.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 82 0.11% 86.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 16 0.02% 86.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 83 0.11% 87.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 81 0.11% 87.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20352-20359 2 0.00% 87.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 176 0.24% 87.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20608-20615 2 0.00% 87.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 17 0.02% 87.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 12 0.02% 87.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21056-21063 1 0.00% 87.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 73 0.10% 87.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21376-21383 2 0.00% 87.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 87 0.12% 87.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21696-21703 1 0.00% 87.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 23 0.03% 87.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 10 0.01% 87.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 89 0.12% 87.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22400-22407 1 0.00% 87.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 223 0.30% 88.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 27 0.04% 88.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22848-22855 1 0.00% 88.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 22 0.03% 88.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 25 0.03% 88.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 23 0.03% 82.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7623 1 0.00% 82.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 12 0.02% 82.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7751 1 0.00% 82.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 24 0.03% 82.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8007 1 0.00% 82.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 265 0.36% 83.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 29 0.04% 83.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8640-8647 1 0.00% 83.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 17 0.02% 83.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 27 0.04% 83.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9095 1 0.00% 83.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 153 0.21% 83.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 18 0.02% 83.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9671 1 0.00% 83.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 16 0.02% 83.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 33 0.04% 83.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10048-10055 1 0.00% 83.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10176-10183 1 0.00% 83.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 214 0.29% 83.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10368-10375 1 0.00% 83.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 86 0.12% 83.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10560-10567 1 0.00% 83.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10624-10631 2 0.00% 83.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 12 0.02% 83.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 17 0.02% 83.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11143 1 0.00% 83.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 106 0.14% 84.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11328-11335 1 0.00% 84.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11392-11399 1 0.00% 84.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 81 0.11% 84.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 14 0.02% 84.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 16 0.02% 84.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12096-12103 3 0.00% 84.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12224-12231 1 0.00% 84.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 158 0.21% 84.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12423 1 0.00% 84.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12480-12487 1 0.00% 84.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 76 0.10% 84.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 84 0.11% 84.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 29 0.04% 84.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13191 1 0.00% 84.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 105 0.14% 84.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13376-13383 1 0.00% 84.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 26 0.03% 84.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 82 0.11% 84.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 13 0.02% 84.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 92 0.12% 85.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 80 0.11% 85.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 81 0.11% 85.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14919 1 0.00% 85.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 16 0.02% 85.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 110 0.15% 85.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15495 1 0.00% 85.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 77 0.10% 85.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15815 1 0.00% 85.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 13 0.02% 85.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 82 0.11% 85.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16263 3 0.00% 85.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 155 0.21% 85.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 83 0.11% 86.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 8 0.01% 86.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17024-17031 2 0.00% 86.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 77 0.10% 86.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 119 0.16% 86.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 21 0.03% 86.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 82 0.11% 86.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17984-17991 1 0.00% 86.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 80 0.11% 86.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18368-18375 1 0.00% 86.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 83 0.11% 86.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18496-18503 3 0.00% 86.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 10 0.01% 86.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18880-18887 1 0.00% 86.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 83 0.11% 86.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 26 0.03% 86.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19328-19335 2 0.00% 86.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 103 0.14% 86.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19584-19591 1 0.00% 86.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19648-19655 1 0.00% 86.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 25 0.03% 87.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19904-19911 1 0.00% 87.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 80 0.11% 87.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20160-20167 1 0.00% 87.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 73 0.10% 87.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 155 0.21% 87.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20608-20615 1 0.00% 87.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 19 0.03% 87.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 16 0.02% 87.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 81 0.11% 87.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21376-21383 2 0.00% 87.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 95 0.13% 87.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 10 0.01% 87.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 9 0.01% 87.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 89 0.12% 87.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22400-22407 1 0.00% 87.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22464-22471 1 0.00% 87.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 219 0.29% 88.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 30 0.04% 88.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22912-22919 1 0.00% 88.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 13 0.02% 88.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 21 0.03% 88.25% # Bytes accessed per row activation system.physmem.bytesPerActivate::23424-23431 2 0.00% 88.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 145 0.19% 88.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 145 0.19% 88.45% # Bytes accessed per row activation system.physmem.bytesPerActivate::23680-23687 1 0.00% 88.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 30 0.04% 88.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 16 0.02% 88.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24128-24135 1 0.00% 88.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 8 0.01% 88.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 269 0.36% 88.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24704-24711 1 0.00% 88.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 5 0.01% 88.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 15 0.02% 88.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 32 0.04% 88.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25472-25479 2 0.00% 88.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25536-25543 1 0.00% 88.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 144 0.19% 89.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25664-25671 1 0.00% 89.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25792-25799 1 0.00% 89.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 22 0.03% 89.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25920-25927 1 0.00% 89.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 20 0.03% 89.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26176-26183 2 0.00% 89.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 26 0.03% 89.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26432-26439 1 0.00% 89.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26496-26503 1 0.00% 89.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 224 0.30% 89.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 85 0.11% 89.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26944-26951 1 0.00% 89.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 6 0.01% 89.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 26 0.03% 89.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27456-27463 2 0.00% 89.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 89 0.12% 89.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27712-27719 1 0.00% 89.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 73 0.10% 89.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 18 0.02% 89.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 16 0.02% 89.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28480-28487 1 0.00% 89.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28544-28551 1 0.00% 89.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 161 0.22% 90.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28800-28807 1 0.00% 90.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28864-28871 2 0.00% 90.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 84 0.11% 90.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 80 0.11% 90.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 15 0.02% 90.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 89 0.12% 90.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 19 0.03% 90.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 82 0.11% 90.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30272-30279 2 0.00% 90.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 5 0.01% 90.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30528-30535 1 0.00% 90.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30592-30599 1 0.00% 90.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30656-30663 1 0.00% 90.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 93 0.12% 90.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30784-30791 1 0.00% 90.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 97 0.13% 90.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31104-31111 1 0.00% 90.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 74 0.10% 91.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31296-31303 1 0.00% 91.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 16 0.02% 91.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 105 0.14% 91.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31872-31879 1 0.00% 91.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31936-31943 2 0.00% 91.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 73 0.10% 91.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 21 0.03% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 75 0.10% 91.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32640-32647 1 0.00% 91.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32704-32711 1 0.00% 91.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 157 0.21% 91.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32832-32839 1 0.00% 91.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32896-32903 1 0.00% 91.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 81 0.11% 91.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 29 0.04% 91.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33344-33351 2 0.00% 91.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 73 0.10% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33664-33671 1 0.00% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 105 0.14% 92.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33920-33927 1 0.00% 92.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 16 0.02% 92.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 71 0.10% 92.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34432-34439 1 0.00% 92.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 97 0.13% 92.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34752-34759 1 0.00% 92.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 90 0.12% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34944-34951 1 0.00% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35008-35015 1 0.00% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 3 0.00% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 81 0.11% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35591 18 0.02% 92.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 87 0.12% 92.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 13 0.02% 92.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36224-36231 1 0.00% 92.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 79 0.11% 92.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 84 0.11% 92.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36672-36679 2 0.00% 92.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 156 0.21% 93.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36992-36999 1 0.00% 93.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37056-37063 1 0.00% 93.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 14 0.02% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 16 0.02% 93.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 75 0.10% 93.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 86 0.12% 93.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38080-38087 1 0.00% 93.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 24 0.03% 93.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 6 0.01% 93.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38528-38535 1 0.00% 93.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38592-38599 1 0.00% 93.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 85 0.11% 93.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 221 0.30% 93.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39104-39111 1 0.00% 93.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 25 0.03% 93.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39360-39367 3 0.00% 93.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 18 0.02% 93.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39552-39559 2 0.00% 93.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39616-39623 1 0.00% 93.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 20 0.03% 93.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 142 0.19% 94.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40000-40007 1 0.00% 94.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 32 0.04% 94.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 14 0.02% 94.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 5 0.01% 94.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 265 0.36% 94.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 6 0.01% 94.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41408-41415 1 0.00% 94.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 13 0.02% 94.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41600-41607 2 0.00% 94.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 31 0.04% 94.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41856-41863 1 0.00% 94.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 146 0.20% 94.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 24 0.03% 94.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 20 0.03% 94.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 27 0.04% 94.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 221 0.30% 95.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 85 0.11% 95.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 9 0.01% 95.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43648-43655 2 0.00% 95.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 22 0.03% 95.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43840-43847 1 0.00% 95.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 84 0.11% 95.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44224-44231 1 0.00% 95.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 73 0.10% 95.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44480-44487 1 0.00% 95.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 13 0.02% 95.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 17 0.02% 95.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44928-44935 1 0.00% 95.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 166 0.22% 95.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45184-45191 1 0.00% 95.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 79 0.11% 95.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45376-45383 1 0.00% 95.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 82 0.11% 96.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45696-45703 2 0.00% 96.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 15 0.02% 96.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 87 0.12% 96.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46144-46151 1 0.00% 96.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 22 0.03% 96.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 79 0.11% 96.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 6 0.01% 96.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46912-46919 1 0.00% 96.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46976-46983 1 0.00% 96.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 93 0.12% 96.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47232-47239 1 0.00% 96.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 101 0.14% 96.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47424-47431 1 0.00% 96.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 79 0.11% 96.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 16 0.02% 96.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48000-48007 2 0.00% 96.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 127 0.17% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48192-48199 1 0.00% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48256-48263 1 0.00% 96.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 87 0.12% 97.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 17 0.02% 97.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48704-48711 1 0.00% 97.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48768-48775 11 0.01% 97.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 76 0.10% 97.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 12 0.02% 97.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 3 0.00% 97.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 5 0.01% 97.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 2061 2.77% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 74432 # Bytes accessed per row activation -system.physmem.totQLat 159552537250 # Total ticks spent queuing -system.physmem.totMemAccLat 202473692250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 33269920000 # Total ticks spent in databus transfers -system.physmem.totBankLat 9651235000 # Total ticks spent accessing banks -system.physmem.avgQLat 23978.50 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1450.44 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::23808-23815 22 0.03% 88.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23872-23879 1 0.00% 88.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24000-24007 1 0.00% 88.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 13 0.02% 88.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 23 0.03% 88.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24384-24391 3 0.00% 88.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 273 0.37% 88.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 26 0.03% 88.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24896-24903 2 0.00% 88.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24960-24967 1 0.00% 88.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 15 0.02% 88.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 24 0.03% 88.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25472-25479 2 0.00% 88.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 143 0.19% 89.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25664-25671 1 0.00% 89.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 19 0.03% 89.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 12 0.02% 89.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 28 0.04% 89.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26432-26439 1 0.00% 89.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26496-26503 2 0.00% 89.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 214 0.29% 89.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 90 0.12% 89.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 12 0.02% 89.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27200-27207 1 0.00% 89.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27264-27271 1 0.00% 89.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 13 0.02% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27456-27463 1 0.00% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27584-27591 1 0.00% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 92 0.12% 89.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 79 0.11% 89.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 14 0.02% 89.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28352-28359 1 0.00% 89.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 19 0.03% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28480-28487 1 0.00% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28608-28615 1 0.00% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 159 0.21% 90.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28800-28807 1 0.00% 90.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 74 0.10% 90.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29120-29127 1 0.00% 90.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 82 0.11% 90.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 26 0.03% 90.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29504-29511 2 0.00% 90.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 92 0.12% 90.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29888-29895 1 0.00% 90.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 27 0.04% 90.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 80 0.11% 90.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30272-30279 1 0.00% 90.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 9 0.01% 90.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30528-30535 2 0.00% 90.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 85 0.11% 90.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 81 0.11% 90.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31104-31111 1 0.00% 90.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 79 0.11% 91.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 18 0.02% 91.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31552-31559 1 0.00% 91.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31616-31623 1 0.00% 91.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 112 0.15% 91.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31936-31943 1 0.00% 91.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 76 0.10% 91.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 8 0.01% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32320-32327 1 0.00% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32384-32391 1 0.00% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32448-32455 1 0.00% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 82 0.11% 91.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 154 0.21% 91.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 83 0.11% 91.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33088-33095 1 0.00% 91.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33152-33159 1 0.00% 91.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33216-33223 2 0.00% 91.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 23 0.03% 91.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33344-33351 1 0.00% 91.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 76 0.10% 91.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33600-33607 1 0.00% 91.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 112 0.15% 92.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33920-33927 2 0.00% 92.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33984-33991 1 0.00% 92.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 18 0.02% 92.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 79 0.11% 92.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34432-34439 1 0.00% 92.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 80 0.11% 92.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 78 0.10% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34880-34887 1 0.00% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35008-35015 2 0.00% 92.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 8 0.01% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 80 0.11% 92.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 27 0.04% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35648-35655 1 0.00% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 91 0.12% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36032-36039 1 0.00% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 24 0.03% 92.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36224-36231 1 0.00% 92.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 82 0.11% 92.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 73 0.10% 92.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 149 0.20% 93.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 15 0.02% 93.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 14 0.02% 93.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 80 0.11% 93.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 93 0.12% 93.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37952-37959 1 0.00% 93.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38080-38087 1 0.00% 93.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 10 0.01% 93.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38272-38279 1 0.00% 93.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38336-38343 1 0.00% 93.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 11 0.01% 93.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38528-38535 1 0.00% 93.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 90 0.12% 93.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 212 0.28% 93.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39040-39047 1 0.00% 93.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39104-39111 1 0.00% 93.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 27 0.04% 93.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 11 0.01% 93.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39552-39559 1 0.00% 93.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 20 0.03% 93.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39872-39879 1 0.00% 93.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 144 0.19% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 21 0.03% 94.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 14 0.02% 94.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40576-40583 1 0.00% 94.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40640-40647 1 0.00% 94.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 25 0.03% 94.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 269 0.36% 94.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41152-41159 2 0.00% 94.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 23 0.03% 94.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 10 0.01% 94.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41600-41607 1 0.00% 94.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 23 0.03% 94.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41856-41863 1 0.00% 94.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 146 0.20% 94.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 21 0.03% 94.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 11 0.01% 94.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42624-42631 1 0.00% 94.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42688-42695 1 0.00% 94.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 31 0.04% 94.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 219 0.29% 95.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43072-43079 1 0.00% 95.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 87 0.12% 95.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 9 0.01% 95.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 1 0.00% 95.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 11 0.01% 95.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 92 0.12% 95.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 80 0.11% 95.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 18 0.02% 95.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 17 0.02% 95.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44928-44935 1 0.00% 95.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 149 0.20% 95.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 71 0.10% 95.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 78 0.10% 96.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45696-45703 1 0.00% 96.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 27 0.04% 96.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45888-45895 1 0.00% 96.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45952-45959 1 0.00% 96.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 99 0.13% 96.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 27 0.04% 96.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 83 0.11% 96.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46656-46663 1 0.00% 96.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 11 0.01% 96.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 90 0.12% 96.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47168-47175 1 0.00% 96.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 82 0.11% 96.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47552-47559 1 0.00% 96.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 83 0.11% 96.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47680-47687 1 0.00% 96.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 18 0.02% 96.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48000-48007 1 0.00% 96.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 130 0.17% 96.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48192-48199 2 0.00% 96.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48256-48263 1 0.00% 96.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48320-48327 2 0.00% 96.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 100 0.13% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48576-48583 1 0.00% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 6 0.01% 97.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 13 0.02% 97.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 79 0.11% 97.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 5 0.01% 97.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 5 0.01% 97.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 6 0.01% 97.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 2052 2.75% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 74541 # Bytes accessed per row activation +system.physmem.totQLat 159547739500 # Total ticks spent queuing +system.physmem.totMemAccLat 202481649500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 33270135000 # Total ticks spent in databus transfers +system.physmem.totBankLat 9663775000 # Total ticks spent accessing banks +system.physmem.avgQLat 23977.62 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1452.32 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30428.94 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 356.02 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 6.07 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.95 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30429.94 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 356.03 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 6.08 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.96 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 5.97 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.83 # Data bus utilization in percentage system.physmem.busUtilRead 2.78 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.50 # Average write queue length when enqueuing -system.physmem.readRowHits 6598277 # Number of row buffer hits during reads -system.physmem.writeRowHits 94784 # Number of row buffer hits during writes +system.physmem.avgWrQLen 12.60 # Average write queue length when enqueuing +system.physmem.readRowHits 6598250 # Number of row buffer hits during reads +system.physmem.writeRowHits 94811 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.16 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.49 # Row buffer hit rate for writes -system.physmem.avgGap 160007.15 # Average gap between requests +system.physmem.writeRowHitRate 83.48 # Row buffer hit rate for writes +system.physmem.avgGap 160005.31 # Average gap between requests system.physmem.pageHitRate 98.90 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 4.90 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 59936382 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 7703367 # Transaction distribution -system.membus.trans_dist::ReadResp 7703367 # Transaction distribution -system.membus.trans_dist::WriteReq 767572 # Transaction distribution -system.membus.trans_dist::WriteResp 767572 # Transaction distribution -system.membus.trans_dist::Writeback 64227 # Transaction distribution -system.membus.trans_dist::UpgradeReq 31703 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 17214 # Transaction distribution -system.membus.trans_dist::UpgradeResp 12043 # Transaction distribution -system.membus.trans_dist::ReadExReq 137706 # Transaction distribution -system.membus.trans_dist::ReadExResp 137264 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382576 # Packet count per connected master and slave (bytes) +system.physmem.prechargeAllPercent 4.94 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 59942042 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 7703387 # Transaction distribution +system.membus.trans_dist::ReadResp 7703387 # Transaction distribution +system.membus.trans_dist::WriteReq 767577 # Transaction distribution +system.membus.trans_dist::WriteResp 767577 # Transaction distribution +system.membus.trans_dist::Writeback 64268 # Transaction distribution +system.membus.trans_dist::UpgradeReq 31533 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 17272 # Transaction distribution +system.membus.trans_dist::UpgradeResp 12040 # Transaction distribution +system.membus.trans_dist::ReadExReq 137758 # Transaction distribution +system.membus.trans_dist::ReadExResp 137334 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382660 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 10320 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 10292 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 910 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1972063 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4365907 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1972105 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4366005 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 17342035 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389894 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 17342133 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390026 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 20640 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 20584 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1820 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17375316 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19787746 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17382228 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19794734 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 71692258 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 71692258 # Total data (bytes) +system.membus.tot_pkt_size::total 71699246 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 71699246 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1224733500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1224801500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 9246500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 9220500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) system.membus.reqLayer5.occupancy 782500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 9211003500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 9211496500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 5080947314 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5081612097 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.respLayer2.occupancy 14657701499 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 14657936499 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 69413 # number of replacements -system.l2c.tags.tagsinuse 53013.525953 # Cycle average of tags in use -system.l2c.tags.total_refs 1672541 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 134599 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 12.426103 # Average number of references to valid blocks. +system.l2c.tags.replacements 69480 # number of replacements +system.l2c.tags.tagsinuse 52958.538682 # Cycle average of tags in use +system.l2c.tags.total_refs 1674406 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 134639 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 12.436263 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 40184.108166 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 40140.336267 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000411 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001543 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3710.656491 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4243.565236 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.742460 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001689 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2809.342303 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2063.107654 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.613161 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001545 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3711.388388 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4232.378884 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.742427 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001688 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2812.770235 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2058.918835 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.612493 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.056620 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.064752 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.056631 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.064581 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.042867 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.031481 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.808922 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.042919 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.031417 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.808083 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65181 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65154 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1920 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 8037 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55165 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1929 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 8108 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55070 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994583 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17211018 # Number of tag accesses -system.l2c.tags.data_accesses 17211018 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 3808 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1739 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 419108 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 205927 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5506 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1908 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 464853 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 143402 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1246251 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 571037 # number of Writeback hits -system.l2c.Writeback_hits::total 571037 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1156 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 566 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1722 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 216 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 102 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 318 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 56302 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 52763 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 109065 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 3808 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1739 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 419108 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 262229 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5506 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1908 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 464853 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 196165 # number of demand (read+write) hits -system.l2c.demand_hits::total 1355316 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 3808 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 1739 # number of overall hits -system.l2c.overall_hits::cpu0.inst 419108 # number of overall hits -system.l2c.overall_hits::cpu0.data 262229 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5506 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1908 # number of overall hits -system.l2c.overall_hits::cpu1.inst 464853 # number of overall hits -system.l2c.overall_hits::cpu1.data 196165 # number of overall hits -system.l2c.overall_hits::total 1355316 # number of overall hits +system.l2c.tags.occ_task_id_percent::1024 0.994171 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 17216542 # Number of tag accesses +system.l2c.tags.data_accesses 17216542 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 3810 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 1731 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 419647 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 206017 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 5550 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1931 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 464603 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 143237 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1246526 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 570959 # number of Writeback hits +system.l2c.Writeback_hits::total 570959 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1148 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 589 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1737 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 220 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 100 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 320 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 56693 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 52725 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 109418 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 3810 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 1731 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 419647 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 262710 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 5550 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 1931 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 464603 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 195962 # number of demand (read+write) hits +system.l2c.demand_hits::total 1355944 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 3810 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 1731 # number of overall hits +system.l2c.overall_hits::cpu0.inst 419647 # number of overall hits +system.l2c.overall_hits::cpu0.data 262710 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 5550 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 1931 # number of overall hits +system.l2c.overall_hits::cpu1.inst 464603 # number of overall hits +system.l2c.overall_hits::cpu1.data 195962 # number of overall hits +system.l2c.overall_hits::total 1355944 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 5729 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 7851 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 5732 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 7847 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 5067 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 3614 # number of ReadReq misses -system.l2c.ReadReq_misses::total 22269 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 4919 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3647 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 8566 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 560 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 475 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1035 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 67124 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 72582 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 139706 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu1.inst 5061 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 3618 # number of ReadReq misses +system.l2c.ReadReq_misses::total 22266 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 4882 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3680 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 8562 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 571 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 474 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1045 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 67309 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 72458 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 139767 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 5729 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 74975 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 5732 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 75156 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 5067 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 76196 # number of demand (read+write) misses -system.l2c.demand_misses::total 161975 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 5061 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 76076 # number of demand (read+write) misses +system.l2c.demand_misses::total 162033 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 5729 # number of overall misses -system.l2c.overall_misses::cpu0.data 74975 # number of overall misses +system.l2c.overall_misses::cpu0.inst 5732 # number of overall misses +system.l2c.overall_misses::cpu0.data 75156 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 5067 # number of overall misses -system.l2c.overall_misses::cpu1.data 76196 # number of overall misses -system.l2c.overall_misses::total 161975 # number of overall misses +system.l2c.overall_misses::cpu1.inst 5061 # number of overall misses +system.l2c.overall_misses::cpu1.data 76076 # number of overall misses +system.l2c.overall_misses::total 162033 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 32000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 149500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 409309750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 588242499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 403588750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 587952999 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 347000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.itb.walker 74500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 364513250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 283018000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1645686499 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 13362921 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 11997484 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 25360405 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1671428 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2463894 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 4135322 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 4512260183 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 5472708624 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9984968807 # number of ReadExReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 364948250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 284058750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1641151749 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 13131433 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 12135478 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 25266911 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1819924 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2531891 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 4351815 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 4527558160 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 5454938401 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9982496561 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu0.dtb.walker 32000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 149500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 409309750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 5100502682 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 403588750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 5115511159 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 347000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.itb.walker 74500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 364513250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 5755726624 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 11630655306 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 364948250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 5738997151 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 11623648310 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.dtb.walker 32000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 149500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 409309750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 5100502682 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 403588750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 5115511159 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 347000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.itb.walker 74500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 364513250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 5755726624 # number of overall miss cycles -system.l2c.overall_miss_latency::total 11630655306 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 3809 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 1741 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 424837 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 213778 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 5510 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 1909 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 469920 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 147016 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1268520 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 571037 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 571037 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 6075 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 4213 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 10288 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 776 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 577 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1353 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 123426 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 125345 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 248771 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 3809 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 1741 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 424837 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 337204 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 5510 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 1909 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 469920 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 272361 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1517291 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 3809 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 1741 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 424837 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 337204 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 5510 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 1909 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 469920 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 272361 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1517291 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000263 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001149 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.013485 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.036725 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000726 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000524 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010783 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.024582 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.017555 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.809712 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.865654 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.832621 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.721649 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.823224 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.764967 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.543840 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.579058 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.561585 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000263 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.001149 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.013485 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.222343 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000726 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.000524 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.010783 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.279761 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.106753 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000263 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.001149 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.013485 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.222343 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000726 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.000524 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.010783 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.279761 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.106753 # miss rate for overall accesses +system.l2c.overall_miss_latency::cpu1.inst 364948250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 5738997151 # number of overall miss cycles +system.l2c.overall_miss_latency::total 11623648310 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 3811 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 1733 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 425379 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 213864 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 5554 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 1932 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 469664 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 146855 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1268792 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 570959 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 570959 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 6030 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 4269 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 10299 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 791 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 574 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1365 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 124002 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 125183 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 249185 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 3811 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 1733 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 425379 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 337866 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 5554 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 1932 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 469664 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 272038 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1517977 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 3811 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 1733 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 425379 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 337866 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 5554 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 1932 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 469664 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 272038 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1517977 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000262 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001154 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.013475 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.036692 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000720 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000518 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.010776 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.024637 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.017549 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.809619 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.862029 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.831343 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.721871 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.825784 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.765568 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.542806 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.578817 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.560897 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000262 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.001154 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.013475 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.222443 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000720 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.000518 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.010776 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.279652 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.106743 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000262 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.001154 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.013475 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.222443 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000720 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.000518 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.010776 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.279652 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.106743 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 32000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 71445.234770 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 74925.805502 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70409.760991 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 74927.105773 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 86750 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 74500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 71938.671798 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 78311.566132 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 73900.332256 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2716.593007 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3289.685769 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 2960.588956 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2984.692857 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5187.145263 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 3995.480193 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 67222.754648 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75400.355791 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 71471.295485 # average ReadExReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72109.909109 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 78512.645108 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 73706.626650 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2689.765055 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3297.684239 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 2951.052441 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3187.257443 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5341.542194 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 4164.416268 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 67265.271509 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75284.142552 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 71422.414168 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 32000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 71445.234770 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 68029.378886 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 70409.760991 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 68065.239755 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 86750 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 71938.671798 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 75538.435403 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 71805.249613 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 72109.909109 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 75437.682725 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 71736.302543 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 32000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 71445.234770 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 68029.378886 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 70409.760991 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 68065.239755 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 86750 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 71938.671798 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 75538.435403 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 71805.249613 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 72109.909109 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 75437.682725 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 71736.302543 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -944,8 +943,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 64227 # number of writebacks -system.l2c.writebacks::total 64227 # number of writebacks +system.l2c.writebacks::writebacks 64268 # number of writebacks +system.l2c.writebacks::total 64268 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits @@ -954,161 +953,161 @@ system.l2c.overall_mshr_hits::cpu0.inst 1 # nu system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 5728 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 7851 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 5731 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 7847 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 5067 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 3614 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 22268 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 4919 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 3647 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 8566 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 560 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 475 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1035 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 67124 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 72582 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 139706 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 5061 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 3618 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 22265 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 4882 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 3680 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 8562 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 571 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 474 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1045 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 67309 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 72458 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 139767 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 1 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 5728 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 74975 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 5731 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 75156 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 5067 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 76196 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 161974 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 5061 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 76076 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 162032 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 5728 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 74975 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 5731 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 75156 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 5067 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 76196 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 161974 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 5061 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 76076 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 162032 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 20000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 125000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 336674000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 490296499 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 330890500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 490057499 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 297000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 300318250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 238087000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1365880249 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 49210416 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 36526138 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 85736554 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5602558 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4753973 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 10356531 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3645878311 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4548664376 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 8194542687 # number of ReadExReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 300853250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 239085250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1361390999 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 48852378 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 36863673 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 85716051 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5720067 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4752971 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 10473038 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3658860326 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4532497595 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 8191357921 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 20000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 125000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 336674000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 4136174810 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 330890500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 4148917825 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 297000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 62500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 300318250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 4786751376 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 9560422936 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 300853250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 4771582845 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 9552748920 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 20000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 336674000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 4136174810 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 330890500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 4148917825 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 297000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 62500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 300318250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 4786751376 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 9560422936 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 300853250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 4771582845 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 9552748920 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 345201250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12449699492 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5636750 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154292835997 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167093373489 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1043988495 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 15722457655 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 16766446150 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12458267494 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5350750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154290476246 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167099295740 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1046790495 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 15722211628 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 16769002123 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 345201250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13493687987 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5636750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 170015293652 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 183859819639 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000263 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001149 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013483 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036725 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000524 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010783 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024582 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.017554 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.809712 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.865654 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.832621 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.721649 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.823224 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.764967 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.543840 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.579058 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.561585 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000263 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001149 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013483 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.222343 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000524 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010783 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.279761 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.106752 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000263 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001149 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013483 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.222343 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000524 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010783 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.279761 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.106752 # mshr miss rate for overall accesses +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13505057989 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5350750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 170012687874 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 183868297863 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000262 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001154 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013473 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036692 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000720 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000518 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010776 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024637 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.017548 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.809619 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.862029 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.831343 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.721871 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.825784 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.765568 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.542806 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.578817 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.560897 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000262 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001154 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013473 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.222443 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000720 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000518 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010776 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.279652 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.106742 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000262 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001154 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013473 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.222443 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000720 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000518 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010776 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.279652 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.106742 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58776.885475 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62450.197300 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 57736.956901 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62451.573722 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74250 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59269.439511 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65879.081350 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 61338.254401 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.150437 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10015.392926 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10008.936960 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.567857 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10008.364211 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10006.310145 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54315.569856 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62669.317131 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 58655.624576 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59445.415926 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66082.158651 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 61144.891040 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10006.632118 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10017.302446 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10011.218290 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10017.630473 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.364979 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10022.045933 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54359.154437 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62553.446065 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 58607.238626 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58776.885475 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55167.386596 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 57736.956901 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55204.079847 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74250 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59269.439511 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62821.557247 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 59024.429452 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59445.415926 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62721.263539 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 58955.940308 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58776.885475 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55167.386596 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 57736.956901 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55204.079847 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74250 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59269.439511 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62821.557247 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 59024.429452 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59445.415926 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62721.263539 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 58955.940308 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -1129,67 +1128,67 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 119505667 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2535246 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2535246 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 767572 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 767572 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 571037 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 30983 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 17532 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 48515 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 260644 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 260644 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 863518 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1226193 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6137 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 12684 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 940579 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4601780 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6235 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15427 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7672553 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27216160 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 41363346 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6964 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 15236 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30075316 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 39635324 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7636 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 22040 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 138342022 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 138342022 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4603396 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4759597686 # Layer occupancy (ticks) +system.toL2Bus.throughput 119544694 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2535779 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2535779 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 767577 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 767577 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 570959 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 30837 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 17592 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 48429 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 260947 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 260947 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 864602 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1227966 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6129 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 12680 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 940064 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4600791 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6258 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15477 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7673967 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27250848 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 41432384 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6932 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 15244 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30058932 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 39583066 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7728 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 22216 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 138377350 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 138377350 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4615184 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4759626187 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1923628472 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1926082966 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1753100289 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1756498781 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.toL2Bus.respLayer2.occupancy 4396000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 8875000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 8869000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 2118090473 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 2116921475 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 2927544636 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 2926499865 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) system.toL2Bus.respLayer8.occupancy 4326000 # Layer occupancy (ticks) system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer9.occupancy 9917499 # Layer occupancy (ticks) +system.toL2Bus.respLayer9.occupancy 9923499 # Layer occupancy (ticks) system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 45391376 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7671402 # Transaction distribution -system.iobus.trans_dist::ReadResp 7671402 # Transaction distribution -system.iobus.trans_dist::WriteReq 7950 # Transaction distribution -system.iobus.trans_dist::WriteResp 7950 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30460 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8060 # Packet count per connected master and slave (bytes) +system.iobus.throughput 45391348 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7671431 # Transaction distribution +system.iobus.trans_dist::ReadResp 7671431 # Transaction distribution +system.iobus.trans_dist::WriteReq 7963 # Transaction distribution +system.iobus.trans_dist::WriteResp 7963 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30550 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8056 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 742 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 496 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 494 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -1206,17 +1205,17 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382576 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382660 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 15358704 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40178 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 15358788 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40319 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16112 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1484 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 271 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1233,14 +1232,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2389894 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390026 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 54294406 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 54294406 # Total data (bytes) -system.iobus.reqLayer0.occupancy 21360000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 54294538 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 54294538 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21418000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4036000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4034000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1250,7 +1249,7 @@ system.iobus.reqLayer4.occupancy 27000 # La system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 298000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 297000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.1 # Layer utilization (%) @@ -1286,9 +1285,9 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374626000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374697000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17778333501 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17777962501 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -1313,25 +1312,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7064121 # DTB read hits -system.cpu0.dtb.read_misses 3756 # DTB read misses -system.cpu0.dtb.write_hits 5649416 # DTB write hits -system.cpu0.dtb.write_misses 801 # DTB write misses +system.cpu0.dtb.read_hits 7070497 # DTB read hits +system.cpu0.dtb.read_misses 3747 # DTB read misses +system.cpu0.dtb.write_hits 5655659 # DTB write hits +system.cpu0.dtb.write_misses 806 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1711 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1708 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 142 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7067877 # DTB read accesses -system.cpu0.dtb.write_accesses 5650217 # DTB write accesses +system.cpu0.dtb.read_accesses 7074244 # DTB read accesses +system.cpu0.dtb.write_accesses 5656465 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12713537 # DTB hits -system.cpu0.dtb.misses 4557 # DTB misses -system.cpu0.dtb.accesses 12718094 # DTB accesses +system.cpu0.dtb.hits 12726156 # DTB hits +system.cpu0.dtb.misses 4553 # DTB misses +system.cpu0.dtb.accesses 12730709 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1353,7 +1352,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 29561361 # ITB inst hits +system.cpu0.itb.inst_hits 29571351 # ITB inst hits system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -1370,88 +1369,88 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 29563566 # ITB inst accesses -system.cpu0.itb.hits 29561361 # DTB hits +system.cpu0.itb.inst_accesses 29573556 # ITB inst accesses +system.cpu0.itb.hits 29571351 # DTB hits system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 29563566 # DTB accesses -system.cpu0.numCycles 2392278482 # number of cpu cycles simulated +system.cpu0.itb.accesses 29573556 # DTB accesses +system.cpu0.numCycles 2392285746 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 28863304 # Number of instructions committed -system.cpu0.committedOps 37189208 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33114268 # Number of integer alu accesses +system.cpu0.committedInsts 28873226 # Number of instructions committed +system.cpu0.committedOps 37212709 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33137047 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1241816 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4372124 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33114268 # number of integer instructions +system.cpu0.num_func_calls 1242091 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4373605 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33137047 # number of integer instructions system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 192166322 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36246326 # number of times the integer registers were written +system.cpu0.num_int_register_reads 192300691 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36265278 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 13380719 # number of memory refs -system.cpu0.num_load_insts 7401377 # Number of load instructions -system.cpu0.num_store_insts 5979342 # Number of store instructions -system.cpu0.num_idle_cycles 2246536230.490122 # Number of idle cycles -system.cpu0.num_busy_cycles 145742251.509878 # Number of busy cycles -system.cpu0.not_idle_fraction 0.060922 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.939078 # Percentage of idle cycles -system.cpu0.Branches 5599941 # Number of branches fetched +system.cpu0.num_mem_refs 13394015 # number of memory refs +system.cpu0.num_load_insts 7407936 # Number of load instructions +system.cpu0.num_store_insts 5986079 # Number of store instructions +system.cpu0.num_idle_cycles 2246427166.466122 # Number of idle cycles +system.cpu0.num_busy_cycles 145858579.533878 # Number of busy cycles +system.cpu0.not_idle_fraction 0.060970 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.939030 # Percentage of idle cycles +system.cpu0.Branches 5601726 # Number of branches fetched system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 46939 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 424872 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.359183 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 29135959 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 425384 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 68.493312 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 76218358000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.359183 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994842 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.994842 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 46915 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 425414 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.356883 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 29145407 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 425926 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 68.428335 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 76234819000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.356883 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994838 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.994838 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 266 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 29986729 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 29986729 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 29135959 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29135959 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29135959 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29135959 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29135959 # number of overall hits -system.cpu0.icache.overall_hits::total 29135959 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 425385 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 425385 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 425385 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 425385 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 425385 # number of overall misses -system.cpu0.icache.overall_misses::total 425385 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5898245722 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5898245722 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5898245722 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5898245722 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5898245722 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5898245722 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 29561344 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 29561344 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 29561344 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 29561344 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 29561344 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 29561344 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014390 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014390 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014390 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014390 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014390 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014390 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13865.664567 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13865.664567 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13865.664567 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13865.664567 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13865.664567 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13865.664567 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 29997261 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 29997261 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 29145407 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 29145407 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29145407 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 29145407 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29145407 # number of overall hits +system.cpu0.icache.overall_hits::total 29145407 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 425927 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 425927 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 425927 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 425927 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 425927 # number of overall misses +system.cpu0.icache.overall_misses::total 425927 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5899388216 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5899388216 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5899388216 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5899388216 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5899388216 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5899388216 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 29571334 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 29571334 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 29571334 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 29571334 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 29571334 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 29571334 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014403 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014403 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014403 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014403 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014403 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014403 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13850.702623 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13850.702623 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13850.702623 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13850.702623 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13850.702623 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13850.702623 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1460,128 +1459,128 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425385 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 425385 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 425385 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 425385 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 425385 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 425385 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5045266278 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5045266278 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5045266278 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5045266278 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5045266278 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5045266278 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425927 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 425927 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 425927 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 425927 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 425927 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 425927 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5045293784 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5045293784 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5045293784 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5045293784 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5045293784 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5045293784 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 437016250 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 437016250 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 437016250 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 437016250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014390 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014390 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014390 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014390 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014390 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014390 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11860.470581 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11860.470581 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11860.470581 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11860.470581 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11860.470581 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11860.470581 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014403 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014403 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014403 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014403 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014403 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014403 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11845.442491 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11845.442491 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11845.442491 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11845.442491 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11845.442491 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11845.442491 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 329699 # number of replacements -system.cpu0.dcache.tags.tagsinuse 455.775151 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 12258801 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 330211 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 37.124145 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 330503 # number of replacements +system.cpu0.dcache.tags.tagsinuse 455.093016 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 12270625 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 331015 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 37.069695 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 667204250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 455.775151 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.890186 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.890186 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 455.093016 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.888854 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.888854 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 345 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 50852132 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 50852132 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6594161 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6594161 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5344638 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5344638 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 148004 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 148004 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149654 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 149654 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11938799 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11938799 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11938799 # number of overall hits -system.cpu0.dcache.overall_hits::total 11938799 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 227537 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 227537 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 141373 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 141373 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9339 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9339 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7481 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7481 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 368910 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 368910 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 368910 # number of overall misses -system.cpu0.dcache.overall_misses::total 368910 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3307426746 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 3307426746 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5667209233 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 5667209233 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 93091750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 93091750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44245560 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 44245560 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 8974635979 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 8974635979 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 8974635979 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 8974635979 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6821698 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6821698 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5486011 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5486011 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157343 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 157343 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157135 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 157135 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12307709 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12307709 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12307709 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12307709 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033355 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.033355 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025770 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.025770 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059354 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059354 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047609 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047609 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029974 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.029974 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029974 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.029974 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14535.775483 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14535.775483 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40086.927723 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 40086.927723 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9968.064033 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9968.064033 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5914.391124 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5914.391124 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24327.440240 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 24327.440240 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24327.440240 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 24327.440240 # average overall miss latency +system.cpu0.dcache.tags.tag_accesses 50903218 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 50903218 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6600273 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6600273 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5350518 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5350518 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147975 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 147975 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149621 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 149621 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11950791 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11950791 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11950791 # number of overall hits +system.cpu0.dcache.overall_hits::total 11950791 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 227769 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 227769 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 141711 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 141711 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9370 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9370 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7532 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7532 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 369480 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 369480 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 369480 # number of overall misses +system.cpu0.dcache.overall_misses::total 369480 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3309712250 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3309712250 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5686464712 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 5686464712 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 92538750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 92538750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44740069 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 44740069 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 8996176962 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 8996176962 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 8996176962 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 8996176962 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6828042 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6828042 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5492229 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5492229 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157345 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 157345 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157153 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 157153 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12320271 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12320271 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12320271 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12320271 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033358 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.033358 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025802 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.025802 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059551 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059551 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047928 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047928 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029990 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.029990 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029990 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029990 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14531.004000 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14531.004000 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40127.193457 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 40127.193457 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9876.067236 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9876.067236 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5939.998540 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5939.998540 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24348.210896 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 24348.210896 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24348.210896 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 24348.210896 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1590,62 +1589,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 305670 # number of writebacks -system.cpu0.dcache.writebacks::total 305670 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227537 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 227537 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141373 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 141373 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9339 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9339 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7479 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7479 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 368910 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 368910 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 368910 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 368910 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2850420254 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2850420254 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5353542767 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5353542767 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 74365250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 74365250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29286440 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29286440 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8203963021 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 8203963021 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8203963021 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 8203963021 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13556999000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13556999000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1167889500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1167889500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14724888500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14724888500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033355 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033355 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025770 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025770 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059354 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059354 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047596 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047596 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029974 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029974 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029974 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029974 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12527.282394 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12527.282394 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37868.212226 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37868.212226 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7962.870757 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7962.870757 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3915.822971 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3915.822971 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22238.386113 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22238.386113 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22238.386113 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22238.386113 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 306085 # number of writebacks +system.cpu0.dcache.writebacks::total 306085 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227769 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 227769 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141711 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 141711 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9370 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9370 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7530 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7530 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 369480 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 369480 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 369480 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 369480 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2852244750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2852244750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5372105288 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5372105288 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 73750250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 73750250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29678931 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29678931 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8224350038 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 8224350038 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8224350038 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 8224350038 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13565968500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13565968500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1170779500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1170779500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14736748000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14736748000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033358 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033358 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025802 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025802 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059551 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059551 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047915 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047915 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029990 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029990 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029990 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029990 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12522.532698 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12522.532698 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37908.879960 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37908.879960 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7870.891142 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7870.891142 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3941.425100 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3941.425100 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22259.256355 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22259.256355 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22259.256355 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22259.256355 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1676,25 +1675,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 8319266 # DTB read hits -system.cpu1.dtb.read_misses 3647 # DTB read misses -system.cpu1.dtb.write_hits 5834802 # DTB write hits -system.cpu1.dtb.write_misses 1433 # DTB write misses +system.cpu1.dtb.read_hits 8312417 # DTB read hits +system.cpu1.dtb.read_misses 3644 # DTB read misses +system.cpu1.dtb.write_hits 5828126 # DTB write hits +system.cpu1.dtb.write_misses 1438 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1863 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1864 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 139 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 8322913 # DTB read accesses -system.cpu1.dtb.write_accesses 5836235 # DTB write accesses +system.cpu1.dtb.read_accesses 8316061 # DTB read accesses +system.cpu1.dtb.write_accesses 5829564 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 14154068 # DTB hits -system.cpu1.dtb.misses 5080 # DTB misses -system.cpu1.dtb.accesses 14159148 # DTB accesses +system.cpu1.dtb.hits 14140543 # DTB hits +system.cpu1.dtb.misses 5082 # DTB misses +system.cpu1.dtb.accesses 14145625 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1716,7 +1715,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 33207997 # ITB inst hits +system.cpu1.itb.inst_hits 33196912 # ITB inst hits system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1733,87 +1732,87 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 33210168 # ITB inst accesses -system.cpu1.itb.hits 33207997 # DTB hits +system.cpu1.itb.inst_accesses 33199083 # ITB inst accesses +system.cpu1.itb.hits 33196912 # DTB hits system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 33210168 # DTB accesses -system.cpu1.numCycles 2390803785 # number of cpu cycles simulated +system.cpu1.itb.accesses 33199083 # DTB accesses +system.cpu1.numCycles 2390815191 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 32596932 # Number of instructions committed -system.cpu1.committedOps 41121940 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 37644247 # Number of integer alu accesses +system.cpu1.committedInsts 32585929 # Number of instructions committed +system.cpu1.committedOps 41097454 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 37620588 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 962790 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3735035 # number of instructions that are conditional controls -system.cpu1.num_int_insts 37644247 # number of integer instructions +system.cpu1.num_func_calls 962436 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3733629 # number of instructions that are conditional controls +system.cpu1.num_int_insts 37620588 # number of integer instructions system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 218344706 # number of times the integer registers were read -system.cpu1.num_int_register_writes 39781553 # number of times the integer registers were written +system.cpu1.num_int_register_reads 218203394 # number of times the integer registers were read +system.cpu1.num_int_register_writes 39762349 # number of times the integer registers were written system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 14692820 # number of memory refs -system.cpu1.num_load_insts 8641241 # Number of load instructions -system.cpu1.num_store_insts 6051579 # Number of store instructions -system.cpu1.num_idle_cycles 1874235342.195830 # Number of idle cycles -system.cpu1.num_busy_cycles 516568442.804169 # Number of busy cycles -system.cpu1.not_idle_fraction 0.216065 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.783935 # Percentage of idle cycles -system.cpu1.Branches 4947677 # Number of branches fetched +system.cpu1.num_mem_refs 14678716 # number of memory refs +system.cpu1.num_load_insts 8634369 # Number of load instructions +system.cpu1.num_store_insts 6044347 # Number of store instructions +system.cpu1.num_idle_cycles 1874341984.155535 # Number of idle cycles +system.cpu1.num_busy_cycles 516473206.844465 # Number of busy cycles +system.cpu1.not_idle_fraction 0.216024 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.783976 # Percentage of idle cycles +system.cpu1.Branches 4945874 # Number of branches fetched system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 44317 # number of quiesce instructions executed -system.cpu1.icache.tags.replacements 469929 # number of replacements -system.cpu1.icache.tags.tagsinuse 478.566840 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 32737552 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 470441 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 69.589071 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 93987616500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 478.566840 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.934701 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.934701 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 469670 # number of replacements +system.cpu1.icache.tags.tagsinuse 478.560169 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 32726726 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 470182 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 69.604379 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 94003216500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 478.560169 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.934688 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.934688 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 448 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 33678434 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 33678434 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 32737552 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 32737552 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 32737552 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 32737552 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 32737552 # number of overall hits -system.cpu1.icache.overall_hits::total 32737552 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 470441 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 470441 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 470441 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 470441 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 470441 # number of overall misses -system.cpu1.icache.overall_misses::total 470441 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6446126723 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6446126723 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6446126723 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6446126723 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6446126723 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6446126723 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 33207993 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 33207993 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 33207993 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 33207993 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 33207993 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 33207993 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014166 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.014166 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014166 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.014166 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014166 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.014166 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13702.306395 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13702.306395 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13702.306395 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13702.306395 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13702.306395 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13702.306395 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 33667090 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 33667090 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 32726726 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 32726726 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 32726726 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 32726726 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 32726726 # number of overall hits +system.cpu1.icache.overall_hits::total 32726726 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 470182 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 470182 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 470182 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 470182 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 470182 # number of overall misses +system.cpu1.icache.overall_misses::total 470182 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6443403725 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 6443403725 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 6443403725 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6443403725 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6443403725 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6443403725 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 33196908 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 33196908 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 33196908 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 33196908 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 33196908 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 33196908 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014163 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.014163 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014163 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.014163 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014163 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.014163 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13704.062948 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13704.062948 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13704.062948 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13704.062948 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13704.062948 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13704.062948 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1822,126 +1821,126 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 470441 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 470441 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 470441 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 470441 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 470441 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 470441 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5503297277 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5503297277 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5503297277 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5503297277 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5503297277 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5503297277 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7106250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 7106250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 7106250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 7106250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014166 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014166 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014166 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.014166 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014166 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.014166 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11698.166778 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11698.166778 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11698.166778 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11698.166778 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11698.166778 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11698.166778 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 470182 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 470182 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 470182 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 470182 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 470182 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 470182 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5501099275 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5501099275 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5501099275 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5501099275 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5501099275 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5501099275 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6820250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6820250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6820250 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 6820250 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014163 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014163 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014163 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.014163 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014163 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.014163 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11699.935929 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11699.935929 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11699.935929 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11699.935929 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11699.935929 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11699.935929 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 292485 # number of replacements -system.cpu1.dcache.tags.tagsinuse 471.346411 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 11976402 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 292833 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 40.898403 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 85276695250 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.346411 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920598 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.920598 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 333 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 15 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.679688 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 49497647 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 49497647 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 6954137 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 6954137 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4834149 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4834149 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 82001 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 82001 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82789 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 82789 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 11788286 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 11788286 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 11788286 # number of overall hits -system.cpu1.dcache.overall_hits::total 11788286 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 170721 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 170721 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 150254 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 150254 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11274 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 11274 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10054 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10054 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 320975 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 320975 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 320975 # number of overall misses -system.cpu1.dcache.overall_misses::total 320975 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2219304994 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2219304994 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6585994013 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 6585994013 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 97542000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 97542000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 52010474 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 52010474 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 8805299007 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 8805299007 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 8805299007 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 8805299007 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 7124858 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 7124858 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 4984403 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4984403 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 93275 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 93275 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92843 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 92843 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 12109261 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 12109261 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 12109261 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 12109261 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023961 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.023961 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030145 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.030145 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120868 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120868 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108290 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108290 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026507 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.026507 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026507 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.026507 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12999.601654 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12999.601654 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 43832.403883 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 43832.403883 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8651.942523 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8651.942523 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5173.112592 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5173.112592 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 27432.974553 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 27432.974553 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27432.974553 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 27432.974553 # average overall miss latency +system.cpu1.dcache.tags.replacements 292321 # number of replacements +system.cpu1.dcache.tags.tagsinuse 471.500981 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 11963226 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 292696 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 40.872530 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 85292295250 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.500981 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920900 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.920900 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 375 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 361 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.732422 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 49443351 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 49443351 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 6947316 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 6947316 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4827697 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4827697 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 82016 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 82016 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82738 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 82738 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 11775013 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 11775013 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 11775013 # number of overall hits +system.cpu1.dcache.overall_hits::total 11775013 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 170735 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 170735 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 150073 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 150073 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11224 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 11224 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10063 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10063 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 320808 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 320808 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 320808 # number of overall misses +system.cpu1.dcache.overall_misses::total 320808 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2220021998 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2220021998 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6568353267 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 6568353267 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 96536250 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 96536250 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 52014971 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 52014971 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 8788375265 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8788375265 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8788375265 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8788375265 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 7118051 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 7118051 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4977770 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4977770 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 93240 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 93240 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92801 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 92801 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 12095821 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 12095821 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 12095821 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 12095821 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023986 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.023986 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030149 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.030149 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120378 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120378 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108436 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108436 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026522 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.026522 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026522 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.026522 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13002.735221 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13002.735221 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 43767.721489 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 43767.721489 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8600.877584 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8600.877584 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5168.932823 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5168.932823 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 27394.501587 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 27394.501587 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27394.501587 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 27394.501587 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1950,62 +1949,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 265367 # number of writebacks -system.cpu1.dcache.writebacks::total 265367 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170721 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 170721 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150254 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 150254 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11274 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11274 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10053 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10053 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 320975 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 320975 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 320975 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 320975 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1877186006 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1877186006 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6262088987 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6262088987 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74982000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74982000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31903526 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31903526 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8139274993 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 8139274993 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8139274993 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 8139274993 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168608498500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168608498500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25182871345 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25182871345 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 193791369845 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 193791369845 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023961 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023961 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030145 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030145 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.120868 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120868 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108280 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108280 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026507 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026507 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026507 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026507 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10995.636190 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10995.636190 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 41676.687389 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 41676.687389 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6650.878127 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6650.878127 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3173.532876 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3173.532876 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25357.971783 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25357.971783 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25357.971783 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25357.971783 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 264874 # number of writebacks +system.cpu1.dcache.writebacks::total 264874 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170735 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 170735 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150073 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 150073 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11224 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11224 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10062 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10062 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 320808 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 320808 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 320808 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 320808 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1877877002 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1877877002 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6244849733 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6244849733 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74077750 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74077750 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31889029 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31889029 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8122726735 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 8122726735 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8122726735 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 8122726735 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168606064250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168606064250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25182609871 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25182609871 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 193788674121 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 193788674121 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023986 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023986 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030149 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030149 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.120378 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120378 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108426 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108426 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026522 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026522 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026522 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026522 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10998.781749 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10998.781749 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 41612.080341 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 41612.080341 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6599.942088 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6599.942088 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3169.253528 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3169.253528 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25319.589084 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25319.589084 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25319.589084 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25319.589084 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2029,10 +2028,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 651805197501 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 651805197501 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 651805197501 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 651805197501 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 651823594501 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 651823594501 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 651823594501 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 651823594501 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |