diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt | 2613 |
1 files changed, 1580 insertions, 1033 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 99dfbb1fa..7372967ce 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,147 +1,147 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.183438 # Number of seconds simulated -sim_ticks 1183437503500 # Number of ticks simulated -final_tick 1183437503500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.194897 # Number of seconds simulated +sim_ticks 1194896580500 # Number of ticks simulated +final_tick 1194896580500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 462248 # Simulator instruction rate (inst/s) -host_op_rate 589061 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8900686287 # Simulator tick rate (ticks/s) -host_mem_usage 440324 # Number of bytes of host memory used -host_seconds 132.96 # Real time elapsed on the host -sim_insts 61460532 # Number of instructions simulated -sim_ops 78321652 # Number of ops (including micro ops) simulated +host_inst_rate 311660 # Simulator instruction rate (inst/s) +host_op_rate 397163 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6068013925 # Simulator tick rate (ticks/s) +host_mem_usage 403588 # Number of bytes of host memory used +host_seconds 196.92 # Real time elapsed on the host +sim_insts 61371297 # Number of instructions simulated +sim_ops 78208202 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 393828 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4708980 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 323164 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4819184 # Number of bytes read from this memory -system.physmem.bytes_read::total 62150116 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 393828 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 323164 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 716992 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4119552 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7146896 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 463972 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6626100 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 255836 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2904240 # Number of bytes read from this memory +system.physmem.bytes_read::total 62155108 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 463972 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 255836 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 719808 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4136192 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 3027304 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory +system.physmem.bytes_written::total 7163536 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12372 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73650 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5131 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 75326 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6654550 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 64368 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 821204 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43859107 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 108 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 332783 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3979069 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 273072 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4072191 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52516602 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 332783 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 273072 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 605855 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3481005 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 14365 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2543729 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6039099 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3481005 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43859107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 108 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 332783 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3993434 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 216 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 273072 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6615920 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 58555700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6654550 # Total number of read requests seen -system.physmem.writeReqs 821204 # Total number of write requests seen -system.physmem.cpureqs 235817 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 425891200 # Total number of bytes read from memory -system.physmem.bytesWritten 52557056 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 62150116 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7146896 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 97 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 11788 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 422295 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 415695 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 415259 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 415928 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 415873 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 415149 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 415167 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 415977 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 415766 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 415145 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 415183 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 415709 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 415657 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 415044 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 414930 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 415676 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 51328 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 51156 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50890 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51482 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51387 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50754 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50751 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51440 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51875 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51227 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51302 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51806 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51729 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51213 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51075 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51789 # Track writes on a per bank basis +system.physmem.num_reads::cpu0.inst 13468 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 103605 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4079 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 45405 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6654628 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 64628 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 756826 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory +system.physmem.num_writes::total 821464 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43438497 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 214 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 388295 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 5545333 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 214107 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2430537 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52017144 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 388295 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 214107 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 602402 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3461548 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 2533528 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 33 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5995110 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3461548 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43438497 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 388295 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 8078862 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 214107 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2430570 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 58012254 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6654628 # Total number of read requests seen +system.physmem.writeReqs 821464 # Total number of write requests seen +system.physmem.cpureqs 235013 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 425896192 # Total number of bytes read from memory +system.physmem.bytesWritten 52573696 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 62155108 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7163536 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 139 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 10646 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 415731 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 415559 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 414958 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 415336 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 422399 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 415419 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 415520 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 415298 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 415351 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 415631 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 415270 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 414902 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 415547 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 416079 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 415762 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 415727 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50036 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 49924 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 51324 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51581 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51864 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51435 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51646 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51464 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51327 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51592 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51318 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51082 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51567 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51872 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51738 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51694 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1183433014000 # Total gap between requests +system.physmem.totGap 1194892168500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6825 # Categorize read packet sizes system.physmem.readPktSize::3 6488064 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 159661 # Categorize read packet sizes +system.physmem.readPktSize::6 159739 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 756836 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 64368 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 571102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 408461 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 415701 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1537889 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1165282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1169319 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1141412 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 29559 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 27546 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 48416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 68998 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 48154 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 5894 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 5718 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 5549 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 5372 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 81 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 64628 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 581008 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 419779 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 439715 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1589810 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1189300 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1185139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1157962 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 13029 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 10446 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 15424 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20310 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 15138 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 4570 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 4445 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 4292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 4046 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 75 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -156,59 +156,336 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35455 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35679 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 35695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 35695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 35705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 35705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 35692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 147040385750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 189361608250 # Sum of mem lat for all requests -system.physmem.totBusLat 33272265000 # Total cycles spent in databus access -system.physmem.totBankLat 9048957500 # Total cycles spent in bank access -system.physmem.avgQLat 22096.54 # Average queueing delay per request -system.physmem.avgBankLat 1359.83 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 34609 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 13824.665723 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 735.190153 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 27804.066503 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-127 7914 22.87% 22.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-191 4043 11.68% 34.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-255 2692 7.78% 42.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-319 1927 5.57% 47.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-383 1400 4.05% 51.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-447 1123 3.24% 55.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-511 878 2.54% 57.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-575 878 2.54% 60.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-639 638 1.84% 62.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-703 541 1.56% 63.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-767 480 1.39% 65.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-831 476 1.38% 66.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-895 262 0.76% 67.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-959 253 0.73% 67.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-1023 191 0.55% 68.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1087 292 0.84% 69.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1151 145 0.42% 69.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1215 146 0.42% 70.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1279 123 0.36% 70.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1343 107 0.31% 70.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1407 79 0.23% 71.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1471 170 0.49% 71.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1535 949 2.74% 74.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1599 246 0.71% 74.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1663 151 0.44% 75.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1727 129 0.37% 75.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1791 98 0.28% 76.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1855 72 0.21% 76.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1919 65 0.19% 76.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1983 51 0.15% 76.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2047 51 0.15% 76.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2111 71 0.21% 76.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2175 44 0.13% 77.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2239 29 0.08% 77.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2303 19 0.05% 77.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2367 23 0.07% 77.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2431 27 0.08% 77.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2495 13 0.04% 77.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2559 27 0.08% 77.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2623 12 0.03% 77.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2687 9 0.03% 77.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2751 14 0.04% 77.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2815 11 0.03% 77.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2879 12 0.03% 77.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2943 14 0.04% 77.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-3007 6 0.02% 77.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3071 7 0.02% 77.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3135 15 0.04% 77.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3199 4 0.01% 77.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3263 7 0.02% 77.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3327 4 0.01% 77.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3391 14 0.04% 77.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3455 11 0.03% 77.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3519 7 0.02% 77.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3583 7 0.02% 77.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3647 11 0.03% 77.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3711 8 0.02% 78.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3775 5 0.01% 78.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3839 12 0.03% 78.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3903 4 0.01% 78.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3967 5 0.01% 78.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-4031 8 0.02% 78.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4095 6 0.02% 78.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4159 41 0.12% 78.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4223 3 0.01% 78.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4287 4 0.01% 78.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4351 5 0.01% 78.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4415 4 0.01% 78.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4479 5 0.01% 78.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4543 4 0.01% 78.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4607 5 0.01% 78.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4671 9 0.03% 78.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4735 4 0.01% 78.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4799 2 0.01% 78.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4863 4 0.01% 78.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4927 4 0.01% 78.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4991 1 0.00% 78.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5055 5 0.01% 78.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5119 3 0.01% 78.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5183 10 0.03% 78.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5247 3 0.01% 78.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5375 2 0.01% 78.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5439 5 0.01% 78.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5503 2 0.01% 78.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5631 5 0.01% 78.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5695 3 0.01% 78.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5759 6 0.02% 78.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5823 2 0.01% 78.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5887 3 0.01% 78.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5951 5 0.01% 78.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-6015 4 0.01% 78.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6079 3 0.01% 78.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6143 3 0.01% 78.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6207 170 0.49% 79.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6271 3 0.01% 79.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6335 1 0.00% 79.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6399 4 0.01% 79.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6463 4 0.01% 79.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6591 1 0.00% 79.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6655 2 0.01% 79.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6719 5 0.01% 79.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6783 3 0.01% 79.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6847 21 0.06% 79.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6911 3 0.01% 79.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6975 1 0.00% 79.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7103 1 0.00% 79.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7167 1 0.00% 79.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7231 4 0.01% 79.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7295 3 0.01% 79.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7359 2 0.01% 79.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7423 1 0.00% 79.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7487 3 0.01% 79.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7551 4 0.01% 79.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7615 3 0.01% 79.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7679 3 0.01% 79.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7743 4 0.01% 79.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7807 2 0.01% 79.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7935 5 0.01% 79.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7999 2 0.01% 79.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8063 2 0.01% 79.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8127 7 0.02% 79.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8191 4 0.01% 79.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8255 318 0.92% 80.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8511 1 0.00% 80.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8767 1 0.00% 80.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-9023 2 0.01% 80.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9279 4 0.01% 80.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9408-9471 1 0.00% 80.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9535 2 0.01% 80.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9663 1 0.00% 80.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9791 2 0.01% 80.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10303 17 0.05% 80.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10559 2 0.01% 80.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10815 1 0.00% 80.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11071 2 0.01% 80.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11200-11263 1 0.00% 80.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11327 2 0.01% 80.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11583 2 0.01% 80.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12095 1 0.00% 80.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12799 1 0.00% 80.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13375 1 0.00% 80.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13631 2 0.01% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13887 1 0.00% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14399 1 0.00% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15423 2 0.01% 80.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15679 1 0.00% 80.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15935 1 0.00% 80.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16191 1 0.00% 80.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16447 1 0.00% 80.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16704-16767 1 0.00% 80.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17215 1 0.00% 80.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17280-17343 1 0.00% 80.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17471 2 0.01% 80.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17728-17791 1 0.00% 80.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17856-17919 1 0.00% 80.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18239 1 0.00% 80.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18495 2 0.01% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19263 1 0.00% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20543 13 0.04% 80.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20799 1 0.00% 80.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-21055 1 0.00% 80.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21567 2 0.01% 80.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21823 1 0.00% 80.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22591 3 0.01% 80.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22847 1 0.00% 80.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23103 2 0.01% 80.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23615 3 0.01% 80.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23871 1 0.00% 80.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24127 1 0.00% 80.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24128-24191 1 0.00% 80.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24383 1 0.00% 80.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24639 1 0.00% 80.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24895 2 0.01% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25216-25279 1 0.00% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25663 3 0.01% 80.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25919 2 0.01% 80.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26687 1 0.00% 80.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26943 3 0.01% 80.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27199 1 0.00% 80.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27455 2 0.01% 80.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27711 1 0.00% 80.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27840-27903 1 0.00% 80.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27967 1 0.00% 80.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27968-28031 1 0.00% 80.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28479 1 0.00% 80.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28735 2 0.01% 80.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28991 2 0.01% 80.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29247 1 0.00% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29504-29567 1 0.00% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29759 4 0.01% 80.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-30015 5 0.01% 80.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30271 1 0.00% 80.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30527 1 0.00% 80.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30783 1 0.00% 80.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31040-31103 1 0.00% 80.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31360-31423 1 0.00% 80.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31680-31743 1 0.00% 80.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31807 2 0.01% 80.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32063 2 0.01% 80.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32319 1 0.00% 80.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32831 6 0.02% 80.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33343 1 0.00% 80.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33472-33535 5 0.01% 80.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33599 49 0.14% 80.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33600-33663 2 0.01% 80.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34879 1 0.00% 80.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35135 1 0.00% 80.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35903 1 0.00% 80.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38016-38079 1 0.00% 80.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38463 1 0.00% 80.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39487 1 0.00% 80.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-41023 1 0.00% 80.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-42047 2 0.01% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42112-42175 1 0.00% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43071 1 0.00% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43327 1 0.00% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46911 1 0.00% 80.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48447 1 0.00% 80.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48576-48639 1 0.00% 80.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53248-53311 1 0.00% 80.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53504-53567 1 0.00% 80.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53760-53823 1 0.00% 80.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54016-54079 1 0.00% 80.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54272-54335 1 0.00% 80.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54528-54591 1 0.00% 80.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::55296-55359 1 0.00% 80.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::55744-55807 1 0.00% 80.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::55808-55871 2 0.01% 80.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56320-56383 3 0.01% 80.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56576-56639 1 0.00% 80.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58880-58943 1 0.00% 80.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::59520-59583 1 0.00% 80.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::60416-60479 1 0.00% 80.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::60608-60671 1 0.00% 80.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62464-62527 1 0.00% 80.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::63488-63551 1 0.00% 80.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65024-65087 7 0.02% 80.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65152-65215 2 0.01% 81.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65216-65279 1 0.00% 81.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65344-65407 1 0.00% 81.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65472-65535 6 0.02% 81.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65599 6201 17.92% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65920-65983 1 0.00% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::66304-66367 1 0.00% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::74240-74303 1 0.00% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::76480-76543 1 0.00% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::76864-76927 1 0.00% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::84416-84479 1 0.00% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::86848-86911 1 0.00% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::87040-87103 1 0.00% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::87424-87487 1 0.00% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::97024-97087 1 0.00% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::97472-97535 1 0.00% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::97600-97663 1 0.00% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::99520-99583 1 0.00% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::109120-109183 1 0.00% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::110080-110143 1 0.00% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::111168-111231 1 0.00% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::114496-114559 1 0.00% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::120896-120959 1 0.00% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::121152-121215 1 0.00% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::121728-121791 1 0.00% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::122112-122175 1 0.00% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::129856-129919 1 0.00% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130112-130175 1 0.00% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131072-131135 336 0.97% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131200-131263 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::132096-132159 3 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::136576-136639 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196032-196095 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196608-196671 2 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 34609 # Bytes accessed per row activation +system.physmem.totQLat 134116991750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 175932036750 # Sum of mem lat for all requests +system.physmem.totBusLat 33272445000 # Total cycles spent in databus access +system.physmem.totBankLat 8542600000 # Total cycles spent in bank access +system.physmem.avgQLat 20154.36 # Average queueing delay per request +system.physmem.avgBankLat 1283.73 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28456.37 # Average memory access latency -system.physmem.avgRdBW 359.88 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 44.41 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 52.52 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.04 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 26438.10 # Average memory access latency +system.physmem.avgRdBW 356.43 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 44.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 52.02 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.16 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.16 # Average read queue length over time -system.physmem.avgWrQLen 11.75 # Average write queue length over time -system.physmem.readRowHits 6612404 # Number of row buffer hits during reads -system.physmem.writeRowHits 800418 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.37 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.47 # Row buffer hit rate for writes -system.physmem.avgGap 158302.83 # Average gap between requests +system.physmem.busUtil 3.13 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.15 # Average read queue length over time +system.physmem.avgWrQLen 12.03 # Average write queue length over time +system.physmem.readRowHits 6636609 # Number of row buffer hits during reads +system.physmem.writeRowHits 804716 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.73 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 97.96 # Row buffer hit rate for writes +system.physmem.avgGap 159828.45 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -219,245 +496,306 @@ system.realview.nvmem.num_reads::cpu0.inst 5 # system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 69541 # number of replacements -system.l2c.tagsinuse 53035.489918 # Cycle average of tags in use -system.l2c.total_refs 1672596 # Total number of references to valid blocks. -system.l2c.sampled_refs 134740 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.413507 # Average number of references to valid blocks. +system.membus.throughput 60028731 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 7703147 # Transaction distribution +system.membus.trans_dist::ReadResp 7703147 # Transaction distribution +system.membus.trans_dist::WriteReq 767201 # Transaction distribution +system.membus.trans_dist::WriteResp 767201 # Transaction distribution +system.membus.trans_dist::Writeback 64628 # Transaction distribution +system.membus.trans_dist::UpgradeReq 27727 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 16403 # Transaction distribution +system.membus.trans_dist::UpgradeResp 10646 # Transaction distribution +system.membus.trans_dist::ReadExReq 137752 # Transaction distribution +system.membus.trans_dist::ReadExResp 137298 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382564 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1966658 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 8856 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 906 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4359022 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 2382564 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 14942786 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.gic.pio 8856 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.local_cpu_timer.pio 906 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 17335150 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389882 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17414132 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 17712 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1812 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19823614 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 2389882 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 69318644 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.gic.pio 17712 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.local_cpu_timer.pio 1812 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 71728126 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 71728126 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1224802500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 9206920000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.8 # Layer utilization (%) +system.membus.reqLayer3.occupancy 7965000 # Layer occupancy (ticks) +system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 2500 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer6.occupancy 777000 # Layer occupancy (ticks) +system.membus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 5076821641 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.respLayer2.occupancy 14663419999 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.2 # Layer utilization (%) +system.l2c.replacements 69621 # number of replacements +system.l2c.tagsinuse 53152.412760 # Cycle average of tags in use +system.l2c.total_refs 1651309 # Total number of references to valid blocks. +system.l2c.sampled_refs 134782 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.251703 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 40180.165903 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 0.000406 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.001420 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3726.817906 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4242.402809 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 2.742182 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2823.857423 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2059.501869 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.613101 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 40039.064508 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 2.667880 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.001518 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4643.192238 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 5788.281913 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.itb.walker 0.001659 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 1923.389950 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 755.813095 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.610948 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000041 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.056867 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.064734 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.043089 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.031426 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.809257 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 3941 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1769 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 419774 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 205645 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5809 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 2015 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 464124 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 143605 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1246682 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 571448 # number of Writeback hits -system.l2c.Writeback_hits::total 571448 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1206 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 615 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1821 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 214 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 104 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 318 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 56897 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 52477 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 109374 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 3941 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1769 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 419774 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 262542 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5809 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 2015 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 464124 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 196082 # number of demand (read+write) hits -system.l2c.demand_hits::total 1356056 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 3941 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 1769 # number of overall hits -system.l2c.overall_hits::cpu0.inst 419774 # number of overall hits -system.l2c.overall_hits::cpu0.data 262542 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5809 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 2015 # number of overall hits -system.l2c.overall_hits::cpu1.inst 464124 # number of overall hits -system.l2c.overall_hits::cpu1.data 196082 # number of overall hits -system.l2c.overall_hits::total 1356056 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses +system.l2c.occ_percent::cpu0.inst 0.070849 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.088322 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.029349 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.011533 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.811041 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 4524 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 1439 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 483114 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 241880 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 3782 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1868 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 372301 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 110577 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1219485 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 576235 # number of Writeback hits +system.l2c.Writeback_hits::total 576235 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1306 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 431 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1737 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 257 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 99 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 356 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 65556 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 45402 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 110958 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 4524 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 1439 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 483114 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 307436 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 3782 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 1868 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 372301 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 155979 # number of demand (read+write) hits +system.l2c.demand_hits::total 1330443 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 4524 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 1439 # number of overall hits +system.l2c.overall_hits::cpu0.inst 483114 # number of overall hits +system.l2c.overall_hits::cpu0.data 307436 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 3782 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 1868 # number of overall hits +system.l2c.overall_hits::cpu1.inst 372301 # number of overall hits +system.l2c.overall_hits::cpu1.data 155979 # number of overall hits +system.l2c.overall_hits::total 1330443 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 5740 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 7867 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 5044 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 3619 # number of ReadReq misses -system.l2c.ReadReq_misses::total 22277 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 4714 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3582 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 8296 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 566 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 479 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1045 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 67030 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 72802 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 139832 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu0.inst 6836 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 9717 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 3992 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1890 # number of ReadReq misses +system.l2c.ReadReq_misses::total 22442 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 3986 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3365 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 7351 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 384 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 475 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 859 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 95133 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 44601 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 139734 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 5740 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 74897 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 5044 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 76421 # number of demand (read+write) misses -system.l2c.demand_misses::total 162109 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses +system.l2c.demand_misses::cpu0.inst 6836 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 104850 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 3992 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 46491 # number of demand (read+write) misses +system.l2c.demand_misses::total 162176 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 5740 # number of overall misses -system.l2c.overall_misses::cpu0.data 74897 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses -system.l2c.overall_misses::cpu1.inst 5044 # number of overall misses -system.l2c.overall_misses::cpu1.data 76421 # number of overall misses -system.l2c.overall_misses::total 162109 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 69000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 82500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 301916500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 419391498 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 247500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 276443000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 222520500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1220670498 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 12958000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 12012000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 24970000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1618000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2458500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 4076500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 3033840500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 3448903999 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6482744499 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 69000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 82500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 301916500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 3453231998 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 247500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 276443000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 3671424499 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 7703414997 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 69000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 82500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 301916500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 3453231998 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 247500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 276443000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 3671424499 # number of overall miss cycles -system.l2c.overall_miss_latency::total 7703414997 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 3942 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 1771 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 425514 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 213512 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 5813 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 2015 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 469168 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 147224 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1268959 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 571448 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 571448 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 5920 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 4197 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 10117 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 780 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 583 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1363 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 123927 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 125279 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 249206 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 3942 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 1771 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 425514 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 337439 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 5813 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 2015 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 469168 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 272503 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1518165 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 3942 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 1771 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 425514 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 337439 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 5813 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 2015 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 469168 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 272503 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1518165 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000254 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001129 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.013490 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.036846 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000688 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010751 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.024582 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.017555 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.796284 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.853467 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.820006 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.725641 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.821612 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.766691 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.540883 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.581119 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.561110 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000254 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.001129 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.013490 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.221957 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000688 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.010751 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.280441 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.106780 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000254 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.001129 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.013490 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.221957 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000688 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.010751 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.280441 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.106780 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 69000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 41250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52598.693380 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 53310.219652 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 61875 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 54806.304520 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 61486.736668 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 54795.102482 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2748.833263 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3353.433836 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 3009.884282 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2858.657244 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5132.567850 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 3900.956938 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 45260.935402 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 47373.753455 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 46360.950991 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 69000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 41250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52598.693380 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 46106.412780 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 61875 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 54806.304520 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 48042.089203 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 47519.971112 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 69000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 41250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52598.693380 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 46106.412780 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 61875 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 54806.304520 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 48042.089203 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 47519.971112 # average overall miss latency +system.l2c.overall_misses::cpu0.inst 6836 # number of overall misses +system.l2c.overall_misses::cpu0.data 104850 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu1.inst 3992 # number of overall misses +system.l2c.overall_misses::cpu1.data 46491 # number of overall misses +system.l2c.overall_misses::total 162176 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 395000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 122500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 487167000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 686875999 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 89000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 283916500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 153770500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1612336499 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 11351000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 12155500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 23506500 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1843000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1049000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 2892000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 6211024494 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 2810090500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9021114994 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 395000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 122500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 487167000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 6897900493 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 89000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 283916500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 2963861000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 10633451493 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 395000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 122500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 487167000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 6897900493 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 89000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 283916500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 2963861000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 10633451493 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 4528 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 1441 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 489950 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 251597 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 3782 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 1869 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 376293 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 112467 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1241927 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 576235 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 576235 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 5292 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 3796 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 9088 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 641 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 574 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1215 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 160689 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 90003 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 250692 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 4528 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 1441 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 489950 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 412286 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 3782 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 1869 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 376293 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 202470 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1492619 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 4528 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 1441 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 489950 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 412286 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 3782 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 1869 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 376293 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 202470 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1492619 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000883 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001388 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.013952 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.038621 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000535 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.010609 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.016805 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.018070 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.753212 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.886459 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.808869 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.599064 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.827526 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.706996 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.592032 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.495550 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.557393 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000883 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.001388 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.013952 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.254314 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.000535 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.010609 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.229619 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.108652 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000883 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.001388 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.013952 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.254314 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.000535 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.010609 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.229619 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.108652 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 98750 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 61250 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 71264.921006 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 70688.072347 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 89000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 71121.367735 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 81360.052910 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 71844.599367 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2847.717010 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3612.332838 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 3197.728200 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4799.479167 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2208.421053 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 3366.705471 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 65287.802277 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 63005.100782 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 64559.198148 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 98750 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 61250 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 71264.921006 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 65788.273658 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 71121.367735 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 63751.285195 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 65567.355792 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 98750 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 61250 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 71264.921006 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 65788.273658 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 71121.367735 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 63751.285195 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 65567.355792 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -466,159 +804,159 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 64368 # number of writebacks -system.l2c.writebacks::total 64368 # number of writebacks +system.l2c.writebacks::writebacks 64628 # number of writebacks +system.l2c.writebacks::total 64628 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 4 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 5739 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 7867 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 5044 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 3619 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 22276 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 4714 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 3582 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 8296 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 566 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 479 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1045 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 67030 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 72802 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 139832 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 6835 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 9717 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 3992 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1890 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 22441 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 3986 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 3365 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 7351 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 384 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 475 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 859 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 95133 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 44601 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 139734 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 4 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 5739 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 74897 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 5044 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 76421 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 162108 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 6835 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 104850 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 3992 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 46491 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 162175 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 4 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 5739 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 74897 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 5044 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 76421 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 162108 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 56251 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 57502 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 229892733 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 321315860 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 197504 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 213223286 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 177293869 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 942037005 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 47255656 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 35939553 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 83195209 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5679055 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4807974 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 10487029 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2184620679 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2537912723 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 4722533402 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 56251 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 57502 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 229892733 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 2505936539 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 197504 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 213223286 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 2715206592 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 5664570407 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 56251 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 57502 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 229892733 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 2505936539 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 197504 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 213223286 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 2715206592 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 5664570407 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 209633632 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12454752325 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3167837 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154325993526 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 166993547320 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1000474745 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8209478823 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 9209953568 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 209633632 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13455227070 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3167837 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 162535472349 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 176203500888 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000254 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001129 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013487 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036846 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000688 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010751 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024582 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.017555 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.796284 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.853467 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.820006 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.725641 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.821612 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.766691 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.540883 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.581119 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.561110 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000254 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001129 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013487 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.221957 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000688 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010751 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.280441 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.106779 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000254 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001129 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013487 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.221957 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000688 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010751 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.280441 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.106779 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 56251 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40057.977522 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40843.505784 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 49376 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 42272.657811 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 48989.739983 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 42289.325058 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10024.534578 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10033.376047 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10028.352097 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10033.666078 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10037.524008 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10035.434450 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 32591.685499 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34860.480797 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 33772.908934 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56251 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40057.977522 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 33458.436773 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 49376 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42272.657811 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 35529.587312 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 34943.188535 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56251 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40057.977522 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 33458.436773 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 49376 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42272.657811 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 35529.587312 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 34943.188535 # average overall mshr miss latency +system.l2c.overall_mshr_misses::cpu0.inst 6835 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 104850 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 3992 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 46491 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 162175 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 345500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 97500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 401430000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 565873249 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 76250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 233821750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 130194500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1331838749 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 39898978 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 33754347 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 73653325 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 3848381 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4768474 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 8616855 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5004861313 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2258786863 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 7263648176 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 345500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 97500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 401430000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 5570734562 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 76250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 233821750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 2388981363 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 8595486925 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 345500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 97500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 401430000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 5570734562 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 76250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 233821750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 2388981363 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 8595486925 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 340227750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12648650244 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 4863250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154086171248 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167079912492 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 16271278232 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 486203500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 16757481732 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 340227750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 28919928476 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 4863250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 154572374748 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 183837394224 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000883 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001388 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013950 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.038621 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000535 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010609 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.016805 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.018070 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.753212 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.886459 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.808869 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.599064 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.827526 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.706996 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.592032 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.495550 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.557393 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000883 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001388 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013950 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.254314 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000535 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010609 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.229619 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.108651 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000883 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001388 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013950 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.254314 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000535 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010609 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.229619 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.108651 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 86375 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58731.528895 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 58235.386333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58572.582665 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 68885.978836 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 59348.458135 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10009.778726 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10031.009510 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10019.497347 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10021.825521 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10038.892632 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10031.263097 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 52609.097926 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 50644.309836 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 51981.966994 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 86375 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58731.528895 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53130.515613 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58572.582665 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51385.888946 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 53001.306767 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 86375 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58731.528895 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53130.515613 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58572.582665 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51385.888946 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 53001.306767 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -639,28 +977,237 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. +system.toL2Bus.throughput 118409228 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2504917 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2504917 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 767201 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 767201 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 576235 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 27028 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 16759 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 43787 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 262464 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 262464 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 993919 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 2951089 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 5837 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 14921 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 753559 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 2879854 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma 6195 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma 11995 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 7617369 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 31383352 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 53719796 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 5764 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 18112 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 24083148 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 27940806 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma 7476 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma 15128 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 137173582 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 137173582 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4313200 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4765991701 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 2214801410 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 2446229482 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 4396000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 10393499 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 1696938433 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 2203617971 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 4326998 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 8213499 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.throughput 45438572 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7671400 # Transaction distribution +system.iobus.trans_dist::ReadResp 7671400 # Transaction distribution +system.iobus.trans_dist::WriteReq 7946 # Transaction distribution +system.iobus.trans_dist::WriteResp 7946 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8062 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 740 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 496 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382564 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.realview_io.pio 8062 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer1.pio 740 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi1.pio 496 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 15358692 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16124 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1480 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2389882 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.realview_io.pio 16124 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer1.pio 1480 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi1.pio 272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 54294394 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 54294394 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21350000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 4037000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 376000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 298000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.1 # Layer utilization (%) +system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) +system.iobus.respLayer0.occupancy 2374618000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) +system.iobus.respLayer1.occupancy 12976128000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.1 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7074446 # DTB read hits -system.cpu0.dtb.read_misses 3765 # DTB read misses -system.cpu0.dtb.write_hits 5659669 # DTB write hits -system.cpu0.dtb.write_misses 803 # DTB write misses +system.cpu0.dtb.read_hits 9653493 # DTB read hits +system.cpu0.dtb.read_misses 3738 # DTB read misses +system.cpu0.dtb.write_hits 7597651 # DTB write hits +system.cpu0.dtb.write_misses 1585 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1806 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1811 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 145 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 134 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7078211 # DTB read accesses -system.cpu0.dtb.write_accesses 5660472 # DTB write accesses +system.cpu0.dtb.read_accesses 9657231 # DTB read accesses +system.cpu0.dtb.write_accesses 7599236 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12734115 # DTB hits -system.cpu0.dtb.misses 4568 # DTB misses -system.cpu0.dtb.accesses 12738683 # DTB accesses -system.cpu0.itb.inst_hits 29576941 # ITB inst hits +system.cpu0.dtb.hits 17251144 # DTB hits +system.cpu0.dtb.misses 5323 # DTB misses +system.cpu0.dtb.accesses 17256467 # DTB accesses +system.cpu0.itb.inst_hits 43299111 # ITB inst hits system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -677,79 +1224,79 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 29579146 # ITB inst accesses -system.cpu0.itb.hits 29576941 # DTB hits +system.cpu0.itb.inst_accesses 43301316 # ITB inst accesses +system.cpu0.itb.hits 43299111 # DTB hits system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 29579146 # DTB accesses -system.cpu0.numCycles 2366875007 # number of cpu cycles simulated +system.cpu0.itb.accesses 43301316 # DTB accesses +system.cpu0.numCycles 2389793161 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 28878978 # Number of instructions committed -system.cpu0.committedOps 37226861 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33113061 # Number of integer alu accesses +system.cpu0.committedInsts 42572187 # Number of instructions committed +system.cpu0.committedOps 53304847 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 48061724 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1241874 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4373945 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33113061 # number of integer instructions +system.cpu0.num_func_calls 1403541 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5582883 # number of instructions that are conditional controls +system.cpu0.num_int_insts 48061724 # number of integer instructions system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 190134215 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36237784 # number of times the integer registers were written +system.cpu0.num_int_register_reads 272457591 # number of times the integer registers were read +system.cpu0.num_int_register_writes 52272439 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 13402466 # number of memory refs -system.cpu0.num_load_insts 7412077 # Number of load instructions -system.cpu0.num_store_insts 5990389 # Number of store instructions -system.cpu0.num_idle_cycles 2224972760.370120 # Number of idle cycles -system.cpu0.num_busy_cycles 141902246.629880 # Number of busy cycles -system.cpu0.not_idle_fraction 0.059953 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.940047 # Percentage of idle cycles +system.cpu0.num_mem_refs 18020656 # number of memory refs +system.cpu0.num_load_insts 10037354 # Number of load instructions +system.cpu0.num_store_insts 7983302 # Number of store instructions +system.cpu0.num_idle_cycles 2150335736.878201 # Number of idle cycles +system.cpu0.num_busy_cycles 239457424.121800 # Number of busy cycles +system.cpu0.not_idle_fraction 0.100200 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.899800 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 46700 # number of quiesce instructions executed -system.cpu0.icache.replacements 425548 # number of replacements -system.cpu0.icache.tagsinuse 509.590371 # Cycle average of tags in use -system.cpu0.icache.total_refs 29150863 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 426060 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 68.419619 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 75070085000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.590371 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.995294 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.995294 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 29150863 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29150863 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29150863 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29150863 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29150863 # number of overall hits -system.cpu0.icache.overall_hits::total 29150863 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 426061 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 426061 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 426061 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 426061 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 426061 # number of overall misses -system.cpu0.icache.overall_misses::total 426061 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5812849500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5812849500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5812849500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5812849500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5812849500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5812849500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 29576924 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 29576924 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 29576924 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 29576924 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 29576924 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 29576924 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014405 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014405 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014405 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014405 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014405 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014405 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13643.233011 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13643.233011 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13643.233011 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13643.233011 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13643.233011 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13643.233011 # average overall miss latency +system.cpu0.kern.inst.quiesce 51313 # number of quiesce instructions executed +system.cpu0.icache.replacements 490180 # number of replacements +system.cpu0.icache.tagsinuse 509.396236 # Cycle average of tags in use +system.cpu0.icache.total_refs 42808401 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 490692 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 87.240878 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 76020026000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.396236 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.994915 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.994915 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 42808401 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 42808401 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 42808401 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 42808401 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 42808401 # number of overall hits +system.cpu0.icache.overall_hits::total 42808401 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 490693 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 490693 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 490693 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 490693 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 490693 # number of overall misses +system.cpu0.icache.overall_misses::total 490693 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6812744000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6812744000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 6812744000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6812744000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 6812744000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6812744000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 43299094 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 43299094 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 43299094 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 43299094 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 43299094 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 43299094 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011333 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011333 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011333 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011333 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011333 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011333 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13883.923349 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13883.923349 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13883.923349 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13883.923349 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13883.923349 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13883.923349 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -758,120 +1305,120 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 426061 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 426061 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 426061 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 426061 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 426061 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 426061 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4960727500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4960727500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4960727500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4960727500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4960727500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4960727500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 299599000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 299599000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 299599000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 299599000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014405 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014405 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014405 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11643.233011 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11643.233011 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11643.233011 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11643.233011 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11643.233011 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11643.233011 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 490693 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 490693 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 490693 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 490693 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 490693 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 490693 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5831313090 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5831313090 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5831313090 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5831313090 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5831313090 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5831313090 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 430167000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 430167000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 430167000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 430167000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011333 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011333 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011333 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.011333 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011333 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.011333 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11883.831826 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11883.831826 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11883.831826 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11883.831826 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11883.831826 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11883.831826 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 330262 # number of replacements -system.cpu0.dcache.tagsinuse 452.976504 # Cycle average of tags in use -system.cpu0.dcache.total_refs 12279097 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 330774 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 37.122316 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 473556000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 452.976504 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.884720 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.884720 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6604621 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6604621 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5354486 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5354486 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147953 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 147953 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149702 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 149702 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11959107 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11959107 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11959107 # number of overall hits -system.cpu0.dcache.overall_hits::total 11959107 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 227474 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 227474 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 141720 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 141720 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9335 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9335 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7505 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7505 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 369194 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 369194 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 369194 # number of overall misses -system.cpu0.dcache.overall_misses::total 369194 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3141338000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 3141338000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4161237500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 4161237500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88637000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 88637000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44352500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 44352500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 7302575500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 7302575500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 7302575500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 7302575500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6832095 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6832095 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5496206 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5496206 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157288 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 157288 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157207 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 157207 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12328301 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12328301 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12328301 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12328301 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033295 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.033295 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025785 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.025785 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059350 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059350 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047740 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047740 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029947 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.029947 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029947 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.029947 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13809.657367 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13809.657367 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 29362.387101 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 29362.387101 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9495.125870 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9495.125870 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5909.726849 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5909.726849 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19779.778382 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19779.778382 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19779.778382 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 19779.778382 # average overall miss latency +system.cpu0.dcache.replacements 406656 # number of replacements +system.cpu0.dcache.tagsinuse 471.250698 # Cycle average of tags in use +system.cpu0.dcache.total_refs 15968393 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 407168 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 39.218192 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 652579000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 471.250698 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.920412 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.920412 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 9137588 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 9137588 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 6495058 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 6495058 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 156529 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 156529 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 159015 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 159015 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 15632646 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 15632646 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 15632646 # number of overall hits +system.cpu0.dcache.overall_hits::total 15632646 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 263671 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 263671 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 176701 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 176701 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9917 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9917 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7374 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7374 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 440372 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 440372 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 440372 # number of overall misses +system.cpu0.dcache.overall_misses::total 440372 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3870373500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3870373500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7511792500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 7511792500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 99127000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 99127000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 40277500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 40277500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 11382166000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11382166000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11382166000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11382166000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 9401259 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 9401259 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 6671759 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 6671759 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 166446 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 166446 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 166389 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 166389 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 16073018 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 16073018 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 16073018 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 16073018 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028046 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.028046 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026485 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.026485 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059581 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059581 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.044318 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.044318 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027398 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.027398 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027398 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.027398 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14678.798579 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14678.798579 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42511.318555 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 42511.318555 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9995.664011 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9995.664011 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5462.096555 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5462.096555 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25846.706875 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 25846.706875 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25846.706875 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 25846.706875 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -880,66 +1427,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 306255 # number of writebacks -system.cpu0.dcache.writebacks::total 306255 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227474 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 227474 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141720 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 141720 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9335 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9335 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7498 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7498 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 369194 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 369194 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 369194 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 369194 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2686390000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2686390000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3877797500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3877797500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69967000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69967000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29358500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29358500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.writebacks::writebacks 376588 # number of writebacks +system.cpu0.dcache.writebacks::total 376588 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 263671 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 263671 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 176701 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 176701 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9917 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9917 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7370 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7370 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 440372 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 440372 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 440372 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 440372 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3343027009 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3343027009 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7158388504 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7158388504 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 79292501 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 79292501 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25539500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25539500 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6564187500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6564187500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6564187500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6564187500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13562288000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13562288000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128633000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128633000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14690921000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14690921000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033295 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033295 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025785 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025785 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059350 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059350 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047695 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047695 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029947 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029947 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029947 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029947 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11809.657367 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11809.657367 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27362.387101 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27362.387101 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7495.125870 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7495.125870 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3915.510803 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3915.510803 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10501415513 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10501415513 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10501415513 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10501415513 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13765210500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13765210500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 25807067504 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 25807067504 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 39572278004 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 39572278004 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028046 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.028046 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026485 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026485 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059581 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059581 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044294 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044294 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027398 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027398 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027398 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.027398 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12678.781546 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12678.781546 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40511.307259 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40511.307259 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7995.613694 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7995.613694 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3465.332429 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3465.332429 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17779.778382 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17779.778382 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17779.778382 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17779.778382 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23846.692144 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23846.692144 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23846.692144 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23846.692144 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -949,26 +1496,26 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 8312224 # DTB read hits -system.cpu1.dtb.read_misses 3649 # DTB read misses -system.cpu1.dtb.write_hits 5828610 # DTB write hits -system.cpu1.dtb.write_misses 1432 # DTB write misses +system.cpu1.dtb.read_hits 5706432 # DTB read hits +system.cpu1.dtb.read_misses 3576 # DTB read misses +system.cpu1.dtb.write_hits 3873109 # DTB write hits +system.cpu1.dtb.write_misses 645 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1964 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1989 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 142 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 8315873 # DTB read accesses -system.cpu1.dtb.write_accesses 5830042 # DTB write accesses +system.cpu1.dtb.read_accesses 5710008 # DTB read accesses +system.cpu1.dtb.write_accesses 3873754 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 14140834 # DTB hits -system.cpu1.dtb.misses 5081 # DTB misses -system.cpu1.dtb.accesses 14145915 # DTB accesses -system.cpu1.itb.inst_hits 33192056 # ITB inst hits +system.cpu1.dtb.hits 9579541 # DTB hits +system.cpu1.dtb.misses 4221 # DTB misses +system.cpu1.dtb.accesses 9583762 # DTB accesses +system.cpu1.itb.inst_hits 19379683 # ITB inst hits system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -985,79 +1532,79 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 33194227 # ITB inst accesses -system.cpu1.itb.hits 33192056 # DTB hits +system.cpu1.itb.inst_accesses 19381854 # ITB inst accesses +system.cpu1.itb.hits 19379683 # DTB hits system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 33194227 # DTB accesses -system.cpu1.numCycles 2365415230 # number of cpu cycles simulated +system.cpu1.itb.accesses 19381854 # DTB accesses +system.cpu1.numCycles 2388360365 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 32581554 # Number of instructions committed -system.cpu1.committedOps 41094791 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 37318858 # Number of integer alu accesses +system.cpu1.committedInsts 18799110 # Number of instructions committed +system.cpu1.committedOps 24903355 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 22267252 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 962092 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3732954 # number of instructions that are conditional controls -system.cpu1.num_int_insts 37318858 # number of integer instructions +system.cpu1.num_func_calls 796685 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2514656 # number of instructions that are conditional controls +system.cpu1.num_int_insts 22267252 # number of integer instructions system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 213696952 # number of times the integer registers were read -system.cpu1.num_int_register_writes 39459665 # number of times the integer registers were written +system.cpu1.num_int_register_reads 130770555 # number of times the integer registers were read +system.cpu1.num_int_register_writes 23319815 # number of times the integer registers were written system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 14678596 # number of memory refs -system.cpu1.num_load_insts 8634126 # Number of load instructions -system.cpu1.num_store_insts 6044470 # Number of store instructions -system.cpu1.num_idle_cycles 1868274479.951726 # Number of idle cycles -system.cpu1.num_busy_cycles 497140750.048273 # Number of busy cycles -system.cpu1.not_idle_fraction 0.210171 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.789829 # Percentage of idle cycles +system.cpu1.num_mem_refs 10014978 # number of memory refs +system.cpu1.num_load_insts 5983060 # Number of load instructions +system.cpu1.num_store_insts 4031918 # Number of store instructions +system.cpu1.num_idle_cycles 1968746844.438183 # Number of idle cycles +system.cpu1.num_busy_cycles 419613520.561817 # Number of busy cycles +system.cpu1.not_idle_fraction 0.175691 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.824309 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 43886 # number of quiesce instructions executed -system.cpu1.icache.replacements 469169 # number of replacements -system.cpu1.icache.tagsinuse 478.729775 # Cycle average of tags in use -system.cpu1.icache.total_refs 32722371 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 469681 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 69.669352 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 92399174500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 478.729775 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.935019 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.935019 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 32722371 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 32722371 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 32722371 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 32722371 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 32722371 # number of overall hits -system.cpu1.icache.overall_hits::total 32722371 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 469681 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 469681 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 469681 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 469681 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 469681 # number of overall misses -system.cpu1.icache.overall_misses::total 469681 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6362521500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6362521500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6362521500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6362521500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6362521500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6362521500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 33192052 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 33192052 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 33192052 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 33192052 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 33192052 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 33192052 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014150 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.014150 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014150 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.014150 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014150 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.014150 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13546.474096 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13546.474096 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13546.474096 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13546.474096 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13546.474096 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13546.474096 # average overall miss latency +system.cpu1.kern.inst.quiesce 39066 # number of quiesce instructions executed +system.cpu1.icache.replacements 376556 # number of replacements +system.cpu1.icache.tagsinuse 474.951242 # Cycle average of tags in use +system.cpu1.icache.total_refs 19002611 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 377068 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 50.395714 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 327008186500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 474.951242 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.927639 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.927639 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 19002611 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 19002611 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 19002611 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 19002611 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 19002611 # number of overall hits +system.cpu1.icache.overall_hits::total 19002611 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 377068 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 377068 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 377068 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 377068 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 377068 # number of overall misses +system.cpu1.icache.overall_misses::total 377068 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5155062500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5155062500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5155062500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5155062500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5155062500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5155062500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 19379679 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 19379679 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 19379679 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 19379679 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 19379679 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 19379679 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.019457 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.019457 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.019457 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.019457 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.019457 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.019457 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13671.439899 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13671.439899 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13671.439899 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13671.439899 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13671.439899 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13671.439899 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1066,120 +1613,120 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 469681 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 469681 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 469681 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 469681 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 469681 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 469681 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5423159500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5423159500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5423159500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5423159500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5423159500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5423159500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4481000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 4481000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 4481000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 4481000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014150 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014150 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014150 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.014150 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014150 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.014150 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11546.474096 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11546.474096 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11546.474096 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11546.474096 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11546.474096 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11546.474096 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 377068 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 377068 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 377068 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 377068 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 377068 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 377068 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4400893067 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4400893067 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4400893067 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4400893067 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4400893067 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4400893067 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6177000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6177000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6177000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 6177000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019457 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019457 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019457 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.019457 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019457 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.019457 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11671.351234 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11671.351234 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11671.351234 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11671.351234 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11671.351234 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11671.351234 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 292058 # number of replacements -system.cpu1.dcache.tagsinuse 471.819179 # Cycle average of tags in use -system.cpu1.dcache.total_refs 11963833 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 292409 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 40.914722 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 83872114000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 471.819179 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.921522 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.921522 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 6947661 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 6947661 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4828322 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4828322 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81798 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 81798 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82734 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 82734 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 11775983 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 11775983 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 11775983 # number of overall hits -system.cpu1.dcache.overall_hits::total 11775983 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 170592 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 170592 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 149961 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 149961 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11053 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 11053 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10044 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10044 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 320553 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 320553 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 320553 # number of overall misses -system.cpu1.dcache.overall_misses::total 320553 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2164105500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2164105500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4535823500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 4535823500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 92227500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 92227500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 51992500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 51992500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6699929000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6699929000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6699929000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6699929000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 7118253 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 7118253 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 4978283 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4978283 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92851 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 92851 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92778 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 92778 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 12096536 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 12096536 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 12096536 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 12096536 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023965 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.023965 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030123 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.030123 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119040 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119040 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108258 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108258 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026500 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.026500 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026500 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.026500 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12685.855726 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12685.855726 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30246.687472 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 30246.687472 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8344.114720 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8344.114720 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5176.473517 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5176.473517 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20901.158311 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20901.158311 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20901.158311 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20901.158311 # average overall miss latency +system.cpu1.dcache.replacements 220463 # number of replacements +system.cpu1.dcache.tagsinuse 471.524014 # Cycle average of tags in use +system.cpu1.dcache.total_refs 8230847 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 220830 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 37.272323 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 106217593500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 471.524014 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.920945 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.920945 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 4389322 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 4389322 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3673243 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3673243 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 73459 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 73459 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 73734 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 73734 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 8062565 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 8062565 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 8062565 # number of overall hits +system.cpu1.dcache.overall_hits::total 8062565 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 133853 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 133853 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 112791 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 112791 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9745 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 9745 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9392 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 9392 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 246644 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 246644 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 246644 # number of overall misses +system.cpu1.dcache.overall_misses::total 246644 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1652691000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1652691000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3703180000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3703180000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 77927500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 77927500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 48937000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 48937000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 5355871000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 5355871000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 5355871000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 5355871000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 4523175 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 4523175 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 3786034 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 3786034 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 83204 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 83204 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 83126 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 83126 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 8309209 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 8309209 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 8309209 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 8309209 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.029593 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.029593 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029791 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.029791 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.117122 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.117122 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.112985 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.112985 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029683 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.029683 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.029683 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.029683 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12347.059834 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12347.059834 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32832.229522 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 32832.229522 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 7996.664956 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 7996.664956 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5210.498296 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5210.498296 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21714.985972 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 21714.985972 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21714.985972 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 21714.985972 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1188,66 +1735,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 265193 # number of writebacks -system.cpu1.dcache.writebacks::total 265193 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170592 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 170592 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149961 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 149961 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11053 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11053 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10042 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10042 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 320553 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 320553 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 320553 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 320553 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1822921500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1822921500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4235901500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4235901500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 70121500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 70121500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31910500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31910500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.writebacks::writebacks 199647 # number of writebacks +system.cpu1.dcache.writebacks::total 199647 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133853 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 133853 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 112791 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 112791 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9745 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9745 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9391 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 9391 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 246644 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 246644 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 246644 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 246644 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1384976517 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1384976517 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3477593010 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3477593010 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 58436502 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 58436502 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30157000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30157000 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6058823000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 6058823000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6058823000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 6058823000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168642031500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168642031500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17668268500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17668268500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186310300000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186310300000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023965 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023965 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030123 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030123 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119040 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119040 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108237 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108237 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026500 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026500 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026500 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026500 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10685.855726 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10685.855726 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28246.687472 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28246.687472 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6344.114720 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6344.114720 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3177.703645 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3177.703645 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4862569527 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4862569527 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4862569527 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4862569527 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168387734500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168387734500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 531024500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 531024500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 168918759000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 168918759000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029593 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029593 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029791 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029791 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117122 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117122 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.112973 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.112973 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029683 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.029683 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.029683 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.029683 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10346.996459 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10346.996459 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30832.185281 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30832.185281 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 5996.562545 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 5996.562545 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3211.266106 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3211.266106 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18901.158311 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18901.158311 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18901.158311 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18901.158311 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19714.931346 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19714.931346 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19714.931346 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19714.931346 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1269,10 +1816,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 509664351240 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 509664351240 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 509664351240 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 509664351240 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 626235127001 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 626235127001 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 626235127001 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 626235127001 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |