diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt | 2034 |
1 files changed, 1096 insertions, 938 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index db4dfffca..70af125f4 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,71 +1,229 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.203606 # Number of seconds simulated -sim_ticks 1203606499000 # Number of ticks simulated -final_tick 1203606499000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.182883 # Number of seconds simulated +sim_ticks 1182883077500 # Number of ticks simulated +final_tick 1182883077500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 418240 # Simulator instruction rate (inst/s) -host_op_rate 532998 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8191230777 # Simulator tick rate (ticks/s) -host_mem_usage 386340 # Number of bytes of host memory used -host_seconds 146.94 # Real time elapsed on the host -sim_insts 61455549 # Number of instructions simulated -sim_ops 78317886 # Number of ops (including micro ops) simulated +host_inst_rate 330156 # Simulator instruction rate (inst/s) +host_op_rate 420694 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6355289452 # Simulator tick rate (ticks/s) +host_mem_usage 400808 # Number of bytes of host memory used +host_seconds 186.13 # Real time elapsed on the host +sim_insts 61450599 # Number of instructions simulated +sim_ops 78301940 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 354084 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4259252 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 364956 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5307824 # Number of bytes read from this memory -system.physmem.bytes_read::total 62191076 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 354084 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 364956 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 719040 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4163904 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 393380 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4712308 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 323164 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4776304 # Number of bytes read from this memory +system.physmem.bytes_read::total 62110116 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 393380 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 323164 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 716544 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4085952 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7191248 # Number of bytes written to this memory +system.physmem.bytes_written::total 7113296 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 11751 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 66623 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5784 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82961 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6655190 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 65061 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 12365 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73702 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5131 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 74656 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6653925 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 63843 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 821897 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43124154 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 294186 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3538741 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 303219 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4409933 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51670605 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 294186 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 303219 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 597405 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3459523 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 14124 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2501103 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5974750 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3459523 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43124154 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 294186 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3552865 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 303219 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6911036 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 57645355 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::total 820679 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43879664 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 108 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 332560 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3983748 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 216 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 273200 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4037850 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52507401 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 332560 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 273200 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 605761 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3454232 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 14372 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2544921 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6013524 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3454232 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43879664 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 108 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 332560 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3998120 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 216 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 273200 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6582771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 58520925 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6653925 # Total number of read requests seen +system.physmem.writeReqs 820679 # Total number of write requests seen +system.physmem.cpureqs 271820 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 425851200 # Total number of bytes read from memory +system.physmem.bytesWritten 52523456 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 62110116 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7113296 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 132 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 11750 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 415519 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 415704 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 415458 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 415465 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 415493 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 415211 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 415304 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 415265 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 422311 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 415383 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 415455 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 415586 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 415355 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 415574 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 415386 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 415324 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50680 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50792 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50611 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 50651 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51629 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51413 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51506 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51453 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51654 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51491 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51429 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51462 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51424 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51618 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51455 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51411 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 1182878628500 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 6825 # Categorize read packet sizes +system.physmem.readPktSize::3 6488064 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 159036 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 756836 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 63843 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 11750 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 6597380 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 40502 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 11414 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1777 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 643 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 481 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 367 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 271 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 201 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 155 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 117 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 69 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 44 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 35674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 35681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 35682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 35682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 35682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 35682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 3516126974 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 123045854974 # Sum of mem lat for all requests +system.physmem.totBusLat 26615172000 # Total cycles spent in databus access +system.physmem.totBankLat 92914556000 # Total cycles spent in bank access +system.physmem.avgQLat 528.44 # Average queueing delay per request +system.physmem.avgBankLat 13964.15 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 18492.59 # Average memory access latency +system.physmem.avgRdBW 360.01 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 44.40 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 52.51 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.01 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 2.53 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.10 # Average read queue length over time +system.physmem.avgWrQLen 15.12 # Average write queue length over time +system.physmem.readRowHits 6625021 # Number of row buffer hits during reads +system.physmem.writeRowHits 788582 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.57 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 96.09 # Row buffer hit rate for writes +system.physmem.avgGap 158253.02 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -76,245 +234,245 @@ system.realview.nvmem.num_reads::cpu0.inst 5 # system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 56 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 56 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 56 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 70188 # number of replacements -system.l2c.tagsinuse 53228.072476 # Cycle average of tags in use -system.l2c.total_refs 1643838 # Total number of references to valid blocks. -system.l2c.sampled_refs 135351 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.145001 # Average number of references to valid blocks. +system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 68923 # number of replacements +system.l2c.tagsinuse 53039.119781 # Cycle average of tags in use +system.l2c.total_refs 1673706 # Total number of references to valid blocks. +system.l2c.sampled_refs 134114 # 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mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.768889 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.540897 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.577062 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.559043 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000241 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001102 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013475 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.221647 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.278314 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.106353 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000241 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001102 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013475 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.221647 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.278314 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.106353 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 56002 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 21002 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 37040.715108 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 38590.549561 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 49002 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 39071.170301 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45826.746479 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 39478.424022 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10031.671086 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10030.762382 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10031.276179 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10025.812057 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10063.204641 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10042.887283 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 32165.809682 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34622.318054 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 33438.062745 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56002 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 21002 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 37040.715108 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32839.279207 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 49002 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 39071.170301 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 35158.109968 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 34270.848407 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56002 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 21002 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 37040.715108 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32839.279207 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 49002 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 39071.170301 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 35158.109968 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 34270.848407 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -498,27 +656,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 4800569 # DTB read hits -system.cpu0.dtb.read_misses 2116 # DTB read misses -system.cpu0.dtb.write_hits 4101188 # DTB write hits -system.cpu0.dtb.write_misses 405 # DTB write misses +system.cpu0.dtb.read_hits 7072899 # DTB read hits +system.cpu0.dtb.read_misses 3762 # DTB read misses +system.cpu0.dtb.write_hits 5658444 # DTB write hits +system.cpu0.dtb.write_misses 809 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1539 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1807 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 91 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 139 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 203 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 4802685 # DTB read accesses -system.cpu0.dtb.write_accesses 4101593 # DTB write accesses +system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7076661 # DTB read accesses +system.cpu0.dtb.write_accesses 5659253 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 8901757 # DTB hits -system.cpu0.dtb.misses 2521 # DTB misses -system.cpu0.dtb.accesses 8904278 # DTB accesses -system.cpu0.itb.inst_hits 19425317 # ITB inst hits -system.cpu0.itb.inst_misses 1350 # ITB inst misses +system.cpu0.dtb.hits 12731343 # DTB hits +system.cpu0.dtb.misses 4571 # DTB misses +system.cpu0.dtb.accesses 12735914 # DTB accesses +system.cpu0.itb.inst_hits 29570664 # ITB inst hits +system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -527,86 +685,86 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1347 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 19426667 # ITB inst accesses -system.cpu0.itb.hits 19425317 # DTB hits -system.cpu0.itb.misses 1350 # DTB misses -system.cpu0.itb.accesses 19426667 # DTB accesses -system.cpu0.numCycles 2405785466 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 29572869 # ITB inst accesses +system.cpu0.itb.hits 29570664 # DTB hits +system.cpu0.itb.misses 2205 # DTB misses +system.cpu0.itb.accesses 29572869 # DTB accesses +system.cpu0.numCycles 2365766155 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 19048205 # Number of instructions committed -system.cpu0.committedOps 25051835 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 22684157 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4364 # Number of float alu accesses -system.cpu0.num_func_calls 868672 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 2620308 # number of instructions that are conditional controls -system.cpu0.num_int_insts 22684157 # number of integer instructions -system.cpu0.num_fp_insts 4364 # number of float instructions -system.cpu0.num_int_register_reads 128951400 # number of times the integer registers were read -system.cpu0.num_int_register_writes 23731440 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3980 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 384 # number of times the floating registers were written -system.cpu0.num_mem_refs 9388218 # number of memory refs -system.cpu0.num_load_insts 5047895 # Number of load instructions -system.cpu0.num_store_insts 4340323 # Number of store instructions -system.cpu0.num_idle_cycles 2301327262.807119 # Number of idle cycles -system.cpu0.num_busy_cycles 104458203.192881 # Number of busy cycles -system.cpu0.not_idle_fraction 0.043420 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.956580 # Percentage of idle cycles +system.cpu0.committedInsts 28872728 # Number of instructions committed +system.cpu0.committedOps 37219681 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33106320 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses +system.cpu0.num_func_calls 1241688 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4373344 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33106320 # number of integer instructions +system.cpu0.num_fp_insts 3860 # number of float instructions +system.cpu0.num_int_register_reads 190095843 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36231130 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written +system.cpu0.num_mem_refs 13399483 # number of memory refs +system.cpu0.num_load_insts 7410404 # Number of load instructions +system.cpu0.num_store_insts 5989079 # Number of store instructions +system.cpu0.num_idle_cycles 2224921697.356119 # Number of idle cycles +system.cpu0.num_busy_cycles 140844457.643881 # Number of busy cycles +system.cpu0.not_idle_fraction 0.059534 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.940466 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 34019 # number of quiesce instructions executed -system.cpu0.icache.replacements 283204 # number of replacements -system.cpu0.icache.tagsinuse 509.502445 # Cycle average of tags in use -system.cpu0.icache.total_refs 19141584 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 283716 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 67.467411 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 75588601000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.502445 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.995122 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.995122 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 19141584 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 19141584 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 19141584 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 19141584 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 19141584 # number of overall hits -system.cpu0.icache.overall_hits::total 19141584 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 283716 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 283716 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 283716 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 283716 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 283716 # number of overall misses -system.cpu0.icache.overall_misses::total 283716 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 3929859500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 3929859500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 3929859500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 3929859500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 3929859500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 3929859500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 19425300 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 19425300 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 19425300 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 19425300 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 19425300 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 19425300 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014605 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014605 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014605 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014605 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014605 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014605 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13851.384836 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13851.384836 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13851.384836 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13851.384836 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13851.384836 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13851.384836 # average overall miss latency +system.cpu0.kern.inst.quiesce 46697 # number of quiesce instructions executed +system.cpu0.icache.replacements 425421 # number of replacements +system.cpu0.icache.tagsinuse 509.627794 # Cycle average of tags in use +system.cpu0.icache.total_refs 29144714 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 425933 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 68.425583 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 74931906000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.627794 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.995367 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.995367 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 29144714 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 29144714 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29144714 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 29144714 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29144714 # number of overall hits +system.cpu0.icache.overall_hits::total 29144714 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 425933 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 425933 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 425933 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 425933 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 425933 # number of overall misses +system.cpu0.icache.overall_misses::total 425933 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5794506500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5794506500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5794506500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5794506500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5794506500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5794506500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 29570647 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 29570647 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 29570647 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 29570647 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 29570647 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 29570647 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014404 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014404 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014404 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014404 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014404 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014404 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13604.267573 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13604.267573 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13604.267573 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13604.267573 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13604.267573 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13604.267573 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -615,120 +773,120 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 283716 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 283716 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 283716 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 283716 # 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average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11604.267573 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 220249 # number of replacements -system.cpu0.dcache.tagsinuse 456.517669 # Cycle average of tags in use -system.cpu0.dcache.total_refs 8560161 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 220619 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 38.800652 # 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average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9466.395112 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9466.395112 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5936.099253 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5936.099253 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19645.160593 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19645.160593 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19645.160593 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 19645.160593 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -737,66 +895,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 205058 # number of writebacks -system.cpu0.dcache.writebacks::total 205058 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 146457 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 146457 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 116961 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 116961 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 7881 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7881 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7690 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7690 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 263418 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 263418 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 263418 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 263418 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1698225500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1698225500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3965521500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3965521500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 54497000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 54497000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 50753000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 50753000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.writebacks::writebacks 306622 # number of writebacks +system.cpu0.dcache.writebacks::total 306622 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 228156 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 228156 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141693 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 141693 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9329 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9329 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7493 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7493 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 369849 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 369849 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 369849 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 369849 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2678104000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2678104000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3847941000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3847941000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69654000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69654000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29513000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29513000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5663747000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 5663747000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5663747000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 5663747000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12130745000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12130745000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1193494500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1193494500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13324239500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13324239500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031846 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031846 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029465 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029465 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062741 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062741 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.061252 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.061252 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030743 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.030743 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030743 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.030743 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11595.386359 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11595.386359 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33904.647703 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33904.647703 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 6914.985408 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6914.985408 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6599.869961 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6599.869961 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6526045000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6526045000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6526045000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6526045000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13559793500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13559793500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128518500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128518500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14688312000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14688312000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033402 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033402 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025786 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025786 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059319 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059319 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047671 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047671 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030007 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.030007 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030007 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.030007 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11738.038886 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11738.038886 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27156.888484 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27156.888484 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7466.395112 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7466.395112 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3938.742827 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3938.742827 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21500.987024 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21500.987024 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21500.987024 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21500.987024 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17645.160593 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17645.160593 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17645.160593 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17645.160593 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -806,27 +964,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 10589201 # DTB read hits -system.cpu1.dtb.read_misses 5231 # DTB read misses -system.cpu1.dtb.write_hits 7383574 # DTB write hits -system.cpu1.dtb.write_misses 1834 # DTB write misses +system.cpu1.dtb.read_hits 8308478 # DTB read hits +system.cpu1.dtb.read_misses 3644 # DTB read misses +system.cpu1.dtb.write_hits 5825596 # DTB write hits +system.cpu1.dtb.write_misses 1434 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2257 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1965 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 193 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 249 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 10594432 # DTB read accesses -system.cpu1.dtb.write_accesses 7385408 # DTB write accesses +system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 8312122 # DTB read accesses +system.cpu1.dtb.write_accesses 5827030 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 17972775 # DTB hits -system.cpu1.dtb.misses 7065 # DTB misses -system.cpu1.dtb.accesses 17979840 # DTB accesses -system.cpu1.itb.inst_hits 43338256 # ITB inst hits -system.cpu1.itb.inst_misses 3017 # ITB inst misses +system.cpu1.dtb.hits 14134074 # DTB hits +system.cpu1.dtb.misses 5078 # DTB misses +system.cpu1.dtb.accesses 14139152 # DTB accesses +system.cpu1.itb.inst_hits 33188345 # ITB inst hits +system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -835,86 +993,86 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1458 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 43341273 # ITB inst accesses -system.cpu1.itb.hits 43338256 # DTB hits -system.cpu1.itb.misses 3017 # DTB misses -system.cpu1.itb.accesses 43341273 # DTB accesses -system.cpu1.numCycles 2407212998 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 33190516 # ITB inst accesses +system.cpu1.itb.hits 33188345 # DTB hits +system.cpu1.itb.misses 2171 # DTB misses +system.cpu1.itb.accesses 33190516 # DTB accesses +system.cpu1.numCycles 2364324255 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 42407344 # Number of instructions committed -system.cpu1.committedOps 53266051 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 47734651 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5457 # Number of float alu accesses -system.cpu1.num_func_calls 1334953 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 5482869 # number of instructions that are conditional controls -system.cpu1.num_int_insts 47734651 # number of integer instructions -system.cpu1.num_fp_insts 5457 # number of float instructions -system.cpu1.num_int_register_reads 274813771 # number of times the integer registers were read -system.cpu1.num_int_register_writes 51971016 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 3577 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1884 # number of times the floating registers were written -system.cpu1.num_mem_refs 18681443 # number of memory refs -system.cpu1.num_load_insts 10999206 # Number of load instructions -system.cpu1.num_store_insts 7682237 # Number of store instructions -system.cpu1.num_idle_cycles 1827286039.250482 # Number of idle cycles -system.cpu1.num_busy_cycles 579926958.749518 # Number of busy cycles -system.cpu1.not_idle_fraction 0.240912 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.759088 # Percentage of idle cycles +system.cpu1.committedInsts 32577871 # Number of instructions committed +system.cpu1.committedOps 41082259 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 37307050 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses +system.cpu1.num_func_calls 961975 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3732476 # number of instructions that are conditional controls +system.cpu1.num_int_insts 37307050 # number of integer instructions +system.cpu1.num_fp_insts 6793 # number of float instructions +system.cpu1.num_int_register_reads 213626787 # number of times the integer registers were read +system.cpu1.num_int_register_writes 39450306 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written +system.cpu1.num_mem_refs 14671800 # number of memory refs +system.cpu1.num_load_insts 8630367 # Number of load instructions +system.cpu1.num_store_insts 6041433 # Number of store instructions +system.cpu1.num_idle_cycles 1868325738.966939 # Number of idle cycles +system.cpu1.num_busy_cycles 495998516.033061 # Number of busy cycles +system.cpu1.not_idle_fraction 0.209784 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.790216 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 56704 # number of quiesce instructions executed -system.cpu1.icache.replacements 582576 # number of replacements -system.cpu1.icache.tagsinuse 479.066528 # Cycle average of tags in use -system.cpu1.icache.total_refs 42755164 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 583088 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 73.325405 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 92849627500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 479.066528 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.935677 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.935677 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 42755164 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 42755164 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 42755164 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 42755164 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 42755164 # number of overall hits -system.cpu1.icache.overall_hits::total 42755164 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 583088 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 583088 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 583088 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 583088 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 583088 # number of overall misses -system.cpu1.icache.overall_misses::total 583088 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7852005500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7852005500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7852005500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7852005500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7852005500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7852005500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 43338252 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 43338252 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 43338252 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 43338252 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 43338252 # 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number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 320038 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 320038 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 320038 # number of overall misses +system.cpu1.dcache.overall_misses::total 320038 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2152137500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2152137500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4507881000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 4507881000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 91883000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 91883000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 51759500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 51759500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6660018500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6660018500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6660018500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6660018500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 7114546 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 7114546 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4975310 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4975310 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92813 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 92813 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92738 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 92738 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 12089856 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 12089856 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 12089856 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 12089856 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023933 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.023933 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030102 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.030102 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119164 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119164 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108240 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108240 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026472 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.026472 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026472 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.026472 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12639.483529 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12639.483529 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30099.294237 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 30099.294237 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8307.685353 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8307.685353 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5156.355848 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5156.355848 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20810.086615 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20810.086615 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20810.086615 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20810.086615 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1045,66 +1203,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 366504 # number of writebacks -system.cpu1.dcache.writebacks::total 366504 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 253127 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 253127 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 178055 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 178055 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13099 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13099 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10394 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10394 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 431182 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 431182 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 431182 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 431182 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2770994500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2770994500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5292766500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5292766500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89595500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89595500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 42224000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 42224000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8063761000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 8063761000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8063761000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 8063761000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 170066366500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 170066366500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40314514000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40314514000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 210380880500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 210380880500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027062 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.027062 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027390 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027390 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.104844 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.104844 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.083244 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.083244 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027196 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027196 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027196 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.027196 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10947.052270 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10947.052270 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29725.458426 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 29725.458426 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6839.873273 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6839.873273 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4062.343660 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4062.343660 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 265110 # number of writebacks +system.cpu1.dcache.writebacks::total 265110 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170271 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 170271 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149767 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 149767 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11060 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11060 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10034 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10034 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 320038 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 320038 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 320038 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 320038 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1811595500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1811595500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4208347000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4208347000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 69763000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 69763000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31693500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31693500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6019942500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 6019942500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6019942500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 6019942500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168625975500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168625975500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17666930000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17666930000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186292905500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186292905500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023933 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023933 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030102 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030102 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119164 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119164 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108197 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108197 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026472 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026472 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026472 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026472 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10639.483529 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10639.483529 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28099.294237 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28099.294237 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6307.685353 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6307.685353 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3158.610724 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3158.610724 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18701.525110 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18701.525110 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18701.525110 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18701.525110 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18810.086615 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18810.086615 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18810.086615 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18810.086615 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1126,10 +1284,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 522347967555 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 522347967555 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 522347967555 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 522347967555 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 446709885400 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 446709885400 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 446709885400 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 446709885400 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |