diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt | 4668 |
1 files changed, 2334 insertions, 2334 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 3db65ab48..a16f61cf0 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,155 +1,155 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.869789 # Number of seconds simulated -sim_ticks 2869788970000 # Number of ticks simulated -final_tick 2869788970000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.869797 # Number of seconds simulated +sim_ticks 2869796829000 # Number of ticks simulated +final_tick 2869796829000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 540600 # Simulator instruction rate (inst/s) -host_op_rate 653886 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11792964574 # Simulator tick rate (ticks/s) -host_mem_usage 618088 # Number of bytes of host memory used -host_seconds 243.35 # Real time elapsed on the host -sim_insts 131553574 # Number of instructions simulated -sim_ops 159121622 # Number of ops (including micro ops) simulated +host_inst_rate 440783 # Simulator instruction rate (inst/s) +host_op_rate 533144 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9620737689 # Simulator tick rate (ticks/s) +host_mem_usage 612476 # Number of bytes of host memory used +host_seconds 298.29 # Real time elapsed on the host +sim_insts 131482259 # Number of instructions simulated +sim_ops 159033076 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1162532 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1281572 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8557696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 146452 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 567572 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 385664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1151908 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1242084 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8334784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 147092 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 510612 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 354880 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12103024 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1162532 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 146452 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1308984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8649280 # Number of bytes written to this memory +system.physmem.bytes_read::total 11742896 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1151908 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 147092 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1299000 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8345408 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8666844 # Number of bytes written to this memory +system.physmem.bytes_written::total 8362972 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26618 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 20544 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 133714 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2443 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8889 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 6026 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26452 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 19927 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 130231 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2453 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 7999 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 5545 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 198258 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 135145 # Number of write requests responded to by this memory +system.physmem.num_reads::total 192631 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 130397 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 139536 # Number of write requests responded to by this memory +system.physmem.num_writes::total 134788 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 405093 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 446574 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2981995 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 51032 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 197775 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 134388 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 401390 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 432813 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2904312 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 51255 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 177926 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 123660 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4217392 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 405093 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 51032 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 456126 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3013908 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4091891 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 401390 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 51255 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 452645 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2908014 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6106 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3020028 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3013908 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2914134 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2908014 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 405093 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 452680 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2981995 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 51032 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 197789 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 134388 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 401390 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 438919 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2904312 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 51255 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 177940 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 123660 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7237420 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 198258 # Number of read requests accepted -system.physmem.writeReqs 139536 # Number of write requests accepted -system.physmem.readBursts 198258 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 139536 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12678976 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9536 # Total number of bytes read from write queue -system.physmem.bytesWritten 8679232 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12103024 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8666844 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 149 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 7006025 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 192631 # Number of read requests accepted +system.physmem.writeReqs 134788 # Number of write requests accepted +system.physmem.readBursts 192631 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 134788 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12319616 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8768 # Total number of bytes read from write queue +system.physmem.bytesWritten 8376000 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11742896 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8362972 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 137 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11529 # Per bank write bursts -system.physmem.perBankRdBursts::1 11853 # Per bank write bursts -system.physmem.perBankRdBursts::2 12105 # Per bank write bursts -system.physmem.perBankRdBursts::3 12154 # Per bank write bursts -system.physmem.perBankRdBursts::4 20931 # Per bank write bursts -system.physmem.perBankRdBursts::5 12788 # Per bank write bursts -system.physmem.perBankRdBursts::6 12012 # Per bank write bursts -system.physmem.perBankRdBursts::7 12170 # Per bank write bursts -system.physmem.perBankRdBursts::8 12327 # Per bank write bursts -system.physmem.perBankRdBursts::9 12530 # Per bank write bursts -system.physmem.perBankRdBursts::10 11492 # Per bank write bursts -system.physmem.perBankRdBursts::11 10989 # Per bank write bursts -system.physmem.perBankRdBursts::12 11634 # Per bank write bursts -system.physmem.perBankRdBursts::13 11866 # Per bank write bursts -system.physmem.perBankRdBursts::14 10750 # Per bank write bursts -system.physmem.perBankRdBursts::15 10979 # Per bank write bursts -system.physmem.perBankWrBursts::0 8343 # Per bank write bursts -system.physmem.perBankWrBursts::1 8774 # Per bank write bursts -system.physmem.perBankWrBursts::2 9050 # Per bank write bursts -system.physmem.perBankWrBursts::3 8765 # Per bank write bursts -system.physmem.perBankWrBursts::4 8633 # Per bank write bursts -system.physmem.perBankWrBursts::5 9228 # Per bank write bursts -system.physmem.perBankWrBursts::6 8690 # Per bank write bursts -system.physmem.perBankWrBursts::7 8516 # Per bank write bursts -system.physmem.perBankWrBursts::8 8766 # Per bank write bursts -system.physmem.perBankWrBursts::9 8956 # Per bank write bursts -system.physmem.perBankWrBursts::10 8280 # Per bank write bursts -system.physmem.perBankWrBursts::11 8060 # Per bank write bursts -system.physmem.perBankWrBursts::12 8431 # Per bank write bursts -system.physmem.perBankWrBursts::13 8106 # Per bank write bursts -system.physmem.perBankWrBursts::14 7529 # Per bank write bursts -system.physmem.perBankWrBursts::15 7486 # Per bank write bursts +system.physmem.perBankRdBursts::0 11574 # Per bank write bursts +system.physmem.perBankRdBursts::1 11705 # Per bank write bursts +system.physmem.perBankRdBursts::2 12139 # Per bank write bursts +system.physmem.perBankRdBursts::3 12297 # Per bank write bursts +system.physmem.perBankRdBursts::4 20811 # Per bank write bursts +system.physmem.perBankRdBursts::5 12493 # Per bank write bursts +system.physmem.perBankRdBursts::6 11636 # Per bank write bursts +system.physmem.perBankRdBursts::7 11627 # Per bank write bursts +system.physmem.perBankRdBursts::8 11518 # Per bank write bursts +system.physmem.perBankRdBursts::9 11803 # Per bank write bursts +system.physmem.perBankRdBursts::10 10854 # Per bank write bursts +system.physmem.perBankRdBursts::11 10225 # Per bank write bursts +system.physmem.perBankRdBursts::12 10900 # Per bank write bursts +system.physmem.perBankRdBursts::13 11460 # Per bank write bursts +system.physmem.perBankRdBursts::14 10649 # Per bank write bursts +system.physmem.perBankRdBursts::15 10803 # Per bank write bursts +system.physmem.perBankWrBursts::0 8359 # Per bank write bursts +system.physmem.perBankWrBursts::1 8644 # Per bank write bursts +system.physmem.perBankWrBursts::2 9057 # Per bank write bursts +system.physmem.perBankWrBursts::3 8858 # Per bank write bursts +system.physmem.perBankWrBursts::4 8408 # Per bank write bursts +system.physmem.perBankWrBursts::5 8900 # Per bank write bursts +system.physmem.perBankWrBursts::6 8435 # Per bank write bursts +system.physmem.perBankWrBursts::7 8166 # Per bank write bursts +system.physmem.perBankWrBursts::8 8021 # Per bank write bursts +system.physmem.perBankWrBursts::9 8475 # Per bank write bursts +system.physmem.perBankWrBursts::10 7798 # Per bank write bursts +system.physmem.perBankWrBursts::11 7415 # Per bank write bursts +system.physmem.perBankWrBursts::12 7820 # Per bank write bursts +system.physmem.perBankWrBursts::13 7815 # Per bank write bursts +system.physmem.perBankWrBursts::14 7421 # Per bank write bursts +system.physmem.perBankWrBursts::15 7283 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 45 # Number of times write queue was full causing retry -system.physmem.totGap 2869788469000 # Total gap between requests +system.physmem.numWrRetry 25 # Number of times write queue was full causing retry +system.physmem.totGap 2869796310500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9732 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 188498 # Read request sizes (log2) +system.physmem.readPktSize::6 182871 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 135145 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 138706 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 15839 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 10261 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8725 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6930 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5461 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4641 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3898 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3401 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 95 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 62 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 46 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 130397 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 135454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 15340 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 9792 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6685 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5269 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4441 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3740 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3238 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 65 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 39 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -181,163 +181,165 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2819 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6581 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8640 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8582 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8458 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9785 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 113 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 89189 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 239.470607 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 135.176312 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 302.792926 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 47900 53.71% 53.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17682 19.83% 73.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5838 6.55% 80.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3495 3.92% 84.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2471 2.77% 86.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1457 1.63% 88.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1048 1.18% 89.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 998 1.12% 90.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8300 9.31% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 89189 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6684 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 29.638989 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 578.089254 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6683 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6684 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6684 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.289198 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.751921 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.518584 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5662 84.71% 84.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 280 4.19% 88.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 70 1.05% 89.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 44 0.66% 90.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 285 4.26% 94.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 29 0.43% 95.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 28 0.42% 95.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 27 0.40% 96.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 17 0.25% 96.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 10 0.15% 96.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.07% 96.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 9 0.13% 96.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 159 2.38% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 2 0.03% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 11 0.16% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 1 0.01% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 9 0.13% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.03% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.01% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.01% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 6 0.09% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 2 0.03% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 8 0.12% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 5 0.07% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.03% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6684 # Writes before turning the bus around for reads -system.physmem.totQLat 4572903146 # Total ticks spent queuing -system.physmem.totMemAccLat 8287446896 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 990545000 # Total ticks spent in databus transfers -system.physmem.avgQLat 23082.76 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 2678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9787 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7846 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7002 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 418 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 97 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 85101 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 243.188118 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 136.988063 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 305.573889 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 45210 53.13% 53.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16886 19.84% 72.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5688 6.68% 79.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3460 4.07% 83.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2293 2.69% 86.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1445 1.70% 88.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 997 1.17% 89.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 929 1.09% 90.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8193 9.63% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 85101 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6403 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 30.062939 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 590.633185 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6402 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6403 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6403 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.439638 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.792302 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.006159 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5407 84.44% 84.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 293 4.58% 89.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 63 0.98% 90.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 46 0.72% 90.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 252 3.94% 94.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 29 0.45% 95.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 22 0.34% 95.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 17 0.27% 95.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 14 0.22% 95.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 8 0.12% 96.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.08% 96.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 12 0.19% 96.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 163 2.55% 98.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.06% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 10 0.16% 99.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 4 0.06% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 10 0.16% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.03% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.02% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 4 0.06% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 4 0.06% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.03% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 3 0.05% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 5 0.08% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 9 0.14% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 3 0.05% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 2 0.03% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6403 # Writes before turning the bus around for reads +system.physmem.totQLat 4388531068 # Total ticks spent queuing +system.physmem.totMemAccLat 7997793568 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 962470000 # Total ticks spent in databus transfers +system.physmem.avgQLat 22798.27 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 41832.76 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.42 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.02 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.22 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.02 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 41548.27 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.29 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.92 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.09 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.91 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.56 # Average write queue length when enqueuing -system.physmem.readRowHits 165757 # Number of row buffer hits during reads -system.physmem.writeRowHits 78775 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.67 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 58.08 # Row buffer hit rate for writes -system.physmem.avgGap 8495676.27 # Average gap between requests -system.physmem.pageHitRate 73.27 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 348221160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 190001625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 823219800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 453593520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 187440467760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 84729042225 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1647547995750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1921532541840 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.573415 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2740710565422 # Time in different power states -system.physmem_0.memoryStateTime::REF 95828460000 # Time in different power states +system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.14 # Average write queue length when enqueuing +system.physmem.readRowHits 160943 # Number of row buffer hits during reads +system.physmem.writeRowHits 77324 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.61 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 59.07 # Row buffer hit rate for writes +system.physmem.avgGap 8764904.63 # Average gap between requests +system.physmem.pageHitRate 73.68 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 343133280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 187225500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 813391800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 445998960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 187440976320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 84650934555 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1647621183000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1921502843415 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.561249 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2740835391788 # Time in different power states +system.physmem_0.memoryStateTime::REF 95828720000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 33249848578 # Time in different power states +system.physmem_0.memoryStateTime::ACT 33132603712 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 326047680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 177903000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 722022600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 425178720 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 187440467760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 84061530045 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1648133532750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1921286682555 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.487743 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2741691180386 # Time in different power states -system.physmem_1.memoryStateTime::REF 95828460000 # Time in different power states +system.physmem_1.actEnergy 300230280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 163816125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 688053600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 402071040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 187440976320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 83039782815 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1649034474000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1921069404180 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.410214 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2743194226190 # Time in different power states +system.physmem_1.memoryStateTime::REF 95828720000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 32266568364 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30771048810 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -356,9 +358,9 @@ system.realview.nvmem.bw_inst_read::total 24 # I system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -366,7 +368,7 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -396,62 +398,61 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 7943 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 7943 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1501 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6442 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 7943 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 7943 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 7943 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6549 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12300.885631 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11415.801761 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 5728.954139 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 6064 92.59% 92.59% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 441 6.73% 99.33% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 34 0.52% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-65535 4 0.06% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 2 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-114687 2 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-147455 1 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6549 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 7605 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 7605 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1343 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6262 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 7605 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 7605 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 7605 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6211 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12321.365320 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11473.330493 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 5604.476225 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 5759 92.72% 92.72% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 412 6.63% 99.36% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 31 0.50% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 4 0.06% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 2 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-114687 2 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6211 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 1125817500 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 1125817500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 1125817500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5087 77.68% 77.68% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1462 22.32% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6549 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7943 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 4907 79.00% 79.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1304 21.00% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6211 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7605 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7943 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6549 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7605 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6211 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6549 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 14492 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6211 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 13816 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25156508 # DTB read hits -system.cpu0.dtb.read_misses 6829 # DTB read misses -system.cpu0.dtb.write_hits 18749941 # DTB write hits -system.cpu0.dtb.write_misses 1114 # DTB write misses +system.cpu0.dtb.read_hits 22785353 # DTB read hits +system.cpu0.dtb.read_misses 6506 # DTB read misses +system.cpu0.dtb.write_hits 17536845 # DTB write hits +system.cpu0.dtb.write_misses 1099 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3392 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3343 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1731 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 1756 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25163337 # DTB read accesses -system.cpu0.dtb.write_accesses 18751055 # DTB write accesses +system.cpu0.dtb.read_accesses 22791859 # DTB read accesses +system.cpu0.dtb.write_accesses 17537944 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 43906449 # DTB hits -system.cpu0.dtb.misses 7943 # DTB misses -system.cpu0.dtb.accesses 43914392 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 40322198 # DTB hits +system.cpu0.dtb.misses 7605 # DTB misses +system.cpu0.dtb.accesses 40329803 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -481,7 +482,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states system.cpu0.itb.walker.walks 3349 # Table walker walks requested system.cpu0.itb.walker.walksShort 3349 # Table walker walks initiated with short descriptors system.cpu0.itb.walker.walksShortTerminationLevel::Level1 299 # Level at which table walker walks with short descriptors terminate @@ -490,16 +491,16 @@ system.cpu0.itb.walker.walkWaitTime::samples 3349 system.cpu0.itb.walker.walkWaitTime::0 3349 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::total 3349 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkCompletionTime::samples 2333 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12856.622375 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 12024.130170 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5718.443506 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 360 15.43% 15.43% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1695 72.65% 88.08% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 216 9.26% 97.34% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 29 1.24% 98.59% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 29 1.24% 99.83% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.04% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12840.762966 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 12002.591700 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5837.643760 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 347 14.87% 14.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1703 73.00% 87.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 210 9.00% 96.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 26 1.11% 97.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 42 1.80% 99.79% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 2 0.09% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.91% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::122880-131071 1 0.04% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::total 2333 # Table walker service (enqueue to completion) latency @@ -516,7 +517,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2333 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2333 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin::total 5682 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 119016789 # ITB inst hits +system.cpu0.itb.inst_hits 108479195 # ITB inst hits system.cpu0.itb.inst_misses 3349 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -533,779 +534,771 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 119020138 # ITB inst accesses -system.cpu0.itb.hits 119016789 # DTB hits +system.cpu0.itb.inst_accesses 108482544 # ITB inst accesses +system.cpu0.itb.hits 108479195 # DTB hits system.cpu0.itb.misses 3349 # DTB misses -system.cpu0.itb.accesses 119020138 # DTB accesses -system.cpu0.numPwrStateTransitions 3732 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 1866 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 1464105256.698285 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 23703834177.511120 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1075 57.61% 57.61% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 786 42.12% 99.73% # Distribution of time spent in the clock gated state +system.cpu0.itb.accesses 108482544 # DTB accesses +system.cpu0.numPwrStateTransitions 3748 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 1874 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 1464520585.209178 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 23650117166.731750 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1082 57.74% 57.74% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 787 42.00% 99.73% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.79% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.21% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 499964077872 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 1866 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 137768561001 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2732020408999 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 5739577940 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 499966342824 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 1874 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 125285252318 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2744511576682 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 5739593658 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1866 # number of quiesce instructions executed -system.cpu0.committedInsts 115352405 # Number of instructions committed -system.cpu0.committedOps 139380194 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 123360698 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 9756 # Number of float alu accesses -system.cpu0.num_func_calls 12675179 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 15700187 # number of instructions that are conditional controls -system.cpu0.num_int_insts 123360698 # number of integer instructions -system.cpu0.num_fp_insts 9756 # number of float instructions -system.cpu0.num_int_register_reads 227063318 # number of times the integer registers were read -system.cpu0.num_int_register_writes 85717152 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 7496 # number of times the floating registers were read +system.cpu0.kern.inst.quiesce 1874 # number of quiesce instructions executed +system.cpu0.committedInsts 105397426 # Number of instructions committed +system.cpu0.committedOps 127063433 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 112192231 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 9820 # Number of float alu accesses +system.cpu0.num_func_calls 10407708 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14566669 # number of instructions that are conditional controls +system.cpu0.num_int_insts 112192231 # number of integer instructions +system.cpu0.num_fp_insts 9820 # number of float instructions +system.cpu0.num_int_register_reads 204819570 # number of times the integer registers were read +system.cpu0.num_int_register_writes 77435370 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 7560 # number of times the floating registers were read system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 504942676 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 52291767 # number of times the CC registers were written -system.cpu0.num_mem_refs 45042977 # number of memory refs -system.cpu0.num_load_insts 25408336 # Number of load instructions -system.cpu0.num_store_insts 19634641 # Number of store instructions -system.cpu0.num_idle_cycles 5464040817.996096 # Number of idle cycles -system.cpu0.num_busy_cycles 275537122.003904 # Number of busy cycles -system.cpu0.not_idle_fraction 0.048007 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.951993 # Percentage of idle cycles -system.cpu0.Branches 29113703 # Number of branches fetched +system.cpu0.num_cc_register_reads 459130085 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 48875384 # number of times the CC registers were written +system.cpu0.num_mem_refs 41457196 # number of memory refs +system.cpu0.num_load_insts 23036367 # Number of load instructions +system.cpu0.num_store_insts 18420829 # Number of store instructions +system.cpu0.num_idle_cycles 5489023153.362087 # Number of idle cycles +system.cpu0.num_busy_cycles 250570504.637913 # Number of busy cycles +system.cpu0.not_idle_fraction 0.043656 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.956344 # Percentage of idle cycles +system.cpu0.Branches 25689353 # Number of branches fetched system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 97981864 68.45% 68.45% # Class of executed instruction -system.cpu0.op_class::IntMult 109763 0.08% 68.53% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 8197 0.01% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::MemRead 25408336 17.75% 86.28% # Class of executed instruction -system.cpu0.op_class::MemWrite 19634641 13.72% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 88685820 68.09% 68.09% # Class of executed instruction +system.cpu0.op_class::IntMult 91693 0.07% 68.16% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 8209 0.01% 68.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 68.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.17% # Class of executed instruction +system.cpu0.op_class::MemRead 23036367 17.69% 85.86% # Class of executed instruction +system.cpu0.op_class::MemWrite 18420829 14.14% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 143145074 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 692159 # number of replacements -system.cpu0.dcache.tags.tagsinuse 489.914647 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 43035506 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 692671 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 62.129793 # Average number of references to valid blocks. +system.cpu0.op_class::total 130245191 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 690306 # number of replacements +system.cpu0.dcache.tags.tagsinuse 490.313655 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 39473136 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 690818 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 57.139704 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 1151827000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 489.914647 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.956865 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.956865 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 490.313655 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.957644 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.957644 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 315 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 96 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 88449499 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 88449499 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 23895288 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23895288 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 18018356 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18018356 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 319106 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 319106 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365501 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 365501 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362365 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 362365 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 41913644 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41913644 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 42232750 # number of overall hits -system.cpu0.dcache.overall_hits::total 42232750 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 396096 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 396096 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 325040 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 325040 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127692 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 127692 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21584 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21584 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19801 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 19801 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 721136 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 721136 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 848828 # number of overall misses -system.cpu0.dcache.overall_misses::total 848828 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5078698000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5078698000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5729362000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 5729362000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 329182500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 329182500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 472585500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 472585500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1446500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1446500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 10808060000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 10808060000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 10808060000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 10808060000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 24291384 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 24291384 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 18343396 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 18343396 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446798 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 446798 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387085 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 387085 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382166 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 382166 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 42634780 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 42634780 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 43081578 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 43081578 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016306 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.016306 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017720 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.017720 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.285794 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.285794 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055760 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055760 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051813 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051813 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016914 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.016914 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019703 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.019703 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12821.886613 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12821.886613 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17626.636722 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 17626.636722 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15251.227761 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15251.227761 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23866.749154 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23866.749154 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 81317769 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 81317769 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 21536394 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 21536394 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 16814376 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 16814376 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 319053 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 319053 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365550 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 365550 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362389 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 362389 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 38350770 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 38350770 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 38669823 # number of overall hits +system.cpu0.dcache.overall_hits::total 38669823 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 394644 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 394644 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 324668 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 324668 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127577 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 127577 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21580 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21580 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19821 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 19821 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 719312 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 719312 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 846889 # number of overall misses +system.cpu0.dcache.overall_misses::total 846889 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5059230000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5059230000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5720917500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 5720917500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 328019500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 328019500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 473718500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 473718500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1421500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1421500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 10780147500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 10780147500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 10780147500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 10780147500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 21931038 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 21931038 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 17139044 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 17139044 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446630 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 446630 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387130 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 387130 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382210 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 382210 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 39070082 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 39070082 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 39516712 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 39516712 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.017995 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.017995 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018943 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018943 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.285644 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.285644 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055744 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055744 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051859 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051859 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018411 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.018411 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021431 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.021431 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12819.731201 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 12819.731201 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17620.823426 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 17620.823426 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15200.162187 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15200.162187 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23899.828465 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23899.828465 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14987.547425 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14987.547425 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12732.921157 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 12732.921157 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14986.747753 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14986.747753 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12729.115032 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 12729.115032 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 692159 # number of writebacks -system.cpu0.dcache.writebacks::total 692159 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25284 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 25284 # number of ReadReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15032 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15032 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 25284 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 25284 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 25284 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 25284 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 370812 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 370812 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325040 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 325040 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100482 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 100482 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6552 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6552 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19801 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 19801 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 695852 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 695852 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 796334 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 796334 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31792 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31792 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28463 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28463 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60255 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60255 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4312931000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4312931000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5404322000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5404322000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1615427000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1615427000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 98795500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 98795500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 452825500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 452825500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1405500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1405500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9717253000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9717253000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11332680000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11332680000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6628901000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6628901000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6628901000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6628901000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015265 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015265 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017720 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017720 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224894 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224894 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016927 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016927 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051813 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051813 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016321 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.016321 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018484 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018484 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11631.044842 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11631.044842 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16626.636722 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16626.636722 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16076.779921 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16076.779921 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15078.678266 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15078.678266 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22868.819757 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22868.819757 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 690306 # number of writebacks +system.cpu0.dcache.writebacks::total 690306 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25258 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 25258 # number of ReadReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14953 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14953 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 25258 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 25258 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 25258 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 25258 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 369386 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 369386 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324668 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 324668 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100493 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 100493 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6627 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6627 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19821 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 19821 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 694054 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 694054 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 794547 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 794547 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 21106 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 21106 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19680 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19680 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 40786 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 40786 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4295278500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4295278500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5396249500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5396249500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1609240500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1609240500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 98443000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 98443000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 453938500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 453938500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1380500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1380500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9691528000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9691528000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11300768500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11300768500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4679128000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4679128000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4679128000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4679128000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016843 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016843 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018943 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018943 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225003 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225003 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017118 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017118 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051859 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051859 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.017764 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.017764 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020107 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.020107 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11628.157266 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11628.157266 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16620.823426 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16620.823426 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16013.458649 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16013.458649 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14854.836276 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14854.836276 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22901.896978 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22901.896978 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13964.539873 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13964.539873 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14231.063850 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14231.063850 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208508.461248 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208508.461248 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110014.123309 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110014.123309 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1103881 # number of replacements +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13963.651243 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13963.651243 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14222.907518 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14222.907518 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221696.579172 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221696.579172 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 114723.875840 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 114723.875840 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 1101713 # number of replacements system.cpu0.icache.tags.tagsinuse 511.449165 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 117912387 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1104393 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 106.766692 # Average number of references to valid blocks. +system.cpu0.icache.tags.total_refs 107376961 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1102225 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 97.418368 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 14058108000 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.449165 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998924 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.998924 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 214 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 220 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 203 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 239137980 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 239137980 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 117912387 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 117912387 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 117912387 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 117912387 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 117912387 # number of overall hits -system.cpu0.icache.overall_hits::total 117912387 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1104402 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1104402 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1104402 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1104402 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1104402 # number of overall misses -system.cpu0.icache.overall_misses::total 1104402 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11028665000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 11028665000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 11028665000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 11028665000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 11028665000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 11028665000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 119016789 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 119016789 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 119016789 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 119016789 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 119016789 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 119016789 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009279 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.009279 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009279 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.009279 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009279 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.009279 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9986.096548 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9986.096548 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9986.096548 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9986.096548 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9986.096548 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9986.096548 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 218060624 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 218060624 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 107376961 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 107376961 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 107376961 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 107376961 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 107376961 # number of overall hits +system.cpu0.icache.overall_hits::total 107376961 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1102234 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1102234 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1102234 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1102234 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1102234 # number of overall misses +system.cpu0.icache.overall_misses::total 1102234 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10984481500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10984481500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10984481500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10984481500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10984481500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10984481500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 108479195 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 108479195 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 108479195 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 108479195 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 108479195 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 108479195 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010161 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.010161 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010161 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.010161 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010161 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.010161 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9965.652938 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9965.652938 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9965.652938 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9965.652938 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9965.652938 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9965.652938 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1103881 # number of writebacks -system.cpu0.icache.writebacks::total 1103881 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1104402 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1104402 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1104402 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1104402 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1104402 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1104402 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 1101713 # number of writebacks +system.cpu0.icache.writebacks::total 1101713 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1102234 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1102234 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1102234 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1102234 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1102234 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1102234 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10476464000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10476464000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10476464000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10476464000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10476464000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10476464000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10433364500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10433364500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10433364500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10433364500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10433364500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10433364500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 811416500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 811416500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 811416500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 811416500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009279 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009279 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009279 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.009279 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009279 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.009279 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9486.096548 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9486.096548 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9486.096548 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9486.096548 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9486.096548 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9486.096548 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010161 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010161 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010161 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.010161 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010161 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.010161 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9465.652938 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9465.652938 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9465.652938 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9465.652938 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9465.652938 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9465.652938 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 89937.541565 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 89937.541565 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 89937.541565 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 89937.541565 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1853175 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1853224 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 43 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1850136 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1850170 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 29 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 238416 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 266444 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16079.510665 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 2925486 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 282538 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 10.354310 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 236334 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 266149 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16069.328191 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 2918942 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 282232 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 10.342350 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14606.769244 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.268403 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.133561 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1470.339456 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.891526 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000138 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.089742 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.981415 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1047 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 14514.612326 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.486543 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.157051 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1554.072270 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.885902 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000030 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000010 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.094853 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.980794 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1018 # Occupied blocks per task id system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15041 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 289 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 351 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 399 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 215 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3327 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7676 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3752 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.063904 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15059 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 235 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 358 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 412 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 218 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3210 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7726 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3842 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.062134 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.918030 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 60110945 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 60110945 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10236 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4573 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 14809 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 476837 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 476837 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 1291246 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 1291246 # number of WritebackClean hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 227142 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 227142 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1059122 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 1059122 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 383679 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 383679 # number of ReadSharedReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10236 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4573 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1059122 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 610821 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1684752 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10236 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4573 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1059122 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 610821 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1684752 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 226 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 140 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 366 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55088 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 55088 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19799 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 19799 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 42810 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 42810 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 45280 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 45280 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 94167 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 94167 # number of ReadSharedReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 226 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 140 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 45280 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 136977 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 182623 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 226 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 140 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 45280 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 136977 # number of overall misses -system.cpu0.l2cache.overall_misses::total 182623 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 5649500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3340000 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 8989500 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 99195500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 99195500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 22445500 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 22445500 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1343499 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1343499 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2047795000 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 2047795000 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2416123000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2416123000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2805928000 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2805928000 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 5649500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3340000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2416123000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 4853723000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 7278835500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 5649500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3340000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2416123000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 4853723000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 7278835500 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10462 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4713 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 15175 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 476837 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 476837 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 1291246 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 1291246 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55088 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 55088 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19799 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 19799 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269952 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 269952 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1104402 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 1104402 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 477846 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 477846 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10462 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4713 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1104402 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 747798 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1867375 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10462 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4713 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1104402 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 747798 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1867375 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.021602 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.029705 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.024119 # miss rate for ReadReq accesses +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.919128 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 59974635 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 59974635 # Number of data accesses +system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 9773 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4523 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 14296 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 475089 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 475089 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 1289020 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 1289020 # number of WritebackClean hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 224372 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 224372 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1057524 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 1057524 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 382410 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 382410 # number of ReadSharedReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 9773 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4523 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1057524 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 606782 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1678602 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 9773 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4523 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1057524 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 606782 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1678602 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 217 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 146 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 363 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55553 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 55553 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19821 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 19821 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44743 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 44743 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 44710 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 44710 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 94096 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 94096 # number of ReadSharedReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 217 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 146 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 44710 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 138839 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 183912 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 217 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 146 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 44710 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 138839 # number of overall misses +system.cpu0.l2cache.overall_misses::total 183912 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 5274500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3487000 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 8761500 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 99258500 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 99258500 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 22708000 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 22708000 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1319000 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1319000 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2047288500 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 2047288500 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2385299500 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2385299500 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2791991500 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2791991500 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 5274500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3487000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2385299500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 4839280000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 7233341000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 5274500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3487000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2385299500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 4839280000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 7233341000 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 9990 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4669 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 14659 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::writebacks 475089 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::total 475089 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::writebacks 1289020 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::total 1289020 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55553 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 55553 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19821 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 19821 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269115 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 269115 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1102234 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 1102234 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 476506 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 476506 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 9990 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4669 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1102234 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 745621 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 1862514 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 9990 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4669 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1102234 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 745621 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 1862514 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.021722 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.031270 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.024763 # miss rate for ReadReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.158584 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.158584 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.041000 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.041000 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.197066 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.197066 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.021602 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.029705 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.041000 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.183174 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.097797 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.021602 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.029705 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.041000 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.183174 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.097797 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 24997.787611 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23857.142857 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 24561.475410 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 1800.673468 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 1800.673468 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1133.668367 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1133.668367 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 671749.500000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 671749.500000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 47834.501285 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 47834.501285 # average ReadExReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 53359.606890 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 53359.606890 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 29797.360009 # average ReadSharedReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 29797.360009 # average ReadSharedReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 24997.787611 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23857.142857 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 53359.606890 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35434.583908 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 39857.167498 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 24997.787611 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23857.142857 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 53359.606890 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35434.583908 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 39857.167498 # average overall miss latency +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.166260 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.166260 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.040563 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.040563 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.197471 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.197471 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.021722 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.031270 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040563 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.186206 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.098744 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.021722 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.031270 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040563 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.186206 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.098744 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 24306.451613 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23883.561644 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 24136.363636 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 1786.735190 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 1786.735190 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1145.653600 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1145.653600 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 45756.621147 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 45756.621147 # average ReadExReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 53350.469694 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 53350.469694 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 29671.734186 # average ReadSharedReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 29671.734186 # average ReadSharedReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 24306.451613 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23883.561644 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 53350.469694 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 34855.336037 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 39330.446083 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 24306.451613 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23883.561644 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 53350.469694 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 34855.336037 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 39330.446083 # average overall miss latency system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l2cache.unused_prefetches 10477 # number of HardPF blocks evicted w/o reference -system.cpu0.l2cache.writebacks::writebacks 227975 # number of writebacks -system.cpu0.l2cache.writebacks::total 227975 # number of writebacks -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1162 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 1162 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 30 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 30 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1192 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 1192 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1192 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 1192 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 226 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 140 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 259577 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 259577 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55088 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55088 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19799 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19799 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41648 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 41648 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 45280 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 45280 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 94137 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 94137 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 226 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 140 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 45280 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 135785 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 181431 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 226 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 140 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 45280 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 135785 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 259577 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 441008 # number of overall MSHR misses +system.cpu0.l2cache.unused_prefetches 11148 # number of HardPF blocks evicted w/o reference +system.cpu0.l2cache.writebacks::writebacks 227538 # number of writebacks +system.cpu0.l2cache.writebacks::total 227538 # number of writebacks +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1132 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 1132 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 31 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 31 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1163 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 1163 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1163 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 1163 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 217 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 146 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 363 # number of ReadReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 258758 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 258758 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55553 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55553 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19821 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19821 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43611 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 43611 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 44710 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 44710 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 94065 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 94065 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 217 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 146 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 44710 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 137676 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 182749 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 217 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 146 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 44710 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 137676 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 258758 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 441507 # number of overall MSHR misses system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31792 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40814 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28463 # number of WriteReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28463 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 21106 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 30128 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 19680 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 19680 # number of WriteReq MSHR uncacheable system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60255 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69277 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 4293500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2500000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 6793500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13785822950 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13785822950 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1059758500 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1059758500 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 304568000 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 304568000 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1097499 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1097499 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1683019500 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1683019500 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2144443000 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2144443000 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2236275000 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2236275000 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 4293500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2500000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2144443000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3919294500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 6070531000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 4293500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2500000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2144443000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3919294500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13785822950 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 19856353950 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 40786 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 49808 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3972500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2611000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 6583500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13423934365 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13423934365 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1067977500 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1067977500 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 305529500 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 305529500 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1073000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1073000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1676618000 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1676618000 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2117039500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2117039500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2223147000 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2223147000 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 3972500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2611000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2117039500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3899765000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 6023388000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 3972500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2611000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2117039500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3899765000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13423934365 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 19447322365 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 743751500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6374150500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7117902000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4509867000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5253618500 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 743751500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6374150500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7117902000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021602 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.029705 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.024119 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4509867000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 5253618500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021722 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.031270 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.024763 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.154279 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.154279 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.041000 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.041000 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.197003 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.197003 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021602 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.029705 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.041000 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.181580 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.097158 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021602 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.029705 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.041000 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.181580 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.162053 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.162053 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.040563 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040563 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.197406 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.197406 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021722 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.031270 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.040563 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.184646 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.098120 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021722 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.031270 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.040563 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.184646 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.236165 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 18997.787611 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17857.142857 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 18561.475410 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53108.799894 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53108.799894 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19237.556274 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19237.556274 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15382.999141 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15382.999141 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 548749.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 548749.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40410.571936 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40410.571936 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 47359.606890 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 47359.606890 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23755.537143 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23755.537143 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 18997.787611 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17857.142857 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 47359.606890 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28863.972456 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33459.171806 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 18997.787611 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17857.142857 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 47359.606890 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28863.972456 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53108.799894 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45024.929140 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.237049 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 18306.451613 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17883.561644 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 18136.363636 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 51878.335607 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 51878.335607 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19224.479326 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19224.479326 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15414.434186 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15414.434186 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38444.841898 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38444.841898 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 47350.469694 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 47350.469694 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23634.157232 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23634.157232 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 18306.451613 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17883.561644 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 47350.469694 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28325.670415 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32959.895813 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 18306.451613 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17883.561644 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 47350.469694 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28325.670415 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 51878.335607 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44047.596901 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 82437.541565 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200495.423377 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174398.539717 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 213677.011276 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174376.609798 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 82437.541565 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105786.250104 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 102745.528819 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 3735263 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1883109 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27957 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 316049 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 311748 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4301 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 61613 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1692022 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28463 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28463 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 705040 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 1319203 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 185302 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 307927 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 87515 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42104 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 112492 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 289204 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 285566 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1104402 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 556293 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3323 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3330729 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2559536 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11112 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 24847 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 5926224 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 141366200 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 96437860 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 18852 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 41848 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 237864760 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 984362 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 2894410 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.124539 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.334666 # Request fanout histogram +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 110573.897906 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 105477.403228 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 3727432 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1879617 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27909 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 314429 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 310730 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3699 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 50409 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1677085 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 19680 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 19680 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 702838 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1316929 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 184068 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 307004 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 88013 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42167 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 112831 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 90 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 288284 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 284624 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1102234 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 554693 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3303 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3324225 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2514874 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11068 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 23857 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 5874024 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 141088696 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 96080240 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 18676 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 39960 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 237227572 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 980964 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 18662568 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 2867653 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.124927 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.334515 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 2538244 87.69% 87.69% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 351865 12.16% 99.85% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 4301 0.15% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 2513105 87.64% 87.64% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 350849 12.23% 99.87% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 3699 0.13% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 2894410 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 3716866999 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 2867653 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 3694518500 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 114649584 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 114067456 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1665625000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1662373000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1205216982 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1187117482 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer2.occupancy 6399000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 14392485 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 13871990 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1335,66 +1328,68 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 3352 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 3352 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 656 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2696 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 3352 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 3352 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 3352 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2582 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 11816.227730 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11080.373538 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 4768.875507 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-4095 5 0.19% 0.19% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::4096-8191 626 24.24% 24.44% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1198 46.40% 70.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::12288-16383 544 21.07% 91.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-20479 85 3.29% 95.20% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::20480-24575 56 2.17% 97.37% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-28671 31 1.20% 98.57% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::28672-32767 20 0.77% 99.34% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-36863 3 0.12% 99.46% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::36864-40959 8 0.31% 99.77% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 3295 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 3295 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 621 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2674 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 3295 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 3295 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 3295 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2525 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 11832.673267 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11118.852324 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 4722.323425 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-4095 1 0.04% 0.04% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::4096-8191 600 23.76% 23.80% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1197 47.41% 71.21% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::12288-16383 525 20.79% 92.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-20479 78 3.09% 95.09% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::20480-24575 55 2.18% 97.27% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-28671 34 1.35% 98.61% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::28672-32767 21 0.83% 99.45% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-36863 5 0.20% 99.64% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::36864-40959 3 0.12% 99.76% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::40960-45055 3 0.12% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-53247 3 0.12% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2582 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::45056-49151 1 0.04% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-53247 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::57344-61439 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2525 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walksPending::samples -2078115828 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 -2078115828 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total -2078115828 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1934 74.90% 74.90% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 648 25.10% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2582 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3352 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 1912 75.72% 75.72% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 613 24.28% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2525 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3295 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3352 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2582 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3295 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2525 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2582 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 5934 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2525 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 5820 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3941258 # DTB read hits -system.cpu1.dtb.read_misses 2845 # DTB read misses -system.cpu1.dtb.write_hits 3419362 # DTB write hits -system.cpu1.dtb.write_misses 507 # DTB write misses +system.cpu1.dtb.read_hits 6294037 # DTB read hits +system.cpu1.dtb.read_misses 2780 # DTB read misses +system.cpu1.dtb.write_hits 4620410 # DTB write hits +system.cpu1.dtb.write_misses 515 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1980 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1950 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 318 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 345 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3944103 # DTB read accesses -system.cpu1.dtb.write_accesses 3419869 # DTB write accesses +system.cpu1.dtb.read_accesses 6296817 # DTB read accesses +system.cpu1.dtb.write_accesses 4620925 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 7360620 # DTB hits -system.cpu1.dtb.misses 3352 # DTB misses -system.cpu1.dtb.accesses 7363972 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 10914447 # DTB hits +system.cpu1.dtb.misses 3295 # DTB misses +system.cpu1.dtb.accesses 10917742 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1424,7 +1419,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states system.cpu1.itb.walker.walks 1746 # Table walker walks requested system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate @@ -1433,20 +1428,20 @@ system.cpu1.itb.walker.walkWaitTime::samples 1746 system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12335.140018 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11518.936586 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5605.729039 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 174 15.72% 15.72% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 657 59.35% 75.07% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 169 15.27% 90.33% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 52 4.70% 95.03% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 1 0.09% 95.12% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 20 1.81% 96.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 16 1.45% 98.37% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 3 0.27% 98.64% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 10 0.90% 99.55% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.18% 99.73% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-53247 2 0.18% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12387.082204 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11535.325922 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5801.640137 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 173 15.63% 15.63% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 662 59.80% 75.43% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 167 15.09% 90.51% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 48 4.34% 94.85% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.18% 95.03% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 22 1.99% 97.02% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 9 0.81% 97.83% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 2 0.18% 98.01% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 17 1.54% 99.55% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.27% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.09% 99.91% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::57344-61439 1 0.09% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples -2078939828 # Table walker pending requests distribution @@ -1462,7 +1457,7 @@ system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 16556610 # ITB inst hits +system.cpu1.itb.inst_hits 27022574 # ITB inst hits system.cpu1.itb.inst_misses 1746 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1479,287 +1474,287 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 16558356 # ITB inst accesses -system.cpu1.itb.hits 16556610 # DTB hits +system.cpu1.itb.inst_accesses 27024320 # ITB inst accesses +system.cpu1.itb.hits 27022574 # DTB hits system.cpu1.itb.misses 1746 # DTB misses -system.cpu1.itb.accesses 16558356 # DTB accesses -system.cpu1.numPwrStateTransitions 5511 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2756 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 1031898407.856313 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 25737040202.524998 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 1964 71.26% 71.26% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 786 28.52% 99.78% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.85% # Distribution of time spent in the clock gated state +system.cpu1.itb.accesses 27024320 # DTB accesses +system.cpu1.numPwrStateTransitions 5545 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2773 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 1021169708.427335 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 25639051633.019150 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 1969 71.01% 71.01% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 798 28.78% 99.78% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.86% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::8e+11-8.5e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 929980631528 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2756 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 25876957948 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 2843912012052 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 5738649789 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 929980591792 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 2773 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 38093227531 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 2831703601469 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 5738665817 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2756 # number of quiesce instructions executed -system.cpu1.committedInsts 16201169 # Number of instructions committed -system.cpu1.committedOps 19741428 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 17804295 # Number of integer alu accesses +system.cpu1.kern.inst.quiesce 2773 # number of quiesce instructions executed +system.cpu1.committedInsts 26084833 # Number of instructions committed +system.cpu1.committedOps 31969643 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 28891717 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 1857 # Number of float alu accesses -system.cpu1.num_func_calls 1029080 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1813608 # number of instructions that are conditional controls -system.cpu1.num_int_insts 17804295 # number of integer instructions +system.cpu1.num_func_calls 3291352 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2940246 # number of instructions that are conditional controls +system.cpu1.num_int_insts 28891717 # number of integer instructions system.cpu1.num_fp_insts 1857 # number of float instructions -system.cpu1.num_int_register_reads 32308777 # number of times the integer registers were read -system.cpu1.num_int_register_writes 12487661 # number of times the integer registers were written +system.cpu1.num_int_register_reads 54405188 # number of times the integer registers were read +system.cpu1.num_int_register_writes 20702345 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1341 # number of times the floating registers were read system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 72166445 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 6418557 # number of times the CC registers were written -system.cpu1.num_mem_refs 7593995 # number of memory refs -system.cpu1.num_load_insts 4052758 # Number of load instructions -system.cpu1.num_store_insts 3541237 # Number of store instructions -system.cpu1.num_idle_cycles 5686904242.264484 # Number of idle cycles -system.cpu1.num_busy_cycles 51745546.735515 # Number of busy cycles -system.cpu1.not_idle_fraction 0.009017 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.990983 # Percentage of idle cycles -system.cpu1.Branches 2921126 # Number of branches fetched +system.cpu1.num_cc_register_reads 117659728 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 9804030 # number of times the CC registers were written +system.cpu1.num_mem_refs 11150743 # number of memory refs +system.cpu1.num_load_insts 6405542 # Number of load instructions +system.cpu1.num_store_insts 4745201 # Number of store instructions +system.cpu1.num_idle_cycles 5662491677.952167 # Number of idle cycles +system.cpu1.num_busy_cycles 76174139.047833 # Number of busy cycles +system.cpu1.not_idle_fraction 0.013274 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.986726 # Percentage of idle cycles +system.cpu1.Branches 6334050 # Number of branches fetched system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 12468405 62.06% 62.06% # Class of executed instruction -system.cpu1.op_class::IntMult 26465 0.13% 62.19% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 3319 0.02% 62.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 62.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.20% # Class of executed instruction -system.cpu1.op_class::MemRead 4052758 20.17% 82.38% # Class of executed instruction -system.cpu1.op_class::MemWrite 3541237 17.62% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 21707276 65.97% 65.97% # Class of executed instruction +system.cpu1.op_class::IntMult 42869 0.13% 66.10% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 3317 0.01% 66.11% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 66.11% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 66.11% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 66.11% # Class of executed instruction +system.cpu1.op_class::MemRead 6405542 19.47% 85.58% # Class of executed instruction +system.cpu1.op_class::MemWrite 4745201 14.42% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 20092250 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 186389 # number of replacements -system.cpu1.dcache.tags.tagsinuse 469.298921 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 7093769 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 186755 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 37.984359 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 127433218000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.298921 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.916599 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.916599 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 366 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 285 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 81 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.714844 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 14939866 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 14939866 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 3629400 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3629400 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3230955 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3230955 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48929 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 48929 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78822 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 78822 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70747 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 70747 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 6860355 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 6860355 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 6909284 # number of overall hits -system.cpu1.dcache.overall_hits::total 6909284 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 133654 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 133654 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 91683 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 91683 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30306 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30306 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17079 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 17079 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23334 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23334 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 225337 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 225337 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 255643 # number of overall misses -system.cpu1.dcache.overall_misses::total 255643 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1974580500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1974580500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2414638500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2414638500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 320455500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 320455500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 569715000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 569715000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3416500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3416500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4389219000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4389219000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4389219000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4389219000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3763054 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3763054 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 3322638 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 3322638 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79235 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 79235 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 95901 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 95901 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94081 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 94081 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 7085692 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 7085692 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 7164927 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 7164927 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035517 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.035517 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027593 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.027593 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.382482 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.382482 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.178090 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.178090 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248020 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248020 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031802 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.031802 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035680 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.035680 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14773.822706 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14773.822706 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26336.818167 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 26336.818167 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18763.130160 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18763.130160 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24415.659553 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24415.659553 # average StoreCondReq miss latency +system.cpu1.op_class::total 32904271 # Class of executed instruction +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 184968 # number of replacements +system.cpu1.dcache.tags.tagsinuse 463.748200 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 10628914 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 185317 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 57.355310 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 117456056000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 463.748200 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.905758 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.905758 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 279 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 70 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.681641 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 22007267 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 22007267 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 5972632 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 5972632 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4424329 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4424329 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48799 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 48799 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78725 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 78725 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70549 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 70549 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 10396961 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 10396961 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 10445760 # number of overall hits +system.cpu1.dcache.overall_hits::total 10445760 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 132851 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 132851 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 90720 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 90720 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30243 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30243 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17042 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 17042 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23391 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23391 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 223571 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 223571 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 253814 # number of overall misses +system.cpu1.dcache.overall_misses::total 253814 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1953731000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1953731000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2328640500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2328640500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 317134000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 317134000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 572176500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 572176500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2893000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2893000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4282371500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4282371500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4282371500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4282371500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 6105483 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 6105483 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4515049 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4515049 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79042 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 79042 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 95767 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 95767 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 93940 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 93940 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 10620532 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 10620532 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 10699574 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 10699574 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.021759 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.021759 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.020093 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.020093 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.382619 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.382619 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.177953 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.177953 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248999 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248999 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.021051 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.021051 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.023722 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.023722 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14706.182114 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14706.182114 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25668.435847 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 25668.435847 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18608.966084 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18608.966084 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24461.395408 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24461.395408 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19478.465587 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 19478.465587 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17169.329886 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 17169.329886 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19154.414034 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 19154.414034 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16872.085464 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16872.085464 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 186389 # number of writebacks -system.cpu1.dcache.writebacks::total 186389 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 283 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 283 # number of ReadReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12013 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12013 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 283 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 283 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 283 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 283 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133371 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 133371 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91683 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 91683 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29541 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 29541 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5066 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5066 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23334 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23334 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 225054 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 225054 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 254595 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 254595 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3095 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3095 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2450 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2450 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5545 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5545 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1833975000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1833975000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2322955500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2322955500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 497374500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 497374500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87920500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87920500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 546440000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 546440000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3357500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3357500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4156930500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4156930500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4654305000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4654305000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 443417000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 443417000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 443417000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 443417000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035442 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035442 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027593 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027593 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.372828 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.372828 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.052825 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.052825 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248020 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248020 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031762 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.031762 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035534 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035534 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13750.927863 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13750.927863 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25336.818167 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 25336.818167 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16836.752310 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16836.752310 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17355.013818 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17355.013818 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23418.188052 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23418.188052 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 184968 # number of writebacks +system.cpu1.dcache.writebacks::total 184968 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 261 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 261 # number of ReadReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11955 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11955 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 261 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 261 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 261 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 261 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 132590 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 132590 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 90720 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 90720 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29532 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 29532 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5087 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5087 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23391 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23391 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 223310 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 223310 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 252842 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 252842 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 13772 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 13772 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11224 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11224 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 24996 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 24996 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1815324500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1815324500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2237920500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2237920500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 484982000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 484982000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 85050000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 85050000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 548834500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 548834500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2844000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2844000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4053245000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4053245000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4538227000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4538227000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2392670000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2392670000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2392670000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2392670000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.021717 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.021717 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.020093 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.020093 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.373624 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.373624 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053119 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053119 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248999 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248999 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.021026 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.021026 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.023631 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.023631 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13691.262539 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13691.262539 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24668.435847 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24668.435847 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16422.253826 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16422.253826 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16719.087871 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16719.087871 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23463.490231 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23463.490231 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18470.813671 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18470.813671 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18281.211336 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18281.211336 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143268.820679 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143268.820679 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 79966.997295 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 79966.997295 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 505464 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.478732 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 16050629 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 505976 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 31.722115 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 85269924000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.478732 # Average occupied blocks per requestor +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18150.754556 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18150.754556 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17948.865299 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17948.865299 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173734.388615 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173734.388615 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95722.115538 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95722.115538 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 504074 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.478768 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 26517983 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 504586 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 52.553941 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 85269939000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.478768 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973591 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.973591 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -1767,368 +1762,370 @@ system.cpu1.icache.tags.age_task_id_blocks_1024::2 388 system.cpu1.icache.tags.age_task_id_blocks_1024::3 121 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 33619186 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 33619186 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 16050629 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 16050629 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 16050629 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 16050629 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 16050629 # number of overall hits -system.cpu1.icache.overall_hits::total 16050629 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 505976 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 505976 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 505976 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 505976 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 505976 # number of overall misses -system.cpu1.icache.overall_misses::total 505976 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4528088500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4528088500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4528088500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4528088500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4528088500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4528088500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 16556605 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 16556605 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 16556605 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 16556605 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 16556605 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 16556605 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030560 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.030560 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030560 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.030560 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030560 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.030560 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8949.215971 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8949.215971 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8949.215971 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8949.215971 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8949.215971 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8949.215971 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 54549724 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 54549724 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 26517983 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 26517983 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 26517983 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 26517983 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 26517983 # number of overall hits +system.cpu1.icache.overall_hits::total 26517983 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 504586 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 504586 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 504586 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 504586 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 504586 # number of overall misses +system.cpu1.icache.overall_misses::total 504586 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4509196500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4509196500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4509196500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4509196500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4509196500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4509196500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 27022569 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 27022569 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 27022569 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 27022569 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 27022569 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 27022569 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.018673 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.018673 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.018673 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.018673 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.018673 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.018673 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8936.428082 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8936.428082 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8936.428082 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8936.428082 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8936.428082 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8936.428082 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 505464 # number of writebacks -system.cpu1.icache.writebacks::total 505464 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 505976 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 505976 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 505976 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 505976 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 505976 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 505976 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 504074 # number of writebacks +system.cpu1.icache.writebacks::total 504074 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 504586 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 504586 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 504586 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 504586 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 504586 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 504586 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4275100500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4275100500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4275100500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4275100500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4275100500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4275100500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4256903500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4256903500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4256903500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4256903500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4256903500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4256903500 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15776500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15776500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15776500 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 15776500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030560 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030560 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030560 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.030560 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030560 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.030560 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8449.215971 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8449.215971 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8449.215971 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8449.215971 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8449.215971 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8449.215971 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.018673 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.018673 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.018673 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.018673 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.018673 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.018673 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8436.428082 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8436.428082 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8436.428082 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8436.428082 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8436.428082 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8436.428082 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 89132.768362 # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 89132.768362 # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 89132.768362 # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 89132.768362 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 197600 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 197600 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 194200 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 194208 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 58944 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 44688 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 14938.485252 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1161636 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 59377 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 19.563737 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 58064 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 39025 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 14524.719643 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1158959 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 53669 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 21.594570 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 14464.281457 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.152749 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.089726 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 468.961320 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.882830 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000192 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000128 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.028623 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.911773 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1029 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13646 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 36 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 993 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 14059.725770 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 5.138677 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.073426 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 457.781770 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.858138 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000314 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000127 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.027941 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.886519 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1036 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 20 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13588 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 48 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 987 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 280 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1684 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11682 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.062805 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.832886 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 23775762 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 23775762 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3761 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2010 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 5771 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 113707 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 113707 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 567008 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 567008 # number of WritebackClean hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27229 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 27229 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 492726 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 492726 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99930 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 99930 # number of ReadSharedReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3761 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2010 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 492726 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 127159 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 625656 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3761 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2010 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 492726 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 127159 # number of overall hits -system.cpu1.l2cache.overall_hits::total 625656 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 318 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 272 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 590 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29672 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 29672 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23330 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 23330 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 4 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34782 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 34782 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13250 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 13250 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 68048 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 68048 # number of ReadSharedReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 318 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 272 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 13250 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 102830 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 116670 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 318 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 272 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 13250 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 102830 # number of overall misses -system.cpu1.l2cache.overall_misses::total 116670 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 6473000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5557000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 12030000 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 65067000 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 65067000 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 32437500 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 32437500 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3268500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3268500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1333613500 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1333613500 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 533576500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 533576500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1512816500 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1512816500 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 6473000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5557000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 533576500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 2846430000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 3392036500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 6473000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5557000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 533576500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 2846430000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 3392036500 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 4079 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2282 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 6361 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 113707 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 113707 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 567008 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 567008 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29672 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 29672 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23330 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23330 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 4 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62011 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 62011 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 505976 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 505976 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 167978 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 167978 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 4079 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2282 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 505976 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 229989 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 742326 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 4079 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2282 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 505976 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 229989 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 742326 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.077960 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.119194 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.092753 # miss rate for ReadReq accesses +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1629 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11648 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.063232 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001221 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.829346 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 23678541 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 23678541 # Number of data accesses +system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3677 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1997 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 5674 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 113054 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 113054 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 564912 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 564912 # number of WritebackClean hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27115 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 27115 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 491676 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 491676 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 100094 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 100094 # number of ReadSharedReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3677 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1997 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 491676 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 127209 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 624559 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3677 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1997 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 491676 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 127209 # number of overall hits +system.cpu1.l2cache.overall_hits::total 624559 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 321 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 267 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 588 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29273 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 29273 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23388 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 23388 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34332 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 34332 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 12910 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 12910 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 67115 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 67115 # number of ReadSharedReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 321 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 267 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 12910 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 101447 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 114945 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 321 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 267 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 12910 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 101447 # number of overall misses +system.cpu1.l2cache.overall_misses::total 114945 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 6521000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5470500 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 11991500 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 64762500 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 64762500 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 33901000 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 33901000 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2768998 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2768998 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1261050000 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 1261050000 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 523740500 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::total 523740500 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1479063500 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1479063500 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 6521000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5470500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 523740500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 2740113500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 3275845500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 6521000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5470500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 523740500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 2740113500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 3275845500 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3998 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2264 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 6262 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::writebacks 113054 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::total 113054 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::writebacks 564912 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::total 564912 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29273 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 29273 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23388 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 23388 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61447 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 61447 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 504586 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::total 504586 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 167209 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 167209 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3998 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2264 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 504586 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 228656 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 739504 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3998 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2264 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 504586 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 228656 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 739504 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.080290 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.117933 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.093900 # miss rate for ReadReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.560900 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.560900 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.026187 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.026187 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.405101 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.405101 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.077960 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.119194 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026187 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.447108 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.157168 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.077960 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.119194 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026187 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.447108 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.157168 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20355.345912 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20430.147059 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20389.830508 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2192.875438 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2192.875438 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1390.377197 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1390.377197 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 817125 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 817125 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 38342.059111 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 38342.059111 # average ReadExReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 40269.924528 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 40269.924528 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22231.608570 # average ReadSharedReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22231.608570 # average ReadSharedReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20355.345912 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20430.147059 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 40269.924528 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27680.929690 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 29073.767892 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20355.345912 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20430.147059 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 40269.924528 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27680.929690 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 29073.767892 # average overall miss latency +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.558725 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.558725 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.025585 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.025585 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.401384 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.401384 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.080290 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.117933 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.025585 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.443666 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.155435 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.080290 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.117933 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.025585 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.443666 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.155435 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20314.641745 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20488.764045 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20393.707483 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2212.362928 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2212.362928 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1449.504019 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1449.504019 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 922999.333333 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 922999.333333 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 36731.038099 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 36731.038099 # average ReadExReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 40568.590240 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 40568.590240 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22037.748640 # average ReadSharedReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22037.748640 # average ReadSharedReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20314.641745 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20488.764045 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 40568.590240 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27010.296017 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 28499.243116 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20314.641745 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20488.764045 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 40568.590240 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27010.296017 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 28499.243116 # average overall miss latency system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l2cache.unused_prefetches 790 # number of HardPF blocks evicted w/o reference -system.cpu1.l2cache.writebacks::writebacks 33019 # number of writebacks -system.cpu1.l2cache.writebacks::total 33019 # number of writebacks -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 57 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 57 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 57 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 57 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 57 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 57 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 318 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 272 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 590 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 24979 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 24979 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29672 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29672 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23330 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23330 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 4 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34725 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 34725 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 13250 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 13250 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 68048 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 68048 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 318 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 272 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 13250 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 102773 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 116613 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 318 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 272 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 13250 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 102773 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 24979 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 141592 # number of overall MSHR misses +system.cpu1.l2cache.unused_prefetches 741 # number of HardPF blocks evicted w/o reference +system.cpu1.l2cache.writebacks::writebacks 28109 # number of writebacks +system.cpu1.l2cache.writebacks::total 28109 # number of writebacks +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 75 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 75 # number of ReadExReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 75 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 75 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 75 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 321 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 267 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 588 # number of ReadReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 23341 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 23341 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29273 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29273 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23388 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23388 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34257 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 34257 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 12910 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 12910 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 67115 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 67115 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 321 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 267 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 12910 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 101372 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 114870 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 321 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 267 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 12910 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 101372 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 23341 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 138211 # number of overall MSHR misses system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3095 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3272 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2450 # number of WriteReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2450 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 13772 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 13949 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11224 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11224 # number of WriteReq MSHR uncacheable system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5545 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5722 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4565000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3925000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 8490000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 780424807 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 780424807 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 494079500 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 494079500 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 371536000 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 371536000 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2914500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2914500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1118604500 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1118604500 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 454076500 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 454076500 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1104528500 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1104528500 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4565000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3925000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 454076500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2223133000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 2685699500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4565000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3925000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 454076500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2223133000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 780424807 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 3466124307 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 24996 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 25173 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4595000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3868500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 8463500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 732704788 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 732704788 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 486199500 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 486199500 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 373432500 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 373432500 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2474998 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2474998 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1046225500 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1046225500 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 446280500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 446280500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1076373500 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1076373500 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4595000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3868500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 446280500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2122599000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 2577343000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4595000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3868500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 446280500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2122599000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 732704788 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 3310047788 # number of overall MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14449000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 418310000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 432759000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2282145500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2296594500 # number of ReadReq MSHR uncacheable cycles system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 14449000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 418310000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 432759000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.077960 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.119194 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.092753 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2282145500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2296594500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.080290 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.117933 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.093900 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses @@ -2137,122 +2134,123 @@ system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.559981 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.559981 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.026187 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.026187 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.405101 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.405101 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.077960 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.119194 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026187 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.446861 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.157091 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.077960 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.119194 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026187 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.446861 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.557505 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.557505 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.025585 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.025585 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.401384 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.401384 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.080290 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.117933 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.025585 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.443338 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.155334 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.080290 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.117933 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.025585 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.443338 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.190741 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14355.345912 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14430.147059 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14389.830508 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31243.236599 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31243.236599 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16651.371664 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16651.371664 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15925.246464 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15925.246464 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 728625 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 728625 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32213.232541 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32213.232541 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 34269.924528 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34269.924528 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16231.608570 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16231.608570 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14355.345912 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14430.147059 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34269.924528 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21631.488815 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23030.875631 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14355.345912 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14430.147059 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34269.924528 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21631.488815 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31243.236599 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24479.662036 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.186897 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14314.641745 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14488.764045 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14393.707483 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31391.319481 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31391.319481 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16609.144946 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16609.144946 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15966.841970 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15966.841970 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 824999.333333 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 824999.333333 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30540.488075 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30540.488075 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 34568.590240 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34568.590240 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16037.748640 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16037.748640 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14314.641745 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14488.764045 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34568.590240 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 20938.710887 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22437.041873 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14314.641745 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14488.764045 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34568.590240 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 20938.710887 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31391.319481 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23949.235502 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81632.768362 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135156.704362 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132261.308068 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165709.083648 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164642.232418 # average ReadReq mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81632.768362 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75439.134355 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75630.723523 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 1487204 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 751274 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11138 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 179165 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 176020 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 3145 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 12644 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 724299 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2450 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2450 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 147816 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 578146 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 101473 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 30088 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 71412 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41204 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 85825 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 69105 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 66696 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 505976 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 245752 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 247 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1517770 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 838774 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5606 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 10127 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2372277 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 64732868 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29385740 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 9128 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 16316 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 94144052 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 388756 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1114505 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.179300 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.390891 # Request fanout histogram +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 91300.428068 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 91232.451436 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 1481374 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 748184 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11076 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 177406 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 174791 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2615 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 23242 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 733434 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 11224 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 11224 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 142093 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 575988 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 98729 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 27772 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 72921 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41250 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 85602 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 90 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 69150 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 66171 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 504586 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 246891 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 241 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1513600 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 873749 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5588 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9967 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2402904 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 64554948 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29333690 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 9056 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 15992 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 93913686 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 383897 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 4632988 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 1125089 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.175565 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.386511 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 917819 82.35% 82.35% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 193541 17.37% 99.72% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 3145 0.28% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 930178 82.68% 82.68% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 192296 17.09% 99.77% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 2615 0.23% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1114505 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 1441037000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1125089 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1449361998 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 80111937 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 81273182 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 759141000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 757056000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 375865500 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 388749000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 6050495 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 5969499 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 31015 # Transaction distribution system.iobus.trans_dist::ReadResp 31015 # Transaction distribution -system.iobus.trans_dist::WriteReq 59422 # Transaction distribution -system.iobus.trans_dist::WriteResp 59422 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 59421 # Transaction distribution +system.iobus.trans_dist::WriteResp 59421 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -2271,11 +2269,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107914 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180874 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 180872 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71544 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) @@ -2294,70 +2292,70 @@ system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484068 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 48726000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2484066 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 48725500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 106000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 321000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 323500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 32000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 16500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 95000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 94500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 601500 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 599000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 23500 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 23000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 48000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6164000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6153000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 32044500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 32045500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187734328 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187736829 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84717000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36445 # number of replacements -system.iocache.tags.tagsinuse 14.386648 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.386581 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 289174340000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.386648 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.899166 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.899166 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 289188615000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.386581 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.899161 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.899161 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328311 # Number of tag accesses system.iocache.tags.data_accesses 328311 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses system.iocache.ReadReq_misses::total 255 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -2366,14 +2364,14 @@ system.iocache.demand_misses::realview.ide 36479 # system.iocache.demand_misses::total 36479 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36479 # number of overall misses system.iocache.overall_misses::total 36479 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 36421877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 36421877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4307524451 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4307524451 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4343946328 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4343946328 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4343946328 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4343946328 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 35445377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 35445377 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4303608452 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4303608452 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4339053829 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4339053829 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4339053829 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4339053829 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -2390,19 +2388,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 142830.890196 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 142830.890196 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118913.550436 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118913.550436 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 119080.740371 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 119080.740371 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 119080.740371 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 119080.740371 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 22 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 139001.478431 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 139001.478431 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118805.445340 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118805.445340 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 118946.622139 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118946.622139 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 118946.622139 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118946.622139 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 15 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 3.142857 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 3.750000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks @@ -2414,14 +2412,14 @@ system.iocache.demand_mshr_misses::realview.ide 36479 system.iocache.demand_mshr_misses::total 36479 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36479 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36479 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 23671877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 23671877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2493982137 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2493982137 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2517654014 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2517654014 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2517654014 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2517654014 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 22695377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 22695377 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2490051224 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2490051224 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2512746601 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2512746601 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2512746601 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2512746601 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2430,565 +2428,566 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 92830.890196 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 92830.890196 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68848.888499 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68848.888499 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 69016.530442 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 69016.530442 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 69016.530442 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 69016.530442 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 126308 # number of replacements -system.l2c.tags.tagsinuse 63017.044477 # Cycle average of tags in use -system.l2c.tags.total_refs 424315 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 190178 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.231147 # Average number of references to valid blocks. +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 89001.478431 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 89001.478431 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68740.371687 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68740.371687 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68882.003372 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68882.003372 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68882.003372 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68882.003372 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 119266 # number of replacements +system.l2c.tags.tagsinuse 63150.928665 # Cycle average of tags in use +system.l2c.tags.total_refs 419498 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 183131 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.290699 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 13637.426679 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.018602 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.043991 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7319.345128 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2841.087210 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35552.012227 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1437.607406 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 447.669169 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1777.834065 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.208091 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 13441.811145 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.006326 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.055729 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7581.242495 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2905.326286 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35913.296254 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1514.615308 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 303.672578 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1486.902543 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.205106 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000061 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.111684 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.043352 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.542481 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.021936 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.006831 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.027128 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.961564 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 30519 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu0.inst 0.115681 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.044332 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.547993 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.023111 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.004634 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.022688 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.963607 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 30886 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 33346 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 165 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 4688 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 25665 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 32974 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 76 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 4718 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 26088 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 347 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2267 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 30712 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.465683 # Percentage of cache occupancy per task id +system.l2c.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 298 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2232 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 30425 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.471283 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.508820 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5890164 # Number of tag accesses -system.l2c.tags.data_accesses 5890164 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 260994 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 260994 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 31980 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 2487 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 34467 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 1985 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 965 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 2950 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 3870 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1490 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5360 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 97 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 76 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 27673 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 45621 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 45892 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 31 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 37 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 10962 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 9208 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5411 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 145008 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 97 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 76 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 27673 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 49491 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 45892 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 31 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 37 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 10962 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 10698 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 5411 # number of demand (read+write) hits -system.l2c.demand_hits::total 150368 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 97 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 76 # number of overall hits -system.l2c.overall_hits::cpu0.inst 27673 # number of overall hits -system.l2c.overall_hits::cpu0.data 49491 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 45892 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 31 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 37 # number of overall hits -system.l2c.overall_hits::cpu1.inst 10962 # number of overall hits -system.l2c.overall_hits::cpu1.data 10698 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 5411 # number of overall hits -system.l2c.overall_hits::total 150368 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 8680 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 2870 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11550 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 542 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1323 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1865 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 11368 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 8031 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 19399 # number of ReadExReq misses +system.l2c.tags.occ_task_id_percent::1024 0.503143 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5778594 # Number of tag accesses +system.l2c.tags.data_accesses 5778594 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 255647 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 255647 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 32152 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 2169 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 34321 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 2017 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 1011 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 3028 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 4187 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1790 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 5977 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 77 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 85 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 27265 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 45372 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46765 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 37 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 32 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 10614 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 8420 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 4646 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 143313 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 77 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 85 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 27265 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 49559 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 46765 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 37 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 32 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 10614 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 10210 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 4646 # number of demand (read+write) hits +system.l2c.demand_hits::total 149290 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 77 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 85 # number of overall hits +system.l2c.overall_hits::cpu0.inst 27265 # number of overall hits +system.l2c.overall_hits::cpu0.data 49559 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 46765 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 37 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 32 # number of overall hits +system.l2c.overall_hits::cpu1.inst 10614 # number of overall hits +system.l2c.overall_hits::cpu1.data 10210 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 4646 # number of overall hits +system.l2c.overall_hits::total 149290 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 8829 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 2766 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 11595 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 562 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1350 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1912 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 10910 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 7277 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 18187 # number of ReadExReq misses system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 7 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 17607 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 8862 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 133884 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 2288 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 856 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6026 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 169532 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 17445 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 8731 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 130401 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 2296 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 718 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 5545 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 165145 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 17607 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 20230 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 133884 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2288 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 8887 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 6026 # number of demand (read+write) misses -system.l2c.demand_misses::total 188931 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 17445 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 19641 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 130401 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2296 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 7995 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 5545 # number of demand (read+write) misses +system.l2c.demand_misses::total 183332 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 17607 # number of overall misses -system.l2c.overall_misses::cpu0.data 20230 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 133884 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2288 # number of overall misses -system.l2c.overall_misses::cpu1.data 8887 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 6026 # number of overall misses -system.l2c.overall_misses::total 188931 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 11274000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 4127500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 15401500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1640500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1015500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 2656000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 1087660500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 661855000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1749515500 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 703500 # number of ReadSharedReq miss cycles +system.l2c.overall_misses::cpu0.inst 17445 # number of overall misses +system.l2c.overall_misses::cpu0.data 19641 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 130401 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2296 # number of overall misses +system.l2c.overall_misses::cpu1.data 7995 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 5545 # number of overall misses +system.l2c.overall_misses::total 183332 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 14927000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 2436000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 17363000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1977500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1602000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 3579500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 1046073500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 591480500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1637554000 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 605500 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 174000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1440677500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 776891500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 12971801632 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.inst 189843000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 77251000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 662486557 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 16119828689 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 703500 # number of demand (read+write) miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1424566500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 766776000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 12582000643 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.inst 188965500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 64274000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 624236555 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 15651598698 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 605500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 174000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1440677500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 1864552000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 12971801632 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 189843000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 739106000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 662486557 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 17869344189 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 703500 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1424566500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 1812849500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 12582000643 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 188965500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 655754500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 624236555 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 17289152698 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 605500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 174000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1440677500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 1864552000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 12971801632 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 189843000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 739106000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 662486557 # number of overall miss cycles -system.l2c.overall_miss_latency::total 17869344189 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 260994 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 260994 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 40660 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 5357 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 46017 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 2527 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 2288 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 4815 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 15238 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 9521 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 24759 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 104 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 78 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 45280 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 54483 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 179776 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 31 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 37 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 13250 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 10064 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11437 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 314540 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 104 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 78 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 45280 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 69721 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 179776 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 31 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 37 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 13250 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 19585 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11437 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 339299 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 104 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 78 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 45280 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 69721 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 179776 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 31 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 37 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 13250 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 19585 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11437 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 339299 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.213478 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.535748 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.250994 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.214484 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.578234 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.387331 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.746030 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.843504 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.783513 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.067308 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.025641 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.388847 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.162656 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.744727 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.172679 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.085056 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.526886 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.538984 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.067308 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.025641 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.388847 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.290156 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.744727 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.172679 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.453766 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.526886 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.556827 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.067308 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.025641 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.388847 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.290156 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.744727 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.172679 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.453766 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.526886 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.556827 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1298.847926 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1438.153310 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1333.463203 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3026.752768 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 767.573696 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 1424.128686 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 95677.383885 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82412.526460 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 90185.860096 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 100500 # average ReadSharedReq miss latency +system.l2c.overall_miss_latency::cpu0.inst 1424566500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 1812849500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 12582000643 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 188965500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 655754500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 624236555 # number of overall miss cycles +system.l2c.overall_miss_latency::total 17289152698 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 255647 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 255647 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 40981 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 4935 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 45916 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 2579 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 2361 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 4940 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 15097 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 9067 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 24164 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 84 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 87 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 44710 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 54103 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 177166 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 37 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 32 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 12910 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 9138 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 10191 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 308458 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 84 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 87 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 44710 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 69200 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 177166 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 37 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 32 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 12910 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 18205 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 10191 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 332622 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 84 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 87 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 44710 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 69200 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 177166 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 37 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 32 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 12910 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 18205 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 10191 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 332622 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.215441 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.560486 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.252526 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.217914 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.571792 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.387045 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.722660 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.802581 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.752649 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.083333 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.022989 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.390181 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.161377 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.736039 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.177847 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.078573 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.544108 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.535389 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.083333 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.022989 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.390181 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.283829 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.736039 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.177847 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.439165 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.544108 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.551172 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.083333 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.022989 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.390181 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.283829 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.736039 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.177847 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.439165 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.544108 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.551172 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1690.678446 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 880.694143 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1497.455800 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3518.683274 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1186.666667 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1872.123431 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 95882.080660 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81280.816270 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 90039.808655 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 86500 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 87000 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 81824.132447 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87665.481833 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 96888.363300 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 82973.339161 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90246.495327 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 109938.028045 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 95084.283138 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 100500 # average overall miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 81660.447120 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87822.242584 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 96486.995061 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 82302.047038 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 89518.105850 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 112576.475203 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 94774.886905 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 86500 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 87000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 81824.132447 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 92167.671775 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 96888.363300 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 82973.339161 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 83167.098008 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 109938.028045 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 94581.324341 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 100500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 81660.447120 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 92299.246474 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 96486.995061 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 82302.047038 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 82020.575360 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 112576.475203 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 94305.155117 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 86500 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 87000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 81824.132447 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 92167.671775 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 96888.363300 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 82973.339161 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 83167.098008 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 109938.028045 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 94581.324341 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 81660.447120 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 92299.246474 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 96486.995061 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 82302.047038 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 82020.575360 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 112576.475203 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 94305.155117 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 98955 # number of writebacks -system.l2c.writebacks::total 98955 # number of writebacks -system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 4 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 10 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 14 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 14 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 3251 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 3251 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 8680 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 2870 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 11550 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 542 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1323 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1865 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 11368 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 8031 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 19399 # number of ReadExReq MSHR misses +system.l2c.writebacks::writebacks 94207 # number of writebacks +system.l2c.writebacks::total 94207 # number of writebacks +system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 8 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 8 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 16 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 16 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 2843 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 2843 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 8829 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 2766 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 11595 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 562 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1350 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1912 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 10910 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 7277 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 18187 # number of ReadExReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 7 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17603 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 8862 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 133884 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2278 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 856 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6026 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 169518 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17437 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 8731 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 130401 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2288 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 718 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 5545 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 165129 # number of ReadSharedReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 7 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 17603 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 20230 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 133884 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 2278 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 8887 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6026 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 188917 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 17437 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 19641 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 130401 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2288 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 7995 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 5545 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 183316 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 7 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 17603 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 20230 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 133884 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2278 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 8887 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6026 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 188917 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 17437 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 19641 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 130401 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2288 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 7995 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5545 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 183316 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31792 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 21106 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3092 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 44083 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28463 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2450 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 30913 # number of WriteReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 13769 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 44074 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 19680 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11224 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 30904 # number of WriteReq MSHR uncacheable system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60255 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 40786 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5542 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 74996 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 208012000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 65421000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 273433000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 13993000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 32976000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 46969000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 973980500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 581545000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1555525500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 633500 # number of ReadSharedReq MSHR miss cycles +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 24993 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 74978 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 211257500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 63038000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 274295500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 14501000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 33544500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 48045500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 936973500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 518710500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1455684000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 535500 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 154000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1264511501 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 688271500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11632958638 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 166489000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 68690501 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 602225559 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 14423934199 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 633500 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1249680003 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 679466000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11277986652 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 165660000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 57094000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 568784560 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 13999360715 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 535500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 154000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1264511501 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 1662252000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11632958638 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 166489000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 650235501 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 602225559 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 15979459699 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 633500 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1249680003 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 1616439500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11277986652 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 165660000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 575804500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 568784560 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 15455044715 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 535500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 154000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1264511501 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 1662252000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11632958638 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 166489000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 650235501 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 602225559 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 15979459699 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1249680003 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 1616439500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11277986652 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 165660000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 575804500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 568784560 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 15455044715 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 581355000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5801887500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4129945000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11263000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 362609000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 6757114500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2034246500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 6756809500 # number of ReadReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 581355000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5801887500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4129945000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 11263000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 362609000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 6757114500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2034246500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 6756809500 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.213478 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.535748 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.250994 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.214484 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.578234 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.387331 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.746030 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.843504 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.783513 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.067308 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.025641 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.388759 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.162656 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744727 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.171925 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.085056 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.526886 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.538939 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.067308 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.025641 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.388759 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.290156 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744727 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.171925 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.453766 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.526886 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.556786 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.067308 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.025641 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.388759 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.290156 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744727 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.171925 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.453766 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.526886 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.556786 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23964.516129 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22794.773519 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23673.852814 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 25817.343173 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24925.170068 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25184.450402 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 85677.383885 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72412.526460 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 80185.860096 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 90500 # average ReadSharedReq mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.215441 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.560486 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.252526 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.217914 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.571792 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.387045 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.722660 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.802581 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.752649 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.083333 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.022989 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.390002 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.161377 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.736039 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.177227 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.078573 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.544108 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.535337 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.083333 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.022989 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.390002 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.283829 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.736039 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.177227 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.439165 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.544108 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.551124 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.083333 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.022989 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.390002 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.283829 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.736039 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.177227 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.439165 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.544108 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.551124 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23927.681504 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22790.310918 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23656.360500 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 25802.491103 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24847.777778 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25128.399582 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 85882.080660 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71280.816270 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 80039.808655 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 76500 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 71834.999773 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77665.481833 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.340937 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73085.601405 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80245.912383 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99937.862429 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 85087.921041 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 90500 # average overall mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 71668.291736 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77822.242584 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86486.964456 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72403.846154 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 79518.105850 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 102576.115419 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 84778.329155 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76500 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71834.999773 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 82167.671775 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.340937 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73085.601405 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73167.041859 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99937.862429 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 84584.551411 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 90500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71668.291736 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 82299.246474 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86486.964456 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72403.846154 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72020.575360 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 102576.115419 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 84308.214858 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76500 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71834.999773 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82167.671775 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.340937 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73085.601405 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73167.041859 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99937.862429 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 84584.551411 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71668.291736 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82299.246474 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86486.964456 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72403.846154 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72020.575360 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 102576.115419 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 84308.214858 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64437.486145 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182495.203196 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 195676.347958 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63632.768362 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117273.285899 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 153281.639181 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 147741.048733 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 153306.019422 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64437.486145 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96288.897187 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 101258.887854 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63632.768362 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65429.267412 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 90099.665315 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 512702 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 293222 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81392.649942 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 90117.227720 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 502889 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 289010 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 588 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 44083 # Transaction distribution -system.membus.trans_dist::ReadResp 213856 # Transaction distribution -system.membus.trans_dist::WriteReq 30913 # Transaction distribution -system.membus.trans_dist::WriteResp 30913 # Transaction distribution -system.membus.trans_dist::WritebackDirty 135145 # Transaction distribution -system.membus.trans_dist::CleanEvict 15700 # Transaction distribution -system.membus.trans_dist::UpgradeReq 75854 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40085 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 44074 # Transaction distribution +system.membus.trans_dist::ReadResp 209458 # Transaction distribution +system.membus.trans_dist::WriteReq 30904 # Transaction distribution +system.membus.trans_dist::WriteResp 30904 # Transaction distribution +system.membus.trans_dist::WritebackDirty 130397 # Transaction distribution +system.membus.trans_dist::CleanEvict 14501 # Transaction distribution +system.membus.trans_dist::UpgradeReq 77693 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40094 # Transaction distribution system.membus.trans_dist::UpgradeResp 16 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 39863 # Transaction distribution -system.membus.trans_dist::ReadExResp 19313 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 169773 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 38557 # Transaction distribution +system.membus.trans_dist::ReadExResp 18075 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 165384 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107914 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13740 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 656506 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 778196 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13706 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 641086 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 762740 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72939 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72939 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 851135 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 835679 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18452748 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18643092 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27412 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17788748 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17979022 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20960212 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 123593 # Total snoops (count) -system.membus.snoop_fanout::samples 436796 # Request fanout histogram -system.membus.snoop_fanout::mean 0.011900 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.108438 # Request fanout histogram +system.membus.pkt_size::total 20296142 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 125256 # Total snoops (count) +system.membus.snoopTraffic 37632 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 432932 # Request fanout histogram +system.membus.snoop_fanout::mean 0.012007 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.108915 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 431598 98.81% 98.81% # Request fanout histogram -system.membus.snoop_fanout::1 5198 1.19% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 427734 98.80% 98.80% # Request fanout histogram +system.membus.snoop_fanout::1 5198 1.20% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 436796 # Request fanout histogram -system.membus.reqLayer0.occupancy 88259500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 432932 # Request fanout histogram +system.membus.reqLayer0.occupancy 88248500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11350000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11302499 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 980369236 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 949242954 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1108695304 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1079420372 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1346131 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1341881 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -3020,76 +3019,77 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 980232 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 530887 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 150046 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 20267 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 19482 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 44086 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 477451 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30913 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30913 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 359949 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 109182 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 110235 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 43035 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 153270 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 100 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 50915 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 50915 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 433367 # Transaction distribution +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 971913 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 526665 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 151758 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 18562 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 17727 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 835 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 44077 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 473751 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30904 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30904 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 349854 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 105962 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 111902 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 43122 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 155024 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 90 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 90 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 50816 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50816 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 429676 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 4592 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1224504 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 296079 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1520583 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 33710224 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4970948 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 38681172 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 378680 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 843567 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.376795 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.486500 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1183270 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 322305 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1505575 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 33366812 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4544754 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 37911566 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 376245 # Total snoops (count) +system.toL2Bus.snoopTraffic 15498572 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 834461 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.383881 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.488383 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 526500 62.41% 62.41% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 316282 37.49% 99.91% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 785 0.09% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 514962 61.71% 61.71% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 318664 38.19% 99.90% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 835 0.10% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 843567 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 877207087 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 834461 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 867249813 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 360619 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 640962681 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 626009420 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 223907403 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 234312270 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |