diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt | 4460 |
1 files changed, 2209 insertions, 2251 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 391769400..64a01b6e7 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,160 +1,156 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.868319 # Number of seconds simulated -sim_ticks 2868318696500 # Number of ticks simulated -final_tick 2868318696500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.868581 # Number of seconds simulated +sim_ticks 2868581440500 # Number of ticks simulated +final_tick 2868581440500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 534652 # Simulator instruction rate (inst/s) -host_op_rate 646675 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11631340017 # Simulator tick rate (ticks/s) -host_mem_usage 586476 # Number of bytes of host memory used -host_seconds 246.60 # Real time elapsed on the host -sim_insts 131846562 # Number of instructions simulated -sim_ops 159471778 # Number of ops (including micro ops) simulated +host_inst_rate 717360 # Simulator instruction rate (inst/s) +host_op_rate 867708 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15647358559 # Simulator tick rate (ticks/s) +host_mem_usage 639748 # Number of bytes of host memory used +host_seconds 183.33 # Real time elapsed on the host +sim_insts 131511324 # Number of instructions simulated +sim_ops 159074269 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1173796 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1283584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8628800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 156308 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 605472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 378048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1161572 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1227520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8321088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 141140 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 467936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 345792 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12227608 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1173796 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 156308 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1330104 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8654400 # Number of bytes written to this memory +system.physmem.bytes_read::total 11666584 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1161572 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 141140 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1302712 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8208384 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8672144 # Number of bytes written to this memory +system.physmem.bytes_written::total 8226128 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26794 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 20582 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 134825 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2597 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9484 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 5907 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26603 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 19706 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 130017 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2360 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 7335 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 5403 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 200214 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 135225 # Number of write requests responded to by this memory +system.physmem.num_reads::total 191448 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 128256 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 139661 # Number of write requests responded to by this memory +system.physmem.num_writes::total 132692 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 409228 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 447504 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3008313 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 54495 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 211090 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 131801 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 404929 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 427919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2900768 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 49202 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 163125 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 120545 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4262988 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 409228 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 54495 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 463723 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3017238 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4067022 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 404929 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 49202 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 454131 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2861478 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6172 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3023424 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3017238 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2867664 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2861478 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 409228 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 453676 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3008313 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 54495 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 211103 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 131801 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 404929 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 434091 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2900768 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 49202 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 163138 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 120545 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7286412 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 200214 # Number of read requests accepted -system.physmem.writeReqs 175885 # Number of write requests accepted -system.physmem.readBursts 200214 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 175885 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12804096 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue -system.physmem.bytesWritten 10892544 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12227608 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10990480 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5671 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 13850 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12188 # Per bank write bursts -system.physmem.perBankRdBursts::1 12046 # Per bank write bursts -system.physmem.perBankRdBursts::2 12591 # Per bank write bursts -system.physmem.perBankRdBursts::3 12330 # Per bank write bursts -system.physmem.perBankRdBursts::4 20750 # Per bank write bursts -system.physmem.perBankRdBursts::5 12582 # Per bank write bursts -system.physmem.perBankRdBursts::6 12043 # Per bank write bursts -system.physmem.perBankRdBursts::7 12246 # Per bank write bursts -system.physmem.perBankRdBursts::8 12442 # Per bank write bursts -system.physmem.perBankRdBursts::9 12402 # Per bank write bursts -system.physmem.perBankRdBursts::10 11722 # Per bank write bursts -system.physmem.perBankRdBursts::11 11146 # Per bank write bursts -system.physmem.perBankRdBursts::12 11467 # Per bank write bursts -system.physmem.perBankRdBursts::13 11916 # Per bank write bursts -system.physmem.perBankRdBursts::14 10852 # Per bank write bursts -system.physmem.perBankRdBursts::15 11341 # Per bank write bursts -system.physmem.perBankWrBursts::0 10835 # Per bank write bursts -system.physmem.perBankWrBursts::1 11264 # Per bank write bursts -system.physmem.perBankWrBursts::2 11493 # Per bank write bursts -system.physmem.perBankWrBursts::3 10899 # Per bank write bursts -system.physmem.perBankWrBursts::4 10487 # Per bank write bursts -system.physmem.perBankWrBursts::5 11152 # Per bank write bursts -system.physmem.perBankWrBursts::6 11024 # Per bank write bursts -system.physmem.perBankWrBursts::7 10595 # Per bank write bursts -system.physmem.perBankWrBursts::8 10782 # Per bank write bursts -system.physmem.perBankWrBursts::9 10958 # Per bank write bursts -system.physmem.perBankWrBursts::10 10716 # Per bank write bursts -system.physmem.perBankWrBursts::11 10408 # Per bank write bursts -system.physmem.perBankWrBursts::12 10444 # Per bank write bursts -system.physmem.perBankWrBursts::13 9906 # Per bank write bursts -system.physmem.perBankWrBursts::14 9416 # Per bank write bursts -system.physmem.perBankWrBursts::15 9817 # Per bank write bursts +system.physmem.bw_total::total 6934686 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 191448 # Number of read requests accepted +system.physmem.writeReqs 168916 # Number of write requests accepted +system.physmem.readBursts 191448 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 168916 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12244160 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8512 # Total number of bytes read from write queue +system.physmem.bytesWritten 9286016 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11666584 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10544464 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 133 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 23799 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 13043 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11402 # Per bank write bursts +system.physmem.perBankRdBursts::1 11523 # Per bank write bursts +system.physmem.perBankRdBursts::2 11617 # Per bank write bursts +system.physmem.perBankRdBursts::3 11771 # Per bank write bursts +system.physmem.perBankRdBursts::4 20348 # Per bank write bursts +system.physmem.perBankRdBursts::5 12097 # Per bank write bursts +system.physmem.perBankRdBursts::6 11123 # Per bank write bursts +system.physmem.perBankRdBursts::7 11241 # Per bank write bursts +system.physmem.perBankRdBursts::8 11419 # Per bank write bursts +system.physmem.perBankRdBursts::9 11532 # Per bank write bursts +system.physmem.perBankRdBursts::10 11480 # Per bank write bursts +system.physmem.perBankRdBursts::11 10715 # Per bank write bursts +system.physmem.perBankRdBursts::12 11252 # Per bank write bursts +system.physmem.perBankRdBursts::13 11225 # Per bank write bursts +system.physmem.perBankRdBursts::14 11052 # Per bank write bursts +system.physmem.perBankRdBursts::15 11518 # Per bank write bursts +system.physmem.perBankWrBursts::0 9249 # Per bank write bursts +system.physmem.perBankWrBursts::1 9496 # Per bank write bursts +system.physmem.perBankWrBursts::2 9535 # Per bank write bursts +system.physmem.perBankWrBursts::3 9435 # Per bank write bursts +system.physmem.perBankWrBursts::4 8870 # Per bank write bursts +system.physmem.perBankWrBursts::5 9467 # Per bank write bursts +system.physmem.perBankWrBursts::6 9116 # Per bank write bursts +system.physmem.perBankWrBursts::7 8737 # Per bank write bursts +system.physmem.perBankWrBursts::8 8796 # Per bank write bursts +system.physmem.perBankWrBursts::9 9230 # Per bank write bursts +system.physmem.perBankWrBursts::10 9164 # Per bank write bursts +system.physmem.perBankWrBursts::11 8822 # Per bank write bursts +system.physmem.perBankWrBursts::12 9029 # Per bank write bursts +system.physmem.perBankWrBursts::13 8642 # Per bank write bursts +system.physmem.perBankWrBursts::14 8756 # Per bank write bursts +system.physmem.perBankWrBursts::15 8750 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 2868318254500 # Total gap between requests +system.physmem.numWrRetry 83 # Number of times write queue was full causing retry +system.physmem.totGap 2868581033500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9742 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 190444 # Read request sizes (log2) +system.physmem.readPktSize::6 181678 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4436 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 171449 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 138850 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 16077 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 10399 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9072 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5697 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4782 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4036 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3549 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 129 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 52 # What read queue length does an incoming req see +system.physmem.writePktSize::6 164480 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 134188 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 15248 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 9686 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8351 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6807 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5320 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3748 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3243 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 74 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 47 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -184,178 +180,162 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 8259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10826 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 11796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 12530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 11837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 11533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 10810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 10665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8094 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 90415 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 262.086778 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 144.561031 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 323.181928 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 46335 51.25% 51.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17813 19.70% 70.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6067 6.71% 77.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3600 3.98% 81.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2534 2.80% 84.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1568 1.73% 86.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1031 1.14% 87.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 985 1.09% 88.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10482 11.59% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 90415 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7120 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.098736 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 516.724228 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7117 99.96% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 2 0.03% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7120 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7120 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.903933 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.122109 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.073987 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5764 80.96% 80.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 237 3.33% 84.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 43 0.60% 84.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 234 3.29% 88.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 121 1.70% 89.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 62 0.87% 90.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 31 0.44% 91.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 36 0.51% 91.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 117 1.64% 93.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 18 0.25% 93.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 25 0.35% 93.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 16 0.22% 94.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 40 0.56% 94.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 10 0.14% 94.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 17 0.24% 95.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 28 0.39% 95.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 58 0.81% 96.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 14 0.20% 96.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 7 0.10% 96.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 6 0.08% 96.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 88 1.24% 97.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.06% 97.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 12 0.17% 98.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.01% 98.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 15 0.21% 98.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 6 0.08% 98.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 14 0.20% 98.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 9 0.13% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 35 0.49% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 6 0.08% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.01% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 4 0.06% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 8 0.11% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.03% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.04% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.01% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 8 0.11% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.03% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.01% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.01% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 4 0.06% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.01% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 3 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 3 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7120 # Writes before turning the bus around for reads -system.physmem.totQLat 4855930250 # Total ticks spent queuing -system.physmem.totMemAccLat 8607130250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1000320000 # Total ticks spent in databus transfers -system.physmem.avgQLat 24271.88 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 2068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5539 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5714 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2401 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2924 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1558 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1629 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 200 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 81717 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 263.471640 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 146.531290 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 321.110863 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 41089 50.28% 50.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16342 20.00% 70.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5746 7.03% 77.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3516 4.30% 81.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2447 2.99% 84.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1416 1.73% 86.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 997 1.22% 87.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 891 1.09% 88.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9273 11.35% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 81717 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5972 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.034494 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 599.214233 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5970 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5972 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5972 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 24.295713 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.853114 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 39.858214 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 5595 93.69% 93.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 97 1.62% 95.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 24 0.40% 95.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 14 0.23% 95.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 35 0.59% 96.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 43 0.72% 97.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 25 0.42% 97.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 12 0.20% 97.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 18 0.30% 98.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 5 0.08% 98.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 30 0.50% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 15 0.25% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 7 0.12% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 4 0.07% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 3 0.05% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 1 0.02% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 3 0.05% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 3 0.05% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 7 0.12% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 2 0.03% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 6 0.10% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 7 0.12% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 1 0.02% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 2 0.03% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 1 0.02% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 1 0.02% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 3 0.05% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 1 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 3 0.05% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5972 # Writes before turning the bus around for reads +system.physmem.totQLat 4538980935 # Total ticks spent queuing +system.physmem.totMemAccLat 8126137185 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 956575000 # Total ticks spent in databus transfers +system.physmem.avgQLat 23725.17 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 43021.88 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.46 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.80 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.26 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.83 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 42475.17 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.27 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.24 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.07 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.68 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.69 # Average write queue length when enqueuing -system.physmem.readRowHits 167229 # Number of row buffer hits during reads -system.physmem.writeRowHits 112615 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.59 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.16 # Row buffer hit rate for writes -system.physmem.avgGap 7626497.96 # Average gap between requests -system.physmem.pageHitRate 75.58 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 354707640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 193540875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 832845000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 568613520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 187344349920 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 84727272375 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1646666587500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1920687916830 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.622475 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2739235632500 # Time in different power states -system.physmem_0.memoryStateTime::REF 95779320000 # Time in different power states +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.09 # Average write queue length when enqueuing +system.physmem.readRowHits 160412 # Number of row buffer hits during reads +system.physmem.writeRowHits 94279 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.85 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 64.97 # Row buffer hit rate for writes +system.physmem.avgGap 7960231.97 # Average gap between requests +system.physmem.pageHitRate 75.70 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 319183200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 174157500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 788743800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 478904400 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 187361640960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83526196590 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1647879002250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1920527828700 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.504870 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2741264066617 # Time in different power states +system.physmem_0.memoryStateTime::REF 95788160000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 33303656000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31529102383 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 328829760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 179421000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 727646400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 534256560 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 187344349920 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 83962556955 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1647337390500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1920414451095 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.527135 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2740355751000 # Time in different power states -system.physmem_1.memoryStateTime::REF 95779320000 # Time in different power states +system.physmem_1.actEnergy 298597320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 162925125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 703505400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 461304720 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 187361640960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 82377359595 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1648886754000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1920252087120 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.408745 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2742945725805 # Time in different power states +system.physmem_1.memoryStateTime::REF 95788160000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 32179536500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 29845454195 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory @@ -411,57 +391,58 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 7749 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 7749 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1459 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6290 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 7749 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 7749 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 7749 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6355 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 8363.375452 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 7097.000757 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 5454.838397 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 6203 97.61% 97.61% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 142 2.23% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 7634 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 7634 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1372 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6262 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 7634 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 7634 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 7634 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6240 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 9567.588141 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 8440.173252 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 5686.595019 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 6084 97.50% 97.50% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 143 2.29% 99.79% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 8 0.13% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 1 0.02% 99.94% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::81920-98303 3 0.05% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6355 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 987959000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 987959000 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 987959000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 4935 77.66% 77.66% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1420 22.34% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6355 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7749 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6240 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 1121059000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 1121059000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 1121059000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 4907 78.64% 78.64% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1333 21.36% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6240 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7634 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7749 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6355 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7634 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6240 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6355 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 14104 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6240 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 13874 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 19044092 # DTB read hits -system.cpu0.dtb.read_misses 6608 # DTB read misses -system.cpu0.dtb.write_hits 15688894 # DTB write hits -system.cpu0.dtb.write_misses 1141 # DTB write misses +system.cpu0.dtb.read_hits 25111402 # DTB read hits +system.cpu0.dtb.read_misses 6533 # DTB read misses +system.cpu0.dtb.write_hits 18719047 # DTB write hits +system.cpu0.dtb.write_misses 1101 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3442 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3405 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1734 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 1785 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 19050700 # DTB read accesses -system.cpu0.dtb.write_accesses 15690035 # DTB write accesses +system.cpu0.dtb.read_accesses 25117935 # DTB read accesses +system.cpu0.dtb.write_accesses 18720148 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 34732986 # DTB hits -system.cpu0.dtb.misses 7749 # DTB misses -system.cpu0.dtb.accesses 34740735 # DTB accesses +system.cpu0.dtb.hits 43830449 # DTB hits +system.cpu0.dtb.misses 7634 # DTB misses +system.cpu0.dtb.accesses 43838083 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -499,20 +480,20 @@ system.cpu0.itb.walker.walkWaitTime::samples 3348 system.cpu0.itb.walker.walkWaitTime::0 3348 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::total 3348 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkCompletionTime::samples 2332 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 8781.732419 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 7396.194245 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5559.104899 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 1469 62.99% 62.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 817 35.03% 98.03% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 4 0.17% 98.20% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 39 1.67% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 9914.451115 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 8640.132285 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5844.480359 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 848 36.36% 36.36% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1427 61.19% 97.56% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 3 0.13% 97.68% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 51 2.19% 99.87% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::106496-114687 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::114688-122879 1 0.04% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::total 2332 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 987617000 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 987617000 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 987617000 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::samples 1120687000 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 1120687000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 1120687000 # Table walker pending requests distribution system.cpu0.itb.walker.walkPageSizes::4K 2034 87.22% 87.22% # Table walker page sizes translated system.cpu0.itb.walker.walkPageSizes::1M 298 12.78% 100.00% # Table walker page sizes translated system.cpu0.itb.walker.walkPageSizes::total 2332 # Table walker page sizes translated @@ -523,7 +504,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2332 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2332 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin::total 5680 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 91510827 # ITB inst hits +system.cpu0.itb.inst_hits 118783416 # ITB inst hits system.cpu0.itb.inst_misses 3348 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -540,172 +521,172 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 91514175 # ITB inst accesses -system.cpu0.itb.hits 91510827 # DTB hits +system.cpu0.itb.inst_accesses 118786764 # ITB inst accesses +system.cpu0.itb.hits 118783416 # DTB hits system.cpu0.itb.misses 3348 # DTB misses -system.cpu0.itb.accesses 91514175 # DTB accesses -system.cpu0.numCycles 5736637393 # number of cpu cycles simulated +system.cpu0.itb.accesses 118786764 # DTB accesses +system.cpu0.numCycles 5737162881 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 89363678 # Number of instructions committed -system.cpu0.committedOps 107297883 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 94350928 # Number of integer alu accesses +system.cpu0.committedInsts 115118664 # Number of instructions committed +system.cpu0.committedOps 139117689 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 123147620 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 9820 # Number of float alu accesses -system.cpu0.num_func_calls 6606472 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 12627044 # number of instructions that are conditional controls -system.cpu0.num_int_insts 94350928 # number of integer instructions +system.cpu0.num_func_calls 12673072 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 15652345 # number of instructions that are conditional controls +system.cpu0.num_int_insts 123147620 # number of integer instructions system.cpu0.num_fp_insts 9820 # number of float instructions -system.cpu0.num_int_register_reads 169124164 # number of times the integer registers were read -system.cpu0.num_int_register_writes 64348180 # number of times the integer registers were written +system.cpu0.num_int_register_reads 226729132 # number of times the integer registers were read +system.cpu0.num_int_register_writes 85574900 # number of times the integer registers were written system.cpu0.num_fp_register_reads 7560 # number of times the floating registers were read system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 385798415 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 43074064 # number of times the CC registers were written -system.cpu0.num_mem_refs 35866705 # number of memory refs -system.cpu0.num_load_insts 19295047 # Number of load instructions -system.cpu0.num_store_insts 16571658 # Number of store instructions -system.cpu0.num_idle_cycles 5512519658.266078 # Number of idle cycles -system.cpu0.num_busy_cycles 224117734.733922 # Number of busy cycles -system.cpu0.not_idle_fraction 0.039068 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.960932 # Percentage of idle cycles -system.cpu0.Branches 19970568 # Number of branches fetched +system.cpu0.num_cc_register_reads 504016583 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 52146919 # number of times the CC registers were written +system.cpu0.num_mem_refs 44965604 # number of memory refs +system.cpu0.num_load_insts 25362826 # Number of load instructions +system.cpu0.num_store_insts 19602778 # Number of store instructions +system.cpu0.num_idle_cycles 5466015382.984095 # Number of idle cycles +system.cpu0.num_busy_cycles 271147498.015905 # Number of busy cycles +system.cpu0.not_idle_fraction 0.047262 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.952738 # Percentage of idle cycles +system.cpu0.Branches 29061799 # Number of branches fetched system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 73557669 67.15% 67.15% # Class of executed instruction -system.cpu0.op_class::IntMult 108302 0.10% 67.25% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 8177 0.01% 67.26% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction -system.cpu0.op_class::MemRead 19295047 17.61% 84.87% # Class of executed instruction -system.cpu0.op_class::MemWrite 16571658 15.13% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 97796607 68.45% 68.45% # Class of executed instruction +system.cpu0.op_class::IntMult 109233 0.08% 68.52% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 8187 0.01% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::MemRead 25362826 17.75% 86.28% # Class of executed instruction +system.cpu0.op_class::MemWrite 19602778 13.72% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 109543126 # Class of executed instruction +system.cpu0.op_class::total 142881904 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1879 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 690539 # number of replacements -system.cpu0.dcache.tags.tagsinuse 487.185772 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 33864824 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 691051 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 49.004812 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1015908000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 487.185772 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.951535 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.951535 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 1874 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 688886 # number of replacements +system.cpu0.dcache.tags.tagsinuse 494.817079 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 42962889 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 689398 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 62.319428 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1149671500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.817079 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966440 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.966440 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 126 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 116 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 70103571 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 70103571 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 17785791 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 17785791 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 14958877 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 14958877 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 318525 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 318525 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 364927 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 364927 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361705 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 361705 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 32744668 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 32744668 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 33063193 # number of overall hits -system.cpu0.dcache.overall_hits::total 33063193 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 394905 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 394905 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 324481 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 324481 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127732 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 127732 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21710 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21710 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20007 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20007 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 719386 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 719386 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 847118 # number of overall misses -system.cpu0.dcache.overall_misses::total 847118 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4990872752 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4990872752 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4944330313 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 4944330313 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 327573000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 327573000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 444426745 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 444426745 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1572500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1572500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 9935203065 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 9935203065 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 9935203065 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 9935203065 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 18180696 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 18180696 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 15283358 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 15283358 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446257 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 446257 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386637 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 386637 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381712 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381712 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 33464054 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 33464054 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 33910311 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 33910311 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.021721 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.021721 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.021231 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.021231 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.286230 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.286230 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056151 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056151 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052414 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052414 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.021497 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.021497 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.024981 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.024981 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12638.160449 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12638.160449 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15237.657407 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 15237.657407 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15088.576693 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15088.576693 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22213.562503 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22213.562503 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 88293922 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 88293922 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 23854264 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23854264 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 17989541 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 17989541 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 318725 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 318725 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 364533 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 364533 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361797 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 361797 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 41843805 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 41843805 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 42162530 # number of overall hits +system.cpu0.dcache.overall_hits::total 42162530 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 393288 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 393288 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 323540 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 323540 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127427 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 127427 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21927 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21927 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19722 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 19722 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 716828 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 716828 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 844255 # number of overall misses +system.cpu0.dcache.overall_misses::total 844255 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5012719236 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5012719236 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5098069375 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 5098069375 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 332035250 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 332035250 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 435652050 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 435652050 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1835500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1835500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 10110788611 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 10110788611 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 10110788611 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 10110788611 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 24247552 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 24247552 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 18313081 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 18313081 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446152 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 446152 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386460 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 386460 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381519 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381519 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 42560633 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 42560633 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 43006785 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 43006785 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016220 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.016220 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017667 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.017667 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.285613 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.285613 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056738 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056738 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051693 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051693 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016843 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.016843 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019631 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.019631 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12745.670440 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 12745.670440 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15757.153289 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 15757.153289 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15142.757787 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15142.757787 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22089.648616 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22089.648616 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13810.670579 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 13810.670579 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11728.239826 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 11728.239826 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14104.901889 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14104.901889 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11975.989021 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 11975.989021 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -714,82 +695,82 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 504116 # number of writebacks -system.cpu0.dcache.writebacks::total 504116 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25128 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 25128 # number of ReadReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15248 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15248 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 25128 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 25128 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 25128 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 25128 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 369777 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 369777 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324481 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 324481 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100470 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 100470 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6462 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6462 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20007 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20007 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 694258 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 694258 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 794728 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 794728 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3859056498 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3859056498 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4283066685 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4283066685 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1502769500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1502769500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 90797250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 90797250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 403751255 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 403751255 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1480500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1480500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8142123183 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 8142123183 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9644892683 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 9644892683 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5991645999 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5991645999 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4628507500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4628507500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10620153499 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10620153499 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.020339 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.020339 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.021231 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021231 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225139 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225139 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016713 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016713 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052414 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052414 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.020746 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.020746 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.023436 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.023436 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10436.172336 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10436.172336 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 13199.745702 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13199.745702 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14957.395242 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14957.395242 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14050.951718 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14050.951718 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20180.499575 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20180.499575 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 504121 # number of writebacks +system.cpu0.dcache.writebacks::total 504121 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25265 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 25265 # number of ReadReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15169 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15169 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 25265 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 25265 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 25265 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 25265 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 368023 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 368023 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 323540 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 323540 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100320 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 100320 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6758 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6758 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19722 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 19722 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 691563 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 691563 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 791883 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 791883 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4066612315 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4066612315 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4601719625 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4601719625 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1548565203 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1548565203 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 97840500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 97840500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 405700950 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 405700950 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1754500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1754500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8668331940 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 8668331940 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10216897143 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10216897143 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6181726750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6181726750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4820424000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4820424000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11002150750 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11002150750 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015178 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015178 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017667 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017667 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224856 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224856 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017487 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017487 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051693 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051693 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016249 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016249 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018413 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018413 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11049.886325 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11049.886325 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14223.031542 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14223.031542 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15436.256011 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15436.256011 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14477.730098 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14477.730098 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20570.984180 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20570.984180 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11727.806065 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11727.806065 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12136.092705 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12136.092705 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12534.406757 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12534.406757 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12902.028637 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12902.028637 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -797,58 +778,58 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1099798 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.479276 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 90410508 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1100310 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 82.168214 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 13323414750 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.479276 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998983 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998983 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1101309 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.453846 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 117681586 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1101821 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 106.806447 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 13496302250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.453846 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998933 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998933 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 215 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 184121973 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 184121973 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 90410508 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 90410508 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 90410508 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 90410508 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 90410508 # number of overall hits -system.cpu0.icache.overall_hits::total 90410508 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1100319 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1100319 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1100319 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1100319 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1100319 # number of overall misses -system.cpu0.icache.overall_misses::total 1100319 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10739818993 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10739818993 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10739818993 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10739818993 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10739818993 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10739818993 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 91510827 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 91510827 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 91510827 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 91510827 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 91510827 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 91510827 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012024 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.012024 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012024 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.012024 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012024 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.012024 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9760.641226 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9760.641226 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9760.641226 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9760.641226 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9760.641226 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9760.641226 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 238668662 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 238668662 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 117681586 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 117681586 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 117681586 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 117681586 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 117681586 # number of overall hits +system.cpu0.icache.overall_hits::total 117681586 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1101830 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1101830 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1101830 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1101830 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1101830 # number of overall misses +system.cpu0.icache.overall_misses::total 1101830 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10869872254 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10869872254 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10869872254 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10869872254 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10869872254 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10869872254 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 118783416 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 118783416 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 118783416 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 118783416 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 118783416 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 118783416 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009276 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.009276 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009276 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.009276 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009276 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.009276 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9865.289794 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9865.289794 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9865.289794 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9865.289794 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9865.289794 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9865.289794 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -857,223 +838,224 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1100319 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1100319 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1100319 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1100319 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1100319 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1100319 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9082830507 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9082830507 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9082830507 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9082830507 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9082830507 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9082830507 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 719096500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 719096500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 719096500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 719096500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.012024 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012024 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.012024 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.012024 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.012024 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.012024 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8254.724773 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8254.724773 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8254.724773 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 8254.724773 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8254.724773 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 8254.724773 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1101830 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1101830 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1101830 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1101830 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1101830 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1101830 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9761619746 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9761619746 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9761619746 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9761619746 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9761619746 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9761619746 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 802157500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 802157500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 802157500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 802157500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009276 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009276 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009276 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009276 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009276 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009276 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8859.460848 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8859.460848 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8859.460848 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 8859.460848 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8859.460848 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 8859.460848 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1853283 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1853292 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1839936 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1839962 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 22 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 238164 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 268426 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16093.899190 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 1968322 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 284663 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.914569 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 237006 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 267761 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16103.938258 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 1970214 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 284001 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.937349 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 7921.036071 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.357121 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.109776 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4473.771805 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1953.197848 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1743.426570 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.483462 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000144 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000007 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.273057 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.119214 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.106410 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.982294 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1127 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15106 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 288 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 7915.761025 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.539297 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.155291 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4574.741605 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1897.934094 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1714.806946 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.483140 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000033 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000009 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.279220 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.115841 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.104664 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.982906 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1117 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15115 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 261 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 418 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 412 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 425 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3213 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7809 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3908 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.068787 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000244 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.921997 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 39654154 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 39654154 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7774 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3610 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1053168 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 381762 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 1446314 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 504114 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 504114 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28406 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 28406 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1700 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 1700 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 227802 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 227802 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7774 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3610 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1053168 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 609564 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1674116 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7774 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3610 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1053168 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 609564 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1674116 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 215 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 122 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 47151 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 94947 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 142435 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26586 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 26586 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18299 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 18299 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 8 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 41687 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 41687 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 215 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 122 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 47151 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 136634 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 184122 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 215 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 122 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 47151 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 136634 # number of overall misses -system.cpu0.l2cache.overall_misses::total 184122 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 4899750 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2713500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2213649997 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2684439955 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 4905703202 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 458226521 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 458226521 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 356750783 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 356750783 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1434495 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1434495 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 1789174823 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 1789174823 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 4899750 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2713500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2213649997 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 4473614778 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 6694878025 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 4899750 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2713500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2213649997 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 4473614778 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 6694878025 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7989 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3732 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1100319 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 476709 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 1588749 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 504114 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 504114 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 54992 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 54992 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19999 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 19999 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 8 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 8 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269489 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 269489 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7989 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3732 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1100319 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 746198 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1858238 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7989 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3732 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1100319 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 746198 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1858238 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.026912 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.032690 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.042852 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.199172 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.089652 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.483452 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.483452 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.914996 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.914996 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 8038 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3680 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.068176 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.922546 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 39636813 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 39636813 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 8046 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3668 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1054676 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 380878 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 1447268 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 504119 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 504119 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28198 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 28198 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1754 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 1754 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 225223 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 225223 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 8046 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3668 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1054676 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 606101 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1672491 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 8046 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3668 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1054676 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 606101 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1672491 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 223 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 133 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 47154 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 94223 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 141733 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26109 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 26109 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 17961 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 17961 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 7 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44010 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 44010 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 223 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 133 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 47154 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 138233 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 185743 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 223 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 133 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 47154 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 138233 # number of overall misses +system.cpu0.l2cache.overall_misses::total 185743 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 5218750 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3033000 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2351090746 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2761351258 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 5120693754 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 483042430 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 483042430 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 364663752 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 364663752 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1698997 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1698997 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 1948619833 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 1948619833 # number of ReadExReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 5218750 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3033000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2351090746 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 4709971091 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 7069313587 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 5218750 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3033000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2351090746 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 4709971091 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 7069313587 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 8269 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3801 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1101830 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 475101 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 1589001 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 504119 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 504119 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 54307 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 54307 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19715 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 19715 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 7 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269233 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 269233 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 8269 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3801 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1101830 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 744334 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 1858234 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 8269 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3801 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1101830 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 744334 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 1858234 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.026968 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.034991 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.042796 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.198322 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.089196 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.480767 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.480767 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.911032 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.911032 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.154689 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.154689 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.026912 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.032690 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.042852 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.183107 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.099084 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.026912 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.032690 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.042852 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.183107 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.099084 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 22789.534884 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22241.803279 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 46948.102840 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 28273.036062 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 34441.697630 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17235.632325 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17235.632325 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19495.643642 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19495.643642 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 179311.875000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 179311.875000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 42919.251157 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 42919.251157 # average ReadExReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 22789.534884 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22241.803279 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 46948.102840 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 32741.592708 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 36361.097669 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 22789.534884 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22241.803279 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 46948.102840 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 32741.592708 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 36361.097669 # average overall miss latency +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.163464 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.163464 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.026968 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.034991 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.042796 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.185714 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.099957 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.026968 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.034991 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.042796 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.185714 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.099957 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 23402.466368 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22804.511278 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 49859.836833 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29306.552094 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 36129.156611 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18500.993144 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18500.993144 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20303.087356 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20303.087356 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 242713.857143 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 242713.857143 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 44276.751488 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 44276.751488 # average ReadExReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 23402.466368 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22804.511278 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 49859.836833 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 34072.696758 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 38059.650092 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 23402.466368 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22804.511278 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 49859.836833 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 34072.696758 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 38059.650092 # average overall miss latency system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1082,128 +1064,128 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 196247 # number of writebacks -system.cpu0.l2cache.writebacks::total 196247 # number of writebacks +system.cpu0.l2cache.writebacks::writebacks 195381 # number of writebacks +system.cpu0.l2cache.writebacks::total 195381 # number of writebacks system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 32 # number of ReadReq MSHR hits system.cpu0.l2cache.ReadReq_mshr_hits::total 32 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1210 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 1210 # number of ReadExReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1242 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 1242 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1242 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 1242 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 215 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 122 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 47151 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 94915 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 142403 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 246323 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 246323 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 26586 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 26586 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 18299 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18299 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 8 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 8 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 40477 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 40477 # number of ReadExReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 215 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 122 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 47151 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 135392 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 182880 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 215 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 122 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 47151 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 135392 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 246323 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 429203 # number of overall MSHR misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3394250 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1859500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 1877090003 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2013208709 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 3895552462 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13906201830 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13906201830 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 448274629 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 448274629 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 246009723 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 246009723 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1112495 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1112495 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1381066645 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1381066645 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 3394250 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1859500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 1877090003 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3394275354 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 5276619107 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 3394250 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1859500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 1877090003 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3394275354 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13906201830 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 19182820937 # number of overall MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 647209500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5743013251 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6390222751 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4419325000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4419325000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 647209500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10162338251 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10809547751 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.026912 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.032690 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.042852 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.199105 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.089632 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1212 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 1212 # number of ReadExReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1244 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 1244 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1244 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 1244 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 223 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 133 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 47154 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 94191 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 141701 # number of ReadReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 243995 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 243995 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 26109 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 26109 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 17961 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 17961 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 7 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 42798 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 42798 # number of ReadExReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 223 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 133 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 47154 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 136989 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 184499 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 223 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 133 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 47154 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 136989 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 243995 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 428494 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3768750 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2168500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2038167254 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2142124308 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 4186228812 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13497828640 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13497828640 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 512289208 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 512289208 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 258190050 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 258190050 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1347997 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1347997 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1547245660 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1547245660 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 3768750 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2168500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2038167254 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3689369968 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 5733474472 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 3768750 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2168500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2038167254 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3689369968 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13497828640 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 19231303112 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 730253500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5927208500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6657462000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4606674000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4606674000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 730253500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10533882500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11264136000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.026968 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.034991 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.042796 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.198255 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.089176 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.483452 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.483452 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.914996 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.914996 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.480767 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.480767 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.911032 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.911032 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.150199 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.150199 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.026912 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.032690 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042852 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.181442 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.098416 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.026912 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.032690 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042852 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.181442 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.158963 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.158963 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.026968 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.034991 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042796 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.184042 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.099287 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.026968 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.034991 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042796 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.184042 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.230973 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 15787.209302 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15241.803279 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 39810.184365 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 21210.648570 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27355.831422 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56455.149661 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56455.149661 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16861.304032 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16861.304032 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13443.888901 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13443.888901 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 139061.875000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 139061.875000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 34119.787657 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 34119.787657 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 15787.209302 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15241.803279 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 39810.184365 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 25069.984593 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 28852.904128 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 15787.209302 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15241.803279 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39810.184365 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 25069.984593 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56455.149661 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44694.051386 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.230592 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16900.224215 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16304.511278 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 43223.634347 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22742.345957 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 29542.690680 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55320.103445 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55320.103445 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19621.173082 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19621.173082 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14375.037581 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14375.037581 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 192571 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 192571 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 36152.288892 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 36152.288892 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16900.224215 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16304.511278 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43223.634347 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 26931.870209 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31075.910829 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16900.224215 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16304.511278 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43223.634347 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 26931.870209 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55320.103445 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44881.149122 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1213,57 +1195,55 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 1737767 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1686227 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 27891 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 27891 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 504114 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 316054 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 89164 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42476 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 112407 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 43 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 81 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 298764 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 285064 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2218682 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2366147 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10130 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 22028 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 4616987 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 70456504 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 84324454 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14928 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 31956 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 154827842 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 648932 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 2984532 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.180419 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.384536 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 1733379 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1686259 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28500 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28500 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 504119 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 307885 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36279 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 88136 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42217 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 111625 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 60 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 107 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 297195 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 284749 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2221704 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2362865 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10199 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 22165 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 4616933 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 70553208 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 84179104 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 15204 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 33076 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 154780592 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 633519 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 2968459 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 3.176473 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.381222 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 2446067 81.96% 81.96% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 538465 18.04% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 2444606 82.35% 82.35% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 523853 17.65% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 2984532 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 1775358935 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 2968459 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 1775328997 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 115165999 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 114507000 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1664866493 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1667097754 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1209535062 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1206509407 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer2.occupancy 6398000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 14039749 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 13896250 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1294,59 +1274,62 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 3332 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 3332 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 642 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2690 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 3332 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 3332 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 3332 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2562 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 8324.355972 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 7260.502547 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 4990.324891 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 2067 80.68% 80.68% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 375 14.64% 95.32% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 62 2.42% 97.74% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 50 1.95% 99.69% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 4 0.16% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 3 0.12% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::81920-90111 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2562 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1455144968 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1455144968 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1455144968 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1928 75.25% 75.25% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 634 24.75% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2562 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3332 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 3283 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 3283 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 611 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2672 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 3283 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 3283 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 3283 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2513 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 9027.258257 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 8086.769918 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 4736.776885 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-4095 485 19.30% 19.30% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::4096-8191 533 21.21% 40.51% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1045 41.58% 82.09% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::12288-16383 324 12.89% 94.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-20479 44 1.75% 96.74% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::20480-24575 19 0.76% 97.49% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-28671 51 2.03% 99.52% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::28672-32767 8 0.32% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::36864-40959 3 0.12% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::45056-49151 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2513 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1651557968 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1651557968 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1651557968 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1910 76.00% 76.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 603 24.00% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2513 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3283 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3332 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2562 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3283 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2513 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2562 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 5894 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2513 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 5796 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 10115566 # DTB read hits -system.cpu1.dtb.read_misses 2828 # DTB read misses -system.cpu1.dtb.write_hits 6544640 # DTB write hits -system.cpu1.dtb.write_misses 504 # DTB write misses +system.cpu1.dtb.read_hits 3974119 # DTB read hits +system.cpu1.dtb.read_misses 2776 # DTB read misses +system.cpu1.dtb.write_hits 3444686 # DTB write hits +system.cpu1.dtb.write_misses 507 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2029 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 346 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 362 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 10118394 # DTB read accesses -system.cpu1.dtb.write_accesses 6545144 # DTB write accesses +system.cpu1.dtb.read_accesses 3976895 # DTB read accesses +system.cpu1.dtb.write_accesses 3445193 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 16660206 # DTB hits -system.cpu1.dtb.misses 3332 # DTB misses -system.cpu1.dtb.accesses 16663538 # DTB accesses +system.cpu1.dtb.hits 7418805 # DTB hits +system.cpu1.dtb.misses 3283 # DTB misses +system.cpu1.dtb.accesses 7422088 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1376,42 +1359,43 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 1746 # Table walker walks requested -system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1578 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 1746 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 8955.736224 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 7685.889357 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5645.921496 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-4095 191 17.25% 17.25% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 643 58.08% 75.34% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 217 19.60% 94.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 1 0.09% 95.03% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 3 0.27% 95.30% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 27 2.44% 97.74% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 19 1.72% 99.46% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 3 0.27% 99.73% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.27% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1454651968 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1454651968 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1454651968 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1107 # Table walker page sizes translated +system.cpu1.itb.walker.walks 1740 # Table walker walks requested +system.cpu1.itb.walker.walksShort 1740 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 164 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1576 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 1740 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 1740 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 1740 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1101 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 9655.767484 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 8490.755174 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5670.300287 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-4095 219 19.89% 19.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 163 14.80% 34.70% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 463 42.05% 76.75% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 204 18.53% 95.28% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 1 0.09% 95.37% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 25 2.27% 97.64% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 21 1.91% 99.55% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 1 0.09% 99.64% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.27% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.09% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1101 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1651010968 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1651010968 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1651010968 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 937 85.10% 85.10% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 164 14.90% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1101 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1746 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1746 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1740 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1740 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 44359905 # ITB inst hits -system.cpu1.itb.inst_misses 1746 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1101 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1101 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 2841 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 16749094 # ITB inst hits +system.cpu1.itb.inst_misses 1740 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1420,178 +1404,178 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1148 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1142 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 44361651 # ITB inst accesses -system.cpu1.itb.hits 44359905 # DTB hits -system.cpu1.itb.misses 1746 # DTB misses -system.cpu1.itb.accesses 44361651 # DTB accesses -system.cpu1.numCycles 5735725430 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 16750834 # ITB inst accesses +system.cpu1.itb.hits 16749094 # DTB hits +system.cpu1.itb.misses 1740 # DTB misses +system.cpu1.itb.accesses 16750834 # DTB accesses +system.cpu1.numCycles 5736248293 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 42482884 # Number of instructions committed -system.cpu1.committedOps 52173895 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 47161467 # Number of integer alu accesses +system.cpu1.committedInsts 16392660 # Number of instructions committed +system.cpu1.committedOps 19956580 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 17976734 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 1857 # Number of float alu accesses -system.cpu1.num_func_calls 7121857 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 4915281 # number of instructions that are conditional controls -system.cpu1.num_int_insts 47161467 # number of integer instructions +system.cpu1.num_func_calls 1033061 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1853914 # number of instructions that are conditional controls +system.cpu1.num_int_insts 17976734 # number of integer instructions system.cpu1.num_fp_insts 1857 # number of float instructions -system.cpu1.num_int_register_reads 90906541 # number of times the integer registers were read -system.cpu1.num_int_register_writes 34070734 # number of times the integer registers were written +system.cpu1.num_int_register_reads 32611379 # number of times the integer registers were read +system.cpu1.num_int_register_writes 12600410 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1341 # number of times the floating registers were read system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 192636366 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 15749934 # number of times the CC registers were written -system.cpu1.num_mem_refs 16924073 # number of memory refs -system.cpu1.num_load_insts 10229886 # Number of load instructions -system.cpu1.num_store_insts 6694187 # Number of store instructions -system.cpu1.num_idle_cycles 5637554126.704413 # Number of idle cycles -system.cpu1.num_busy_cycles 98171303.295587 # Number of busy cycles -system.cpu1.not_idle_fraction 0.017116 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.982884 # Percentage of idle cycles -system.cpu1.Branches 12116511 # Number of branches fetched +system.cpu1.num_cc_register_reads 72918750 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 6543930 # number of times the CC registers were written +system.cpu1.num_mem_refs 7653523 # number of memory refs +system.cpu1.num_load_insts 4085696 # Number of load instructions +system.cpu1.num_store_insts 3567827 # Number of store instructions +system.cpu1.num_idle_cycles 5685220667.433728 # Number of idle cycles +system.cpu1.num_busy_cycles 51027625.566272 # Number of busy cycles +system.cpu1.not_idle_fraction 0.008896 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.991104 # Percentage of idle cycles +system.cpu1.Branches 2968133 # Number of branches fetched system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 37117349 68.64% 68.64% # Class of executed instruction -system.cpu1.op_class::IntMult 29132 0.05% 68.70% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 3361 0.01% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::MemRead 10229886 18.92% 87.62% # Class of executed instruction -system.cpu1.op_class::MemWrite 6694187 12.38% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 12626391 62.17% 62.17% # Class of executed instruction +system.cpu1.op_class::IntMult 25909 0.13% 62.30% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 3321 0.02% 62.32% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 62.32% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.32% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.32% # Class of executed instruction +system.cpu1.op_class::MemRead 4085696 20.12% 82.43% # Class of executed instruction +system.cpu1.op_class::MemWrite 3567827 17.57% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 54073981 # Class of executed instruction +system.cpu1.op_class::total 20309210 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2789 # number of quiesce instructions executed -system.cpu1.dcache.tags.replacements 191058 # number of replacements -system.cpu1.dcache.tags.tagsinuse 472.360308 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 16390617 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 191421 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 85.626013 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 104654883500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.360308 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922579 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.922579 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 363 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 312 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 51 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.708984 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 33541448 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 33541448 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 9797337 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 9797337 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 6353174 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 6353174 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49731 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 49731 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79655 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 79655 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71640 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 71640 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 16150511 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 16150511 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 16200242 # number of overall hits -system.cpu1.dcache.overall_hits::total 16200242 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 137366 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 137366 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 93147 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 93147 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30426 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30426 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17223 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 17223 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23379 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23379 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 230513 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 230513 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 260939 # number of overall misses -system.cpu1.dcache.overall_misses::total 260939 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1997360003 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1997360003 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2352005341 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2352005341 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 320800000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 320800000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 539390293 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 539390293 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1691000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1691000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4349365344 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4349365344 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4349365344 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4349365344 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 9934703 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 9934703 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 6446321 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 6446321 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80157 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 80157 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96878 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 96878 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95019 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 95019 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 16381024 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 16381024 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 16461181 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 16461181 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.013827 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.013827 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.014450 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.014450 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.379580 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.379580 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.177780 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.177780 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.246046 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.246046 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.014072 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.014072 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.015852 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.015852 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14540.424872 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14540.424872 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25250.467981 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 25250.467981 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18626.255588 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18626.255588 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23071.572480 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23071.572480 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 2726 # number of quiesce instructions executed +system.cpu1.dcache.tags.replacements 187627 # number of replacements +system.cpu1.dcache.tags.tagsinuse 465.215072 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 7146939 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 187994 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 38.016846 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 104853894000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 465.215072 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.908623 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.908623 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 367 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 315 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 52 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.716797 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 15057330 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 15057330 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 3659340 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3659340 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3255921 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3255921 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49714 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 49714 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79782 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 79782 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71812 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 71812 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 6915261 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 6915261 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 6964975 # number of overall hits +system.cpu1.dcache.overall_hits::total 6964975 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 134401 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 134401 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 90853 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 90853 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30496 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30496 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17326 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 17326 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23466 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23466 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 225254 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 225254 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 255750 # number of overall misses +system.cpu1.dcache.overall_misses::total 255750 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1931922000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1931922000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2253615359 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2253615359 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 317972750 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 317972750 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 552026738 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 552026738 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2980000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2980000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4185537359 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4185537359 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4185537359 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4185537359 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3793741 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3793741 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 3346774 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 3346774 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80210 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 80210 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97108 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 97108 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95278 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 95278 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 7140515 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 7140515 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 7220725 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 7220725 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035427 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.035427 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027146 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.027146 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380202 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380202 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.178420 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.178420 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.246290 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.246290 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031546 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.031546 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035419 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.035419 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14374.312691 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14374.312691 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24805.073679 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 24805.073679 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18352.346185 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18352.346185 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23524.534987 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23524.534987 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18868.199815 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 18868.199815 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16668.130651 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 16668.130651 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18581.411913 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18581.411913 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16365.737474 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16365.737474 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1600,82 +1584,82 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 118649 # number of writebacks -system.cpu1.dcache.writebacks::total 118649 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 239 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 239 # number of ReadReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12076 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12076 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 239 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 239 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 239 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 239 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 137127 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 137127 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 93147 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 93147 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29658 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 29658 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5147 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5147 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23379 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23379 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 230274 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 230274 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 259932 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 259932 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1715737747 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1715737747 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2159697659 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2159697659 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 467259500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 467259500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 82226250 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 82226250 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 491497707 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 491497707 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1621000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1621000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3875435406 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3875435406 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4342694906 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4342694906 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 525084500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 525084500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 379956000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 379956000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 905040500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 905040500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013803 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013803 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014450 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014450 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.369999 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.369999 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053129 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053129 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.246046 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246046 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014057 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.014057 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015791 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.015791 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12512.034443 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12512.034443 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23185.906782 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23185.906782 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15754.922786 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15754.922786 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15975.568292 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15975.568292 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21023.042346 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21023.042346 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 117066 # number of writebacks +system.cpu1.dcache.writebacks::total 117066 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 249 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 249 # number of ReadReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12071 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12071 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 249 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 249 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 249 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 249 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 134152 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 134152 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 90853 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 90853 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29793 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 29793 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5255 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5255 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23466 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23466 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 225005 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 225005 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 254798 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 254798 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1724213250 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1724213250 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2112235141 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2112235141 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 459472252 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 459472252 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 82571000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 82571000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 515647762 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 515647762 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2900500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2900500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3836448391 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3836448391 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4295920643 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4295920643 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 406973750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 406973750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 280407500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 280407500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 687381250 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 687381250 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035361 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035361 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027146 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027146 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.371437 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.371437 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054115 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054115 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.246290 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246290 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031511 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031511 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035287 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035287 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12852.683896 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12852.683896 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23248.931142 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23248.931142 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15422.154600 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15422.154600 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15712.844910 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15712.844910 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21974.250490 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21974.250490 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16829.669898 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16829.669898 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16707.042250 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16707.042250 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17050.502838 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17050.502838 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16860.103466 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16860.103466 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1683,58 +1667,58 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 526723 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.608741 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 43832665 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 527235 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 83.136865 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 84507534000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.608741 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973845 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.973845 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 506368 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.574535 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 16242209 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 506880 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 32.043499 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 84702777500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.574535 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973778 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.973778 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 387 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 122 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 388 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 121 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 89247035 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 89247035 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 43832665 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 43832665 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 43832665 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 43832665 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 43832665 # number of overall hits -system.cpu1.icache.overall_hits::total 43832665 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 527235 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 527235 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 527235 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 527235 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 527235 # number of overall misses -system.cpu1.icache.overall_misses::total 527235 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4617960760 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4617960760 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4617960760 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4617960760 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4617960760 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4617960760 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 44359900 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 44359900 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 44359900 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 44359900 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 44359900 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 44359900 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011885 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.011885 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011885 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.011885 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011885 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.011885 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8758.828151 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8758.828151 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8758.828151 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8758.828151 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8758.828151 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8758.828151 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 34005058 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 34005058 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 16242209 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 16242209 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 16242209 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 16242209 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 16242209 # number of overall hits +system.cpu1.icache.overall_hits::total 16242209 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 506880 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 506880 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 506880 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 506880 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 506880 # number of overall misses +system.cpu1.icache.overall_misses::total 506880 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4441098014 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4441098014 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4441098014 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4441098014 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4441098014 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4441098014 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 16749089 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 16749089 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 16749089 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 16749089 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 16749089 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 16749089 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030263 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.030263 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030263 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.030263 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030263 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.030263 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8761.635918 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8761.635918 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8761.635918 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8761.635918 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8761.635918 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8761.635918 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1743,219 +1727,220 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 527235 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 527235 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 527235 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 527235 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 527235 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 527235 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3826248740 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3826248740 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3826248740 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3826248740 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3826248740 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3826248740 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13994500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13994500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13994500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 13994500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011885 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011885 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011885 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.011885 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011885 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.011885 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7257.197910 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7257.197910 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7257.197910 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 7257.197910 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7257.197910 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 7257.197910 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 506880 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 506880 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 506880 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 506880 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 506880 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 506880 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3933409986 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3933409986 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3933409986 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3933409986 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3933409986 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3933409986 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15446750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15446750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15446750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 15446750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030263 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030263 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030263 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.030263 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030263 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.030263 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7760.041797 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7760.041797 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7760.041797 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 7760.041797 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7760.041797 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 7760.041797 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 199846 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 199846 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 194594 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 194618 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 21 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 59474 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 47689 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15083.724459 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 731618 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 62301 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 11.743279 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 58318 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 39568 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 14853.795199 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 710508 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 54174 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 13.115295 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 8757.920968 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.140482 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.100736 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3269.623984 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2111.182929 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 939.755359 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.534541 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000192 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000128 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.199562 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.128856 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.057358 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.920637 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1198 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 23 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13391 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 29 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1169 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 8945.748297 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 4.024093 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.068283 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3300.044649 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1917.167815 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 684.742061 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.546005 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000246 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000126 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.201419 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.117015 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.041793 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.906604 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1123 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13469 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 10 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 38 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1075 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 282 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1514 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11595 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.073120 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001404 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.817322 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 15244499 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 15244499 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3091 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1729 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 513133 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 102720 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 620673 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 118649 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 118649 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1485 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 1485 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 867 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 867 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 28139 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 28139 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3091 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1729 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 513133 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 130859 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 648812 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3091 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1729 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 513133 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 130859 # number of overall hits -system.cpu1.l2cache.overall_hits::total 648812 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 321 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 276 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 14102 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 69212 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 83911 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28339 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 28339 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22509 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22509 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 35184 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 35184 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 321 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 276 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 14102 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 104396 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 119095 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 321 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 276 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 14102 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 104396 # number of overall misses -system.cpu1.l2cache.overall_misses::total 119095 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 6369000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5421000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 483830740 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1476489366 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 1972110106 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 522569379 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 522569379 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 435248439 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 435248439 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1586000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1586000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1289152696 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1289152696 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 6369000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5421000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 483830740 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 2765642062 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 3261262802 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 6369000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5421000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 483830740 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 2765642062 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 3261262802 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3412 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2005 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 527235 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 171932 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 704584 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 118649 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 118649 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29824 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 29824 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23376 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23376 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63323 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 63323 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3412 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2005 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 527235 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 235255 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 767907 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3412 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2005 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 527235 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 235255 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 767907 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.094080 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.137656 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026747 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.402554 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.119093 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.950208 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.950208 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.962911 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.962911 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 291 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1497 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11681 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.068542 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.822083 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 14802624 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 14802624 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 2949 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1668 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 493694 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 102403 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 600714 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 117066 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 117066 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1062 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 1062 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 911 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 911 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27911 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 27911 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 2949 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1668 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 493694 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 130314 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 628625 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 2949 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1668 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 493694 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 130314 # number of overall hits +system.cpu1.l2cache.overall_hits::total 628625 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 319 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 267 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 13186 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 66797 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 80569 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 27938 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 27938 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22546 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 22546 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 9 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 9 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33942 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 33942 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 319 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 267 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 13186 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 100739 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 114511 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 319 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 267 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 13186 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 100739 # number of overall misses +system.cpu1.l2cache.overall_misses::total 114511 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 6370500 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5365500 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 469517986 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1430715000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 1911968986 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 536455892 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 536455892 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 454234073 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 454234073 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2847500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2847500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1211409437 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 1211409437 # number of ReadExReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 6370500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5365500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 469517986 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 2642124437 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 3123378423 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 6370500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5365500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 469517986 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 2642124437 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 3123378423 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3268 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1935 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 506880 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.data 169200 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 681283 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 117066 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 117066 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29000 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 29000 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23457 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 23457 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 9 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 9 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61853 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 61853 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3268 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1935 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 506880 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 231053 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 743136 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3268 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1935 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 506880 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 231053 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 743136 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.097613 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.137984 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026014 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.394781 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.118261 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.963379 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.963379 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.961163 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.961163 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.555627 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.555627 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.094080 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.137656 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026747 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.443757 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.155090 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.094080 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.137656 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026747 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.443757 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.155090 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 19841.121495 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19641.304348 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 34309.370302 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 21332.852193 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 23502.402617 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18439.937154 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18439.937154 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19336.640411 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19336.640411 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 528666.666667 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 528666.666667 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 36640.310823 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 36640.310823 # average ReadExReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 19841.121495 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19641.304348 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34309.370302 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 26491.839362 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 27383.708821 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 19841.121495 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19641.304348 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34309.370302 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 26491.839362 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 27383.708821 # average overall miss latency +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.548753 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.548753 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.097613 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.137984 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026014 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.436000 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.154092 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.097613 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.137984 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026014 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.436000 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.154092 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 19970.219436 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20095.505618 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 35607.309722 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 21418.851146 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 23730.826819 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19201.656955 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19201.656955 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20146.991617 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20146.991617 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 316388.888889 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 316388.888889 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 35690.573243 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 35690.573243 # average ReadExReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 19970.219436 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20095.505618 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35607.309722 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 26227.423709 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 27275.793793 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 19970.219436 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20095.505618 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35607.309722 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 26227.423709 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 27275.793793 # average overall miss latency system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1964,126 +1949,126 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 31472 # number of writebacks -system.cpu1.l2cache.writebacks::total 31472 # number of writebacks -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 76 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 76 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 76 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 76 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 76 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 321 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 276 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 14102 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 69212 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 83911 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 24018 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 24018 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28339 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28339 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22509 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22509 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 35108 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 35108 # number of ReadExReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 321 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 276 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 14102 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 104320 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 119019 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 321 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 276 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 14102 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 104320 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 24018 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 143037 # number of overall MSHR misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4122000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3489000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 384250260 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 991800372 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1383661632 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 814752860 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 814752860 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 402368047 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 402368047 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 306023777 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 306023777 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1341000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1341000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1031661014 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1031661014 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4122000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3489000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 384250260 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2023461386 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 2415322646 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4122000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3489000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 384250260 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2023461386 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 814752860 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 3230075506 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12590000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 494236499 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 506826499 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 356773500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 356773500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12590000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 851009999 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 863599999 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.094080 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.137656 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.026747 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.402554 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.119093 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.writebacks::writebacks 25242 # number of writebacks +system.cpu1.l2cache.writebacks::total 25242 # number of writebacks +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 89 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 89 # number of ReadExReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 89 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 89 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 89 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 89 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 319 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 267 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 13186 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 66797 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 80569 # number of ReadReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 22684 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 22684 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 27938 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 27938 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22546 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22546 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 9 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 9 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33853 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 33853 # number of ReadExReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 319 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 267 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 13186 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 100650 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 114422 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 319 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 267 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 13186 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 100650 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 22684 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 137106 # number of overall MSHR misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4297000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3630000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 382998014 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 996392500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1387317514 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 708613533 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 708613533 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 439996296 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 439996296 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 340047738 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 340047738 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2503000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2503000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 980626782 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 980626782 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4297000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3630000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 382998014 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 1977019282 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 2367944296 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4297000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3630000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 382998014 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 1977019282 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 708613533 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 3076557829 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14041750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 382270250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 396312000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 262085000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 262085000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 14041750 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 644355250 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 658397000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.097613 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.137984 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.026014 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.394781 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.118261 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.950208 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.950208 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.962911 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.962911 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.963379 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.963379 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.961163 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.961163 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.554427 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.554427 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.094080 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.137656 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026747 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.443434 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.154991 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.094080 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.137656 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026747 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.443434 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.547314 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.547314 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.097613 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.137984 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026014 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.435614 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.153972 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.097613 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.137984 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026014 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.435614 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.186269 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 12841.121495 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12641.304348 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27247.926535 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 14329.890366 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16489.633445 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33922.593888 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33922.593888 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14198.385511 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14198.385511 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13595.618508 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13595.618508 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 447000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 447000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29385.354164 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29385.354164 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 12841.121495 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12641.304348 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27247.926535 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19396.677396 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20293.588805 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 12841.121495 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12641.304348 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27247.926535 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19396.677396 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33922.593888 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 22582.097681 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.184497 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13470.219436 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13595.505618 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 29045.807220 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 14916.725302 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 17218.998796 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31238.473506 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31238.473506 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15749.026272 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15749.026272 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15082.397676 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15082.397676 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 278111.111111 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 278111.111111 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 28967.204738 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 28967.204738 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13470.219436 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13595.505618 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29045.807220 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19642.516463 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20694.834000 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13470.219436 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13595.505618 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29045.807220 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19642.516463 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31238.473506 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 22439.264722 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2093,64 +2078,62 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 1051189 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 750269 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 3091 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 3091 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 118649 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 33325 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 74679 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41637 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 85827 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 81 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 85544 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 68027 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1054824 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 784590 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5329 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9434 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 1854177 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33743748 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25394480 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8020 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13648 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 59159896 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 572639 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1437265 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.343414 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.474848 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 1026038 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 726618 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2443 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2443 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 117066 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 27637 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36279 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 75553 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41371 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 85405 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 63 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 107 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 84221 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 66421 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1014114 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 770781 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5251 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9223 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 1799369 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 32441028 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25029390 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7740 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13072 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 57491230 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 567913 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1404964 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 3.347502 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.476177 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 943688 65.66% 65.66% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 493577 34.34% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 916736 65.25% 65.25% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 488228 34.75% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1437265 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 595732734 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 1404964 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 579509000 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 80038500 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 80431999 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 791497760 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 760939764 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 388635637 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 380431845 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 3316000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 6022000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 5955000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31024 # Transaction distribution -system.iobus.trans_dist::ReadResp 31024 # Transaction distribution -system.iobus.trans_dist::WriteReq 59440 # Transaction distribution -system.iobus.trans_dist::WriteResp 23216 # Transaction distribution +system.iobus.trans_dist::ReadReq 31015 # Transaction distribution +system.iobus.trans_dist::ReadResp 31015 # Transaction distribution +system.iobus.trans_dist::WriteReq 59423 # Transaction distribution +system.iobus.trans_dist::WriteResp 23199 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56604 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -2171,11 +2154,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107918 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180928 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 180876 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71548 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -2196,11 +2179,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162798 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484122 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2484070 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 40093000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2240,23 +2223,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347109131 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 198981721 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84719000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36846525 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36787516 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36445 # number of replacements -system.iocache.tags.tagsinuse 14.387294 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.385318 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 287959539000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.387294 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.899206 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.899206 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 288337625000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.385318 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.899082 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.899082 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -2270,14 +2253,14 @@ system.iocache.demand_misses::realview.ide 255 # system.iocache.demand_misses::total 255 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 255 # number of overall misses system.iocache.overall_misses::total 255 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 31782377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 31782377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9599974229 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9599974229 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 31782377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 31782377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 31782377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 31782377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 32669377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 32669377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6649988828 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6649988828 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 32669377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 32669377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 32669377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 32669377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -2294,19 +2277,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124636.772549 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124636.772549 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265016.956410 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 265016.956410 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124636.772549 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124636.772549 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124636.772549 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124636.772549 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 55555 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 128115.203922 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 128115.203922 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183579.638582 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183579.638582 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 128115.203922 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 128115.203922 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 128115.203922 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 128115.203922 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 22637 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7160 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3456 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.759078 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.550058 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -2320,14 +2303,14 @@ system.iocache.demand_mshr_misses::realview.ide 255 system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 18521377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 18521377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7716276279 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7716276279 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 18521377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 18521377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 18521377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 18521377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 19398377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 19398377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4766308860 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4766308860 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 19398377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 19398377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 19398377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 19398377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -2336,303 +2319,290 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72632.850980 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72632.850980 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213015.577490 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213015.577490 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 72632.850980 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72632.850980 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 72632.850980 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72632.850980 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76072.066667 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76072.066667 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131578.756073 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131578.756073 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 76072.066667 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76072.066667 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 76072.066667 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76072.066667 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 130735 # number of replacements -system.l2c.tags.tagsinuse 63966.604731 # Cycle average of tags in use -system.l2c.tags.total_refs 343053 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 195063 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.758678 # Average number of references to valid blocks. +system.l2c.tags.replacements 120296 # number of replacements +system.l2c.tags.tagsinuse 63905.436039 # Cycle average of tags in use +system.l2c.tags.total_refs 339434 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 184689 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.837868 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12083.139597 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.938906 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 1.007553 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 6678.027236 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2760.487108 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38360.306045 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.955640 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1552.248405 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 535.801693 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1990.692549 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.184374 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000060 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.101899 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.042122 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.585332 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.023685 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.008176 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.030376 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.976053 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 32989 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 31331 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 170 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 4524 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 28295 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 254 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 1895 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 29170 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.503372 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000122 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.478073 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 4931105 # Number of tag accesses -system.l2c.tags.data_accesses 4931105 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 82 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 63 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 29372 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 45566 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 45492 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 34 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 41 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 11667 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 8537 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 5785 # number of ReadReq hits -system.l2c.ReadReq_hits::total 146639 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 227719 # number of Writeback hits -system.l2c.Writeback_hits::total 227719 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 2362 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 770 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 3132 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 164 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 164 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 328 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 3862 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1497 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5359 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 82 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 63 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 29372 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 49428 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 45492 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 34 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 41 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 11667 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 10034 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 5785 # number of demand (read+write) hits -system.l2c.demand_hits::total 151998 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 82 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 63 # number of overall hits -system.l2c.overall_hits::cpu0.inst 29372 # number of overall hits -system.l2c.overall_hits::cpu0.data 49428 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 45492 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 34 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 41 # number of overall hits -system.l2c.overall_hits::cpu1.inst 11667 # number of overall hits -system.l2c.overall_hits::cpu1.data 10034 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 5785 # number of overall hits -system.l2c.overall_hits::total 151998 # number of overall hits +system.l2c.tags.occ_blocks::writebacks 11082.113172 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.011404 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.058569 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7219.690376 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2883.100910 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 39595.862719 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1402.790170 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 257.162663 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1460.646056 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.169100 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000061 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.110164 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.043993 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.604185 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.021405 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.003924 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.022288 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.975120 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 33682 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 30706 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 154 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 4910 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 28614 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 227 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 1859 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 28608 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.513947 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.468536 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 4789457 # Number of tag accesses +system.l2c.tags.data_accesses 4789457 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 83 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 70 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 29564 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 45272 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 47744 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 28 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 33 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 10986 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 7565 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 4624 # number of ReadReq hits +system.l2c.ReadReq_hits::total 145969 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 220623 # number of Writeback hits +system.l2c.Writeback_hits::total 220623 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 2700 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 726 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 3426 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 152 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 169 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 321 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 4139 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 2014 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 6153 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 83 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 70 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 29564 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 49411 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 47744 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 28 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 33 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 10986 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 9579 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 4624 # number of demand (read+write) hits +system.l2c.demand_hits::total 152122 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 83 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 70 # number of overall hits +system.l2c.overall_hits::cpu0.inst 29564 # number of overall hits +system.l2c.overall_hits::cpu0.data 49411 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 47744 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 28 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 33 # number of overall hits +system.l2c.overall_hits::cpu1.inst 10986 # number of overall hits +system.l2c.overall_hits::cpu1.data 9579 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 4624 # number of overall hits +system.l2c.overall_hits::total 152122 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 7 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 17779 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 8894 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 134996 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2435 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 924 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 5907 # number of ReadReq misses -system.l2c.ReadReq_misses::total 170945 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 8889 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 2898 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11787 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 758 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1209 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1967 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 11387 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 8562 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 19949 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu0.inst 17590 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 8761 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 130188 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 2200 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 584 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 5403 # number of ReadReq misses +system.l2c.ReadReq_misses::total 164735 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 8579 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 2656 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 11235 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 453 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1262 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1715 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 10640 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 6753 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 17393 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 17779 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 20281 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 134996 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2435 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 9486 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 5907 # number of demand (read+write) misses -system.l2c.demand_misses::total 190894 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 17590 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 19401 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 130188 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2200 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 7337 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 5403 # number of demand (read+write) misses +system.l2c.demand_misses::total 182128 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 17779 # number of overall misses -system.l2c.overall_misses::cpu0.data 20281 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 134996 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2435 # number of overall misses -system.l2c.overall_misses::cpu1.data 9486 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 5907 # number of overall misses -system.l2c.overall_misses::total 190894 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 494750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 149500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 1299838245 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 708631748 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 13069199153 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 75000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 182647247 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 78676500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 680911899 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 16020624042 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 5423319 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 2108409 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 7531728 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 679977 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 605974 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 1285951 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 888864663 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 627516972 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1516381635 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 494750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 149500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1299838245 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 1597496411 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 13069199153 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 75000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 182647247 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 706193472 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 680911899 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 17537005677 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 494750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 149500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1299838245 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 1597496411 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 13069199153 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 75000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 182647247 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 706193472 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 680911899 # number of overall miss cycles -system.l2c.overall_miss_latency::total 17537005677 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 89 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 65 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 47151 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 54460 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 180488 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 35 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 41 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 14102 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 9461 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 11692 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 317584 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 227719 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 227719 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 11251 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 3668 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 14919 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 922 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1373 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2295 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 15249 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 10059 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 25308 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 89 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 65 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 47151 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 69709 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 180488 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 35 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 41 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 14102 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 19520 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11692 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 342892 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 89 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 65 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 47151 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 69709 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 180488 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 35 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 41 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 14102 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 19520 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11692 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 342892 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.078652 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.030769 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.377065 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.163313 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.747950 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.028571 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.172671 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.097664 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.505217 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.538267 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.790063 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.790076 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.790066 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.822126 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.880554 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.857081 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.746737 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.851178 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.788249 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.078652 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.030769 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.377065 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.290938 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.747950 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.028571 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.172671 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.485963 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.505217 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.556718 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.078652 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.030769 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.377065 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.290938 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.747950 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.028571 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.172671 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.485963 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.505217 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.556718 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 70678.571429 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 73110.874909 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 79675.258376 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 96811.751111 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 75000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75009.136345 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 85147.727273 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 115272.033012 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 93718.003112 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 610.115761 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 727.539337 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 638.986002 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 897.067282 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 501.219189 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 653.762583 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 78059.599807 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73290.933427 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 76012.914682 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 70678.571429 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 73110.874909 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 78768.128347 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 96811.751111 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 75000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 75009.136345 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 74445.864643 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 115272.033012 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 91867.767855 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 70678.571429 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 73110.874909 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 78768.128347 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 96811.751111 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 75000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 75009.136345 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 74445.864643 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 115272.033012 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 91867.767855 # average overall miss latency +system.l2c.overall_misses::cpu0.inst 17590 # number of overall misses +system.l2c.overall_misses::cpu0.data 19401 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 130188 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2200 # number of overall misses +system.l2c.overall_misses::cpu1.data 7337 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 5403 # number of overall misses +system.l2c.overall_misses::total 182128 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 549750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 165000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 1421225252 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 758301308 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 12728769957 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 181920507 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 52732500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 614628925 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 15758293199 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 14082590 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 2976406 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 17058996 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1006973 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1562950 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 2569923 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 947359927 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 541992722 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1489352649 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 549750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 165000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1421225252 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 1705661235 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 12728769957 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 181920507 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 594725222 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 614628925 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 17247645848 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 549750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 165000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1421225252 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 1705661235 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 12728769957 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 181920507 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 594725222 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 614628925 # number of overall miss cycles +system.l2c.overall_miss_latency::total 17247645848 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 90 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 72 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 47154 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 54033 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 177932 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 28 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 33 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 13186 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 8149 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 10027 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 310704 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 220623 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 220623 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 11279 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 3382 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 14661 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 605 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1431 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2036 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 14779 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 8767 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 23546 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 90 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 72 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 47154 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 68812 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 177932 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 28 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 33 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 13186 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 16916 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 10027 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 334250 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 90 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 72 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 47154 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 68812 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 177932 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 28 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 33 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 13186 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 16916 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 10027 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 334250 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.077778 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.027778 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.373033 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.162142 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.731673 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.166844 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.071665 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.538845 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.530199 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.760617 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.785334 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.766319 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.748760 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.881901 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.842338 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.719940 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.770275 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.738682 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.077778 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.027778 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.373033 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.281942 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.731673 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.166844 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.433731 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.538845 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.544886 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.077778 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.027778 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.373033 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.281942 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.731673 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.166844 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.433731 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.538845 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.544886 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 78535.714286 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 82500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80797.342354 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 86554.195640 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 97772.221380 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 82691.139545 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 90295.376712 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 113756.972978 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 95658.440520 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1641.518825 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1120.634789 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1518.379706 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2222.898455 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1238.470681 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1498.497376 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 89037.587124 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 80259.547164 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 85629.428448 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 78535.714286 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 82500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 80797.342354 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 87916.150456 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 97772.221380 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 82691.139545 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 81058.364727 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 113756.972978 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 94700.682202 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 78535.714286 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 82500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 80797.342354 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 87916.150456 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 97772.221380 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 82691.139545 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 81058.364727 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 113756.972978 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 94700.682202 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2641,186 +2611,174 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 99035 # number of writebacks -system.l2c.writebacks::total 99035 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu1.inst 3 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 4 # number of overall MSHR hits +system.l2c.writebacks::writebacks 92066 # number of writebacks +system.l2c.writebacks::total 92066 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 2 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 5 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 5 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 5 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 7 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 7 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 17779 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 8894 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 134996 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 2432 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 923 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 5907 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 170941 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 8889 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 2898 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 11787 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 758 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1209 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1967 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 11387 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 8562 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 19949 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 17588 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 8761 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 130188 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 2195 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 584 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 5403 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 164728 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 8579 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 2656 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 11235 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 453 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1262 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1715 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 10640 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 6753 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 17393 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 7 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 17779 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 20281 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 134996 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 2432 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 9485 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 5907 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 190890 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 17588 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 19401 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 130188 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2195 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 7337 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 5403 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 182121 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 7 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 17779 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 20281 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 134996 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2432 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 9485 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5907 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 190890 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 408750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 125000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1075716745 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 597785248 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11388842153 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 151904497 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 67178000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 608475899 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 13890498792 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 90106352 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 29086385 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 119192737 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7710755 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 12095707 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 19806462 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 746306335 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 519227026 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1265533361 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 408750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 125000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1075716745 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 1344091583 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11388842153 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 62500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 151904497 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 586405026 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 608475899 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 15156032153 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 408750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1075716745 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 1344091583 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11388842153 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 62500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 151904497 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 586405026 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 608475899 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 15156032153 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 476665000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5183212748 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 9260500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 424539000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 6093677248 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3944737000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 304049000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 4248786000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 476665000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9127949748 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 9260500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 728588000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 10342463248 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.078652 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.030769 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.377065 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.163313 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.747950 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.028571 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.172458 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.097558 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.505217 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.538254 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.790063 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.790076 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.790066 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.822126 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.880554 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.857081 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.746737 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.851178 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.788249 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.078652 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.030769 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.377065 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.290938 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.747950 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.028571 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.172458 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.485912 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.505217 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.556706 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.078652 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.030769 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.377065 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.290938 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.747950 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.028571 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.172458 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.485912 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.505217 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.556706 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 58392.857143 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60504.907194 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 67212.193389 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84364.293409 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62460.730674 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 72782.231853 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103009.293889 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 81259.023827 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10136.837890 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10036.709800 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10112.219988 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10172.500000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10004.720430 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10069.375699 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 65540.206815 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60643.193880 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 63438.436062 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 58392.857143 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60504.907194 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 66273.437355 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84364.293409 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62460.730674 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61824.462414 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103009.293889 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 79396.679517 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 58392.857143 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60504.907194 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 66273.437355 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84364.293409 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62460.730674 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61824.462414 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103009.293889 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 79396.679517 # average overall mshr miss latency +system.l2c.overall_mshr_misses::cpu0.inst 17588 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 19401 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 130188 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2195 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 7337 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5403 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 182121 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 462250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 140000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1200652248 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 648693692 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11121813439 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 154097993 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 45421500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 548259369 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 13719540491 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 153128559 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 47338644 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 200467203 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 8146450 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 22467762 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 30614212 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 815815573 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 457532278 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1273347851 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 462250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 140000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1200652248 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 1464509265 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11121813439 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 154097993 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 502953778 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 548259369 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 14992888342 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 462250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 140000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1200652248 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 1464509265 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11121813439 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 154097993 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 502953778 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 548259369 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 14992888342 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 549810500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5306549000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 10505750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 321692750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 6188558000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4079142000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 216691500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4295833500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 549810500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9385691000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 10505750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 538384250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10484391500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.077778 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.027778 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.372991 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.162142 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.731673 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.166464 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.071665 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.538845 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.530177 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.760617 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.785334 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.766319 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.748760 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.881901 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.842338 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.719940 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.770275 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.738682 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.077778 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.027778 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.372991 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.281942 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.731673 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.166464 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.433731 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.538845 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.544865 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.077778 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.027778 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.372991 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.281942 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.731673 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.166464 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.433731 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.538845 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.544865 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 66035.714286 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68265.422333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 74043.338888 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 85428.867784 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70204.097039 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 77776.541096 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101473.138812 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 83286.026000 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17849.231729 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17823.284639 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17843.097730 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17983.333333 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17803.297940 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17850.852478 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 76674.395959 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 67752.447505 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 73210.363422 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 66035.714286 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68265.422333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 75486.277254 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 85428.867784 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70204.097039 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 68550.330925 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101473.138812 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 82323.775633 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66035.714286 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68265.422333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 75486.277254 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 85428.867784 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70204.097039 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 68550.330925 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101473.138812 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 82323.775633 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -2835,58 +2793,58 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 215303 # Transaction distribution -system.membus.trans_dist::ReadResp 215303 # Transaction distribution -system.membus.trans_dist::WriteReq 30982 # Transaction distribution -system.membus.trans_dist::WriteResp 30982 # Transaction distribution -system.membus.trans_dist::Writeback 135225 # Transaction distribution +system.membus.trans_dist::ReadReq 209058 # Transaction distribution +system.membus.trans_dist::ReadResp 209058 # Transaction distribution +system.membus.trans_dist::WriteReq 30943 # Transaction distribution +system.membus.trans_dist::WriteResp 30943 # Transaction distribution +system.membus.trans_dist::Writeback 128256 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 76008 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40410 # Transaction distribution -system.membus.trans_dist::UpgradeResp 13867 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 5 # Transaction distribution -system.membus.trans_dist::ReadExReq 40350 # Transaction distribution -system.membus.trans_dist::ReadExResp 19836 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 77066 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40095 # Transaction distribution +system.membus.trans_dist::UpgradeResp 13060 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution +system.membus.trans_dist::ReadExReq 37613 # Transaction distribution +system.membus.trans_dist::ReadExResp 17283 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13762 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 659440 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 781206 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13672 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 634735 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 756359 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108908 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108908 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 890114 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 865267 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162798 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27524 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18582632 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18773074 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17575592 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17765802 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23408530 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 123675 # Total snoops (count) -system.membus.snoop_fanout::samples 499419 # Request fanout histogram +system.membus.pkt_size::total 22401258 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 125085 # Total snoops (count) +system.membus.snoop_fanout::samples 484369 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 499419 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 484369 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 499419 # Request fanout histogram -system.membus.reqLayer0.occupancy 88165000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 484369 # Request fanout histogram +system.membus.reqLayer0.occupancy 88115000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 18500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11453500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11464500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1828859499 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1931425684 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38544475 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1105573957 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 1100453088 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 37520484 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2919,44 +2877,44 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 482729 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 482714 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30982 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30982 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 227719 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 79027 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 40738 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 119765 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 81 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 81 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51496 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51496 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1065854 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 282098 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1347952 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31837086 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4944756 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 36781842 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 286323 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 873908 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.041744 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.200003 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 476594 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 476579 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30943 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30943 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 220623 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36279 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 80382 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 40416 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 120798 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 107 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 107 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 50330 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50330 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1064234 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 261111 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1325345 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31566808 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4207570 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 35774378 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 289326 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 860656 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.042449 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.201611 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 837428 95.83% 95.83% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36480 4.17% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 824122 95.76% 95.76% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36534 4.24% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 873908 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1446151615 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1080000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 860656 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 750507689 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 360000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1735034184 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 618323353 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 653714719 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 219646363 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |