diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt | 1602 |
1 files changed, 801 insertions, 801 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 0a013f420..db4dfffca 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,320 +1,320 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.203695 # Number of seconds simulated -sim_ticks 1203694548000 # Number of ticks simulated -final_tick 1203694548000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.203606 # Number of seconds simulated +sim_ticks 1203606499000 # Number of ticks simulated +final_tick 1203606499000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 610810 # Simulator instruction rate (inst/s) -host_op_rate 778429 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11963163223 # Simulator tick rate (ticks/s) -host_mem_usage 383784 # Number of bytes of host memory used -host_seconds 100.62 # Real time elapsed on the host -sim_insts 61457649 # Number of instructions simulated -sim_ops 78322983 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 56 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 56 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 56 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 418240 # Simulator instruction rate (inst/s) +host_op_rate 532998 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8191230777 # Simulator tick rate (ticks/s) +host_mem_usage 386340 # Number of bytes of host memory used +host_seconds 146.94 # Real time elapsed on the host +sim_insts 61455549 # Number of instructions simulated +sim_ops 78317886 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 354404 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 354084 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 4259252 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 364636 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5307760 # Number of bytes read from this memory -system.physmem.bytes_read::total 62191012 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 354404 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 364636 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.inst 364956 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5307824 # Number of bytes read from this memory +system.physmem.bytes_read::total 62191076 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 354084 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 364956 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 719040 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4163840 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 4163904 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7191184 # Number of bytes written to this memory +system.physmem.bytes_written::total 7191248 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 11756 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 11751 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 66623 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5779 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82960 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6655189 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 65060 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5784 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82961 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6655190 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 65061 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 821896 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43120999 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 821897 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43124154 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 53 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 294430 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3538482 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 294186 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3538741 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 302931 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4409557 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51666772 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 294430 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 302931 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 597361 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3459216 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 14123 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2500920 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5974260 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3459216 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43120999 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 303219 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4409933 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51670605 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 294186 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 303219 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 597405 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3459523 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 14124 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2501103 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5974750 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3459523 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43124154 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 53 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 294430 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3552606 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 294186 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3552865 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 302931 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6910477 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 57641032 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 70187 # number of replacements -system.l2c.tagsinuse 53228.642974 # Cycle average of tags in use -system.l2c.total_refs 1643789 # Total number of references to valid blocks. -system.l2c.sampled_refs 135350 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.144728 # Average number of references to valid blocks. +system.physmem.bw_total::cpu1.inst 303219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6911036 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 57645355 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 56 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 56 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 56 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 70188 # number of replacements +system.l2c.tagsinuse 53228.072476 # Cycle average of tags in use +system.l2c.total_refs 1643838 # Total number of references to valid blocks. +system.l2c.sampled_refs 135351 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.145001 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 40454.040636 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 40453.574010 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.dtb.walker 0.000402 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.003088 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3394.914064 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2735.381228 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 2.669984 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3118.851455 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 3522.782116 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.617280 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu0.itb.walker 0.003089 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 3394.604865 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2735.402876 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 2.669960 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 3118.943835 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 3522.873439 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.617273 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.051802 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.051798 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.data 0.041739 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.047590 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.053753 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.812205 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.047591 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.053755 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.812196 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.dtb.walker 2523 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 1490 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 278283 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 124654 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5208 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 278308 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 124645 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 5210 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 1502 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 576279 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 223386 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1213325 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 571443 # number of Writeback hits -system.l2c.Writeback_hits::total 571443 # number of Writeback hits +system.l2c.ReadReq_hits::cpu1.inst 576222 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 223363 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1213263 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 571562 # number of Writeback hits +system.l2c.Writeback_hits::total 571562 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 992 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 888 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1880 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 191 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 95 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 286 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 39230 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 70245 # number of ReadExReq hits +system.l2c.UpgradeReq_hits::cpu1.data 878 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1870 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 189 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 96 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 285 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 39231 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 70244 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 109475 # number of ReadExReq hits system.l2c.demand_hits::cpu0.dtb.walker 2523 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 1490 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 278283 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 163884 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5208 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 278308 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 163876 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 5210 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 1502 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 576279 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 293631 # number of demand (read+write) hits -system.l2c.demand_hits::total 1322800 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 576222 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 293607 # number of demand (read+write) hits +system.l2c.demand_hits::total 1322738 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.dtb.walker 2523 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 1490 # number of overall hits -system.l2c.overall_hits::cpu0.inst 278283 # number of overall hits -system.l2c.overall_hits::cpu0.data 163884 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5208 # number of overall hits +system.l2c.overall_hits::cpu0.inst 278308 # number of overall hits +system.l2c.overall_hits::cpu0.data 163876 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 5210 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 1502 # number of overall hits -system.l2c.overall_hits::cpu1.inst 576279 # number of overall hits -system.l2c.overall_hits::cpu1.data 293631 # number of overall hits -system.l2c.overall_hits::total 1322800 # number of overall hits +system.l2c.overall_hits::cpu1.inst 576222 # number of overall hits +system.l2c.overall_hits::cpu1.data 293607 # number of overall hits +system.l2c.overall_hits::total 1322738 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 5124 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6001 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 5119 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6000 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 5692 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 5607 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 5697 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 5608 # number of ReadReq misses system.l2c.ReadReq_misses::total 22431 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 4012 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4909 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 8921 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 655 # number of SCUpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 4011 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 4908 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 8919 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 652 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 388 # 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mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000396 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.002009 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018076 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.291570 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000576 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009781 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.223357 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.109536 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018058 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.291580 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000575 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009790 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.223373 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.109541 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40014.444661 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40009.498417 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 41333.333333 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40164.441321 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40089.798466 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40070.196166 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40047.606680 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40029.842942 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40037.831745 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40003.051908 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40020.615979 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40009.585810 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40010.813699 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40147.319169 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40087.526994 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40013.774912 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40002.833333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40015.007899 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40003.655492 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40008.626839 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40012.464971 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40013.447229 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40013.005494 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40002.299080 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40009.018041 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40004.805769 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40010.496176 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40004.762820 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40007.274170 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40014.444661 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40010.696679 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 41333.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40164.441321 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40143.499941 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40085.138012 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40013.774912 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40009.814529 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40015.007899 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40004.689284 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40007.460628 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40014.444661 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40010.696679 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 41333.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40164.441321 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40143.499941 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40085.138012 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40013.774912 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40009.814529 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40015.007899 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40004.689284 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40007.460628 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -498,9 +498,9 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 4800541 # DTB read hits +system.cpu0.dtb.read_hits 4800569 # DTB read hits system.cpu0.dtb.read_misses 2116 # DTB read misses -system.cpu0.dtb.write_hits 4101169 # DTB write hits +system.cpu0.dtb.write_hits 4101188 # DTB write hits system.cpu0.dtb.write_misses 405 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -511,13 +511,13 @@ system.cpu0.dtb.align_faults 0 # Nu system.cpu0.dtb.prefetch_faults 91 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 203 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 4802657 # DTB read accesses -system.cpu0.dtb.write_accesses 4101574 # DTB write accesses +system.cpu0.dtb.read_accesses 4802685 # DTB read accesses +system.cpu0.dtb.write_accesses 4101593 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 8901710 # DTB hits +system.cpu0.dtb.hits 8901757 # DTB hits system.cpu0.dtb.misses 2521 # DTB misses -system.cpu0.dtb.accesses 8904231 # DTB accesses -system.cpu0.itb.inst_hits 19425295 # ITB inst hits +system.cpu0.dtb.accesses 8904278 # DTB accesses +system.cpu0.itb.inst_hits 19425317 # ITB inst hits system.cpu0.itb.inst_misses 1350 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -534,79 +534,79 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 19426645 # ITB inst accesses -system.cpu0.itb.hits 19425295 # DTB hits +system.cpu0.itb.inst_accesses 19426667 # ITB inst accesses +system.cpu0.itb.hits 19425317 # DTB hits system.cpu0.itb.misses 1350 # DTB misses -system.cpu0.itb.accesses 19426645 # DTB accesses -system.cpu0.numCycles 2405961611 # number of cpu cycles simulated +system.cpu0.itb.accesses 19426667 # DTB accesses +system.cpu0.numCycles 2405785466 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 19048182 # Number of instructions committed -system.cpu0.committedOps 25051772 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 22684080 # Number of integer alu accesses +system.cpu0.committedInsts 19048205 # Number of instructions committed +system.cpu0.committedOps 25051835 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 22684157 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 4364 # Number of float alu accesses -system.cpu0.num_func_calls 868675 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 2620305 # number of instructions that are conditional controls -system.cpu0.num_int_insts 22684080 # number of integer instructions +system.cpu0.num_func_calls 868672 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 2620308 # number of instructions that are conditional controls +system.cpu0.num_int_insts 22684157 # number of integer instructions system.cpu0.num_fp_insts 4364 # number of float instructions -system.cpu0.num_int_register_reads 128950966 # number of times the integer registers were read -system.cpu0.num_int_register_writes 23731370 # number of times the integer registers were written +system.cpu0.num_int_register_reads 128951400 # number of times the integer registers were read +system.cpu0.num_int_register_writes 23731440 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3980 # number of times the floating registers were read system.cpu0.num_fp_register_writes 384 # number of times the floating registers were written -system.cpu0.num_mem_refs 9388163 # number of memory refs -system.cpu0.num_load_insts 5047859 # Number of load instructions -system.cpu0.num_store_insts 4340304 # Number of store instructions -system.cpu0.num_idle_cycles 2301502404.823749 # Number of idle cycles -system.cpu0.num_busy_cycles 104459206.176251 # Number of busy cycles -system.cpu0.not_idle_fraction 0.043417 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.956583 # Percentage of idle cycles +system.cpu0.num_mem_refs 9388218 # number of memory refs +system.cpu0.num_load_insts 5047895 # Number of load instructions +system.cpu0.num_store_insts 4340323 # Number of store instructions +system.cpu0.num_idle_cycles 2301327262.807119 # Number of idle cycles +system.cpu0.num_busy_cycles 104458203.192881 # Number of busy cycles +system.cpu0.not_idle_fraction 0.043420 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.956580 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 34020 # number of quiesce instructions executed -system.cpu0.icache.replacements 283184 # number of replacements -system.cpu0.icache.tagsinuse 509.502628 # Cycle average of tags in use -system.cpu0.icache.total_refs 19141582 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 283696 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 67.472160 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 34019 # number of quiesce instructions executed +system.cpu0.icache.replacements 283204 # number of replacements +system.cpu0.icache.tagsinuse 509.502445 # Cycle average of tags in use +system.cpu0.icache.total_refs 19141584 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 283716 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 67.467411 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 75588601000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.502628 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu0.inst 509.502445 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.995122 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.995122 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 19141582 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 19141582 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 19141582 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 19141582 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 19141582 # number of overall hits -system.cpu0.icache.overall_hits::total 19141582 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 283696 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 283696 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 283696 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 283696 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 283696 # number of overall misses -system.cpu0.icache.overall_misses::total 283696 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 3929923500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 3929923500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 3929923500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 3929923500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 3929923500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 3929923500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 19425278 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 19425278 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 19425278 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 19425278 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 19425278 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 19425278 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014604 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014604 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014604 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014604 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014604 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014604 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13852.586924 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13852.586924 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13852.586924 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13852.586924 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13852.586924 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13852.586924 # average overall miss latency +system.cpu0.icache.ReadReq_hits::cpu0.inst 19141584 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 19141584 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 19141584 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 19141584 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 19141584 # number of overall hits +system.cpu0.icache.overall_hits::total 19141584 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 283716 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 283716 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 283716 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 283716 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 283716 # number of overall misses +system.cpu0.icache.overall_misses::total 283716 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 3929859500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 3929859500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 3929859500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 3929859500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 3929859500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 3929859500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 19425300 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 19425300 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 19425300 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 19425300 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 19425300 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 19425300 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014605 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014605 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014605 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014605 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014605 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014605 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13851.384836 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13851.384836 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13851.384836 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13851.384836 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13851.384836 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13851.384836 # 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average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11852.586924 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11852.586924 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11852.586924 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11852.586924 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014605 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014605 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014605 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014605 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014605 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014605 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11851.384836 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11851.384836 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11851.384836 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11851.384836 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11851.384836 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11851.384836 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # 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number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 7881 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7692 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7692 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 263418 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 263418 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 263418 # number of overall misses +system.cpu0.dcache.overall_misses::total 263418 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 1991139500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 1991139500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4199443500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 4199443500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 70259000 # 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miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.029464 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.062733 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.062733 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.061308 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.061308 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 8568408 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 8568408 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 8568408 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 8568408 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.031846 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.031846 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.029465 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.029465 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.062741 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.062741 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.061268 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.061268 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030743 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.030743 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030743 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.030743 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13596.209913 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13596.209913 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35907.261581 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 35907.261581 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 8916.687817 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8916.687817 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8618.227881 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8618.227881 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23502.313804 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 23502.313804 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23502.313804 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 23502.313804 # average overall miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13595.386359 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13595.386359 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35904.647703 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 35904.647703 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 8914.985408 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8914.985408 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8597.373895 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8597.373895 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23500.987024 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 23500.987024 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23500.987024 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 23500.987024 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -737,66 +737,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 204960 # number of writebacks -system.cpu0.dcache.writebacks::total 204960 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 146461 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 146461 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 116958 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 116958 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 7880 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7880 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7695 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7695 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 263419 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 263419 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 263419 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 263419 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1698392500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1698392500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3965725500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3965725500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 54503500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 54503500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 50946500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 50946500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.writebacks::writebacks 205058 # number of writebacks +system.cpu0.dcache.writebacks::total 205058 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 146457 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 146457 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 116961 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 116961 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 7881 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7881 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7690 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7690 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 263418 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 263418 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 263418 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 263418 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1698225500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1698225500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3965521500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3965521500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 54497000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 54497000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 50753000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 50753000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5664118000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 5664118000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5664118000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 5664118000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12130688000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12130688000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1193496500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1193496500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13324184500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13324184500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031847 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031847 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029464 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029464 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062733 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062733 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.061292 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.061292 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5663747000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 5663747000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5663747000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 5663747000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12130745000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12130745000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1193494500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1193494500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13324239500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13324239500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031846 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031846 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029465 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029465 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062741 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062741 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.061252 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.061252 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030743 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.030743 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030743 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.030743 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11596.209913 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11596.209913 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33907.261581 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33907.261581 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 6916.687817 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6916.687817 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6620.727745 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6620.727745 # average StoreCondReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11595.386359 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11595.386359 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33904.647703 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33904.647703 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 6914.985408 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6914.985408 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6599.869961 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6599.869961 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21502.313804 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21502.313804 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21502.313804 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21502.313804 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21500.987024 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21500.987024 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21500.987024 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21500.987024 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -806,26 +806,26 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 10590618 # DTB read hits -system.cpu1.dtb.read_misses 5230 # DTB read misses -system.cpu1.dtb.write_hits 7384755 # DTB write hits -system.cpu1.dtb.write_misses 1835 # DTB write misses +system.cpu1.dtb.read_hits 10589201 # DTB read hits +system.cpu1.dtb.read_misses 5231 # DTB read misses +system.cpu1.dtb.write_hits 7383574 # DTB write hits +system.cpu1.dtb.write_misses 1834 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 2257 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 194 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 193 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 249 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 10595848 # DTB read accesses -system.cpu1.dtb.write_accesses 7386590 # DTB write accesses +system.cpu1.dtb.read_accesses 10594432 # DTB read accesses +system.cpu1.dtb.write_accesses 7385408 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 17975373 # DTB hits +system.cpu1.dtb.hits 17972775 # DTB hits system.cpu1.dtb.misses 7065 # DTB misses -system.cpu1.dtb.accesses 17982438 # DTB accesses -system.cpu1.itb.inst_hits 43340388 # ITB inst hits +system.cpu1.dtb.accesses 17979840 # DTB accesses +system.cpu1.itb.inst_hits 43338256 # ITB inst hits system.cpu1.itb.inst_misses 3017 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -842,79 +842,79 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 43343405 # ITB inst accesses -system.cpu1.itb.hits 43340388 # DTB hits +system.cpu1.itb.inst_accesses 43341273 # ITB inst accesses +system.cpu1.itb.hits 43338256 # DTB hits system.cpu1.itb.misses 3017 # DTB misses -system.cpu1.itb.accesses 43343405 # DTB accesses -system.cpu1.numCycles 2407389096 # number of cpu cycles simulated +system.cpu1.itb.accesses 43341273 # DTB accesses +system.cpu1.numCycles 2407212998 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 42409467 # Number of instructions committed -system.cpu1.committedOps 53271211 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 47739499 # Number of integer alu accesses +system.cpu1.committedInsts 42407344 # Number of instructions committed +system.cpu1.committedOps 53266051 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 47734651 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 5457 # Number of float alu accesses -system.cpu1.num_func_calls 1335008 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 5483103 # number of instructions that are conditional controls -system.cpu1.num_int_insts 47739499 # number of integer instructions +system.cpu1.num_func_calls 1334953 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 5482869 # number of instructions that are conditional controls +system.cpu1.num_int_insts 47734651 # number of integer instructions system.cpu1.num_fp_insts 5457 # number of float instructions -system.cpu1.num_int_register_reads 274842107 # number of times the integer registers were read -system.cpu1.num_int_register_writes 51975033 # number of times the integer registers were written +system.cpu1.num_int_register_reads 274813771 # number of times the integer registers were read +system.cpu1.num_int_register_writes 51971016 # number of times the integer registers were written system.cpu1.num_fp_register_reads 3577 # number of times the floating registers were read system.cpu1.num_fp_register_writes 1884 # number of times the floating registers were written -system.cpu1.num_mem_refs 18684058 # number of memory refs -system.cpu1.num_load_insts 11000639 # Number of load instructions -system.cpu1.num_store_insts 7683419 # Number of store instructions -system.cpu1.num_idle_cycles 1827105047.254482 # Number of idle cycles -system.cpu1.num_busy_cycles 580284048.745518 # Number of busy cycles -system.cpu1.not_idle_fraction 0.241043 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.758957 # Percentage of idle cycles +system.cpu1.num_mem_refs 18681443 # number of memory refs +system.cpu1.num_load_insts 10999206 # Number of load instructions +system.cpu1.num_store_insts 7682237 # Number of store instructions +system.cpu1.num_idle_cycles 1827286039.250482 # Number of idle cycles +system.cpu1.num_busy_cycles 579926958.749518 # Number of busy cycles +system.cpu1.not_idle_fraction 0.240912 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.759088 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 56706 # number of quiesce instructions executed -system.cpu1.icache.replacements 582628 # number of replacements -system.cpu1.icache.tagsinuse 479.068937 # Cycle average of tags in use -system.cpu1.icache.total_refs 42757244 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 583140 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 73.322434 # Average number of references to valid blocks. +system.cpu1.kern.inst.quiesce 56704 # number of quiesce instructions executed +system.cpu1.icache.replacements 582576 # number of replacements +system.cpu1.icache.tagsinuse 479.066528 # Cycle average of tags in use +system.cpu1.icache.total_refs 42755164 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 583088 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 73.325405 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 92849627500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 479.068937 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.935682 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.935682 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 42757244 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 42757244 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 42757244 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 42757244 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 42757244 # number of overall hits -system.cpu1.icache.overall_hits::total 42757244 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 583140 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 583140 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 583140 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 583140 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 583140 # number of overall misses -system.cpu1.icache.overall_misses::total 583140 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7853505000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7853505000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7853505000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7853505000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7853505000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7853505000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 43340384 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 43340384 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 43340384 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 43340384 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 43340384 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 43340384 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013455 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.013455 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013455 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.013455 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013455 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.013455 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13467.614981 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13467.614981 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13467.614981 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13467.614981 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13467.614981 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13467.614981 # average overall miss latency +system.cpu1.icache.occ_blocks::cpu1.inst 479.066528 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.935677 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.935677 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 42755164 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 42755164 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 42755164 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 42755164 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 42755164 # number of overall hits +system.cpu1.icache.overall_hits::total 42755164 # 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number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 124862 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 124862 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 15854421 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 15854421 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 15854421 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 15854421 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027062 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.027062 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027390 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.027390 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.104844 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.104844 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.083284 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.083284 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027196 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.027196 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027196 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.027196 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12947.052270 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12947.052270 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31725.458426 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 31725.458426 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8839.873273 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8839.873273 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 6059.044139 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 6059.044139 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20701.525110 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20701.525110 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20701.525110 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20701.525110 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1045,66 +1045,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 366483 # number of writebacks -system.cpu1.dcache.writebacks::total 366483 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 253200 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 253200 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 178129 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 178129 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13100 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13100 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10399 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10399 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 431329 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 431329 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 431329 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 431329 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2771848500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2771848500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5304406500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5304406500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89559000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89559000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 42226500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 42226500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.writebacks::writebacks 366504 # number of writebacks +system.cpu1.dcache.writebacks::total 366504 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 253127 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 253127 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 178055 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 178055 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13099 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13099 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10394 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10394 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 431182 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 431182 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 431182 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 431182 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2770994500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2770994500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5292766500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5292766500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89595500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89595500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 42224000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 42224000 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2000 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8076255000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 8076255000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8076255000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 8076255000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 170163530000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 170163530000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40377042500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40377042500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 210540572500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 210540572500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027065 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.027065 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027397 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027397 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.104839 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.104839 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.083274 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.083274 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027201 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027201 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027201 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.027201 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10947.268957 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10947.268957 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29778.455501 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 29778.455501 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6836.564885 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6836.564885 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4060.630830 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4060.630830 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8063761000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 8063761000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8063761000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 8063761000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 170066366500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 170066366500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40314514000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40314514000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 210380880500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 210380880500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027062 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.027062 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027390 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027390 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.104844 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.104844 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.083244 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.083244 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027196 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027196 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027196 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.027196 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10947.052270 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10947.052270 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29725.458426 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 29725.458426 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6839.873273 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6839.873273 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4062.343660 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4062.343660 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18724.117785 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18724.117785 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18724.117785 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18724.117785 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18701.525110 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18701.525110 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18701.525110 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18701.525110 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1126,10 +1126,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 567076826640 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 567076826640 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 567076826640 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 567076826640 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 522347967555 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 522347967555 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 522347967555 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 522347967555 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |