diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini | 255 |
1 files changed, 250 insertions, 5 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index 267723514..35aadccd5 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -12,11 +12,12 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=134217728 -boot_loader=/dist/m5/system/binaries/boot_emm.arm +boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb +default_p_state=UNDEFINED +dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -29,7 +30,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -41,10 +42,14 @@ mmap_using_noreserve=false multi_proc=true multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh +power_model=Null +readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh reset_addr_64=0 symbolfile= thermal_components= @@ -61,8 +66,13 @@ system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain +default_p_state=UNDEFINED delay=50000 eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 @@ -89,7 +99,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/m5/system/disks/linux-aarch32-ael.img +image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -107,6 +117,7 @@ branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -124,6 +135,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -142,12 +157,17 @@ addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -166,8 +186,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -190,9 +215,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker [system.cpu.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.dtb] @@ -206,9 +236,14 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[3] @@ -219,12 +254,17 @@ addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -243,8 +283,13 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -302,9 +347,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker [system.cpu.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.itb] @@ -318,9 +368,14 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[2] @@ -331,12 +386,17 @@ addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -355,8 +415,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=4194304 @@ -364,10 +429,15 @@ size=4194304 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 @@ -412,9 +482,14 @@ sys=system [system.iobus] type=NoncoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=1 frontend_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null response_latency=2 use_default_range=false width=16 @@ -428,12 +503,17 @@ addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=50 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=50 @@ -452,8 +532,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=50 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1024 @@ -461,10 +546,15 @@ size=1024 type=CoherentXBar children=badaddr_responder clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=true +power_model=Null response_latency=2 snoop_filter=Null snoop_response_latency=4 @@ -478,11 +568,16 @@ slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side s [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=0 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -527,6 +622,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -538,7 +634,11 @@ max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 page_policy=open_adaptive +power_model=Null range=2147483648:2415919103 ranks_per_channel=2 read_buffer_size=32 @@ -581,10 +681,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470024192 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[18] @@ -665,14 +770,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 +default_p_state=UNDEFINED disks= eventq_index=0 host=system.realview.pci_host io_shift=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[2] pio=system.iobus.master[9] @@ -681,13 +791,18 @@ pio=system.iobus.master[9] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=46 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471793664 pio_latency=10000 pixel_clock=41667 +power_model=Null system=system vnc=system.vncserver dma=system.iobus.slave[1] @@ -768,10 +883,15 @@ voltage_domain=system.voltage_domain [system.realview.energy_ctrl] type=EnergyCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED dvfs_handler=system.dvfs_handler eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470286336 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[22] @@ -851,17 +971,22 @@ SubsystemVendorID=32902 VendorID=32902 clk_domain=system.clk_domain config_latency=20000 +default_p_state=UNDEFINED eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 host=system.realview.pci_host +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 +power_model=Null rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -887,13 +1012,18 @@ type=Pl390 clk_domain=system.clk_domain cpu_addr=738205696 cpu_pio_delay=10000 +default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 gem5_extensions=true int_latency=10000 it_lines=128 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 platform=system.realview +power_model=Null system=system pio=system.membus.master[2] @@ -901,14 +1031,19 @@ pio=system.membus.master[2] type=HDLcd amba_id=1314816 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=117 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=721420288 pio_latency=10000 pixel_buffer_size=2048 pixel_chunk=32 +power_model=Null pxl_clk=system.realview.dcc.osc_pxl system=system vnc=system.vncserver @@ -994,14 +1129,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 +default_p_state=UNDEFINED disks=system.cf0 eventq_index=0 host=system.realview.pci_host io_shift=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -1010,13 +1150,18 @@ pio=system.iobus.master[23] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=44 is_mouse=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470155264 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[7] @@ -1025,13 +1170,18 @@ pio=system.iobus.master[7] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=45 is_mouse=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470220800 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[8] @@ -1039,11 +1189,16 @@ pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=739246080 pio_latency=100000 pio_size=4095 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1057,11 +1212,16 @@ pio=system.iobus.master[12] [system.realview.lan_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=436207616 pio_latency=100000 pio_size=65535 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1075,12 +1235,17 @@ pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=738721792 pio_latency=100000 +power_model=Null system=system pio=system.membus.master[4] @@ -1148,10 +1313,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470089728 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[21] @@ -1160,11 +1330,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:67108863 port=system.membus.master[1] @@ -1174,21 +1349,31 @@ clk_domain=system.clk_domain conf_base=805306368 conf_device_bits=16 conf_size=268435456 +default_p_state=UNDEFINED eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_dma_base=0 pci_mem_base=0 pci_pio_base=0 platform=system.realview +power_model=Null system=system pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 idreg=35979264 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469827584 pio_latency=100000 +power_model=Null proc_id0=335544320 proc_id1=335544320 system=system @@ -1198,12 +1383,17 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=36 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471269376 pio_latency=100000 +power_model=Null system=system time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[10] @@ -1212,10 +1402,15 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469893120 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[16] @@ -1225,12 +1420,17 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=34 int_num1=34 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470876160 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[3] @@ -1240,26 +1440,36 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=35 int_num1=35 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470941696 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[4] [system.realview.uart] type=Pl011 clk_domain=system.clk_domain +default_p_state=UNDEFINED end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=37 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470351872 pio_latency=100000 platform=system.realview +power_model=Null system=system terminal=system.terminal pio=system.iobus.master[0] @@ -1268,10 +1478,15 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470417408 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[13] @@ -1279,10 +1494,15 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470482944 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[14] @@ -1290,21 +1510,31 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470548480 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[15] [system.realview.usb_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=452984832 pio_latency=100000 pio_size=131071 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1318,11 +1548,16 @@ pio=system.iobus.master[20] [system.realview.vgic] type=VGic clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic hv_addr=738213888 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_delay=10000 platform=system.realview +power_model=Null ppint=25 system=system vcpu_addr=738222080 @@ -1333,11 +1568,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=402653184:436207615 port=system.iobus.master[11] @@ -1345,10 +1585,15 @@ port=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470745088 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[17] |