diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt | 286 |
1 files changed, 143 insertions, 143 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index f83b43588..c670f647a 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -4,13 +4,13 @@ sim_seconds 2.902619 # Nu sim_ticks 2902619131000 # Number of ticks simulated final_tick 2902619131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 744858 # Simulator instruction rate (inst/s) -host_op_rate 898074 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 19216925045 # Simulator tick rate (ticks/s) -host_mem_usage 553548 # Number of bytes of host memory used -host_seconds 151.05 # Real time elapsed on the host -sim_insts 112506996 # Number of instructions simulated -sim_ops 135649573 # Number of ops (including micro ops) simulated +host_inst_rate 756630 # Simulator instruction rate (inst/s) +host_op_rate 912268 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19520630002 # Simulator tick rate (ticks/s) +host_mem_usage 553652 # Number of bytes of host memory used +host_seconds 148.70 # Real time elapsed on the host +sim_insts 112506995 # Number of instructions simulated +sim_ops 135649572 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory @@ -100,7 +100,7 @@ system.physmem.perBankWrBursts::14 7284 # Pe system.physmem.perBankWrBursts::15 7101 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 2902618699500 # Total gap between requests +system.physmem.totGap 2902618754500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) @@ -211,20 +211,20 @@ system.physmem.wrQLenPdf::60 13 # Wh system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 58554 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 313.684599 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 183.647731 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.576547 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21465 36.66% 36.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14645 25.01% 61.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5517 9.42% 71.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 58557 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 313.668528 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.635625 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 334.571119 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21469 36.66% 36.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14643 25.01% 61.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5518 9.42% 71.09% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 3471 5.93% 77.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2275 3.89% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2279 3.89% 80.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 1576 2.69% 83.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1002 1.71% 85.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1065 1.82% 87.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7538 12.87% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 58554 # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 998 1.70% 85.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1064 1.82% 87.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7539 12.87% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 58557 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 5863 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 28.669452 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::stdev 558.899894 # Reads before turning the bus around for writes @@ -268,12 +268,12 @@ system.physmem.wrPerTurnAround::140-143 1 0.02% 99.97% # Wr system.physmem.wrPerTurnAround::164-167 1 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::176-179 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5863 # Writes before turning the bus around for reads -system.physmem.totQLat 1491787750 # Total ticks spent queuing -system.physmem.totMemAccLat 4643569000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1492072500 # Total ticks spent queuing +system.physmem.totMemAccLat 4643853750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 840475000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8874.67 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8876.36 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27624.67 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27626.36 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.71 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.62 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s @@ -284,49 +284,49 @@ system.physmem.busUtilRead 0.03 # Da system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 27.72 # Average write queue length when enqueuing -system.physmem.readRowHits 138438 # Number of row buffer hits during reads +system.physmem.readRowHits 138435 # Number of row buffer hits during reads system.physmem.writeRowHits 90000 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.36 # Row buffer hit rate for reads system.physmem.writeRowHitRate 75.68 # Row buffer hit rate for writes -system.physmem.avgGap 9972509.98 # Average gap between requests +system.physmem.avgGap 9972510.17 # Average gap between requests system.physmem.pageHitRate 79.59 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2755208941000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2755208852500 # Time in different power states system.physmem.memoryStateTime::REF 96924620000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 50485479500 # Time in different power states +system.physmem.memoryStateTime::ACT 50485568000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 226724400 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 215943840 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 123708750 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 117826500 # Energy for precharge commands per rank (pJ) +system.physmem.actEnergy::0 226739520 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 215951400 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 123717000 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 117830625 # Energy for precharge commands per rank (pJ) system.physmem.readEnergy::0 698794200 # Energy for read commands per rank (pJ) system.physmem.readEnergy::1 612339000 # Energy for read commands per rank (pJ) system.physmem.writeEnergy::0 389791440 # Energy for write commands per rank (pJ) system.physmem.writeEnergy::1 380667600 # Energy for write commands per rank (pJ) system.physmem.refreshEnergy::0 189584556720 # Energy for refresh commands per rank (pJ) system.physmem.refreshEnergy::1 189584556720 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 86731413750 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 85564066005 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1665487627500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1666511616750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1943242616760 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1942987016415 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.480430 # Core power per rank (mW) -system.physmem.averagePower::1 669.392372 # Core power per rank (mW) -system.realview.nvmem.bytes_read::cpu.inst 24 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 24 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 24 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 24 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 6 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 70650 # Transaction distribution -system.membus.trans_dist::ReadResp 70650 # Transaction distribution +system.physmem.actBackEnergy::0 86731424865 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 85566193245 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1665487617750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1666509750750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1943242641495 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1942987289340 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.480439 # Core power per rank (mW) +system.physmem.averagePower::1 669.392466 # Core power per rank (mW) +system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 70649 # Transaction distribution +system.membus.trans_dist::ReadResp 70649 # Transaction distribution system.membus.trans_dist::WriteReq 27618 # Transaction distribution system.membus.trans_dist::WriteResp 27618 # Transaction distribution system.membus.trans_dist::Writeback 82180 # Transaction distribution @@ -338,21 +338,21 @@ system.membus.trans_dist::UpgradeResp 4505 # Tr system.membus.trans_dist::ReadExReq 128451 # Transaction distribution system.membus.trans_dist::ReadExResp 128451 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 12 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 436476 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 544160 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 544158 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 616857 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 616855 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 24 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15471548 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15635013 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15635009 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17954309 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17954305 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 219 # Total snoops (count) system.membus.snoop_fanout::samples 281834 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram @@ -367,13 +367,13 @@ system.membus.snoop_fanout::max_value 1 # Re system.membus.snoop_fanout::total 281834 # Request fanout histogram system.membus.reqLayer0.occupancy 86774000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 6000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 1752500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer5.occupancy 1264018000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1594856745 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1594857995 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) system.membus.respLayer3.occupancy 38339991 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) @@ -604,20 +604,20 @@ system.cpu.itb.accesses 115610659 # DT system.cpu.numCycles 5805238262 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112506996 # Number of instructions committed -system.cpu.committedOps 135649573 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 119948924 # Number of integer alu accesses +system.cpu.committedInsts 112506995 # Number of instructions committed +system.cpu.committedOps 135649572 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 119948923 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses system.cpu.num_func_calls 9898964 # number of times a function call or return occured system.cpu.num_conditional_control_insts 15236398 # number of instructions that are conditional controls -system.cpu.num_int_insts 119948924 # number of integer instructions +system.cpu.num_int_insts 119948923 # number of integer instructions system.cpu.num_fp_insts 11161 # number of float instructions -system.cpu.num_int_register_reads 218165442 # number of times the integer registers were read -system.cpu.num_int_register_writes 82686636 # number of times the integer registers were written +system.cpu.num_int_register_reads 218165441 # number of times the integer registers were read +system.cpu.num_int_register_writes 82686635 # number of times the integer registers were written system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 489970612 # number of times the CC registers were read -system.cpu.num_cc_register_writes 51914328 # number of times the CC registers were written +system.cpu.num_cc_register_reads 489970609 # number of times the CC registers were read +system.cpu.num_cc_register_writes 51914327 # number of times the CC registers were written system.cpu.num_mem_refs 45428231 # number of memory refs system.cpu.num_load_insts 24855392 # Number of load instructions system.cpu.num_store_insts 20572839 # Number of store instructions @@ -627,7 +627,7 @@ system.cpu.not_idle_fraction 0.072139 # Pe system.cpu.idle_fraction 0.927861 # Percentage of idle cycles system.cpu.Branches 25929456 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 93218055 67.17% 67.18% # Class of executed instruction +system.cpu.op_class::IntAlu 93218054 67.17% 67.18% # Class of executed instruction system.cpu.op_class::IntMult 114528 0.08% 67.26% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction @@ -660,7 +660,7 @@ system.cpu.op_class::MemRead 24855392 17.91% 85.18% # Cl system.cpu.op_class::MemWrite 20572839 14.82% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 138771626 # Class of executed instruction +system.cpu.op_class::total 138771625 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3032 # number of quiesce instructions executed system.cpu.icache.tags.replacements 1699818 # number of replacements @@ -736,10 +736,10 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19835992000 system.cpu.icache.demand_mshr_miss_latency::total 19835992000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19835992000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 19835992000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 598490500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 598490500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 598490500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 598490500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 597905000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 597905000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 597905000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 597905000 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014708 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014708 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014708 # mshr miss rate for demand accesses @@ -837,18 +837,18 @@ system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 467980 system.cpu.l2cache.UpgradeReq_miss_latency::total 467980 # number of UpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 46998 # number of SCUpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::total 46998 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8982693466 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8982693466 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8982758466 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8982758466 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 567750 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 149500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 1312883000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9901382466 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 11214982716 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9901447466 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 11215047716 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 567750 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 149500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 1312883000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9901382466 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 11214982716 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9901447466 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 11215047716 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7104 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3702 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 1700312 # number of ReadReq accesses(hits+misses) @@ -902,18 +902,18 @@ system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 172.114748 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 172.114748 # average UpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 23499 # average SCUpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 23499 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68972.960157 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68972.960157 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68973.459254 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68973.459254 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 81107.142857 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72780.253894 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69519.487074 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69886.602914 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69519.943451 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69887.007964 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 81107.142857 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72780.253894 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69519.487074 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69886.602914 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69519.943451 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69887.007964 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -954,26 +954,26 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27220719 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27220719 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7352957534 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7352957534 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7353022534 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7353022534 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 480750 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1087047500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8119492534 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9207145784 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8119557534 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9207210784 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 480750 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1087047500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8119492534 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9207145784 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 474790500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5385176750 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5859967250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8119557534 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9207210784 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 474215000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5385932000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5860147000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4098166000 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4098166000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 474790500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9483342750 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9958133250 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 474215000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9484098000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9958313000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000985 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000540 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010609 # mshr miss rate for ReadReq accesses @@ -1004,18 +1004,18 @@ system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10011.297904 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10011.297904 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56459.151027 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56459.151027 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56459.650125 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56459.650125 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60260.962359 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57008.499389 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57374.688635 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57008.955767 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57375.093685 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60260.962359 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57008.499389 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57374.688635 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57008.955767 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57375.093685 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1072,16 +1072,16 @@ system.cpu.dcache.overall_misses::cpu.data 820348 # system.cpu.dcache.overall_misses::total 820348 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 5900820250 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 5900820250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11658401753 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11658401753 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11658466753 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11658466753 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 279152000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 279152000 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 53002 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 53002 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17559222003 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17559222003 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17559222003 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17559222003 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17559287003 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17559287003 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17559287003 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17559287003 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 23524552 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 23524552 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19130383 # number of WriteReq accesses(hits+misses) @@ -1112,16 +1112,16 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.019004 system.cpu.dcache.overall_miss_rate::total 0.019004 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14672.562020 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 14672.562020 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38987.919957 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38987.919957 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38988.137329 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38988.137329 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12302.322507 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12302.322507 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 26501 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26501 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25041.924268 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25041.924268 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21404.601465 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21404.601465 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25042.016967 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25042.016967 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21404.680700 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21404.680700 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 58 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked @@ -1156,24 +1156,24 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 817570 system.cpu.dcache.overall_mshr_misses::total 817570 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5083703250 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 5083703250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11002851247 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11002851247 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11002916247 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11002916247 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1411190000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1411190000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 99471250 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 99471250 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 48998 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 48998 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16086554497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16086554497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17497744497 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 17497744497 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5790648000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5790648000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16086619497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16086619497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17497809497 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 17497809497 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5791402750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5791402750 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4429678000 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4429678000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10220326000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10220326000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10221080750 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10221080750 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017069 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017069 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015631 # mshr miss rate for WriteReq accesses @@ -1190,18 +1190,18 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018940 system.cpu.dcache.overall_mshr_miss_rate::total 0.018940 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12660.515142 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12660.515142 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36795.633982 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36795.633982 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36795.851354 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36795.851354 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12061.040648 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12061.040648 # average SoftPFReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11745.335931 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11745.335931 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 24499 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24499 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22962.225539 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22962.225539 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21402.136205 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21402.136205 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22962.318321 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22962.318321 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21402.215709 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21402.215709 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1209,8 +1209,8 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2294827 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2294812 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2294826 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2294811 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27618 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27618 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 686231 # Transaction distribution @@ -1220,16 +1220,16 @@ system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # system.cpu.toL2Bus.trans_dist::UpgradeResp 2744 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 296284 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 296284 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3418694 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3418692 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2456076 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12917 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24956 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5912643 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108856060 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5912641 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108856056 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96807049 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14808 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 28416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205706333 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205706329 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 52963 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 3276134 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 5.011129 # Request fanout histogram @@ -1246,13 +1246,13 @@ system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 3276134 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2353775000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 2353774500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2564913000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2564911500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1311853505 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1311853255 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |