diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt | 190 |
1 files changed, 95 insertions, 95 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index db033150d..e1254a2d4 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -4,13 +4,13 @@ sim_seconds 2.909587 # Nu sim_ticks 2909586837500 # Number of ticks simulated final_tick 2909586837500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 581636 # Simulator instruction rate (inst/s) -host_op_rate 701272 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15048595995 # Simulator tick rate (ticks/s) -host_mem_usage 573724 # Number of bytes of host memory used -host_seconds 193.35 # Real time elapsed on the host -sim_insts 112457033 # Number of instructions simulated -sim_ops 135588117 # Number of ops (including micro ops) simulated +host_inst_rate 495886 # Simulator instruction rate (inst/s) +host_op_rate 597884 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12830006266 # Simulator tick rate (ticks/s) +host_mem_usage 573732 # Number of bytes of host memory used +host_seconds 226.78 # Real time elapsed on the host +sim_insts 112457035 # Number of instructions simulated +sim_ops 135588119 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory @@ -261,12 +261,12 @@ system.physmem.wrPerTurnAround::148-151 1 0.02% 99.89% # Wr system.physmem.wrPerTurnAround::160-163 4 0.07% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::176-179 2 0.04% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5615 # Writes before turning the bus around for reads -system.physmem.totQLat 1624802000 # Total ticks spent queuing -system.physmem.totMemAccLat 4747089500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1624800000 # Total ticks spent queuing +system.physmem.totMemAccLat 4747087500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 832610000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9757.28 # Average queueing delay per DRAM burst +system.physmem.avgQLat 9757.27 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28507.28 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28507.27 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.59 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.47 # Average system read bandwidth in MiByte/s @@ -302,14 +302,14 @@ system.physmem_1.preEnergy 116362125 # En system.physmem_1.readEnergy 596668800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 370733760 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 190039717920 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 88049301345 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1668512802000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1947898845990 # Total energy per rank (pJ) +system.physmem_1.actBackEnergy 88049300490 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1668512802750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1947898845885 # Total energy per rank (pJ) system.physmem_1.averagePower 669.477277 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2775567504000 # Time in different power states +system.physmem_1.memoryStateTime::IDLE 2775567506000 # Time in different power states system.physmem_1.memoryStateTime::REF 97157320000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 36861865500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 36861863500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -389,9 +389,9 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7382 system.cpu.dtb.walker.walkRequestOrigin::total 16928 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24520655 # DTB read hits +system.cpu.dtb.read_hits 24520656 # DTB read hits system.cpu.dtb.read_misses 8124 # DTB read misses -system.cpu.dtb.write_hits 19606816 # DTB write hits +system.cpu.dtb.write_hits 19606817 # DTB write hits system.cpu.dtb.write_misses 1422 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -402,12 +402,12 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 1650 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24528779 # DTB read accesses -system.cpu.dtb.write_accesses 19608238 # DTB write accesses +system.cpu.dtb.read_accesses 24528780 # DTB read accesses +system.cpu.dtb.write_accesses 19608239 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44127471 # DTB hits +system.cpu.dtb.hits 44127473 # DTB hits system.cpu.dtb.misses 9546 # DTB misses -system.cpu.dtb.accesses 44137017 # DTB accesses +system.cpu.dtb.accesses 44137019 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -491,19 +491,19 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed -system.cpu.committedInsts 112457033 # Number of instructions committed -system.cpu.committedOps 135588117 # Number of ops (including micro ops) committed +system.cpu.committedInsts 112457035 # Number of instructions committed +system.cpu.committedOps 135588119 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 119893391 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses system.cpu.num_func_calls 9892146 # number of times a function call or return occured system.cpu.num_conditional_control_insts 15230571 # number of instructions that are conditional controls system.cpu.num_int_insts 119893391 # number of integer instructions system.cpu.num_fp_insts 11161 # number of float instructions -system.cpu.num_int_register_reads 218063465 # number of times the integer registers were read -system.cpu.num_int_register_writes 82646448 # number of times the integer registers were written +system.cpu.num_int_register_reads 218063466 # number of times the integer registers were read +system.cpu.num_int_register_writes 82646452 # number of times the integer registers were written system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 489743456 # number of times the CC registers were read +system.cpu.num_cc_register_reads 489743459 # number of times the CC registers were read system.cpu.num_cc_register_writes 51893999 # number of times the CC registers were written system.cpu.num_mem_refs 45407924 # number of memory refs system.cpu.num_load_insts 24843119 # Number of load instructions @@ -550,9 +550,9 @@ system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class::total 138708215 # Class of executed instruction system.cpu.dcache.tags.replacements 819223 # number of replacements system.cpu.dcache.tags.tagsinuse 511.702328 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 43236235 # Total number of references to valid blocks. +system.cpu.dcache.tags.total_refs 43236237 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 819735 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 52.744161 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 52.744164 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1736147500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.702328 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999419 # Average percentage of cache occupancy @@ -563,22 +563,22 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 344 system.cpu.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 177112671 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 177112671 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23112983 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23112983 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18824226 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18824226 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 177112679 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 177112679 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23112984 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23112984 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18824227 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18824227 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 392786 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 392786 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 443250 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 443250 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 460223 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 460223 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41937209 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41937209 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42329995 # number of overall hits -system.cpu.dcache.overall_hits::total 42329995 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 41937211 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41937211 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42329997 # number of overall hits +system.cpu.dcache.overall_hits::total 42329997 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 399912 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 399912 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 298709 # number of WriteReq misses @@ -605,20 +605,20 @@ system.cpu.dcache.demand_miss_latency::cpu.data 25589348500 system.cpu.dcache.demand_miss_latency::total 25589348500 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 25589348500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 25589348500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23512895 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23512895 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19122935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19122935 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 23512896 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23512896 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19122936 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19122936 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 511167 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 511167 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466006 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 466006 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 460225 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 460225 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42635830 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42635830 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43146997 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43146997 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 42635832 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42635832 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43146999 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43146999 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017008 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.017008 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015620 # miss rate for WriteReq accesses @@ -760,12 +760,12 @@ system.cpu.icache.demand_misses::cpu.inst 1696239 # n system.cpu.icache.demand_misses::total 1696239 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1696239 # number of overall misses system.cpu.icache.overall_misses::total 1696239 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 24272134000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 24272134000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 24272134000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 24272134000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 24272134000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 24272134000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 24272132000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 24272132000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 24272132000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 24272132000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 24272132000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 24272132000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 115554258 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 115554258 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 115554258 # number of demand (read+write) accesses @@ -778,12 +778,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.014679 system.cpu.icache.demand_miss_rate::total 0.014679 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.014679 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.014679 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14309.383289 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14309.383289 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14309.383289 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14309.383289 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14309.383289 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14309.383289 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14309.382109 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14309.382109 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14309.382109 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14309.382109 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14309.382109 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14309.382109 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -802,12 +802,12 @@ system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022 system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22575895000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22575895000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22575895000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22575895000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22575895000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22575895000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22575893000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22575893000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22575893000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22575893000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22575893000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22575893000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1142541000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1142541000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1142541000 # number of overall MSHR uncacheable cycles @@ -818,12 +818,12 @@ system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014679 system.cpu.icache.demand_mshr_miss_rate::total 0.014679 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014679 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.014679 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13309.383289 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13309.383289 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13309.383289 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13309.383289 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13309.383289 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13309.383289 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13309.382109 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13309.382109 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13309.382109 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13309.382109 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13309.382109 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13309.382109 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126639.436932 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average overall mshr uncacheable latency @@ -914,20 +914,20 @@ system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 159000 system.cpu.l2cache.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16382558000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 16382558000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2351294500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 2351294500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2351292500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 2351292500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1615422500 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 1615422500 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 957500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 266000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 2351294500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 2351292500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 17997980500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20350498500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20350496500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 957500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 266000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 2351294500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 2351292500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 17997980500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20350498500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20350496500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7814 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4041 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 11855 # number of ReadReq accesses(hits+misses) @@ -987,20 +987,20 @@ system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127082.280298 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127082.280298 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130787.323395 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130787.323395 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130787.212148 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130787.212148 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132705.372546 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132705.372546 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 136785.714286 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 133000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130787.323395 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130787.212148 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 127567.444679 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 127931.820611 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 127931.808038 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 136785.714286 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 133000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130787.323395 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130787.212148 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 127567.444679 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 127931.820611 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 127931.808038 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1049,20 +1049,20 @@ system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 139000 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 139000 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15093428000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15093428000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2171514500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2171514500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2171512500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2171512500 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1493692500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1493692500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 887500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 246000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2171514500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2171512500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16587120500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18759768500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18759766500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 887500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 246000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2171514500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2171512500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16587120500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18759768500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18759766500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1029766000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5888804000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6918570000 # number of ReadReq MSHR uncacheable cycles @@ -1101,20 +1101,20 @@ system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117082.280298 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117082.280298 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120787.323395 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120787.323395 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120787.212148 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120787.212148 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122705.372546 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122705.372546 # average ReadSharedReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120787.323395 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120787.212148 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117567.444679 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 117931.820611 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 117931.808038 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120787.323395 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120787.212148 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117567.444679 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117931.820611 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117931.808038 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189119.532404 # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172275.149402 # average ReadReq mshr uncacheable latency |