diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt | 1336 |
1 files changed, 678 insertions, 658 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 563f1978d..51c016582 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,134 +1,146 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.614581 # Number of seconds simulated -sim_ticks 2614581252500 # Number of ticks simulated -final_tick 2614581252500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.614572 # Number of seconds simulated +sim_ticks 2614571564500 # Number of ticks simulated +final_tick 2614571564500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 331710 # Simulator instruction rate (inst/s) -host_op_rate 396174 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 14409825510 # Simulator tick rate (ticks/s) -host_mem_usage 433940 # Number of bytes of host memory used -host_seconds 181.44 # Real time elapsed on the host -sim_insts 60186875 # Number of instructions simulated -sim_ops 71883476 # Number of ops (including micro ops) simulated +host_inst_rate 536806 # Simulator instruction rate (inst/s) +host_op_rate 641128 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 23319189669 # Simulator tick rate (ticks/s) +host_mem_usage 459056 # Number of bytes of host memory used +host_seconds 112.12 # Real time elapsed on the host +sim_insts 60187274 # Number of instructions simulated +sim_ops 71883961 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 704520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9109080 # Number of bytes read from this memory -system.physmem.bytes_read::total 132497440 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 704520 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704520 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3720512 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 704648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9109336 # Number of bytes read from this memory +system.physmem.bytes_read::total 132497824 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 704648 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704648 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3720832 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6736584 # Number of bytes written to this memory +system.physmem.bytes_written::total 6736904 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142355 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15495006 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58133 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 17222 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142359 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15495012 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58138 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812151 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46922769 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 812156 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46922943 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 269458 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3483954 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50676352 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 269458 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 269458 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1422986 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1153558 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2576544 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1422986 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46922769 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 269508 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3484065 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50676687 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 269508 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 269508 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1423113 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1153563 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2576676 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1423113 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46922943 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 269458 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4637512 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53252896 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15495006 # Number of read requests accepted -system.physmem.writeReqs 812151 # Number of write requests accepted -system.physmem.readBursts 15495006 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 812151 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 991553920 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 126464 # Total number of bytes read from write queue -system.physmem.bytesWritten 6744512 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 132497440 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6736584 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1976 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706747 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_total::cpu.inst 269508 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4637627 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53253363 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15495012 # Number of read requests accepted +system.physmem.writeReqs 812156 # Number of write requests accepted +system.physmem.readBursts 15495012 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 812156 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 991563904 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 116864 # Total number of bytes read from write queue +system.physmem.bytesWritten 6748800 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 132497824 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6736904 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1826 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706685 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 4511 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 968147 # Per bank write bursts +system.physmem.perBankRdBursts::0 968097 # Per bank write bursts system.physmem.perBankRdBursts::1 967810 # Per bank write bursts system.physmem.perBankRdBursts::2 967673 # Per bank write bursts system.physmem.perBankRdBursts::3 967915 # Per bank write bursts -system.physmem.perBankRdBursts::4 974375 # Per bank write bursts -system.physmem.perBankRdBursts::5 968054 # Per bank write bursts +system.physmem.perBankRdBursts::4 974446 # Per bank write bursts +system.physmem.perBankRdBursts::5 968066 # Per bank write bursts system.physmem.perBankRdBursts::6 967653 # Per bank write bursts -system.physmem.perBankRdBursts::7 967480 # Per bank write bursts -system.physmem.perBankRdBursts::8 968459 # Per bank write bursts +system.physmem.perBankRdBursts::7 967482 # Per bank write bursts +system.physmem.perBankRdBursts::8 968460 # Per bank write bursts system.physmem.perBankRdBursts::9 968209 # Per bank write bursts system.physmem.perBankRdBursts::10 967967 # Per bank write bursts system.physmem.perBankRdBursts::11 967960 # Per bank write bursts -system.physmem.perBankRdBursts::12 967929 # Per bank write bursts -system.physmem.perBankRdBursts::13 967878 # Per bank write bursts +system.physmem.perBankRdBursts::12 967930 # Per bank write bursts +system.physmem.perBankRdBursts::13 967880 # Per bank write bursts system.physmem.perBankRdBursts::14 967953 # Per bank write bursts -system.physmem.perBankRdBursts::15 967568 # Per bank write bursts -system.physmem.perBankWrBursts::0 6652 # Per bank write bursts -system.physmem.perBankWrBursts::1 6388 # Per bank write bursts -system.physmem.perBankWrBursts::2 6319 # Per bank write bursts -system.physmem.perBankWrBursts::3 6364 # Per bank write bursts -system.physmem.perBankWrBursts::4 6622 # Per bank write bursts -system.physmem.perBankWrBursts::5 6858 # Per bank write bursts -system.physmem.perBankWrBursts::6 6646 # Per bank write bursts -system.physmem.perBankWrBursts::7 6573 # Per bank write bursts -system.physmem.perBankWrBursts::8 7007 # Per bank write bursts +system.physmem.perBankRdBursts::15 967685 # Per bank write bursts +system.physmem.perBankWrBursts::0 6670 # Per bank write bursts +system.physmem.perBankWrBursts::1 6386 # Per bank write bursts +system.physmem.perBankWrBursts::2 6320 # Per bank write bursts +system.physmem.perBankWrBursts::3 6360 # Per bank write bursts +system.physmem.perBankWrBursts::4 6634 # Per bank write bursts +system.physmem.perBankWrBursts::5 6864 # Per bank write bursts +system.physmem.perBankWrBursts::6 6659 # Per bank write bursts +system.physmem.perBankWrBursts::7 6574 # Per bank write bursts +system.physmem.perBankWrBursts::8 7028 # Per bank write bursts system.physmem.perBankWrBursts::9 6769 # Per bank write bursts system.physmem.perBankWrBursts::10 6571 # Per bank write bursts -system.physmem.perBankWrBursts::11 6647 # Per bank write bursts +system.physmem.perBankWrBursts::11 6645 # Per bank write bursts system.physmem.perBankWrBursts::12 6565 # Per bank write bursts -system.physmem.perBankWrBursts::13 6381 # Per bank write bursts -system.physmem.perBankWrBursts::14 6555 # Per bank write bursts -system.physmem.perBankWrBursts::15 6466 # Per bank write bursts +system.physmem.perBankWrBursts::13 6383 # Per bank write bursts +system.physmem.perBankWrBursts::14 6560 # Per bank write bursts +system.physmem.perBankWrBursts::15 6462 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2614576987500 # Total gap between requests +system.physmem.totGap 2614567301000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 6644 # Read request sizes (log2) system.physmem.readPktSize::3 15335434 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 152928 # Read request sizes (log2) +system.physmem.readPktSize::6 152934 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 58133 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1126497 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 970808 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 976433 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1092616 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 986699 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1053397 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2722203 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2628336 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3415970 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 138177 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 115073 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 106569 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 103082 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19658 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18818 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18605 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 89 # What read queue length does an incoming req see +system.physmem.writePktSize::6 58138 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1126447 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 970731 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 976234 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1093523 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 987097 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1054685 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2721121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2624601 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3412795 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 139881 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 116829 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 107818 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 104436 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19578 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18770 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18545 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 95 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -159,25 +171,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -208,45 +220,45 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1027240 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 971.825895 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 905.842120 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 203.903622 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22776 2.22% 2.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22448 2.19% 4.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8450 0.82% 5.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2555 0.25% 5.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2575 0.25% 5.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1819 0.18% 5.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8664 0.84% 6.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 942 0.09% 6.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 957011 93.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1027240 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6120 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2531.539869 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 116318.280129 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 6115 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1027284 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 971.798163 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 905.747967 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 203.998959 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22800 2.22% 2.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22532 2.19% 4.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8422 0.82% 5.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2556 0.25% 5.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2545 0.25% 5.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1785 0.17% 5.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8607 0.84% 6.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 981 0.10% 6.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 957056 93.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1027284 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6124 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2529.911822 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 116281.505657 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 6119 99.92% 99.92% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::524288-1.04858e+06 3 0.05% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6120 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6120 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.219444 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.191199 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.977796 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2386 38.99% 38.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 19 0.31% 39.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 3702 60.49% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 12 0.20% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6120 # Writes before turning the bus around for reads -system.physmem.totQLat 400457727500 # Total ticks spent queuing -system.physmem.totMemAccLat 690952040000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 77465150000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25847.61 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6124 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6124 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.219138 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.190607 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.983110 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2397 39.14% 39.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 24 0.39% 39.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 3669 59.91% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 32 0.52% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6124 # Writes before turning the bus around for reads +system.physmem.totQLat 400730693500 # Total ticks spent queuing +system.physmem.totMemAccLat 691227931000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 77465930000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25864.96 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44597.61 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 379.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44614.96 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 379.25 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.58 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 50.68 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.58 # Average system write bandwidth in MiByte/s @@ -254,74 +266,71 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 2.98 # Data bus utilization in percentage system.physmem.busUtilRead 2.96 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.67 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.38 # Average write queue length when enqueuing -system.physmem.readRowHits 14482583 # Number of row buffer hits during reads -system.physmem.writeRowHits 88590 # Number of row buffer hits during writes +system.physmem.avgRdQLen 6.80 # Average read queue length when enqueuing +system.physmem.avgWrQLen 28.13 # Average write queue length when enqueuing +system.physmem.readRowHits 14482679 # Number of row buffer hits during reads +system.physmem.writeRowHits 88673 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 84.05 # Row buffer hit rate for writes -system.physmem.avgGap 160333.10 # Average gap between requests +system.physmem.writeRowHitRate 84.07 # Row buffer hit rate for writes +system.physmem.avgGap 160332.39 # Average gap between requests system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2239817846000 # Time in different power states -system.physmem.memoryStateTime::REF 87306440000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2239359524750 # Time in different power states +system.physmem.memoryStateTime::REF 87306180000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 287452006500 # Time in different power states +system.physmem.memoryStateTime::ACT 287902801500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54170150 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16546653 # Transaction distribution -system.membus.trans_dist::ReadResp 16546653 # Transaction distribution +system.membus.trans_dist::ReadReq 16546657 # Transaction distribution +system.membus.trans_dist::ReadResp 16546657 # Transaction distribution system.membus.trans_dist::WriteReq 763381 # Transaction distribution system.membus.trans_dist::WriteResp 763381 # Transaction distribution -system.membus.trans_dist::Writeback 58133 # Transaction distribution +system.membus.trans_dist::Writeback 58138 # Transaction distribution system.membus.trans_dist::UpgradeReq 4511 # Transaction distribution system.membus.trans_dist::UpgradeResp 4511 # Transaction distribution -system.membus.trans_dist::ReadExReq 132457 # Transaction distribution -system.membus.trans_dist::ReadExResp 132457 # Transaction distribution +system.membus.trans_dist::ReadExReq 132459 # Transaction distribution +system.membus.trans_dist::ReadExResp 132459 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383082 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3840 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1894355 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4281289 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1894372 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4281306 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34952137 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390530 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7680 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16550632 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18948866 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 141632258 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 141632258 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1207280500 # Layer occupancy (ticks) +system.membus.pkt_count::total 34952154 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390530 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7680 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16551336 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18949570 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 141632962 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 215583 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 215583 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 215583 # Request fanout histogram +system.membus.reqLayer0.occupancy 1204828500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3534000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3334000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17916889500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17917176000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4952195664 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4952454428 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37921268500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 37912905250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -329,7 +338,6 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 47837076 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16518783 # Transaction distribution system.iobus.trans_dist::ReadResp 16518783 # Transaction distribution system.iobus.trans_dist::WriteReq 8182 # Transaction distribution @@ -361,34 +369,33 @@ system.iobus.pkt_count_system.bridge.master::total 2383082 system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 33053930 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15884 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1064 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2080 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390530 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 125073922 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 125073922 # Total data (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15884 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1064 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2080 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 2390530 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 125073922 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 3976000 # Layer occupancy (ticks) @@ -435,11 +442,11 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 15335424000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 15335424000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374900000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38692913500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 38695381750 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -465,9 +472,9 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 13160128 # DTB read hits +system.cpu.dtb.read_hits 13160242 # DTB read hits system.cpu.dtb.read_misses 7329 # DTB read misses -system.cpu.dtb.write_hits 11227968 # DTB write hits +system.cpu.dtb.write_hits 11228050 # DTB write hits system.cpu.dtb.write_misses 2212 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -478,12 +485,12 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 189 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 13167457 # DTB read accesses -system.cpu.dtb.write_accesses 11230180 # DTB write accesses +system.cpu.dtb.read_accesses 13167571 # DTB read accesses +system.cpu.dtb.write_accesses 11230262 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 24388096 # DTB hits +system.cpu.dtb.hits 24388292 # DTB hits system.cpu.dtb.misses 9541 # DTB misses -system.cpu.dtb.accesses 24397637 # DTB accesses +system.cpu.dtb.accesses 24397833 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -505,7 +512,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 61480692 # ITB inst hits +system.cpu.itb.inst_hits 61481095 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -522,37 +529,37 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61485163 # ITB inst accesses -system.cpu.itb.hits 61480692 # DTB hits +system.cpu.itb.inst_accesses 61485566 # ITB inst accesses +system.cpu.itb.hits 61481095 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61485163 # DTB accesses -system.cpu.numCycles 5229162505 # number of cpu cycles simulated +system.cpu.itb.accesses 61485566 # DTB accesses +system.cpu.numCycles 5229143129 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60186875 # Number of instructions committed -system.cpu.committedOps 71883476 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 64248071 # Number of integer alu accesses +system.cpu.committedInsts 60187274 # Number of instructions committed +system.cpu.committedOps 71883961 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 64248492 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2139776 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7549008 # number of instructions that are conditional controls -system.cpu.num_int_insts 64248071 # number of integer instructions +system.cpu.num_func_calls 2139801 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7549047 # number of instructions that are conditional controls +system.cpu.num_int_insts 64248492 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 116109819 # number of times the integer registers were read -system.cpu.num_int_register_writes 42862791 # number of times the integer registers were written +system.cpu.num_int_register_reads 116110622 # number of times the integer registers were read +system.cpu.num_int_register_writes 42863098 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_cc_register_reads 257767219 # number of times the CC registers were read -system.cpu.num_cc_register_writes 28995131 # number of times the CC registers were written -system.cpu.num_mem_refs 25244051 # number of memory refs -system.cpu.num_load_insts 13512687 # Number of load instructions -system.cpu.num_store_insts 11731364 # Number of store instructions -system.cpu.num_idle_cycles 4584182254.578246 # Number of idle cycles -system.cpu.num_busy_cycles 644980250.421753 # Number of busy cycles -system.cpu.not_idle_fraction 0.123343 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.876657 # Percentage of idle cycles -system.cpu.Branches 10306559 # Number of branches fetched +system.cpu.num_cc_register_reads 257769006 # number of times the CC registers were read +system.cpu.num_cc_register_writes 28995258 # number of times the CC registers were written +system.cpu.num_mem_refs 25244235 # number of memory refs +system.cpu.num_load_insts 13512788 # Number of load instructions +system.cpu.num_store_insts 11731447 # Number of store instructions +system.cpu.num_idle_cycles 4584209782.584247 # Number of idle cycles +system.cpu.num_busy_cycles 644933346.415753 # Number of busy cycles +system.cpu.not_idle_fraction 0.123334 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.876666 # Percentage of idle cycles +system.cpu.Branches 10306630 # Number of branches fetched system.cpu.op_class::No_OpClass 28518 0.04% 0.04% # Class of executed instruction -system.cpu.op_class::IntAlu 47576706 65.23% 65.27% # Class of executed instruction +system.cpu.op_class::IntAlu 47577014 65.23% 65.27% # Class of executed instruction system.cpu.op_class::IntMult 87551 0.12% 65.39% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 65.39% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 65.39% # Class of executed instruction @@ -581,20 +588,20 @@ system.cpu.op_class::SimdFloatMisc 2109 0.00% 65.39% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 65.39% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.39% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.39% # Class of executed instruction -system.cpu.op_class::MemRead 13512687 18.53% 83.92% # Class of executed instruction -system.cpu.op_class::MemWrite 11731364 16.08% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 13512788 18.53% 83.92% # Class of executed instruction +system.cpu.op_class::MemWrite 11731447 16.08% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 72938935 # Class of executed instruction +system.cpu.op_class::total 72939427 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83001 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 855859 # number of replacements -system.cpu.icache.tags.tagsinuse 510.877209 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 60624321 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 856371 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 70.792123 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 19627747250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.877209 # Average occupied blocks per requestor +system.cpu.kern.inst.quiesce 83004 # number of quiesce instructions executed +system.cpu.icache.tags.replacements 855897 # number of replacements +system.cpu.icache.tags.tagsinuse 510.877214 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 60624686 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 856409 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 70.789408 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 19623933250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.877214 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.997807 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.997807 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -603,44 +610,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 194 system.cpu.icache.tags.age_task_id_blocks_1024::2 266 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 62337063 # Number of tag accesses -system.cpu.icache.tags.data_accesses 62337063 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 60624321 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60624321 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60624321 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60624321 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60624321 # number of overall hits -system.cpu.icache.overall_hits::total 60624321 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 856371 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 856371 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 856371 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 856371 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 856371 # number of overall misses -system.cpu.icache.overall_misses::total 856371 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11763954000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11763954000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11763954000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11763954000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11763954000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11763954000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 61480692 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 61480692 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 61480692 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 61480692 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 61480692 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 61480692 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013929 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.013929 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.013929 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.013929 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.013929 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.013929 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13736.983153 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13736.983153 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13736.983153 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13736.983153 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13736.983153 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13736.983153 # average overall miss latency +system.cpu.icache.tags.tag_accesses 62337504 # Number of tag accesses +system.cpu.icache.tags.data_accesses 62337504 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 60624686 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60624686 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60624686 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60624686 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60624686 # number of overall hits +system.cpu.icache.overall_hits::total 60624686 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 856409 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 856409 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 856409 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 856409 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 856409 # number of overall misses +system.cpu.icache.overall_misses::total 856409 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11766778500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11766778500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11766778500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11766778500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11766778500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11766778500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 61481095 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61481095 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61481095 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61481095 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61481095 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 61481095 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013930 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.013930 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.013930 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.013930 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.013930 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.013930 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13739.671699 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13739.671699 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13739.671699 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13739.671699 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13739.671699 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13739.671699 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -649,186 +656,186 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856371 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 856371 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 856371 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 856371 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 856371 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 856371 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10047194000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10047194000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10047194000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10047194000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10047194000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10047194000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856409 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 856409 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 856409 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 856409 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 856409 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 856409 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10049953500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10049953500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10049953500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10049953500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10049953500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10049953500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 440846250 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 440846250 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 440846250 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 440846250 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013929 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013929 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013929 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.013929 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013929 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.013929 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11732.291262 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11732.291262 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11732.291262 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11732.291262 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11732.291262 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11732.291262 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013930 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013930 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013930 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.013930 # 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average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 62821 # number of replacements -system.cpu.l2cache.tags.tagsinuse 50750.711022 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1678966 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 128205 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 13.095948 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2564782857000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 37685.579713 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 62827 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69993.462530 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -837,92 +844,92 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 58133 # number of writebacks -system.cpu.l2cache.writebacks::total 58133 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 58138 # number of writebacks +system.cpu.l2cache.writebacks::total 58138 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5 # 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number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166664674250 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167014182000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 16705839575 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16705839575 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166662160750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167011668500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 16705919061 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16705919061 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 349507750 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183370513825 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183720021575 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183368079811 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183717587561 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000663 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000642 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012394 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026055 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016453 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991102 # 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mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012394 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229809 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.103597 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012396 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229798 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.103596 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58038.465169 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62306.914894 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60094.597235 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.381215 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.381215 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56954.786346 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56954.786346 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58237.400906 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61751.696718 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59929.865690 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.036269 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.036269 # 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average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58038.465169 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57321.777973 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57370.690455 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58237.400906 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57429.738834 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57484.890754 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -932,94 +939,94 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 625842 # number of replacements +system.cpu.dcache.tags.replacements 625894 # number of replacements system.cpu.dcache.tags.tagsinuse 511.875658 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 21786000 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 626354 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 34.782248 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 21786154 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 626406 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 34.779606 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 668864250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.875658 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999757 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999757 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 116 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 321 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 113 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 90403758 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 90403758 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 11249339 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11249339 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9965366 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9965366 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 84253 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 84253 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236457 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236457 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247663 # 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average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13711.884421 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45175.314481 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45175.314481 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13846.881413 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13846.881413 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28317.527202 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28317.527202 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23956.809401 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23956.809401 # average overall miss latency +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.543003 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.543003 # 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average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13827.913098 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28347.450827 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28347.450827 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23982.306362 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23982.306362 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 58 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -1028,70 +1035,70 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 58 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 594981 # number of writebacks -system.cpu.dcache.writebacks::total 594981 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 534 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 534 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 4836 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 4836 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 5370 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 5370 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 5370 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 5370 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 294129 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 294129 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250461 # 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number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182058544250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182058544250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26242551425 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26242551425 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208301095675 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 208301095675 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025479 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025479 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024505 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024505 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.398565 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.398565 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045251 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045251 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025022 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025022 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028159 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.028159 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11714.476471 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11714.476471 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42972.780149 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42972.780149 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16715.952857 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16715.952857 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11841.706077 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11841.706077 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26090.403311 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26090.403311 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24975.923787 # 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number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15453754489 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15453754489 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182056011250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182056011250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26242438939 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26242438939 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208298450189 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 208298450189 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025482 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025482 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024506 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024506 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.398573 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.398573 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045254 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045254 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025024 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025024 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028161 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028161 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11708.909255 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11708.909255 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43057.923596 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43057.923596 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16665.359072 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16665.359072 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11822.872056 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11822.872056 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26125.917103 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26125.917103 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25001.261066 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25001.261066 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1099,33 +1106,46 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 52981595 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2453579 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2453579 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2453657 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2453657 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763381 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763381 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 594981 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2922 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2922 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 247539 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 247539 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1724389 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5748549 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12041 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::Writeback 595027 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2921 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2921 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 247551 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 247551 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1724466 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5748697 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12042 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 26252 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7511231 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54730908 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83579878 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12460 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 30172 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 138353418 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 138353418 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 171268 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3007873000 # Layer occupancy (ticks) +system.cpu.toL2Bus.pkt_count::total 7511457 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54733404 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83586150 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 30172 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 138362190 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 18590 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2108398 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 2108398 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 2108398 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3007986500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1294746250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1294797750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2533153086 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2533255572 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) @@ -1147,10 +1167,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1760059764500 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1760059764500 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1760059764500 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1760059764500 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1760318460750 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1760318460750 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1760318460750 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1760318460750 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |