diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt | 1721 |
1 files changed, 868 insertions, 853 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 79e3a7b0a..05fb1382f 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.909343 # Number of seconds simulated -sim_ticks 2909343316500 # Number of ticks simulated -final_tick 2909343316500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.909604 # Number of seconds simulated +sim_ticks 2909603958500 # Number of ticks simulated +final_tick 2909603958500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 666869 # Simulator instruction rate (inst/s) -host_op_rate 804035 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17251437084 # Simulator tick rate (ticks/s) -host_mem_usage 624248 # Number of bytes of host memory used -host_seconds 168.64 # Real time elapsed on the host -sim_insts 112463069 # Number of instructions simulated -sim_ops 135595282 # Number of ops (including micro ops) simulated +host_inst_rate 894735 # Simulator instruction rate (inst/s) +host_op_rate 1078768 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 23149732072 # Simulator tick rate (ticks/s) +host_mem_usage 579968 # Number of bytes of host memory used +host_seconds 125.69 # Real time elapsed on the host +sim_insts 112455934 # Number of instructions simulated +sim_ops 135586369 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1184996 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8901092 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1186596 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8901732 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10087624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1184996 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1184996 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7517376 # Number of bytes written to this memory +system.physmem.bytes_read::total 10089864 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1186596 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1186596 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7512000 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7534900 # Number of bytes written to this memory +system.physmem.bytes_written::total 7529524 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 26969 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 139599 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 26994 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 139609 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166592 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117459 # Number of write requests responded to by this memory +system.physmem.num_reads::total 166627 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117375 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121840 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121756 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 407307 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3059485 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 407820 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3059431 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3467320 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 407307 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 407307 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2583874 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3467779 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 407820 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 407820 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2581795 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6023 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2589897 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2583874 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2587817 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2581795 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 407307 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3065508 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 407820 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3065454 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6057217 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166592 # Number of read requests accepted -system.physmem.writeReqs 121840 # Number of write requests accepted -system.physmem.readBursts 166592 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 121840 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10654272 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7616 # Total number of bytes read from write queue -system.physmem.bytesWritten 7547776 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10087624 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7534900 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6055597 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166627 # Number of read requests accepted +system.physmem.writeReqs 121756 # Number of write requests accepted +system.physmem.readBursts 166627 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 121756 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10656896 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7232 # Total number of bytes read from write queue +system.physmem.bytesWritten 7542080 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10089864 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7529524 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 113 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 40724 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10226 # Per bank write bursts -system.physmem.perBankRdBursts::1 9700 # Per bank write bursts -system.physmem.perBankRdBursts::2 10356 # Per bank write bursts -system.physmem.perBankRdBursts::3 10496 # Per bank write bursts -system.physmem.perBankRdBursts::4 18505 # Per bank write bursts -system.physmem.perBankRdBursts::5 10022 # Per bank write bursts -system.physmem.perBankRdBursts::6 10179 # Per bank write bursts -system.physmem.perBankRdBursts::7 10614 # Per bank write bursts -system.physmem.perBankRdBursts::8 9478 # Per bank write bursts -system.physmem.perBankRdBursts::9 10041 # Per bank write bursts -system.physmem.perBankRdBursts::10 9320 # Per bank write bursts -system.physmem.perBankRdBursts::11 9342 # Per bank write bursts -system.physmem.perBankRdBursts::12 9424 # Per bank write bursts -system.physmem.perBankRdBursts::13 10229 # Per bank write bursts -system.physmem.perBankRdBursts::14 9340 # Per bank write bursts -system.physmem.perBankRdBursts::15 9201 # Per bank write bursts -system.physmem.perBankWrBursts::0 7577 # Per bank write bursts -system.physmem.perBankWrBursts::1 7036 # Per bank write bursts -system.physmem.perBankWrBursts::2 7887 # Per bank write bursts -system.physmem.perBankWrBursts::3 8049 # Per bank write bursts -system.physmem.perBankWrBursts::4 7151 # Per bank write bursts -system.physmem.perBankWrBursts::5 7579 # Per bank write bursts -system.physmem.perBankWrBursts::6 7566 # Per bank write bursts -system.physmem.perBankWrBursts::7 7770 # Per bank write bursts -system.physmem.perBankWrBursts::8 7275 # Per bank write bursts -system.physmem.perBankWrBursts::9 7619 # Per bank write bursts -system.physmem.perBankWrBursts::10 6810 # Per bank write bursts -system.physmem.perBankWrBursts::11 7097 # Per bank write bursts -system.physmem.perBankWrBursts::12 7200 # Per bank write bursts -system.physmem.perBankWrBursts::13 7753 # Per bank write bursts -system.physmem.perBankWrBursts::14 6925 # Per bank write bursts -system.physmem.perBankWrBursts::15 6640 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 47113 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10077 # Per bank write bursts +system.physmem.perBankRdBursts::1 9979 # Per bank write bursts +system.physmem.perBankRdBursts::2 10695 # Per bank write bursts +system.physmem.perBankRdBursts::3 10661 # Per bank write bursts +system.physmem.perBankRdBursts::4 18797 # Per bank write bursts +system.physmem.perBankRdBursts::5 9659 # Per bank write bursts +system.physmem.perBankRdBursts::6 9665 # Per bank write bursts +system.physmem.perBankRdBursts::7 10488 # Per bank write bursts +system.physmem.perBankRdBursts::8 9276 # Per bank write bursts +system.physmem.perBankRdBursts::9 9973 # Per bank write bursts +system.physmem.perBankRdBursts::10 9230 # Per bank write bursts +system.physmem.perBankRdBursts::11 8679 # Per bank write bursts +system.physmem.perBankRdBursts::12 9820 # Per bank write bursts +system.physmem.perBankRdBursts::13 10379 # Per bank write bursts +system.physmem.perBankRdBursts::14 9723 # Per bank write bursts +system.physmem.perBankRdBursts::15 9413 # Per bank write bursts +system.physmem.perBankWrBursts::0 7393 # Per bank write bursts +system.physmem.perBankWrBursts::1 7263 # Per bank write bursts +system.physmem.perBankWrBursts::2 8282 # Per bank write bursts +system.physmem.perBankWrBursts::3 8171 # Per bank write bursts +system.physmem.perBankWrBursts::4 7489 # Per bank write bursts +system.physmem.perBankWrBursts::5 7265 # Per bank write bursts +system.physmem.perBankWrBursts::6 7108 # Per bank write bursts +system.physmem.perBankWrBursts::7 7662 # Per bank write bursts +system.physmem.perBankWrBursts::8 7080 # Per bank write bursts +system.physmem.perBankWrBursts::9 7523 # Per bank write bursts +system.physmem.perBankWrBursts::10 6693 # Per bank write bursts +system.physmem.perBankWrBursts::11 6470 # Per bank write bursts +system.physmem.perBankWrBursts::12 7534 # Per bank write bursts +system.physmem.perBankWrBursts::13 7859 # Per bank write bursts +system.physmem.perBankWrBursts::14 7265 # Per bank write bursts +system.physmem.perBankWrBursts::15 6788 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 3 # Number of times write queue was full causing retry -system.physmem.totGap 2909342872000 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2909603601500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 157020 # Read request sizes (log2) +system.physmem.readPktSize::6 157055 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117459 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 165675 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 528 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 258 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117375 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 165631 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 614 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 257 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -159,109 +159,116 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6014 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5882 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6822 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7989 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6661 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7824 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6630 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6026 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 12 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 58587 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 310.682984 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 183.521208 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.535953 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21321 36.39% 36.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14587 24.90% 61.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6073 10.37% 71.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3205 5.47% 77.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2612 4.46% 81.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1486 2.54% 84.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1112 1.90% 86.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1062 1.81% 87.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7129 12.17% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 58587 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5766 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.870621 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 589.954659 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5765 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 58748 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 309.779261 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 182.856223 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.388013 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21447 36.51% 36.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14643 24.93% 61.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6082 10.35% 71.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3222 5.48% 77.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2599 4.42% 81.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1493 2.54% 84.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1038 1.77% 86.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1067 1.82% 87.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7157 12.18% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 58748 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5762 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.896737 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 590.107660 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5761 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5766 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5766 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.453347 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.695263 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.074003 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4962 86.06% 86.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 90 1.56% 87.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 33 0.57% 88.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 174 3.02% 91.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 30 0.52% 91.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 151 2.62% 94.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 46 0.80% 95.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 5 0.09% 95.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 17 0.29% 95.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 15 0.26% 95.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 7 0.12% 95.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.03% 95.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 166 2.88% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.09% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 8 0.14% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 26 0.45% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 2 0.03% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.03% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 17 0.29% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 4 0.07% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5766 # Writes before turning the bus around for reads -system.physmem.totQLat 1636363750 # Total ticks spent queuing -system.physmem.totMemAccLat 4757732500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 832365000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9829.60 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5762 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5762 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.452100 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.700018 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.100411 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4964 86.15% 86.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 94 1.63% 87.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 35 0.61% 88.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 168 2.92% 91.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 22 0.38% 91.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 152 2.64% 94.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 51 0.89% 95.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 7 0.12% 95.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 11 0.19% 95.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 15 0.26% 95.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 3 0.05% 95.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 4 0.07% 95.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 174 3.02% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 7 0.12% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.05% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 18 0.31% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 4 0.07% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.03% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.02% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 15 0.26% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5762 # Writes before turning the bus around for reads +system.physmem.totQLat 1626690000 # Total ticks spent queuing +system.physmem.totMemAccLat 4748827500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 832570000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9769.09 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28579.60 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28519.09 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.59 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.47 # Average system read bandwidth in MiByte/s @@ -271,40 +278,40 @@ system.physmem.busUtil 0.05 # Da system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.26 # Average write queue length when enqueuing -system.physmem.readRowHits 136200 # Number of row buffer hits during reads -system.physmem.writeRowHits 89619 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.98 # Row buffer hit rate for writes -system.physmem.avgGap 10086754.84 # Average gap between requests -system.physmem.pageHitRate 79.39 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 229098240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 125004000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 702764400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 392785200 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 190023952560 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 90217297485 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1666466226750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1948157128635 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.621597 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2772138232000 # Time in different power states -system.physmem_0.memoryStateTime::REF 97149260000 # Time in different power states +system.physmem.avgWrQLen 26.01 # Average write queue length when enqueuing +system.physmem.readRowHits 136108 # Number of row buffer hits during reads +system.physmem.writeRowHits 89502 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.74 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.93 # Row buffer hit rate for writes +system.physmem.avgGap 10089372.82 # Average gap between requests +system.physmem.pageHitRate 79.33 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 230496840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 125767125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 702163800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 392901840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 190040735040 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 90194010705 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1666640821500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1948326896850 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.620811 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2772423900000 # Time in different power states +system.physmem_0.memoryStateTime::REF 97157840000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 40052866750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 40015565000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 213819480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 116667375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 595717200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 371427120 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 190023952560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 88066202985 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1668353151750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1947740938470 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.478544 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2775299661000 # Time in different power states -system.physmem_1.memoryStateTime::REF 97149260000 # Time in different power states +system.physmem_1.actEnergy 213638040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 116568375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 596637600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 370733760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 190040735040 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 88104913965 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1668473362500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1947916589280 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.479792 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2775503002250 # Time in different power states +system.physmem_1.memoryStateTime::REF 97157840000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 36894247500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 36942968250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -354,55 +361,56 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 9555 # Table walker walks requested -system.cpu.dtb.walker.walksShort 9555 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1270 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8285 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 9555 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 9555 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 9555 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7391 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 12962.724936 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 10716.855962 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 8397.253568 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-32767 7386 99.93% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-163839 4 0.05% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7391 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walks 9546 # Table walker walks requested +system.cpu.dtb.walker.walksShort 9546 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1255 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8291 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 9546 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 9546 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 9546 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7382 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 13188.702249 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 10926.693941 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 9189.684239 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 7377 99.93% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-163839 3 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-360447 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7382 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walksPending::samples 1638910500 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 1638910500 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total 1638910500 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6168 83.45% 83.45% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1223 16.55% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7391 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9555 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkPageSizes::4K 6174 83.64% 83.64% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1208 16.36% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7382 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9546 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9555 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7391 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9546 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7382 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7391 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 16946 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7382 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 16928 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24521784 # DTB read hits -system.cpu.dtb.read_misses 8135 # DTB read misses -system.cpu.dtb.write_hits 19607400 # DTB write hits -system.cpu.dtb.write_misses 1420 # DTB write misses +system.cpu.dtb.read_hits 24520223 # DTB read hits +system.cpu.dtb.read_misses 8124 # DTB read misses +system.cpu.dtb.write_hits 19606444 # DTB write hits +system.cpu.dtb.write_misses 1422 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 4272 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1651 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 1650 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24529919 # DTB read accesses -system.cpu.dtb.write_accesses 19608820 # DTB write accesses +system.cpu.dtb.read_accesses 24528347 # DTB read accesses +system.cpu.dtb.write_accesses 19607866 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44129184 # DTB hits -system.cpu.dtb.misses 9555 # DTB misses -system.cpu.dtb.accesses 44138739 # DTB accesses +system.cpu.dtb.hits 44126667 # DTB hits +system.cpu.dtb.misses 9546 # DTB misses +system.cpu.dtb.accesses 44136213 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -440,11 +448,11 @@ system.cpu.itb.walker.walkWaitTime::samples 4763 # system.cpu.itb.walker.walkWaitTime::0 4763 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::total 4763 # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkCompletionTime::samples 3108 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 12663.288288 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 10495.066195 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7808.701731 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-16383 2418 77.80% 77.80% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-32767 688 22.14% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 12722.007722 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 10527.196882 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7865.701982 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-16383 2410 77.54% 77.54% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-32767 696 22.39% 99.94% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.06% 100.00% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::total 3108 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walksPending::samples 1638383000 # Table walker pending requests distribution @@ -460,7 +468,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3108 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 3108 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 7871 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 115560644 # ITB inst hits +system.cpu.itb.inst_hits 115553087 # ITB inst hits system.cpu.itb.inst_misses 4763 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -477,38 +485,40 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 115565407 # ITB inst accesses -system.cpu.itb.hits 115560644 # DTB hits +system.cpu.itb.inst_accesses 115557850 # ITB inst accesses +system.cpu.itb.hits 115553087 # DTB hits system.cpu.itb.misses 4763 # DTB misses -system.cpu.itb.accesses 115565407 # DTB accesses -system.cpu.numCycles 5818686633 # number of cpu cycles simulated +system.cpu.itb.accesses 115557850 # DTB accesses +system.cpu.numCycles 5819207917 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112463069 # Number of instructions committed -system.cpu.committedOps 135595282 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 119900050 # Number of integer alu accesses +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed +system.cpu.committedInsts 112455934 # Number of instructions committed +system.cpu.committedOps 135586369 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 119891885 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses -system.cpu.num_func_calls 9893453 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15231190 # number of instructions that are conditional controls -system.cpu.num_int_insts 119900050 # number of integer instructions +system.cpu.num_func_calls 9891908 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 15230427 # number of instructions that are conditional controls +system.cpu.num_int_insts 119891885 # number of integer instructions system.cpu.num_fp_insts 11161 # number of float instructions -system.cpu.num_int_register_reads 218076436 # number of times the integer registers were read -system.cpu.num_int_register_writes 82650791 # number of times the integer registers were written +system.cpu.num_int_register_reads 218060317 # number of times the integer registers were read +system.cpu.num_int_register_writes 82644878 # number of times the integer registers were written system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 489768723 # number of times the CC registers were read -system.cpu.num_cc_register_writes 51897400 # number of times the CC registers were written -system.cpu.num_mem_refs 45409486 # number of memory refs -system.cpu.num_load_insts 24844046 # Number of load instructions -system.cpu.num_store_insts 20565440 # Number of store instructions -system.cpu.num_idle_cycles 5379802959.980151 # Number of idle cycles -system.cpu.num_busy_cycles 438883673.019849 # Number of busy cycles -system.cpu.not_idle_fraction 0.075427 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.924573 # Percentage of idle cycles -system.cpu.Branches 25918657 # Number of branches fetched +system.cpu.num_cc_register_reads 489736143 # number of times the CC registers were read +system.cpu.num_cc_register_writes 51894204 # number of times the CC registers were written +system.cpu.num_mem_refs 45406948 # number of memory refs +system.cpu.num_load_insts 24842511 # Number of load instructions +system.cpu.num_store_insts 20564437 # Number of store instructions +system.cpu.num_idle_cycles 5379072532.100152 # Number of idle cycles +system.cpu.num_busy_cycles 440135384.899849 # Number of busy cycles +system.cpu.not_idle_fraction 0.075635 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.924365 # Percentage of idle cycles +system.cpu.Branches 25916368 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 93180998 67.17% 67.18% # Class of executed instruction -system.cpu.op_class::IntMult 114440 0.08% 67.26% # Class of executed instruction +system.cpu.op_class::IntAlu 93174225 67.17% 67.18% # Class of executed instruction +system.cpu.op_class::IntMult 114427 0.08% 67.26% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction @@ -536,256 +546,254 @@ system.cpu.op_class::SimdFloatMisc 8455 0.01% 67.26% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::MemRead 24844046 17.91% 85.17% # Class of executed instruction -system.cpu.op_class::MemWrite 20565440 14.83% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 24842511 17.91% 85.17% # Class of executed instruction +system.cpu.op_class::MemWrite 20564437 14.83% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 138715716 # Class of executed instruction -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 821347 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.702129 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 43235829 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 821859 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 52.607356 # Average number of references to valid blocks. +system.cpu.op_class::total 138706392 # Class of executed instruction +system.cpu.dcache.tags.replacements 819093 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.702336 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 43235572 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 819605 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 52.751718 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1736147500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.702129 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999418 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999418 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 511.702336 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999419 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999419 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 177121649 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 177121649 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23112263 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23112263 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18824569 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18824569 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 392807 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 392807 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443229 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443229 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460200 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460200 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41936832 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41936832 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42329639 # number of overall hits -system.cpu.dcache.overall_hits::total 42329639 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 401818 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 401818 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 298972 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 298972 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 118323 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 118323 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22757 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22757 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 177109325 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 177109325 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23112645 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23112645 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18823942 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18823942 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 392782 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 392782 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443235 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443235 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460203 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460203 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41936587 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41936587 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42329369 # number of overall hits +system.cpu.dcache.overall_hits::total 42329369 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 399856 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 399856 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 298641 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 298641 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 118367 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 118367 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22751 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22751 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 700790 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 700790 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 819113 # number of overall misses -system.cpu.dcache.overall_misses::total 819113 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6512815000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6512815000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19103648000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19103648000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 294606000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 294606000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 698497 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 698497 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 816864 # number of overall misses +system.cpu.dcache.overall_misses::total 816864 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6484051000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6484051000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19116145000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19116145000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 294006500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 294006500 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 164000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 25616463000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 25616463000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 25616463000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 25616463000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23514081 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23514081 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19123541 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19123541 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 511130 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 511130 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 25600196000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 25600196000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 25600196000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 25600196000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23512501 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23512501 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19122583 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19122583 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 511149 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 511149 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465986 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 465986 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460202 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460202 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42637622 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42637622 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43148752 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43148752 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017088 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.017088 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015634 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015634 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.231493 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.231493 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048836 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048836 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460205 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460205 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 42635084 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42635084 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43146233 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43146233 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017006 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.017006 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015617 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015617 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.231570 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.231570 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048823 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048823 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.016436 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.016436 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.018983 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.018983 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16208.370456 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16208.370456 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63897.783070 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63897.783070 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12945.730984 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12945.730984 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.016383 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.016383 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.018932 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.018932 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16215.965247 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16215.965247 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64010.450675 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64010.450675 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12922.794602 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12922.794602 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36553.693689 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 36553.693689 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31273.417709 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31273.417709 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36650.402221 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 36650.402221 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31339.606103 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31339.606103 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 100 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 20 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 685107 # number of writebacks -system.cpu.dcache.writebacks::total 685107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 939 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 939 # number of ReadReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14240 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 14240 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 939 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 939 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 939 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 939 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 400879 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 400879 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298972 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 298972 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116280 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 116280 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8517 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8517 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 683726 # number of writebacks +system.cpu.dcache.writebacks::total 683726 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 924 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 924 # number of ReadReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14242 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 14242 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 924 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 924 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 924 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 924 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 398932 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 398932 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298641 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 298641 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116310 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 116310 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8509 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8509 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 699851 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 699851 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 816131 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 816131 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 697573 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 697573 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 813883 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 813883 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 31138 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 58727 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6080968000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6080968000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18804676000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 18804676000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1617499500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1617499500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 115437000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 115437000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6055510500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6055510500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18817504000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 18817504000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1617135000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1617135000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 115280000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 115280000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24885644000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 24885644000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26503143500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26503143500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5936758500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5936758500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4791465500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4791465500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10728224000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10728224000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017048 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017048 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015634 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015634 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227496 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227496 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018277 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018277 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24873014500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 24873014500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26490149500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26490149500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6279074500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6279074500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5089978000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5089978000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11369052500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11369052500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016967 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016967 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015617 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015617 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227546 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227546 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018260 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018260 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016414 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016414 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018914 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.018914 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15169.085934 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15169.085934 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62897.783070 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62897.783070 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13910.384417 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13910.384417 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13553.716097 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13553.716097 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016361 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016361 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018863 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.018863 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15179.304994 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15179.304994 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63010.450675 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63010.450675 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13903.662626 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13903.662626 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13548.007992 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13548.007992 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35558.488878 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 35558.488878 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32474.129153 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 32474.129153 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 190659.595992 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190659.595992 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173673.039980 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173673.039980 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 182679.585199 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 182679.585199 # average overall mshr uncacheable latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35656.504050 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 35656.504050 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32547.859459 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 32547.859459 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201653.108742 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201653.108742 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184493.022581 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184493.022581 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193591.576277 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193591.576277 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1696276 # number of replacements -system.cpu.icache.tags.tagsinuse 510.440576 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 113863850 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1696788 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 67.105525 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 28967481500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.440576 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996954 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996954 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1695571 # number of replacements +system.cpu.icache.tags.tagsinuse 510.436867 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 113856998 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1696083 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 67.129379 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 29070355500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.436867 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996947 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996947 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 117257438 # Number of tag accesses -system.cpu.icache.tags.data_accesses 117257438 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 113863850 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 113863850 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 113863850 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 113863850 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 113863850 # number of overall hits -system.cpu.icache.overall_hits::total 113863850 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1696794 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1696794 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1696794 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1696794 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1696794 # number of overall misses -system.cpu.icache.overall_misses::total 1696794 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 24262817500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 24262817500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 24262817500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 24262817500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 24262817500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 24262817500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 115560644 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 115560644 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 115560644 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 115560644 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 115560644 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 115560644 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014683 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014683 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014683 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014683 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014683 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014683 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14299.212220 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14299.212220 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14299.212220 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14299.212220 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14299.212220 # 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number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1105000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 193639500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 193639500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1323500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 194003000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 194003000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 139000 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 139000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15089096500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15089096500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2179028000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2179028000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1501592500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1501592500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 859000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15102053500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15102053500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2171050500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2171050500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1491782500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1491782500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1077500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 246000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2179028000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16590689000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18770822000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 859000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2171050500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16593836000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18766210000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1077500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 246000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2179028000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16590689000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18770822000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2171050500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16593836000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18766210000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1029766000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5547532500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6577298500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4474192000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4474192000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5889729000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6919495000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4772574500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4772574500 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1029766000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10021724500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11051490500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000900 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000762 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991301 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991301 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10662303500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11692069500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000895 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000759 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991676 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991676 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.434832 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.434832 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010581 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010581 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.023362 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023362 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000900 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010581 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.171658 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.062853 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000900 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010581 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.171658 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.062853 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 122714.285714 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.435700 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.435700 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010600 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010600 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.023240 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023240 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000895 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010600 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172134 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.062936 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000895 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010600 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172134 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.062936 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 153928.571429 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 123000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 122777.777778 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70800.548446 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70800.548446 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 147055.555556 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70804.014599 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70804.014599 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117148.641724 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117148.641724 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121367.271917 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121367.271917 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122269.562739 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122269.562739 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 122714.285714 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117148.281025 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117148.281025 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120754.797263 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120754.797263 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122558.535984 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122558.535984 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 153928.571429 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121367.271917 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117594.404752 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118020.597685 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 122714.285714 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120754.797263 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117615.043307 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 117971.572979 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 153928.571429 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121367.271917 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117594.404752 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118020.597685 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120754.797263 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117615.043307 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117971.572979 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 178159.563877 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163777.353088 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 162173.039980 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162173.039980 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189149.238872 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172298.182271 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172988.310559 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172988.310559 # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 170649.352087 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 163124.038731 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181557.094692 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 172579.218881 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5058225 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2539566 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38059 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 583 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 583 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5052300 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2536604 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38129 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 581 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 581 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 67216 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2289899 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 67213 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2287266 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 802569 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1801014 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2759 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 801101 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1664804 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 134612 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2763 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2761 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296213 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296213 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1696794 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 525904 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2765 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 295878 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 295878 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1696089 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 523979 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5077168 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2580972 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13250 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 25621 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7697011 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108629432 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96644509 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 16136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 31124 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205321201 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 175948 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5294343 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.018110 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.133351 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5074993 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2574186 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13257 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 25655 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7688091 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 215131128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96411485 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 16164 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 31272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 311590049 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 175874 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2773719 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.020869 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.142946 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5198460 98.19% 98.19% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 95883 1.81% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2715834 97.91% 97.91% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 57885 2.09% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5294343 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3265837500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.snoop_fanout::total 2773719 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4957066000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2554213000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2553155500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1279146500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1275758999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 9216000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 17840000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 17837000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 30177 # Transaction distribution system.iobus.trans_dist::ReadResp 30177 # Transaction distribution @@ -1235,63 +1250,63 @@ system.iobus.pkt_size_system.bridge.master::total 159125 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321056 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321056 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480181 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 46338000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 97000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 16000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 94500 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 644500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 52500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6288500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 174000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 36469500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 127000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 186318027 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 186222546 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 37000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36728000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36418 # number of replacements -system.iocache.tags.tagsinuse 1.083918 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.084136 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36434 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 313622510000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.083918 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.067745 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.067745 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 313818895000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.084136 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.067758 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.067758 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1305,14 +1320,14 @@ system.iocache.demand_misses::realview.ide 228 # system.iocache.demand_misses::total 228 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 228 # number of overall misses system.iocache.overall_misses::total 228 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28366877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28366877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4697294150 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4697294150 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28366877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28366877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28366877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28366877 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 28180377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28180377 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4715427169 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4715427169 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28180377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28180377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28180377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28180377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 228 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 228 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -1329,19 +1344,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124416.127193 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124416.127193 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129673.535501 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 129673.535501 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124416.127193 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124416.127193 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124416.127193 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124416.127193 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 123598.144737 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123598.144737 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130174.115752 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130174.115752 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 123598.144737 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 123598.144737 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 123598.144737 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 123598.144737 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 753 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 81 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.296296 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1355,14 +1370,14 @@ system.iocache.demand_mshr_misses::realview.ide 228 system.iocache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 228 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 228 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 16966877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 16966877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2886094150 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2886094150 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 16966877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 16966877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 16966877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 16966877 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16780377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16780377 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2904227169 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2904227169 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16780377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16780377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16780377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16780377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1371,68 +1386,68 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74416.127193 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 74416.127193 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79673.535501 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79673.535501 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 74416.127193 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 74416.127193 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 74416.127193 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 74416.127193 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73598.144737 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 73598.144737 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80174.115752 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80174.115752 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 73598.144737 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 73598.144737 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 73598.144737 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 73598.144737 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 40160 # Transaction distribution -system.membus.trans_dist::ReadResp 70632 # Transaction distribution +system.membus.trans_dist::ReadResp 70548 # Transaction distribution system.membus.trans_dist::WriteReq 27589 # Transaction distribution system.membus.trans_dist::WriteResp 27589 # Transaction distribution -system.membus.trans_dist::Writeback 117459 # Transaction distribution -system.membus.trans_dist::CleanEvict 6342 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4500 # Transaction distribution +system.membus.trans_dist::WritebackDirty 117375 # Transaction distribution +system.membus.trans_dist::CleanEvict 6392 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4497 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4502 # Transaction distribution -system.membus.trans_dist::ReadExReq 127038 # Transaction distribution -system.membus.trans_dist::ReadExResp 127038 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 30472 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4499 # Transaction distribution +system.membus.trans_dist::ReadExReq 127157 # Transaction distribution +system.membus.trans_dist::ReadExResp 127157 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 30388 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 438793 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 546385 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 438823 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 546415 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108894 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108894 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 655279 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 655309 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15305404 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15468757 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15302268 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15465621 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17785877 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17782741 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 492 # Total snoops (count) -system.membus.snoop_fanout::samples 390004 # Request fanout histogram +system.membus.snoop_fanout::samples 389999 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 390004 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 389999 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 390004 # Request fanout histogram -system.membus.reqLayer0.occupancy 90504500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 389999 # Request fanout histogram +system.membus.reqLayer0.occupancy 90471000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1698500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1726000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 821932659 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 823075656 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 952275997 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 952261248 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64458066 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64129261 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA |