diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing')
4 files changed, 616 insertions, 604 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index 663527e71..eecdc36d4 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -8,22 +8,23 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem -children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver +children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver atags_addr=256 -boot_loader=/projects/pd/randd/dist/binaries/boot.arm +boot_loader=/gem5/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 -clock=1 +clock=1000 dtb_filename= early_kernel_symbols=false +enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing -memories=system.physmem system.realview.nvmem -midr_regval=890224640 +mem_ranges=0:134217727 +memories=system.realview.nvmem system.physmem multi_proc=true num_work_ids=16 readfile=tests/halt.sh @@ -39,7 +40,7 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge -clock=1 +clock=1000 delay=50000 ranges=268435456:520093695 1073741824:1610612735 req_size=16 @@ -64,16 +65,15 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img +image_file=/gem5/dist/disks/linux-arm-ael.img read_only=true [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache interrupts itb tracer +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer checker=Null clock=500 cpu_id=0 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -81,6 +81,7 @@ dtb=system.cpu.dtb function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts +isa=system.cpu.isa itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -89,6 +90,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +switched_out=false system=system tracer=system.cpu.tracer workload= @@ -100,27 +102,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true -hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null -response_latency=1000 +response_latency=2 size=32768 -subblock_size=0 system=system -tgts_per_mshr=8 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.toL2Bus.slave[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -130,41 +127,53 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true -hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null -response_latency=1000 +response_latency=2 size=32768 -subblock_size=0 system=system -tgts_per_mshr=8 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.toL2Bus.slave[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -173,10 +182,42 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[2] +port=system.cpu.toL2Bus.slave[2] + +[system.cpu.l2cache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=8 +block_size=64 +clock=500 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +size=4194304 +system=system +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.toL2Bus] +type=CoherentBus +block_size=64 +clock=500 +header_cycles=1 +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -197,56 +238,24 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] type=BaseCache -addr_ranges=0:268435455 +addr_ranges=0:134217727 assoc=8 block_size=64 -clock=1 +clock=1000 forward_snoops=false -hash_delay=1 -hit_latency=50000 -is_top_level=false +hit_latency=50 +is_top_level=true max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null -response_latency=50000 +response_latency=50 size=1024 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.iobus.master[25] -mem_side=system.membus.slave[1] - -[system.l2c] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=8 -block_size=64 -clock=1 -forward_snoops=true -hash_delay=1 -hit_latency=10000 -is_top_level=false -max_miss_count=0 -mshrs=92 -prefetch_on_access=false -prefetcher=Null -prioritizeRequests=false -repl=Null -response_latency=10000 -size=4194304 -subblock_size=0 -system=system -tgts_per_mshr=16 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] [system.membus] @@ -259,11 +268,11 @@ use_default_range=false width=8 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio -slave=system.system_port system.iocache.mem_side system.l2c.mem_side +slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=0 pio_latency=100000 @@ -279,15 +288,28 @@ warn_access=warn pio=system.membus.default [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=true in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[2] @@ -302,7 +324,7 @@ system=system [system.realview.a9scu] type=A9SCU -clock=1 +clock=1000 pio_addr=520093696 pio_latency=100000 system=system @@ -311,7 +333,7 @@ pio=system.membus.master[5] [system.realview.aaci_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -358,7 +380,7 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 -clock=1 +clock=1000 config_latency=20000 ctrl_offset=2 disks=system.cf0 @@ -376,11 +398,12 @@ pio=system.iobus.master[7] [system.realview.clcd] type=Pl111 amba_id=1315089 -clock=41667 +clock=1000 gic=system.realview.gic int_num=55 pio_addr=268566528 pio_latency=10000 +pixel_clock=41667 system=system vnc=system.vncserver dma=system.iobus.slave[1] @@ -389,7 +412,7 @@ pio=system.iobus.master[4] [system.realview.dmac_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -398,7 +421,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake -clock=1 +clock=1000 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -415,7 +438,7 @@ pio=system.iobus.master[24] [system.realview.gic] type=Gic -clock=1 +clock=1000 cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 @@ -429,7 +452,7 @@ pio=system.membus.master[3] [system.realview.gpio0_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -439,7 +462,7 @@ pio=system.iobus.master[16] [system.realview.gpio1_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -449,7 +472,7 @@ pio=system.iobus.master[17] [system.realview.gpio2_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -459,7 +482,7 @@ pio=system.iobus.master[18] [system.realview.kmi0] type=Pl050 amba_id=1314896 -clock=1 +clock=1000 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -473,7 +496,7 @@ pio=system.iobus.master[5] [system.realview.kmi1] type=Pl050 amba_id=1314896 -clock=1 +clock=1000 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -486,7 +509,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -515,7 +538,7 @@ pio=system.membus.master[6] [system.realview.mmc_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -525,7 +548,7 @@ pio=system.iobus.master[22] [system.realview.nvmem] type=SimpleMemory bandwidth=73.000000 -clock=1 +clock=1000 conf_table_reported=false in_addr_map=true latency=30000 @@ -537,7 +560,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl -clock=1 +clock=1000 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -549,7 +572,7 @@ pio=system.iobus.master[1] [system.realview.rtc] type=PL031 amba_id=3412017 -clock=1 +clock=1000 gic=system.realview.gic int_delay=100000 int_num=42 @@ -562,7 +585,7 @@ pio=system.iobus.master[23] [system.realview.sci_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -572,7 +595,7 @@ pio=system.iobus.master[20] [system.realview.smc_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -582,7 +605,7 @@ pio=system.iobus.master[13] [system.realview.sp810_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -592,7 +615,7 @@ pio=system.iobus.master[14] [system.realview.ssp_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -602,7 +625,7 @@ pio=system.iobus.master[19] [system.realview.timer0] type=Sp804 amba_id=1316868 -clock=1 +clock=1000 clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -616,7 +639,7 @@ pio=system.iobus.master[2] [system.realview.timer1] type=Sp804 amba_id=1316868 -clock=1 +clock=1000 clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -629,7 +652,7 @@ pio=system.iobus.master[3] [system.realview.uart] type=Pl011 -clock=1 +clock=1000 end_on_eot=false gic=system.realview.gic int_delay=100000 @@ -644,7 +667,7 @@ pio=system.iobus.master[0] [system.realview.uart1_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -654,7 +677,7 @@ pio=system.iobus.master[10] [system.realview.uart2_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -664,7 +687,7 @@ pio=system.iobus.master[11] [system.realview.uart3_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -674,7 +697,7 @@ pio=system.iobus.master[12] [system.realview.watchdog_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -688,16 +711,6 @@ number=0 output=true port=3456 -[system.toL2Bus] -type=CoherentBus -block_size=64 -clock=1000 -header_cycles=1 -use_default_range=false -width=8 -master=system.l2c.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port - [system.vncserver] type=VncServer frame_capture=false diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr index 9a28ceb37..3ee89fc27 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr @@ -11,7 +11,6 @@ warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: LCD dual screen mode not supported -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr bpiallis' unimplemented hack: be nice to actually delete the event here diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout index 956979587..fedaf9185 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 11:19:18 -gem5 executing on u200540-lin +gem5 compiled Jan 4 2013 21:17:24 +gem5 started Jan 4 2013 23:31:27 +gem5 executing on u200540 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2629149747000 because m5_exit instruction encountered +Exiting @ tick 2603634694000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 50e9a8afa..fcb402e49 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,68 +1,80 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.603636 # Number of seconds simulated -sim_ticks 2603636076000 # Number of ticks simulated -final_tick 2603636076000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.603635 # Number of seconds simulated +sim_ticks 2603634694000 # Number of ticks simulated +final_tick 2603634694000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 264193 # Simulator instruction rate (inst/s) -host_op_rate 336182 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11426847777 # Simulator tick rate (ticks/s) -host_mem_usage 395692 # Number of bytes of host memory used -host_seconds 227.85 # Real time elapsed on the host -sim_insts 60197128 # Number of instructions simulated -sim_ops 76599899 # Number of ops (including micro ops) simulated +host_inst_rate 156094 # Simulator instruction rate (inst/s) +host_op_rate 198627 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6751306864 # Simulator tick rate (ticks/s) +host_mem_usage 397752 # Number of bytes of host memory used +host_seconds 385.65 # Real time elapsed on the host +sim_insts 60197457 # Number of instructions simulated +sim_ops 76600355 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 704800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9050128 # Number of bytes read from this memory -system.physmem.bytes_read::total 132438832 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 704800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704800 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3677504 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 705120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9050192 # Number of bytes read from this memory +system.physmem.bytes_read::total 132439216 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 705120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 705120 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3677632 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6693576 # Number of bytes written to this memory +system.physmem.bytes_written::total 6693704 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17215 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15494089 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57461 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141443 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15494095 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57463 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811479 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47120023 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 811481 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47120048 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 123 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 270698 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3475957 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50866875 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 270698 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 270698 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1412449 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 270821 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3475984 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50867050 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 270821 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 270821 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1412499 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 1158408 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2570857 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1412449 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47120023 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2570908 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1412499 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47120048 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 123 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 270698 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4634365 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53437732 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15494089 # Total number of read requests seen -system.physmem.writeReqs 811479 # Total number of write requests seen -system.physmem.cpureqs 213984 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 991621696 # Total number of bytes read from memory -system.physmem.bytesWritten 51934656 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 132438832 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6693576 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu.inst 270821 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4634392 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53437957 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15494095 # Total number of read requests seen +system.physmem.writeReqs 811481 # Total number of write requests seen +system.physmem.cpureqs 213992 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 991622080 # Total number of bytes read from memory +system.physmem.bytesWritten 51934784 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 132439216 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6693704 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 336 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 4510 # Reqs where no action is needed system.physmem.perBankRdReqs::0 968203 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 968434 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 967969 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 967930 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 967593 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 967596 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 967540 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 967550 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 967729 # Track reads on a per bank basis @@ -73,12 +85,12 @@ system.physmem.perBankRdReqs::11 968056 # Tr system.physmem.perBankRdReqs::12 968172 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 968177 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 968121 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 967789 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 967792 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 50184 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 50353 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 49939 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 49917 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50620 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50621 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 50586 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 50545 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 50763 # Track writes on a per bank basis @@ -89,17 +101,17 @@ system.physmem.perBankWrReqs::11 51005 # Tr system.physmem.perBankWrReqs::12 51208 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 51196 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 51260 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51037 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51038 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2603631716000 # Total gap between requests +system.physmem.totGap 2603630334000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6652 # Categorize read packet sizes system.physmem.readPktSize::3 15335424 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 152013 # Categorize read packet sizes +system.physmem.readPktSize::6 152019 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -108,7 +120,7 @@ system.physmem.writePktSize::2 754018 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 57461 # categorize write packet sizes +system.physmem.writePktSize::6 57463 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -120,23 +132,23 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 4510 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 15419657 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 56436 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 11795 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2249 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1058 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 797 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 575 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 386 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 213 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 132 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 117 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 85 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 73 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 46 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1119077 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 964362 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 964947 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1001106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2807161 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2816119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5525790 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 40935 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 32313 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 31944 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 31968 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 59731 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 31858 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 59202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 3664 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 3479 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 103 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -153,10 +165,10 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 35270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35279 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 35282 # What write queue length does an incoming req see @@ -169,56 +181,44 @@ system.physmem.wrQLenPdf::12 35282 # Wh system.physmem.wrQLenPdf::13 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 35281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3750171610 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 281910621610 # Sum of mem lat for all requests -system.physmem.totBusLat 61975012000 # Total cycles spent in databus access -system.physmem.totBankLat 216185438000 # Total cycles spent in bank access -system.physmem.avgQLat 242.04 # Average queueing delay per request -system.physmem.avgBankLat 13953.07 # Average bank access latency per request +system.physmem.totQLat 288491080973 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 367329340973 # Sum of mem lat for all requests +system.physmem.totBusLat 61975036000 # Total cycles spent in databus access +system.physmem.totBankLat 16863224000 # Total cycles spent in bank access +system.physmem.avgQLat 18619.82 # Average queueing delay per request +system.physmem.avgBankLat 1088.39 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 18195.12 # Average memory access latency +system.physmem.avgMemAccLat 23708.21 # Average memory access latency system.physmem.avgRdBW 380.86 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 19.95 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 50.87 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 2.51 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.11 # Average read queue length over time -system.physmem.avgWrQLen 12.38 # Average write queue length over time -system.physmem.readRowHits 15449450 # Number of row buffer hits during reads -system.physmem.writeRowHits 784611 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.71 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 96.69 # Row buffer hit rate for writes -system.physmem.avgGap 159677.46 # Average gap between requests -system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +system.physmem.avgRdQLen 0.14 # Average read queue length over time +system.physmem.avgWrQLen 12.40 # Average write queue length over time +system.physmem.readRowHits 15451886 # Number of row buffer hits during reads +system.physmem.writeRowHits 785061 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.73 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 96.74 # Row buffer hit rate for writes +system.physmem.avgGap 159677.30 # Average gap between requests system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -227,9 +227,9 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14995523 # DTB read hits -system.cpu.dtb.read_misses 7332 # DTB read misses -system.cpu.dtb.write_hits 11230789 # DTB write hits +system.cpu.dtb.read_hits 14995645 # DTB read hits +system.cpu.dtb.read_misses 7331 # DTB read misses +system.cpu.dtb.write_hits 11230857 # DTB write hits system.cpu.dtb.write_misses 2203 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -240,13 +240,13 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 184 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15002855 # DTB read accesses -system.cpu.dtb.write_accesses 11232992 # DTB write accesses +system.cpu.dtb.read_accesses 15002976 # DTB read accesses +system.cpu.dtb.write_accesses 11233060 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26226312 # DTB hits -system.cpu.dtb.misses 9535 # DTB misses -system.cpu.dtb.accesses 26235847 # DTB accesses -system.cpu.itb.inst_hits 61491068 # ITB inst hits +system.cpu.dtb.hits 26226502 # DTB hits +system.cpu.dtb.misses 9534 # DTB misses +system.cpu.dtb.accesses 26236036 # DTB accesses +system.cpu.itb.inst_hits 61491397 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -263,79 +263,79 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61495539 # ITB inst accesses -system.cpu.itb.hits 61491068 # DTB hits +system.cpu.itb.inst_accesses 61495868 # ITB inst accesses +system.cpu.itb.hits 61491397 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61495539 # DTB accesses -system.cpu.numCycles 5207272152 # number of cpu cycles simulated +system.cpu.itb.accesses 61495868 # DTB accesses +system.cpu.numCycles 5207269388 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60197128 # Number of instructions committed -system.cpu.committedOps 76599899 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68867725 # Number of integer alu accesses +system.cpu.committedInsts 60197457 # Number of instructions committed +system.cpu.committedOps 76600355 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68868122 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2139710 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7947746 # number of instructions that are conditional controls -system.cpu.num_int_insts 68867725 # number of integer instructions +system.cpu.num_func_calls 2139722 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7947784 # number of instructions that are conditional controls +system.cpu.num_int_insts 68868122 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 394752708 # number of times the integer registers were read -system.cpu.num_int_register_writes 74175592 # number of times the integer registers were written +system.cpu.num_int_register_reads 394755172 # number of times the integer registers were read +system.cpu.num_int_register_writes 74176009 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27393681 # number of memory refs -system.cpu.num_load_insts 15659530 # Number of load instructions -system.cpu.num_store_insts 11734151 # Number of store instructions -system.cpu.num_idle_cycles 4579080256.576241 # Number of idle cycles -system.cpu.num_busy_cycles 628191895.423759 # Number of busy cycles -system.cpu.not_idle_fraction 0.120637 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.879363 # Percentage of idle cycles +system.cpu.num_mem_refs 27393871 # number of memory refs +system.cpu.num_load_insts 15659652 # Number of load instructions +system.cpu.num_store_insts 11734219 # Number of store instructions +system.cpu.num_idle_cycles 4579130410.576241 # Number of idle cycles +system.cpu.num_busy_cycles 628138977.423759 # Number of busy cycles +system.cpu.not_idle_fraction 0.120627 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.879373 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 83000 # number of quiesce instructions executed -system.cpu.icache.replacements 855500 # number of replacements -system.cpu.icache.tagsinuse 510.984783 # Cycle average of tags in use -system.cpu.icache.total_refs 60635056 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 856012 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 70.834353 # Average number of references to valid blocks. +system.cpu.icache.replacements 855485 # number of replacements +system.cpu.icache.tagsinuse 510.984782 # Cycle average of tags in use +system.cpu.icache.total_refs 60635400 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 855997 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 70.835996 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 18657050000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.984783 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 510.984782 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.998017 # 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number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166694484565 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166891951116 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 9175103106 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 9175103106 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166684815565 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166882282116 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 9180297506 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 9180297506 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 197466551 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 175869587671 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 176067054222 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 175865113071 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 176062579622 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012405 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025931 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016414 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991028 # 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average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37614.027267 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33282.876758 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33582.006717 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37229.212939 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33142.491338 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33424.895128 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # 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number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10223558 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247679 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 247679 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247678 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247678 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 23787461 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23787461 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23787461 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23787461 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027188 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.027188 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024503 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.024503 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046035 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046035 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.026034 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.026034 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.026034 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.026034 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14105.130145 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14105.130145 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32117.582132 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 32117.582132 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13575.425364 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13575.425364 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 21391.364480 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 21391.364480 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21391.364480 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21391.364480 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 596029 # number of writebacks +system.cpu.dcache.writebacks::total 596029 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368781 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368781 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250510 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250510 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11402 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11402 # 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number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12008897500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12008897500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12008897500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182078406500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182078406500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 18714752000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18714752000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200793158500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 200793158500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027188 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027188 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024503 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024503 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046035 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046035 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026034 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.026034 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026034 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.026034 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12105.130145 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12105.130145 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30117.582132 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30117.582132 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11575.425364 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11575.425364 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19391.364480 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19391.364480 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19391.364480 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19391.364480 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -765,10 +765,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1052665426345 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1052665426345 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1052665426345 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1052665426345 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1130504893187 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1130504893187 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1130504893187 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1130504893187 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |