diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt | 114 |
1 files changed, 109 insertions, 5 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index b2b55eb3a..f0c87683a 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu sim_ticks 2783867165000 # Number of ticks simulated final_tick 2783867165000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1108011 # Simulator instruction rate (inst/s) -host_op_rate 1348825 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 21604583679 # Simulator tick rate (ticks/s) -host_mem_usage 560868 # Number of bytes of host memory used -host_seconds 128.86 # Real time elapsed on the host +host_inst_rate 1311458 # Simulator instruction rate (inst/s) +host_op_rate 1596489 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25571502260 # Simulator tick rate (ticks/s) +host_mem_usage 616488 # Number of bytes of host memory used +host_seconds 108.87 # Real time elapsed on the host sim_insts 142773109 # Number of instructions simulated sim_ops 173803334 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -87,6 +87,14 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -108,6 +116,24 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 5682 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 5682 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 5682 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 5682 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 5682 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3049 65.42% 65.42% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1612 34.58% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 4661 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5682 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5682 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4661 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4661 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 10343 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses system.cpu0.dtb.read_hits 15994592 # DTB read hits @@ -129,6 +155,14 @@ system.cpu0.dtb.inst_accesses 0 # IT system.cpu0.dtb.hits 27280368 # DTB hits system.cpu0.dtb.misses 5682 # DTB misses system.cpu0.dtb.accesses 27286050 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -150,6 +184,24 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.walker.walks 2611 # Table walker walks requested +system.cpu0.itb.walker.walksShort 2611 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walkWaitTime::samples 2611 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 2611 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 2611 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1374 72.85% 72.85% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 512 27.15% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 1886 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2611 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2611 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1886 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1886 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 4497 # Table walker requests started/completed, data/inst system.cpu0.itb.inst_hits 74779253 # ITB inst hits system.cpu0.itb.inst_misses 2611 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits @@ -408,6 +460,14 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -429,6 +489,24 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 6203 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 6203 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 6203 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 6203 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 6203 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walksPending::samples 1000002000 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1000002000 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1000002000 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 3703 73.18% 73.18% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 1357 26.82% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 5060 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6203 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6203 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5060 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5060 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 11263 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses system.cpu1.dtb.read_hits 15530019 # DTB read hits @@ -450,6 +528,14 @@ system.cpu1.dtb.inst_accesses 0 # IT system.cpu1.dtb.hits 27368468 # DTB hits system.cpu1.dtb.misses 6203 # DTB misses system.cpu1.dtb.accesses 27374671 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -471,6 +557,24 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.walker.walks 3040 # Table walker walks requested +system.cpu1.itb.walker.walksShort 3040 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walkWaitTime::samples 3040 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 3040 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 3040 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 1720 81.52% 81.52% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 390 18.48% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2110 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3040 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3040 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2110 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2110 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 5150 # Table walker requests started/completed, data/inst system.cpu1.itb.inst_hits 72259450 # ITB inst hits system.cpu1.itb.inst_misses 3040 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits |