diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt | 2763 |
1 files changed, 1394 insertions, 1369 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index 5b65637a2..505a1af3b 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,137 +1,137 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.903641 # Number of seconds simulated -sim_ticks 2903640922500 # Number of ticks simulated -final_tick 2903640922500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.903518 # Number of seconds simulated +sim_ticks 2903517798500 # Number of ticks simulated +final_tick 2903517798500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 541770 # Simulator instruction rate (inst/s) -host_op_rate 653210 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 13988619879 # Simulator tick rate (ticks/s) -host_mem_usage 561968 # Number of bytes of host memory used -host_seconds 207.57 # Real time elapsed on the host -sim_insts 112456119 # Number of instructions simulated -sim_ops 135587804 # Number of ops (including micro ops) simulated +host_inst_rate 707460 # Simulator instruction rate (inst/s) +host_op_rate 852978 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18263496849 # Simulator tick rate (ticks/s) +host_mem_usage 621100 # Number of bytes of host memory used +host_seconds 158.98 # Real time elapsed on the host +sim_insts 112471533 # Number of instructions simulated +sim_ops 135605825 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 582564 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 3808480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 588836 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 3938784 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 602944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5025476 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 600704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5102020 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10021000 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 582564 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 602944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1185508 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7434688 # Number of bytes written to this memory +system.physmem.bytes_read::total 10231944 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 588836 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 600704 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1189540 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7646016 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 7452212 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 3 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7663540 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 17556 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 60026 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 17654 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 62062 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 9421 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 78524 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 9386 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 79720 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165551 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116167 # Number of write requests responded to by this memory +system.physmem.num_reads::total 168847 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 119469 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120548 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 66 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 123850 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 88 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 44 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 200632 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1311622 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 202801 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1356556 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 88 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 207651 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1730750 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 206888 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1757186 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3451184 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 200632 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 207651 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 408283 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2560471 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6032 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3523982 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 202801 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 206888 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 409689 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2633363 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6033 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2566506 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2560471 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 66 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2639398 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2633363 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 88 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 200632 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1317655 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 202801 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1362589 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 88 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 207651 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1730753 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 206888 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1757188 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6017690 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165551 # Number of read requests accepted -system.physmem.writeReqs 156772 # Number of write requests accepted -system.physmem.readBursts 165551 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 156772 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10588736 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6528 # Total number of bytes read from write queue -system.physmem.bytesWritten 8522624 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10021000 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9770548 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 102 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 23601 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4489 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9899 # Per bank write bursts -system.physmem.perBankRdBursts::1 9526 # Per bank write bursts -system.physmem.perBankRdBursts::2 9759 # Per bank write bursts -system.physmem.perBankRdBursts::3 9793 # Per bank write bursts -system.physmem.perBankRdBursts::4 18999 # Per bank write bursts -system.physmem.perBankRdBursts::5 10033 # Per bank write bursts -system.physmem.perBankRdBursts::6 10462 # Per bank write bursts -system.physmem.perBankRdBursts::7 10803 # Per bank write bursts -system.physmem.perBankRdBursts::8 9925 # Per bank write bursts -system.physmem.perBankRdBursts::9 10243 # Per bank write bursts -system.physmem.perBankRdBursts::10 9858 # Per bank write bursts -system.physmem.perBankRdBursts::11 9250 # Per bank write bursts -system.physmem.perBankRdBursts::12 9247 # Per bank write bursts -system.physmem.perBankRdBursts::13 9475 # Per bank write bursts -system.physmem.perBankRdBursts::14 9028 # Per bank write bursts -system.physmem.perBankRdBursts::15 9149 # Per bank write bursts -system.physmem.perBankWrBursts::0 8258 # Per bank write bursts -system.physmem.perBankWrBursts::1 8244 # Per bank write bursts -system.physmem.perBankWrBursts::2 8572 # Per bank write bursts -system.physmem.perBankWrBursts::3 8149 # Per bank write bursts -system.physmem.perBankWrBursts::4 8563 # Per bank write bursts -system.physmem.perBankWrBursts::5 8536 # Per bank write bursts -system.physmem.perBankWrBursts::6 8718 # Per bank write bursts -system.physmem.perBankWrBursts::7 9117 # Per bank write bursts -system.physmem.perBankWrBursts::8 8657 # Per bank write bursts -system.physmem.perBankWrBursts::9 8771 # Per bank write bursts -system.physmem.perBankWrBursts::10 8610 # Per bank write bursts -system.physmem.perBankWrBursts::11 7990 # Per bank write bursts -system.physmem.perBankWrBursts::12 7949 # Per bank write bursts -system.physmem.perBankWrBursts::13 7964 # Per bank write bursts -system.physmem.perBankWrBursts::14 7531 # Per bank write bursts -system.physmem.perBankWrBursts::15 7537 # Per bank write bursts +system.physmem.bw_total::total 6163380 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 168847 # Number of read requests accepted +system.physmem.writeReqs 123850 # Number of write requests accepted +system.physmem.readBursts 168847 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 123850 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10798016 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8192 # Total number of bytes read from write queue +system.physmem.bytesWritten 7677504 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10231944 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7663540 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 128 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 40733 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10014 # Per bank write bursts +system.physmem.perBankRdBursts::1 9659 # Per bank write bursts +system.physmem.perBankRdBursts::2 10299 # Per bank write bursts +system.physmem.perBankRdBursts::3 9948 # Per bank write bursts +system.physmem.perBankRdBursts::4 18863 # Per bank write bursts +system.physmem.perBankRdBursts::5 10091 # Per bank write bursts +system.physmem.perBankRdBursts::6 10301 # Per bank write bursts +system.physmem.perBankRdBursts::7 10599 # Per bank write bursts +system.physmem.perBankRdBursts::8 9915 # Per bank write bursts +system.physmem.perBankRdBursts::9 10209 # Per bank write bursts +system.physmem.perBankRdBursts::10 9947 # Per bank write bursts +system.physmem.perBankRdBursts::11 9027 # Per bank write bursts +system.physmem.perBankRdBursts::12 9869 # Per bank write bursts +system.physmem.perBankRdBursts::13 10471 # Per bank write bursts +system.physmem.perBankRdBursts::14 9980 # Per bank write bursts +system.physmem.perBankRdBursts::15 9527 # Per bank write bursts +system.physmem.perBankWrBursts::0 7419 # Per bank write bursts +system.physmem.perBankWrBursts::1 7262 # Per bank write bursts +system.physmem.perBankWrBursts::2 8122 # Per bank write bursts +system.physmem.perBankWrBursts::3 7539 # Per bank write bursts +system.physmem.perBankWrBursts::4 7355 # Per bank write bursts +system.physmem.perBankWrBursts::5 7348 # Per bank write bursts +system.physmem.perBankWrBursts::6 7576 # Per bank write bursts +system.physmem.perBankWrBursts::7 7905 # Per bank write bursts +system.physmem.perBankWrBursts::8 7603 # Per bank write bursts +system.physmem.perBankWrBursts::9 7846 # Per bank write bursts +system.physmem.perBankWrBursts::10 7540 # Per bank write bursts +system.physmem.perBankWrBursts::11 6940 # Per bank write bursts +system.physmem.perBankWrBursts::12 7394 # Per bank write bursts +system.physmem.perBankWrBursts::13 7835 # Per bank write bursts +system.physmem.perBankWrBursts::14 7358 # Per bank write bursts +system.physmem.perBankWrBursts::15 6919 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 32 # Number of times write queue was full causing retry -system.physmem.totGap 2903640597500 # Total gap between requests +system.physmem.numWrRetry 4 # Number of times write queue was full causing retry +system.physmem.totGap 2903517476500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 155979 # Read request sizes (log2) +system.physmem.readPktSize::6 159275 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 152391 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 164623 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 542 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 272 # What read queue length does an incoming req see +system.physmem.writePktSize::6 119469 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 167922 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 537 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 248 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -161,183 +161,178 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 195 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 164 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5453 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5989 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1872 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1557 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 394 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 40 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 57876 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 330.211072 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 191.290947 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 346.940345 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 20714 35.79% 35.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14256 24.63% 60.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5208 9.00% 69.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3123 5.40% 74.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2440 4.22% 79.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1489 2.57% 81.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1071 1.85% 83.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1111 1.92% 85.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8464 14.62% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 57876 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5262 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 31.441087 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 579.786182 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5260 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::14 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2651 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6093 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6081 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 59278 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 311.674753 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 182.487125 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 333.482596 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21806 36.79% 36.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14989 25.29% 62.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5586 9.42% 71.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3267 5.51% 77.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2330 3.93% 80.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1628 2.75% 83.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1108 1.87% 85.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1064 1.79% 87.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7500 12.65% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 59278 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5882 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.683781 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 547.352228 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5880 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5262 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5262 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 25.307108 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.699141 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 47.946490 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-15 45 0.86% 0.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 4897 93.06% 93.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 79 1.50% 95.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 16 0.30% 95.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 14 0.27% 95.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 19 0.36% 96.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 31 0.59% 96.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 27 0.51% 97.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 13 0.25% 97.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 8 0.15% 97.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 3 0.06% 97.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 23 0.44% 98.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 14 0.27% 98.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 10 0.19% 98.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 3 0.06% 98.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 3 0.06% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 3 0.06% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 4 0.08% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 8 0.15% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 4 0.08% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 3 0.06% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 5 0.10% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 8 0.15% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 1 0.02% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 1 0.02% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-431 1 0.02% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::432-447 1 0.02% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::464-479 1 0.02% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 3 0.06% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 1 0.02% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 3 0.06% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 3 0.06% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::608-623 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::656-671 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::672-687 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::688-703 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::720-735 2 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5262 # Writes before turning the bus around for reads -system.physmem.totQLat 1437662314 # Total ticks spent queuing -system.physmem.totMemAccLat 4539831064 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 827245000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8689.46 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5882 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5882 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.394594 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.624984 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.894436 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 16 0.27% 0.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 8 0.14% 0.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 7 0.12% 0.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 10 0.17% 0.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4921 83.66% 84.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 66 1.12% 85.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 241 4.10% 89.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 88 1.50% 91.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 77 1.31% 92.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 178 3.03% 95.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 14 0.24% 95.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 7 0.12% 95.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 9 0.15% 95.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 13 0.22% 96.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 6 0.10% 96.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 5 0.09% 96.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 174 2.96% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.07% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.05% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 3 0.05% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.02% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.03% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.02% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.03% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.03% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 14 0.24% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 4 0.07% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::204-207 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5882 # Writes before turning the bus around for reads +system.physmem.totQLat 1493162250 # Total ticks spent queuing +system.physmem.totMemAccLat 4656643500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 843595000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8849.99 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27439.46 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.65 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.94 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.45 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.36 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 27599.99 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.72 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.64 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.64 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.50 # Average write queue length when enqueuing -system.physmem.readRowHits 136363 # Number of row buffer hits during reads -system.physmem.writeRowHits 104375 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.42 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.38 # Row buffer hit rate for writes -system.physmem.avgGap 9008480.93 # Average gap between requests -system.physmem.pageHitRate 80.62 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 229453560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 125197875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 696337200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 441657360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 189651686640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 86953063950 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1665909868500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1944007265085 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.506799 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2771232360210 # Time in different power states -system.physmem_0.memoryStateTime::REF 96958940000 # Time in different power states +system.physmem.avgWrQLen 12.20 # Average write queue length when enqueuing +system.physmem.readRowHits 138806 # Number of row buffer hits during reads +system.physmem.writeRowHits 90595 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.27 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.52 # Row buffer hit rate for writes +system.physmem.avgGap 9919874.40 # Average gap between requests +system.physmem.pageHitRate 79.47 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 229302360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 125115375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 700237200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 392208480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 189643549680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 87298782345 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1665531858750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1943921054190 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.505834 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2770598960250 # Time in different power states +system.physmem_0.memoryStateTime::REF 96954780000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 35449523540 # Time in different power states +system.physmem_0.memoryStateTime::ACT 35962503500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 208089000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 113540625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 594157200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 421258320 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 189651686640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 84877892595 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1667730194250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1943596818630 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.365444 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2774279366726 # Time in different power states -system.physmem_1.memoryStateTime::REF 96958940000 # Time in different power states +system.physmem_1.actEnergy 218839320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 119406375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 615763200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 385138800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 189643549680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 86123693430 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1666562638500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1943669029305 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.419034 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2772326743250 # Time in different power states +system.physmem_1.memoryStateTime::REF 96954780000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 32402517024 # Time in different power states +system.physmem_1.memoryStateTime::ACT 34236177250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -387,56 +382,60 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 6899 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 6899 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 2220 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 4679 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 6899 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 6899 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 6899 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 5841 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12315.228557 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 10506.489584 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 6688.963614 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 4458 76.32% 76.32% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1381 23.64% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 1 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 5841 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 937449500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 937449500 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 937449500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3645 62.40% 62.40% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 2196 37.60% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 5841 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 6899 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 6827 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 6827 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 2216 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 4610 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 1 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 6826 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 6826 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 6826 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 5786 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12342.983063 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 10713.852920 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 6703.217150 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 4631 80.04% 80.04% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1152 19.91% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 2 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::163840-180223 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 5786 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples -1209080312 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.765375 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 925400000 -76.54% -76.54% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 -2134480312 176.54% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total -1209080312 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3595 62.14% 62.14% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 2190 37.86% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 5785 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 6827 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 6899 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5841 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 6827 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5785 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5841 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 12740 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5785 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 12612 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 12462635 # DTB read hits -system.cpu0.dtb.read_misses 5988 # DTB read misses -system.cpu0.dtb.write_hits 9832923 # DTB write hits -system.cpu0.dtb.write_misses 911 # DTB write misses -system.cpu0.dtb.flush_tlb 2938 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 496 # Number of times TLB was flushed by MVA +system.cpu0.dtb.read_hits 12507441 # DTB read hits +system.cpu0.dtb.read_misses 5917 # DTB read misses +system.cpu0.dtb.write_hits 9856816 # DTB write hits +system.cpu0.dtb.write_misses 910 # DTB write misses +system.cpu0.dtb.flush_tlb 2937 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 486 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 4660 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 4603 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 940 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 884 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 240 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 12468623 # DTB read accesses -system.cpu0.dtb.write_accesses 9833834 # DTB write accesses +system.cpu0.dtb.perms_faults 232 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 12513358 # DTB read accesses +system.cpu0.dtb.write_accesses 9857726 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 22295558 # DTB hits -system.cpu0.dtb.misses 6899 # DTB misses -system.cpu0.dtb.accesses 22302457 # DTB accesses +system.cpu0.dtb.hits 22364257 # DTB hits +system.cpu0.dtb.misses 6827 # DTB misses +system.cpu0.dtb.accesses 22371084 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -466,456 +465,457 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 3577 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3577 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 835 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2742 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3577 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3577 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3577 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2726 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12637.197359 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 10746.267304 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 6704.748097 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 633 23.22% 23.22% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1408 51.65% 74.87% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 683 25.06% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 3521 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3521 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 830 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2691 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3521 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3521 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3521 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2670 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12834.082397 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11032.722243 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 6917.920498 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 769 28.80% 28.80% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1283 48.05% 76.85% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 616 23.07% 99.93% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2726 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 937122000 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 937122000 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 937122000 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1891 69.37% 69.37% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 835 30.63% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2726 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::total 2670 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 925066000 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 925066000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 925066000 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1840 68.91% 68.91% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 830 31.09% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2670 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3577 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3577 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3521 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3521 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2726 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2726 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6303 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 58414032 # ITB inst hits -system.cpu0.itb.inst_misses 3577 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2670 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2670 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6191 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 58595537 # ITB inst hits +system.cpu0.itb.inst_misses 3521 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 2938 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 496 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb 2937 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 486 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2760 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2691 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 58417609 # ITB inst accesses -system.cpu0.itb.hits 58414032 # DTB hits -system.cpu0.itb.misses 3577 # DTB misses -system.cpu0.itb.accesses 58417609 # DTB accesses -system.cpu0.numCycles 2904051621 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 58599058 # ITB inst accesses +system.cpu0.itb.hits 58595537 # DTB hits +system.cpu0.itb.misses 3521 # DTB misses +system.cpu0.itb.accesses 58599058 # DTB accesses +system.cpu0.numCycles 2904052506 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 56844590 # Number of instructions committed -system.cpu0.committedOps 68476862 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 60556147 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5891 # Number of float alu accesses -system.cpu0.num_func_calls 5072041 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 7664286 # number of instructions that are conditional controls -system.cpu0.num_int_insts 60556147 # number of integer instructions -system.cpu0.num_fp_insts 5891 # number of float instructions -system.cpu0.num_int_register_reads 110162183 # number of times the integer registers were read -system.cpu0.num_int_register_writes 41899351 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 4609 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1284 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 247668564 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 26017746 # number of times the CC registers were written -system.cpu0.num_mem_refs 22952183 # number of memory refs -system.cpu0.num_load_insts 12628752 # Number of load instructions -system.cpu0.num_store_insts 10323431 # Number of store instructions -system.cpu0.num_idle_cycles 2690582406.498001 # Number of idle cycles -system.cpu0.num_busy_cycles 213469214.501999 # Number of busy cycles -system.cpu0.not_idle_fraction 0.073507 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.926493 # Percentage of idle cycles -system.cpu0.Branches 13135796 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2207 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 47055843 67.15% 67.15% # Class of executed instruction -system.cpu0.op_class::IntMult 59396 0.08% 67.24% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 4431 0.01% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::MemRead 12628752 18.02% 85.27% # Class of executed instruction -system.cpu0.op_class::MemWrite 10323431 14.73% 100.00% # Class of executed instruction +system.cpu0.committedInsts 57017963 # Number of instructions committed +system.cpu0.committedOps 68702056 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 60736686 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5415 # Number of float alu accesses +system.cpu0.num_func_calls 5101109 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 7710665 # number of instructions that are conditional controls +system.cpu0.num_int_insts 60736686 # number of integer instructions +system.cpu0.num_fp_insts 5415 # number of float instructions +system.cpu0.num_int_register_reads 110496547 # number of times the integer registers were read +system.cpu0.num_int_register_writes 42022968 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4193 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1224 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 248490103 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 26091255 # number of times the CC registers were written +system.cpu0.num_mem_refs 23020484 # number of memory refs +system.cpu0.num_load_insts 12672781 # Number of load instructions +system.cpu0.num_store_insts 10347703 # Number of store instructions +system.cpu0.num_idle_cycles 2689228469.175671 # Number of idle cycles +system.cpu0.num_busy_cycles 214824036.824329 # Number of busy cycles +system.cpu0.not_idle_fraction 0.073974 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.926026 # Percentage of idle cycles +system.cpu0.Branches 13203328 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2205 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 47217639 67.16% 67.16% # Class of executed instruction +system.cpu0.op_class::IntMult 59885 0.09% 67.25% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 67.25% # 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Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1008982250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 377.484524 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 134.343284 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.737274 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.262389 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999664 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 3029 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 820099 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.829843 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 43241744 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 820611 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 52.694570 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 996611500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 401.515698 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 110.314145 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.784210 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.215457 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999668 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 373 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 177115546 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 177115546 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 11742107 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 11368313 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23110420 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 9438605 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 9386535 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18825140 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 200385 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 191808 # 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average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14862.037736 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38543.347522 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44383.456290 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 41579.460554 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12429.618327 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12336.523562 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12384.434171 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016036 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.016770 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.016398 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018564 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.019335 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.018945 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14855.663924 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14905.012606 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14880.043682 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39166.370664 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44706.658239 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 42042.831884 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12453.976341 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12347.927928 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12402.076628 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 82000 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24653.112522 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27793.101127 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 26243.863565 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 20986.894480 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23878.360021 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 22445.098968 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 57 # number of cycles access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24935.630869 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27995.591593 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 26480.222983 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21283.889208 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23994.939426 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 22649.552053 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # 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number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 18734092905 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2822172000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3011105500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5833277500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2259926000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2253271000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4513197000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5082098000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5264376500 # 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number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5907784500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2320925500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2251479500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4572405000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5224954000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5255235500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10480189500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016883 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.017138 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017008 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014948 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.016285 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015614 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224761 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.230313 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.227484 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.018543 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.018121 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018341 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000008 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016045 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016797 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.016417 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018583 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.019270 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018923 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13300.130634 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13398.710420 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13349.090780 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36876.900060 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42672.221713 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39889.729495 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12597.144817 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12611.043361 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12603.948842 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12236.533830 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12577.756654 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12394.678102 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 80500 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23082.157511 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 26209.375227 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24666.266072 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21542.085648 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24325.170689 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22945.118773 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 181268.674931 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 193354.234894 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187312.231071 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 143051.398911 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 191019.922007 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163557.186345 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 162020.531131 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 192348.149366 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 176152.180945 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016023 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016752 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016383 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018510 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.019265 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018883 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13848.742423 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13901.949866 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13875.022814 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38166.370664 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43706.658239 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41042.831884 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13128.246088 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13091.368228 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13109.936430 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12710.590586 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12988.507168 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12842.105263 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 81000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23940.059481 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27007.575306 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25488.307810 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22375.664050 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25050.026809 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23722.338878 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183023.161278 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 196696.745465 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189729.093070 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 145348.540832 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 193742.319938 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165732.900794 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 164126.087639 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 195420.031980 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 178456.067907 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1701384 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.734068 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 113852033 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1701896 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 66.897174 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 25697074250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 399.197143 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 111.536926 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.779682 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.217846 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997527 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1697906 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.737364 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 113870601 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1698418 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.045098 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 25672110500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 416.223441 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 94.513923 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.812936 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.184598 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997534 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 251 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 117255837 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 117255837 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 57557381 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 56294652 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 113852033 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 57557381 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 56294652 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 113852033 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 57557381 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 56294652 # number of overall hits -system.cpu0.icache.overall_hits::total 113852033 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 856651 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 845251 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1701902 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 856651 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 845251 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1701902 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 856651 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 845251 # number of overall misses -system.cpu0.icache.overall_misses::total 1701902 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11730914498 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 11646451999 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 23377366497 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 11730914498 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 11646451999 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 23377366497 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 11730914498 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 11646451999 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 23377366497 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 58414032 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 57139903 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 115553935 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 58414032 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 57139903 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 115553935 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 58414032 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 57139903 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 115553935 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014665 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014793 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014728 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014665 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014793 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014728 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014665 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014793 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014728 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13693.924945 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13778.690589 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13736.023870 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13693.924945 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13778.690589 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13736.023870 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13693.924945 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13778.690589 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13736.023870 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 117267449 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 117267449 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 57739156 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 56131445 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 113870601 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 57739156 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 56131445 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 113870601 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 57739156 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 56131445 # number of overall hits +system.cpu0.icache.overall_hits::total 113870601 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 856381 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 842043 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1698424 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 856381 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 842043 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1698424 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 856381 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 842043 # number of overall misses +system.cpu0.icache.overall_misses::total 1698424 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11736376500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 11602280500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 23338657000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 11736376500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 11602280500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 23338657000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 11736376500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 11602280500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 23338657000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 58595537 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 56973488 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 115569025 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 58595537 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 56973488 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 115569025 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 58595537 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 56973488 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 115569025 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014615 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014780 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014696 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014615 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014780 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014696 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014615 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014780 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014696 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13704.620373 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13778.726858 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13741.360814 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13704.620373 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13778.726858 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13741.360814 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13704.620373 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13778.726858 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13741.360814 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -924,54 +924,54 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 856651 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 845251 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1701902 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 856651 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 845251 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1701902 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 856651 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 845251 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1701902 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 856381 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 842043 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1698424 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 856381 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 842043 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1698424 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 856381 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 842043 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1698424 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10442855002 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 10375133501 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 20817988503 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10442855002 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 10375133501 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 20817988503 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10442855002 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 10375133501 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 20817988503 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 677067750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 677067750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 677067750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 677067750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014665 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014793 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014728 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014665 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014793 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014728 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014665 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014793 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014728 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12190.326051 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12274.618428 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12232.189928 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12190.326051 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12274.618428 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12232.189928 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12190.326051 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12274.618428 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12232.189928 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 75046.303480 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 75046.303480 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 75046.303480 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 75046.303480 # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10879995500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 10760237500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 21640233000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10879995500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 10760237500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 21640233000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10879995500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 10760237500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 21640233000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 676974000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 676974000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 676974000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 676974000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014615 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014780 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014696 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014615 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014780 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014696 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014615 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014780 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014696 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12704.620373 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12778.726858 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12741.360814 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12704.620373 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12778.726858 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12741.360814 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12704.620373 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12778.726858 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12741.360814 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 75035.912215 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 75035.912215 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 75035.912215 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 75035.912215 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1002,60 +1002,60 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 6646 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 6646 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 1848 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4797 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walks 6604 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 6604 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 1835 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4768 # Level at which table walker walks with short descriptors terminate system.cpu1.dtb.walker.walksSquashedBefore 1 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 6645 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 6645 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 6645 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 5540 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 12435.469314 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 10508.495094 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6654.820556 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 1371 24.75% 24.75% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2761 49.84% 74.58% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 1405 25.36% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkWaitTime::samples 6603 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 6603 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 6603 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5481 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 12293.559569 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 10651.112974 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6472.015315 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 1651 30.12% 30.12% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2769 50.52% 80.64% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 1058 19.30% 99.95% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::81920-90111 3 0.05% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 5540 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -586099820 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 2.706592 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkCompletionTime::total 5481 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -1004634564 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 1.995586 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1000233500 -170.66% -170.66% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 -1586333320 270.66% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -586099820 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3714 67.05% 67.05% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 1825 32.95% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 5539 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6646 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walksPending::0 1000200000 -99.56% -99.56% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 -2004834564 199.56% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1004634564 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 3666 66.90% 66.90% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 1814 33.10% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 5480 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6604 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6646 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5539 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6604 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5480 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5539 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 12185 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5480 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 12084 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 12057381 # DTB read hits -system.cpu1.dtb.read_misses 5757 # DTB read misses -system.cpu1.dtb.write_hits 9774636 # DTB write hits -system.cpu1.dtb.write_misses 889 # DTB write misses -system.cpu1.dtb.flush_tlb 2932 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 421 # Number of times TLB was flushed by MVA +system.cpu1.dtb.read_hits 12016469 # DTB read hits +system.cpu1.dtb.read_misses 5667 # DTB read misses +system.cpu1.dtb.write_hits 9752712 # DTB write hits +system.cpu1.dtb.write_misses 937 # DTB write misses +system.cpu1.dtb.flush_tlb 2933 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 431 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 4087 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 4084 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 1001 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 937 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 205 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12063138 # DTB read accesses -system.cpu1.dtb.write_accesses 9775525 # DTB write accesses +system.cpu1.dtb.perms_faults 213 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 12022136 # DTB read accesses +system.cpu1.dtb.write_accesses 9753649 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 21832017 # DTB hits -system.cpu1.dtb.misses 6646 # DTB misses -system.cpu1.dtb.accesses 21838663 # DTB accesses +system.cpu1.dtb.hits 21769181 # DTB hits +system.cpu1.dtb.misses 6604 # DTB misses +system.cpu1.dtb.accesses 21775785 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1085,124 +1085,124 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 3230 # Table walker walks requested -system.cpu1.itb.walker.walksShort 3230 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 673 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walks 3234 # Table walker walks requested +system.cpu1.itb.walker.walksShort 3234 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 677 # Level at which table walker walks with short descriptors terminate system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2557 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 3230 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 3230 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 3230 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 2426 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12666.941467 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 10866.952957 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 6275.492791 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::2048-4095 541 22.30% 22.30% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::10240-12287 673 27.74% 50.04% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-14335 619 25.52% 75.56% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-22527 528 21.76% 97.32% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::22528-24575 65 2.68% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 2426 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1000198000 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1000198000 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1000198000 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1753 72.26% 72.26% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 673 27.74% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 2426 # Table walker page sizes translated +system.cpu1.itb.walker.walkWaitTime::samples 3234 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 3234 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 3234 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 2430 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12793.004115 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11015.336185 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 6613.791032 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-6143 712 29.30% 29.30% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::6144-8191 1 0.04% 29.34% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::10240-12287 673 27.70% 57.04% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-14335 477 19.63% 76.67% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::14336-16383 16 0.66% 77.33% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::22528-24575 551 22.67% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 2430 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1000178000 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1000178000 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1000178000 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 1753 72.14% 72.14% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 677 27.86% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2430 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3230 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3230 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3234 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3234 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2426 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2426 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 5656 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 57139903 # ITB inst hits -system.cpu1.itb.inst_misses 3230 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2430 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2430 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 5664 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 56973488 # ITB inst hits +system.cpu1.itb.inst_misses 3234 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 2932 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 421 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb 2933 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 431 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2427 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2428 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 57143133 # ITB inst accesses -system.cpu1.itb.hits 57139903 # DTB hits -system.cpu1.itb.misses 3230 # DTB misses -system.cpu1.itb.accesses 57143133 # DTB accesses -system.cpu1.numCycles 2903230224 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 56976722 # ITB inst accesses +system.cpu1.itb.hits 56973488 # DTB hits +system.cpu1.itb.misses 3234 # DTB misses +system.cpu1.itb.accesses 56976722 # DTB accesses +system.cpu1.numCycles 2902983091 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 55611529 # Number of instructions committed -system.cpu1.committedOps 67110942 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 59336824 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5270 # Number of float alu accesses -system.cpu1.num_func_calls 4819801 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 7566653 # number of instructions that are conditional controls -system.cpu1.num_int_insts 59336824 # number of integer instructions -system.cpu1.num_fp_insts 5270 # number of float instructions -system.cpu1.num_int_register_reads 107900734 # number of times the integer registers were read -system.cpu1.num_int_register_writes 40745080 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 3840 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1432 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 242074272 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 25879956 # number of times the CC registers were written -system.cpu1.num_mem_refs 22456627 # number of memory refs -system.cpu1.num_load_insts 12214155 # Number of load instructions -system.cpu1.num_store_insts 10242472 # Number of store instructions -system.cpu1.num_idle_cycles 2696428184.778518 # Number of idle cycles -system.cpu1.num_busy_cycles 206802039.221482 # Number of busy cycles -system.cpu1.not_idle_fraction 0.071232 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.928768 # Percentage of idle cycles -system.cpu1.Branches 12781357 # Number of branches fetched -system.cpu1.op_class::No_OpClass 130 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 46119057 67.20% 67.20% # Class of executed instruction -system.cpu1.op_class::IntMult 54779 0.08% 67.28% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4036 0.01% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::MemRead 12214155 17.80% 85.08% # Class of executed instruction -system.cpu1.op_class::MemWrite 10242472 14.92% 100.00% # Class of executed instruction +system.cpu1.committedInsts 55453570 # Number of instructions committed +system.cpu1.committedOps 66903769 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 59172733 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5746 # Number of float alu accesses +system.cpu1.num_func_calls 4791563 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 7521701 # number of instructions that are conditional controls +system.cpu1.num_int_insts 59172733 # number of integer instructions +system.cpu1.num_fp_insts 5746 # number of float instructions +system.cpu1.num_int_register_reads 107592864 # number of times the integer registers were read +system.cpu1.num_int_register_writes 40634379 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4256 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1492 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 241317525 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 25809860 # number of times the CC registers were written +system.cpu1.num_mem_refs 22393766 # number of memory refs +system.cpu1.num_load_insts 12173697 # Number of load instructions +system.cpu1.num_store_insts 10220069 # Number of store instructions +system.cpu1.num_idle_cycles 2697480671.520393 # Number of idle cycles +system.cpu1.num_busy_cycles 205502419.479607 # Number of busy cycles +system.cpu1.not_idle_fraction 0.070790 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.929210 # Percentage of idle cycles +system.cpu1.Branches 12715726 # Number of branches fetched +system.cpu1.op_class::No_OpClass 132 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 45969122 67.18% 67.19% # Class of executed instruction +system.cpu1.op_class::IntMult 54656 0.08% 67.27% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 4033 0.01% 67.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::MemRead 12173697 17.79% 85.06% # Class of executed instruction +system.cpu1.op_class::MemWrite 10220069 14.94% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 68634629 # Class of executed instruction +system.cpu1.op_class::total 68421709 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iobus.trans_dist::ReadReq 30183 # Transaction distribution system.iobus.trans_dist::ReadResp 30183 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution -system.iobus.trans_dist::WriteResp 22790 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.iobus.trans_dist::WriteResp 59014 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -1293,23 +1293,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 198848287 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 187451467 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36807005 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.134606 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.079135 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 299121172000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.134606 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.070913 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.070913 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 309074032000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.079135 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.067446 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.067446 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1317,49 +1317,49 @@ system.iocache.tags.tag_accesses 328122 # Nu system.iocache.tags.data_accesses 328122 # Number of data accesses system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses system.iocache.ReadReq_misses::total 234 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses system.iocache.demand_misses::total 234 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 234 # number of overall misses system.iocache.overall_misses::total 234 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 29267377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 29267377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6633096905 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 6633096905 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 29267377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 29267377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 29267377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 29267377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 28776877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28776877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4271859590 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4271859590 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28776877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28776877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28776877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28776877 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 125074.260684 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125074.260684 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183113.320036 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 183113.320036 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 125074.260684 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125074.260684 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 125074.260684 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125074.260684 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 22198 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 122978.106838 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122978.106838 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117928.986031 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 117928.986031 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 122978.106838 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 122978.106838 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 122978.106838 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 122978.106838 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3387 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.553882 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1367,272 +1367,284 @@ system.iocache.writebacks::writebacks 36190 # nu system.iocache.writebacks::total 36190 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ide 234 # 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number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 16965377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 17076877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 17076877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2460659590 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2460659590 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 17076877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 17076877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 17076877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 17076877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # 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average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131113.044252 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131113.044252 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 72501.611111 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72501.611111 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 72501.611111 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72501.611111 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72978.106838 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72978.106838 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67928.986031 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67928.986031 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 72978.106838 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72978.106838 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 72978.106838 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72978.106838 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 86345 # number of replacements -system.l2c.tags.tagsinuse 64916.534496 # Cycle average of tags in use -system.l2c.tags.total_refs 2772933 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 151598 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 18.291356 # Average number of references to valid blocks. +system.l2c.tags.replacements 89754 # number of replacements +system.l2c.tags.tagsinuse 64926.218037 # Cycle average of tags in use +system.l2c.tags.total_refs 4554949 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 154987 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 29.389233 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 50295.187878 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.860187 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.965052 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4502.634002 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2814.628972 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.894234 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 5158.115832 # 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Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65248 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2139 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6724 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 56346 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.995605 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 26318997 # Number of tag accesses -system.l2c.tags.data_accesses 26318997 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 6505 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3514 # 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number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6217 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3258 # number of overall hits -system.l2c.overall_hits::cpu1.inst 835810 # number of overall hits -system.l2c.overall_hits::cpu1.data 334576 # number of overall hits -system.l2c.overall_hits::total 2385600 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 3 # number of ReadReq misses +system.l2c.tags.occ_percent::cpu1.inst 0.075614 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.031095 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.990695 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65227 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2130 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6959 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 56093 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.995285 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 40606108 # Number of tag accesses +system.l2c.tags.data_accesses 40606108 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 5766 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3120 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 5525 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 2899 # number of ReadReq hits +system.l2c.ReadReq_hits::total 17310 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 683625 # number of Writeback hits +system.l2c.Writeback_hits::total 683625 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 10 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 23 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 85842 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 79037 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 164879 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 847732 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 832646 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1680378 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 259316 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 253156 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 512472 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 5766 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3120 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 847732 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 345158 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 5525 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 2899 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 832646 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 332193 # number of demand (read+write) hits +system.l2c.demand_hits::total 2375039 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 5766 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3120 # number of overall hits +system.l2c.overall_hits::cpu0.inst 847732 # number of overall hits +system.l2c.overall_hits::cpu0.data 345158 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 5525 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 2899 # number of overall hits +system.l2c.overall_hits::cpu1.inst 832646 # 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number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 1261862500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 446355500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 445666000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 892021500 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 291000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 145500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 604558000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 4203774000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 365000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 657304500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 5371428000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 10837866000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 291000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 145500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 604558000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 4203774000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 365000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 657304500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 5371428000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 10837866000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 564199000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2705690000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2812868500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 6082757500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2137293500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2117838000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4255131500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 564199000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4842983500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4930706500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10337889000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000693 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000641 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000723 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.000577 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.990573 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.992642 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.991600 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.383799 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.477609 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.432582 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000461 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000569 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009970 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.148150 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000643 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011146 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.192187 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.062127 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000461 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000569 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009970 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.148150 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000643 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011146 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.192187 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.062127 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 74583.333333 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67221.929282 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 70268.112784 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67488.164738 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 70544.877827 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 68590.245697 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17807.427504 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17821.146520 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17814.355531 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 67500 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 64219.555845 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63447.661929 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 63776.377369 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 74583.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67221.929282 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64817.438245 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67488.164738 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63995.741504 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 64693.110291 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 74583.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67221.929282 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64817.438245 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67488.164738 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63995.741504 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 64693.110291 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60545.084239 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167244.026591 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 179351.891094 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 147970.993925 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 130046.334979 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178017.166836 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 150553.109372 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60545.084239 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 148509.396818 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 178776.626841 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 149022.543464 # average overall mshr uncacheable latency +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.396333 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.485711 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.442756 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.010088 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.011147 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010613 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.023104 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.023751 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.023424 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000693 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000641 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.010088 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.153298 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000723 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011147 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.195653 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.063607 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000693 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000641 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.010088 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.153298 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000723 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011147 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.195653 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.063607 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 72750 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 72750 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 91250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 80150 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20784.773060 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20791.326909 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20788.029466 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 69500 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66669.360705 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65989.175430 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 66281.796739 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 69980.090288 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70030.311102 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 70006.241331 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 72779.308658 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72360.123397 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 72569.272698 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 72750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 72750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69980.090288 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 67268.994431 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 91250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70030.311102 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66474.778476 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 67177.826952 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 72750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 72750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69980.090288 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 67268.994431 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 91250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70030.311102 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66474.778476 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 67177.826952 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62535.912215 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170523.098254 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 184196.745465 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 151463.085159 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 133848.540832 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 182242.319938 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 154232.900794 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62535.912215 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 152127.642532 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 183352.167931 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 152591.019794 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 70492 # Transaction distribution -system.membus.trans_dist::ReadResp 70492 # Transaction distribution -system.membus.trans_dist::WriteReq 27594 # Transaction distribution -system.membus.trans_dist::WriteResp 27594 # Transaction distribution -system.membus.trans_dist::Writeback 116167 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4489 # Transaction distribution +system.membus.trans_dist::ReadReq 40160 # Transaction distribution +system.membus.trans_dist::ReadResp 70721 # Transaction distribution +system.membus.trans_dist::WriteReq 27589 # Transaction distribution +system.membus.trans_dist::WriteResp 27589 # Transaction distribution +system.membus.trans_dist::Writeback 119469 # Transaction distribution +system.membus.trans_dist::CleanEvict 6488 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4509 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4491 # Transaction distribution -system.membus.trans_dist::ReadExReq 126147 # Transaction distribution -system.membus.trans_dist::ReadExResp 126147 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4511 # Transaction distribution +system.membus.trans_dist::ReadExReq 129210 # Transaction distribution +system.membus.trans_dist::ReadExResp 129210 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 30561 # Transaction distribution +system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 429068 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 536678 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 645565 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 445477 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 553069 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108900 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108900 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 661969 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15156092 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 15319481 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19954937 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15578364 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 15741717 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 18058837 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 498 # Total snoops (count) -system.membus.snoop_fanout::samples 381147 # Request fanout histogram +system.membus.snoop_fanout::samples 394437 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 381147 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 394437 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 381147 # Request fanout histogram -system.membus.reqLayer0.occupancy 90494500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 394437 # Request fanout histogram +system.membus.reqLayer0.occupancy 90486000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1721500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1696500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 960656101 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 834684564 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 947025657 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 964305240 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 37465995 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64480996 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1888,50 +1910,53 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 2303937 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2303837 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 27594 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 27594 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 687030 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36246 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2732 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 74970 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2298377 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 803098 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1802826 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2738 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2734 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 295743 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 295743 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3421816 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2454612 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18880 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 35749 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5931057 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108955768 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96785921 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 27096 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50916 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 205819701 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 52269 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3353284 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.021354 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.144561 # Request fanout histogram +system.toL2Bus.trans_dist::UpgradeResp 2740 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 295883 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 295883 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1698424 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 524998 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5081680 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2577380 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18024 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 34106 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7711190 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108733880 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96470557 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 24084 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 45196 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 205273717 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 180370 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 5305015 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.037219 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.189299 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3281678 97.86% 97.86% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 71606 2.14% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 5107565 96.28% 96.28% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 197450 3.72% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3353284 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2359229000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 5305015 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3268607000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 201000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2567253247 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2556658000 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1309775845 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1277273499 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 12106000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 12003000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 23020250 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 22807000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |