diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt | 144 |
1 files changed, 121 insertions, 23 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt index 818a22f67..83b8a4ab7 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 47.177080 # Nu sim_ticks 47177080006500 # Number of ticks simulated final_tick 47177080006500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1024538 # Simulator instruction rate (inst/s) -host_op_rate 1205255 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49483118923 # Simulator tick rate (ticks/s) -host_mem_usage 669884 # Number of bytes of host memory used -host_seconds 953.40 # Real time elapsed on the host +host_inst_rate 1049876 # Simulator instruction rate (inst/s) +host_op_rate 1235062 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50706899360 # Simulator tick rate (ticks/s) +host_mem_usage 670076 # Number of bytes of host memory used +host_seconds 930.39 # Real time elapsed on the host sim_insts 976792036 # Number of instructions simulated sim_ops 1149086878 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -105,6 +105,14 @@ system.cf0.dma_write_full_pages 1667 # Nu system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -126,6 +134,24 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 123914 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 123914 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 123914 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 123914 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 123914 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 95376 89.74% 89.74% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 10905 10.26% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 106281 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 123914 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 123914 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 106281 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 106281 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 230195 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses system.cpu0.dtb.read_hits 91355479 # DTB read hits @@ -147,6 +173,14 @@ system.cpu0.dtb.inst_accesses 0 # IT system.cpu0.dtb.hits 175957422 # DTB hits system.cpu0.dtb.misses 123914 # DTB misses system.cpu0.dtb.accesses 176081336 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -168,6 +202,24 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.walker.walks 60226 # Table walker walks requested +system.cpu0.itb.walker.walksLong 60226 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 60226 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 60226 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 60226 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 54190 98.81% 98.81% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 654 1.19% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 54844 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 60226 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 60226 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 54844 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 54844 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 115070 # Table walker requests started/completed, data/inst system.cpu0.itb.inst_hits 491372488 # ITB inst hits system.cpu0.itb.inst_misses 60226 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits @@ -392,15 +444,12 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu0.l2cache.tags.replacements 2648971 # number of replacements system.cpu0.l2cache.tags.tagsinuse 16219.904236 # Cycle average of tags in use system.cpu0.l2cache.tags.total_refs 11415809 # Total number of references to valid blocks. @@ -576,6 +625,14 @@ system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::total 20196192 # Request fanout histogram +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -597,6 +654,24 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 144852 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 144852 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 144852 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 144852 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 144852 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walksPending::samples -274403872 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -274403872 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -274403872 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 112422 89.02% 89.02% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 13865 10.98% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 126287 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144852 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144852 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 126287 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 126287 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 271139 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses system.cpu1.dtb.read_hits 91720002 # DTB read hits @@ -618,6 +693,14 @@ system.cpu1.dtb.inst_accesses 0 # IT system.cpu1.dtb.hits 174219015 # DTB hits system.cpu1.dtb.misses 144852 # DTB misses system.cpu1.dtb.accesses 174363867 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -639,6 +722,24 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.walker.walks 61939 # Table walker walks requested +system.cpu1.itb.walker.walksLong 61939 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walkWaitTime::samples 61939 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 61939 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 61939 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walksPending::samples -274404872 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -274404872 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -274404872 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 54929 99.06% 99.06% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 521 0.94% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 55450 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61939 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 61939 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55450 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55450 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 117389 # Table walker requests started/completed, data/inst system.cpu1.itb.inst_hits 485906850 # ITB inst hits system.cpu1.itb.inst_misses 61939 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits @@ -861,15 +962,12 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu1.l2cache.tags.replacements 2333825 # number of replacements system.cpu1.l2cache.tags.tagsinuse 13484.024344 # Cycle average of tags in use system.cpu1.l2cache.tags.total_refs 11006559 # Total number of references to valid blocks. |