diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt | 4822 |
1 files changed, 2455 insertions, 2367 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt index 36c2b5576..2d0abc648 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt @@ -1,175 +1,172 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.566016 # Number of seconds simulated -sim_ticks 47566015848000 # Number of ticks simulated -final_tick 47566015848000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.398431 # Number of seconds simulated +sim_ticks 47398431268500 # Number of ticks simulated +final_tick 47398431268500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 675626 # Simulator instruction rate (inst/s) -host_op_rate 794684 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35963293075 # Simulator tick rate (ticks/s) -host_mem_usage 873656 # Number of bytes of host memory used -host_seconds 1322.63 # Real time elapsed on the host -sim_insts 893600449 # Number of instructions simulated -sim_ops 1051070162 # Number of ops (including micro ops) simulated +host_inst_rate 671569 # Simulator instruction rate (inst/s) +host_op_rate 790318 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 37657329129 # Simulator tick rate (ticks/s) +host_mem_usage 861000 # Number of bytes of host memory used +host_seconds 1258.68 # Real time elapsed on the host +sim_insts 845288376 # Number of instructions simulated +sim_ops 994755388 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 233408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 408704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 743028 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 13616152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 28206528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 271488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 437568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 534776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 13513568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 26761152 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 461312 # Number of bytes read from this memory -system.physmem.bytes_read::total 85187684 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 743028 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 534776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1277804 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 43935424 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 56825292 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 43859652 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 6846976 # Number of bytes written to this memory -system.physmem.bytes_written::total 151467344 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 3647 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 6386 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 52017 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 212774 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 440727 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 4242 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 6837 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 8444 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 211164 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 418143 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 7208 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1371589 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 686491 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 890172 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 685308 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 106984 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2368955 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 4907 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 8592 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 15621 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 286258 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 592997 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 5708 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 9199 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 11243 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 284101 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 562611 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9698 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1790936 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 15621 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 11243 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 26864 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 923673 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 1194662 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 922080 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 143947 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3184361 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 923673 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 4907 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 8592 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 15621 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1480920 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 592997 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 5708 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 9199 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 11243 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1206181 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 562611 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 153645 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4975296 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1371589 # Number of read requests accepted -system.physmem.writeReqs 2368955 # Number of write requests accepted -system.physmem.readBursts 1371589 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 2368955 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 87480576 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 301120 # Total number of bytes read from write queue -system.physmem.bytesWritten 145871552 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 85187684 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 151467344 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 4705 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 89687 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 96177 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 85059 # Per bank write bursts -system.physmem.perBankRdBursts::1 83413 # Per bank write bursts -system.physmem.perBankRdBursts::2 77756 # Per bank write bursts -system.physmem.perBankRdBursts::3 83623 # Per bank write bursts -system.physmem.perBankRdBursts::4 79267 # Per bank write bursts -system.physmem.perBankRdBursts::5 92440 # Per bank write bursts -system.physmem.perBankRdBursts::6 79265 # Per bank write bursts -system.physmem.perBankRdBursts::7 88179 # Per bank write bursts -system.physmem.perBankRdBursts::8 75468 # Per bank write bursts -system.physmem.perBankRdBursts::9 124700 # Per bank write bursts -system.physmem.perBankRdBursts::10 77875 # Per bank write bursts -system.physmem.perBankRdBursts::11 89966 # Per bank write bursts -system.physmem.perBankRdBursts::12 78954 # Per bank write bursts -system.physmem.perBankRdBursts::13 87199 # Per bank write bursts -system.physmem.perBankRdBursts::14 85039 # Per bank write bursts -system.physmem.perBankRdBursts::15 78681 # Per bank write bursts -system.physmem.perBankWrBursts::0 146127 # Per bank write bursts -system.physmem.perBankWrBursts::1 131230 # Per bank write bursts -system.physmem.perBankWrBursts::2 144620 # Per bank write bursts -system.physmem.perBankWrBursts::3 127213 # Per bank write bursts -system.physmem.perBankWrBursts::4 148937 # Per bank write bursts -system.physmem.perBankWrBursts::5 150009 # Per bank write bursts -system.physmem.perBankWrBursts::6 182023 # Per bank write bursts -system.physmem.perBankWrBursts::7 144700 # Per bank write bursts -system.physmem.perBankWrBursts::8 124458 # Per bank write bursts -system.physmem.perBankWrBursts::9 140305 # Per bank write bursts -system.physmem.perBankWrBursts::10 119798 # Per bank write bursts -system.physmem.perBankWrBursts::11 155853 # Per bank write bursts -system.physmem.perBankWrBursts::12 153554 # Per bank write bursts -system.physmem.perBankWrBursts::13 129042 # Per bank write bursts -system.physmem.perBankWrBursts::14 144270 # Per bank write bursts -system.physmem.perBankWrBursts::15 137104 # Per bank write bursts +system.physmem.bytes_read::cpu0.dtb.walker 36416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 41984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 768052 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7936536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 44723840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 83456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 97984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 589368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 8667104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 21031552 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 441920 # Number of bytes read from this memory +system.physmem.bytes_read::total 84418212 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 768052 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 589368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1357420 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65101248 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory +system.physmem.bytes_written::total 65122064 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 569 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 656 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 52408 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 124030 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 698810 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1304 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1531 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 9297 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 135438 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 328618 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6905 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1359566 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1017207 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1019810 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 768 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 886 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 16204 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 167443 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 943572 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1761 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2067 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 12434 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 182856 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 443718 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9324 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1781034 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 16204 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 12434 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 28639 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1373490 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1373929 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1373490 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 768 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 886 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 16204 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 167882 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 943572 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2067 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 12434 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 182856 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 443718 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9324 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3154963 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1359566 # Number of read requests accepted +system.physmem.writeReqs 1139623 # Number of write requests accepted +system.physmem.readBursts 1359566 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1139623 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 86962304 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 49920 # Total number of bytes read from write queue +system.physmem.bytesWritten 72439488 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 84418212 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 72790096 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 780 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 7732 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 85004 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 81504 # Per bank write bursts +system.physmem.perBankRdBursts::1 94599 # Per bank write bursts +system.physmem.perBankRdBursts::2 79086 # Per bank write bursts +system.physmem.perBankRdBursts::3 89082 # Per bank write bursts +system.physmem.perBankRdBursts::4 90127 # Per bank write bursts +system.physmem.perBankRdBursts::5 94039 # Per bank write bursts +system.physmem.perBankRdBursts::6 78740 # Per bank write bursts +system.physmem.perBankRdBursts::7 79772 # Per bank write bursts +system.physmem.perBankRdBursts::8 80197 # Per bank write bursts +system.physmem.perBankRdBursts::9 124149 # Per bank write bursts +system.physmem.perBankRdBursts::10 71869 # Per bank write bursts +system.physmem.perBankRdBursts::11 83577 # Per bank write bursts +system.physmem.perBankRdBursts::12 73174 # Per bank write bursts +system.physmem.perBankRdBursts::13 83519 # Per bank write bursts +system.physmem.perBankRdBursts::14 78794 # Per bank write bursts +system.physmem.perBankRdBursts::15 76558 # Per bank write bursts +system.physmem.perBankWrBursts::0 70549 # Per bank write bursts +system.physmem.perBankWrBursts::1 76959 # Per bank write bursts +system.physmem.perBankWrBursts::2 69527 # Per bank write bursts +system.physmem.perBankWrBursts::3 76268 # Per bank write bursts +system.physmem.perBankWrBursts::4 71760 # Per bank write bursts +system.physmem.perBankWrBursts::5 76111 # Per bank write bursts +system.physmem.perBankWrBursts::6 67646 # Per bank write bursts +system.physmem.perBankWrBursts::7 68141 # Per bank write bursts +system.physmem.perBankWrBursts::8 69345 # Per bank write bursts +system.physmem.perBankWrBursts::9 72887 # Per bank write bursts +system.physmem.perBankWrBursts::10 65485 # Per bank write bursts +system.physmem.perBankWrBursts::11 73987 # Per bank write bursts +system.physmem.perBankWrBursts::12 65828 # Per bank write bursts +system.physmem.perBankWrBursts::13 73935 # Per bank write bursts +system.physmem.perBankWrBursts::14 66021 # Per bank write bursts +system.physmem.perBankWrBursts::15 67418 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 9 # Number of times write queue was full causing retry -system.physmem.totGap 47566012867000 # Total gap between requests +system.physmem.numWrRetry 5 # Number of times write queue was full causing retry +system.physmem.totGap 47398428076000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43195 # Read request sizes (log2) system.physmem.readPktSize::3 37 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1328352 # Read request sizes (log2) +system.physmem.readPktSize::6 1316329 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2601 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 2366352 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 854051 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 158360 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 84564 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 68503 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 51448 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 44074 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 37830 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 31756 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 25068 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4404 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1973 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1347 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1006 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 782 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 591 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 292 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 229 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 76 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1137020 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 566894 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 282234 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 134057 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 101972 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 67644 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 58693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 53670 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 46721 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 35916 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 3762 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1955 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1465 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 882 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 709 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 471 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 229 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 184 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 107 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 75 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see @@ -191,157 +188,158 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 89303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 97776 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 118763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 123056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 124315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 149365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 133979 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 128880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 131405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 133820 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 133411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 132599 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 131583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 133798 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 128352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 124285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 123534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 120195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 5413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 4121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2998 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 869 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 22 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 832768 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 280.211728 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 152.211424 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 337.275385 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 413524 49.66% 49.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 160093 19.22% 68.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 57236 6.87% 75.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 29306 3.52% 79.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 24972 3.00% 82.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 16042 1.93% 84.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 12534 1.51% 85.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 12228 1.47% 87.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 106833 12.83% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 832768 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 117976 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 11.586017 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 192.972695 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 117973 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::20480-22527 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::24576-26623 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-59391 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 117976 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 117976 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.319548 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.993188 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 4.933657 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 75459 63.96% 63.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 36712 31.12% 95.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 3025 2.56% 97.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 865 0.73% 98.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 773 0.66% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 198 0.17% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 143 0.12% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 73 0.06% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 88 0.07% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 20 0.02% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 14 0.01% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 14 0.01% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 383 0.32% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 36 0.03% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 51 0.04% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 22 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 46 0.04% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 4 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 9 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 5 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 6 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 16 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 4 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 117976 # Writes before turning the bus around for reads -system.physmem.totQLat 39242427762 # Total ticks spent queuing -system.physmem.totMemAccLat 64871502762 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6834420000 # Total ticks spent in databus transfers -system.physmem.avgQLat 28709.41 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 16911 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 22466 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 30737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 39170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 44059 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 50283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 58139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 68202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 72051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 76579 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 76851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 78478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 78341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 80363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 74556 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 75992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 78312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 75395 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 11828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 7611 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 4129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1099 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 777 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 712 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 642 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 418 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 5 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 648906 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 245.646870 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 142.183985 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 295.195613 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 325424 50.15% 50.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 135792 20.93% 71.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 50411 7.77% 78.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 26706 4.12% 82.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 22287 3.43% 86.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 16108 2.48% 88.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 10950 1.69% 90.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 13619 2.10% 92.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 47609 7.34% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 648906 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 58676 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.156827 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 139.787244 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 58673 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::24576-25599 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 58676 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 58676 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.290119 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.850822 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.308232 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 54948 93.65% 93.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 970 1.65% 95.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 598 1.02% 96.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 219 0.37% 96.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 626 1.07% 97.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 147 0.25% 98.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 195 0.33% 98.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 132 0.22% 98.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 184 0.31% 98.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 81 0.14% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 205 0.35% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 24 0.04% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 63 0.11% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 38 0.06% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 129 0.22% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 15 0.03% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 27 0.05% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 11 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 19 0.03% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 8 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 11 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 5 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 6 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 3 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 4 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-279 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 58676 # Writes before turning the bus around for reads +system.physmem.totQLat 69966976258 # Total ticks spent queuing +system.physmem.totMemAccLat 95444213758 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6793930000 # Total ticks spent in databus transfers +system.physmem.avgQLat 51492.27 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47459.41 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.84 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.07 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.79 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.18 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 70242.27 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.83 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.53 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.78 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.54 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.04 # Data bus utilization in percentage +system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.32 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.10 # Average write queue length when enqueuing -system.physmem.readRowHits 1063781 # Number of row buffer hits during reads -system.physmem.writeRowHits 1749574 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.83 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 76.76 # Row buffer hit rate for writes -system.physmem.avgGap 12716335.61 # Average gap between requests -system.physmem.pageHitRate 77.16 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 45509072189751 # Time in different power states -system.physmem.memoryStateTime::REF 1588333760000 # Time in different power states +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.44 # Average write queue length when enqueuing +system.physmem.readRowHits 1114788 # Number of row buffer hits during reads +system.physmem.writeRowHits 726958 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.04 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 64.23 # Row buffer hit rate for writes +system.physmem.avgGap 18965523.65 # Average gap between requests +system.physmem.pageHitRate 73.95 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 45538400789750 # Time in different power states +system.physmem.memoryStateTime::REF 1582737780000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 468608703999 # Time in different power states +system.physmem.memoryStateTime::ACT 277292625250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 3171472920 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 3124253160 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1730466375 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1704701625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 5218192200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 5443409400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 7613086320 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 7156408320 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3106780834560 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3106780834560 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 1266482203425 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1265693181210 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 27428659482750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 27429351607500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 31819655738550 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 31819254395775 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.957784 # Core power per rank (mW) -system.physmem.averagePower::1 668.949346 # Core power per rank (mW) +system.physmem.actEnergy::0 2564850960 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 2340878400 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 1399472250 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 1277265000 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 5358202200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 5240320800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 3738707280 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 3595790880 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 3095835097680 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 3095835097680 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 1171174509540 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 1161726671475 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 27411712647750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 27420000225000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 31691783487660 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 31690016249235 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.625157 # Core power per rank (mW) +system.physmem.averagePower::1 668.587872 # Core power per rank (mW) system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory @@ -371,9 +369,9 @@ system.realview.nvmem.bw_total::total 4 # To system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 1674 # Number of DMA write transactions. +system.cf0.dma_write_full_pages 1670 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6842880 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1673 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -398,25 +396,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 86716512 # DTB read hits -system.cpu0.dtb.read_misses 82712 # DTB read misses -system.cpu0.dtb.write_hits 78633728 # DTB write hits -system.cpu0.dtb.write_misses 28389 # DTB write misses +system.cpu0.dtb.read_hits 74706058 # DTB read hits +system.cpu0.dtb.read_misses 64792 # DTB read misses +system.cpu0.dtb.write_hits 67192400 # DTB write hits +system.cpu0.dtb.write_misses 21129 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 41884 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 34135 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 37660 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 33482 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4682 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 3817 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 9159 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 86799224 # DTB read accesses -system.cpu0.dtb.write_accesses 78662117 # DTB write accesses +system.cpu0.dtb.perms_faults 8375 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 74770850 # DTB read accesses +system.cpu0.dtb.write_accesses 67213529 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 165350240 # DTB hits -system.cpu0.dtb.misses 111101 # DTB misses -system.cpu0.dtb.accesses 165461341 # DTB accesses +system.cpu0.dtb.hits 141898458 # DTB hits +system.cpu0.dtb.misses 85921 # DTB misses +system.cpu0.dtb.accesses 141984379 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -438,283 +436,295 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 459685693 # ITB inst hits -system.cpu0.itb.inst_misses 60045 # ITB inst misses +system.cpu0.itb.inst_hits 397874920 # ITB inst hits +system.cpu0.itb.inst_misses 49120 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 41884 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 24187 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 37660 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 23760 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 459745738 # ITB inst accesses -system.cpu0.itb.hits 459685693 # DTB hits -system.cpu0.itb.misses 60045 # DTB misses -system.cpu0.itb.accesses 459745738 # DTB accesses -system.cpu0.numCycles 95132031682 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 397924040 # ITB inst accesses +system.cpu0.itb.hits 397874920 # DTB hits +system.cpu0.itb.misses 49120 # DTB misses +system.cpu0.itb.accesses 397924040 # DTB accesses +system.cpu0.numCycles 94796862537 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 459439593 # Number of instructions committed -system.cpu0.committedOps 539347874 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 495403687 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 451172 # Number of float alu accesses -system.cpu0.num_func_calls 27064307 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 69711991 # number of instructions that are conditional controls -system.cpu0.num_int_insts 495403687 # number of integer instructions -system.cpu0.num_fp_insts 451172 # number of float instructions -system.cpu0.num_int_register_reads 715734727 # number of times the integer registers were read -system.cpu0.num_int_register_writes 392523746 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 749199 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 337216 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 119686995 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 119275623 # number of times the CC registers were written -system.cpu0.num_mem_refs 165340768 # number of memory refs -system.cpu0.num_load_insts 86711184 # Number of load instructions -system.cpu0.num_store_insts 78629584 # Number of store instructions -system.cpu0.num_idle_cycles 94014587829.536469 # Number of idle cycles -system.cpu0.num_busy_cycles 1117443852.463529 # Number of busy cycles -system.cpu0.not_idle_fraction 0.011746 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.988254 # Percentage of idle cycles -system.cpu0.Branches 102470244 # Number of branches fetched +system.cpu0.committedInsts 397643174 # Number of instructions committed +system.cpu0.committedOps 466635553 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 429030148 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 322477 # Number of float alu accesses +system.cpu0.num_func_calls 23930039 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 59901605 # number of instructions that are conditional controls +system.cpu0.num_int_insts 429030148 # number of integer instructions +system.cpu0.num_fp_insts 322477 # number of float instructions +system.cpu0.num_int_register_reads 621630892 # number of times the integer registers were read +system.cpu0.num_int_register_writes 340702516 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 547437 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 211832 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 102593685 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 102325899 # number of times the CC registers were written +system.cpu0.num_mem_refs 141893093 # number of memory refs +system.cpu0.num_load_insts 74704433 # Number of load instructions +system.cpu0.num_store_insts 67188660 # Number of store instructions +system.cpu0.num_idle_cycles 93886429062.298019 # Number of idle cycles +system.cpu0.num_busy_cycles 910433474.701981 # Number of busy cycles +system.cpu0.not_idle_fraction 0.009604 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.990396 # Percentage of idle cycles +system.cpu0.Branches 88352328 # Number of branches fetched system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 373021399 69.12% 69.12% # Class of executed instruction -system.cpu0.op_class::IntMult 1165287 0.22% 69.34% # Class of executed instruction -system.cpu0.op_class::IntDiv 62749 0.01% 69.35% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 46895 0.01% 69.36% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.36% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.36% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.36% # Class of executed instruction -system.cpu0.op_class::MemRead 86711184 16.07% 85.43% # Class of executed instruction -system.cpu0.op_class::MemWrite 78629584 14.57% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 323823287 69.35% 69.35% # Class of executed instruction +system.cpu0.op_class::IntMult 1114929 0.24% 69.59% # Class of executed instruction +system.cpu0.op_class::IntDiv 56737 0.01% 69.61% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 22377 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::MemRead 74704433 16.00% 85.61% # Class of executed instruction +system.cpu0.op_class::MemWrite 67188660 14.39% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 539637098 # Class of executed instruction +system.cpu0.op_class::total 466910423 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 5368 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 5553236 # number of replacements -system.cpu0.dcache.tags.tagsinuse 507.463915 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 159572063 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5553747 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.732325 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 5105 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 4859280 # number of replacements +system.cpu0.dcache.tags.tagsinuse 480.680410 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 136835586 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 4859789 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.156693 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 3644536500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 507.463915 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.991140 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.991140 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 348 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 336276505 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 336276505 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 80841388 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 80841388 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 74354122 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 74354122 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 186421 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 186421 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 887570 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 887570 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1858688 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1858688 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1820106 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1820106 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 155195510 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 155195510 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 155381931 # number of overall hits -system.cpu0.dcache.overall_hits::total 155381931 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3020518 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3020518 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1355895 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1355895 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 638649 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 638649 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 156836 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 156836 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 194186 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 194186 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 4376413 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 4376413 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 5015062 # number of overall misses -system.cpu0.dcache.overall_misses::total 5015062 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 44235181893 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 44235181893 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 23644478419 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 23644478419 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2243299062 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2243299062 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4135736633 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4135736633 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1563000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1563000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 67879660312 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 67879660312 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 67879660312 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 67879660312 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 83861906 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 83861906 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 75710017 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 75710017 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 825070 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 825070 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 887570 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 887570 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2015524 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2015524 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2014292 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2014292 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 159571923 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 159571923 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 160396993 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 160396993 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036018 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.036018 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017909 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.017909 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.774054 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.774054 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.077814 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.077814 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.096404 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.096404 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027426 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.027426 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031267 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.031267 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14644.899283 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14644.899283 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17438.281297 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 17438.281297 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14303.470262 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14303.470262 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21297.810517 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21297.810517 # average StoreCondReq miss latency +system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.680410 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938829 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.938829 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 406 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 9 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 288671468 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 288671468 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 69599952 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 69599952 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 63413457 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 63413457 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 173858 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 173858 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 133135 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 133135 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1596886 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1596886 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1561841 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1561841 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 133013409 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 133013409 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 133187267 # number of overall hits +system.cpu0.dcache.overall_hits::total 133187267 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 2622769 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 2622769 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1185607 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1185607 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 553155 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 553155 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 697992 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 697992 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 145021 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 145021 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 178721 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 178721 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3808376 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3808376 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 4361531 # number of overall misses +system.cpu0.dcache.overall_misses::total 4361531 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 36725560788 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 36725560788 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 18496940456 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 18496940456 # number of WriteReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 11951080104 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 11951080104 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2007745317 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2007745317 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3807661334 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 3807661334 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 927000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 927000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 55222501244 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 55222501244 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 55222501244 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 55222501244 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 72222721 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 72222721 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 64599064 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 64599064 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 727013 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 727013 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 831127 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 831127 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1741907 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 1741907 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1740562 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1740562 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 136821785 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 136821785 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 137548798 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 137548798 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036315 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.036315 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018353 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018353 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.760860 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.760860 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.839814 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.839814 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.083254 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.083254 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.102680 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.102680 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027835 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.027835 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031709 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.031709 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14002.590693 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14002.590693 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15601.240931 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 15601.240931 # average WriteReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 17122.087508 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 17122.087508 # average WriteInvalidateReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13844.514360 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13844.514360 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21305.058354 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21305.058354 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15510.341531 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15510.341531 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13535.158750 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 13535.158750 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14500.275510 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14500.275510 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12661.265332 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 12661.265332 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 887570 # number of fast writes performed +system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 3048439 # number of writebacks -system.cpu0.dcache.writebacks::total 3048439 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 28957 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 28957 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21342 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 21342 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43075 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43075 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 50299 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 50299 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 50299 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 50299 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2991561 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 2991561 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1334553 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1334553 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 637409 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 637409 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 113761 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 113761 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 194186 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 194186 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4326114 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4326114 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 4963523 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 4963523 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 36853741584 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 36853741584 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 20599874090 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 20599874090 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14249969925 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14249969925 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 39555111210 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 39555111210 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1322683967 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1322683967 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3736995367 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3736995367 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1491000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1491000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 57453615674 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 57453615674 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 71703585599 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 71703585599 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2269904707 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2269904707 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2228690449 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2228690449 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4498595156 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4498595156 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035672 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035672 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017627 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017627 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.772551 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.772551 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056442 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056442 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.096404 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.096404 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027111 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027111 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030945 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.030945 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12319.234535 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12319.234535 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15435.785683 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15435.785683 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22356.085222 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22356.085222 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11626.866562 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11626.866562 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19244.411889 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19244.411889 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 3276433 # number of writebacks +system.cpu0.dcache.writebacks::total 3276433 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 20828 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 20828 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21424 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 21424 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 36174 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 36174 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 42252 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 42252 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 42252 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 42252 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2601941 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 2601941 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1164183 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1164183 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 551435 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 551435 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 697992 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 697992 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 108847 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 108847 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 178721 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 178721 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 3766124 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 3766124 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4317559 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 4317559 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 30561578872 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 30561578872 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 15647124797 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 15647124797 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 11524265112 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 11524265112 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 10542114896 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 10542114896 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1234908207 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1234908207 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3440508666 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3440508666 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 879000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 879000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 46208703669 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 46208703669 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 57732968781 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 57732968781 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2384094697 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2384094697 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2386757695 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2386757695 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4770852392 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4770852392 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036027 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036027 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018022 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018022 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.758494 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.758494 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.839814 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.839814 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062487 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062487 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.102680 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.102680 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027526 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027526 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031389 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031389 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11745.684807 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11745.684807 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 13440.434019 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13440.434019 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20898.682731 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 20898.682731 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 15103.489576 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 15103.489576 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11345.358228 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11345.358228 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19250.724123 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19250.724123 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13280.652261 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13280.652261 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14446.107251 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14446.107251 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12269.565120 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12269.565120 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13371.668756 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13371.668756 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -722,58 +732,59 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 5136279 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.921269 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 454548902 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 5136791 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 88.488884 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 24248022750 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.921269 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999846 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999846 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 4269396 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.932974 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 393605012 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 4269908 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 92.181146 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 18918806750 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.932974 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999869 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999869 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 81 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 269 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 222 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 924508177 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 924508177 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 454548902 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 454548902 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 454548902 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 454548902 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 454548902 # number of overall hits -system.cpu0.icache.overall_hits::total 454548902 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 5136791 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 5136791 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 5136791 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 5136791 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 5136791 # number of overall misses -system.cpu0.icache.overall_misses::total 5136791 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 44728233484 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 44728233484 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 44728233484 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 44728233484 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 44728233484 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 44728233484 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 459685693 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 459685693 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 459685693 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 459685693 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 459685693 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 459685693 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011175 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011175 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011175 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011175 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011175 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011175 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8707.427163 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8707.427163 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8707.427163 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8707.427163 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8707.427163 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8707.427163 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 800019748 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 800019748 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 393605012 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 393605012 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 393605012 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 393605012 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 393605012 # number of overall hits +system.cpu0.icache.overall_hits::total 393605012 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 4269908 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 4269908 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 4269908 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 4269908 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 4269908 # number of overall misses +system.cpu0.icache.overall_misses::total 4269908 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 37643365597 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 37643365597 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 37643365597 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 37643365597 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 37643365597 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 37643365597 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 397874920 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 397874920 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 397874920 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 397874920 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 397874920 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 397874920 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010732 # 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average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -782,365 +793,384 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5136791 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 5136791 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 5136791 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 5136791 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 5136791 # 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Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 8789.482396 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.237006 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002985 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003403 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.054952 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.157848 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.536467 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.992662 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8304 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 112 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7669 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 44 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 543 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 2171 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5264 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 282 # Occupied blocks per task id +system.cpu0.l2cache.tags.replacements 3291824 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16191.272385 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 9909292 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 3307923 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 2.995624 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 16044231500 # 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Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.162836 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.455922 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.988237 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8632 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 100 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7367 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 22 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 210 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 1111 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 7012 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 277 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 6 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 10 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 43 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 59 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 738 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3430 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3305 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 150 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.506836 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.006836 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.468079 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 240919913 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 240919913 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 231031 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 134927 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 4959117 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 2742170 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 8067245 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 3048439 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 3048439 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 86825 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 86825 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 33826 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 33826 # 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number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12665 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 11145 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 177674 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 1000560 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 1202044 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 109590 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 109590 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 160357 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 160357 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 3 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 232216 # 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mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.825803 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.070057 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.070057 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.585799 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.585799 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.824608 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.824608 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.198807 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.198807 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.051970 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.076298 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.029376 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.250201 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.134182 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.051970 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.076298 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.029376 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.250201 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.172158 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.172158 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.053612 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.066552 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.032837 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.243863 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.135483 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.053612 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.066552 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.032837 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.243863 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.379230 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 35343.766601 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 56047.873755 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 21091.262702 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 25156.730107 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25036.918858 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 29174.283567 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 29174.283567 # average HardPFReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16985.050817 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16985.050817 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13836.770949 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13836.770949 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 400999.666667 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 400999.666667 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 37095.485130 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 37095.485130 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 35343.766601 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 56047.873755 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 21091.262702 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27376.273319 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26998.409412 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 35343.766601 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 56047.873755 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 21091.262702 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27376.273319 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 29174.283567 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 28404.400626 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.469001 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 19129.700667 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 21397.343606 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 21780.932052 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22395.109853 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22273.429726 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 43752.426923 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 43752.426923 # average HardPFReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 18274.092453 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 18274.092453 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16661.502488 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16661.502488 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13865.687238 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13865.687238 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 687000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 687000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 29683.053592 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 29683.053592 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 19129.700667 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 21397.343606 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 21780.932052 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 23590.654453 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23328.795643 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 19129.700667 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 21397.343606 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 21780.932052 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 23590.654453 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 43752.426923 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 37852.554233 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1150,58 +1180,58 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 12709886 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 9530898 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 15163 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 15163 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 3048439 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 3732092 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1679869 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 887570 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 380241 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 351950 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 457079 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 47 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 80 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1289201 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1150842 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 10359832 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15601688 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 325277 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 566209 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 26853006 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 328927124 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 571100341 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1168576 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1949568 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 903145609 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 8562261 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 23134597 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.358060 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.479430 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 11465749 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 8074092 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 15773 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 15773 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 3276433 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 4228803 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 811507 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 696929 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 407420 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 328722 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 423022 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 30 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1108208 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 995011 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 8626066 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 14109371 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 260774 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 426575 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 23422786 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 273446612 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 532438419 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 912728 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1410280 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 808208039 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 8581549 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 21569506 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.385644 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.486747 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 14851033 64.19% 64.19% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 8283564 35.81% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 13251364 61.44% 61.44% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 8318142 38.56% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 23134597 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 11405856452 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 21569506 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 10644176370 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 183601993 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 173370992 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 7759954717 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 6459583336 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8048372726 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 6973558574 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 179758799 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 146771777 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 322845049 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 250366041 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -1226,25 +1256,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 81769828 # DTB read hits -system.cpu1.dtb.read_misses 79673 # DTB read misses -system.cpu1.dtb.write_hits 74311746 # DTB write hits -system.cpu1.dtb.write_misses 27355 # DTB write misses +system.cpu1.dtb.read_hits 84980512 # DTB read hits +system.cpu1.dtb.read_misses 74547 # DTB read misses +system.cpu1.dtb.write_hits 77969612 # DTB write hits +system.cpu1.dtb.write_misses 26781 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 41884 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 41105 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 37660 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 37319 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4547 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4156 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 10770 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 81849501 # DTB read accesses -system.cpu1.dtb.write_accesses 74339101 # DTB write accesses +system.cpu1.dtb.perms_faults 10210 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 85055059 # DTB read accesses +system.cpu1.dtb.write_accesses 77996393 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 156081574 # DTB hits -system.cpu1.dtb.misses 107028 # DTB misses -system.cpu1.dtb.accesses 156188602 # DTB accesses +system.cpu1.dtb.hits 162950124 # DTB hits +system.cpu1.dtb.misses 101328 # DTB misses +system.cpu1.dtb.accesses 163051452 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1266,283 +1296,295 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 434473512 # ITB inst hits -system.cpu1.itb.inst_misses 57336 # ITB inst misses +system.cpu1.itb.inst_hits 447940407 # ITB inst hits +system.cpu1.itb.inst_misses 68561 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 41884 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 28749 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 37660 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 26339 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 434530848 # ITB inst accesses -system.cpu1.itb.hits 434473512 # DTB hits -system.cpu1.itb.misses 57336 # DTB misses -system.cpu1.itb.accesses 434530848 # DTB accesses -system.cpu1.numCycles 95132031696 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 448008968 # ITB inst accesses +system.cpu1.itb.hits 447940407 # DTB hits +system.cpu1.itb.misses 68561 # DTB misses +system.cpu1.itb.accesses 448008968 # DTB accesses +system.cpu1.numCycles 94796862537 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 434160856 # Number of instructions committed -system.cpu1.committedOps 511722288 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 470175639 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 456535 # Number of float alu accesses -system.cpu1.num_func_calls 26230713 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 66122636 # number of instructions that are conditional controls -system.cpu1.num_int_insts 470175639 # number of integer instructions -system.cpu1.num_fp_insts 456535 # number of float instructions -system.cpu1.num_int_register_reads 688104482 # number of times the integer registers were read -system.cpu1.num_int_register_writes 373632663 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 726332 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 408756 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 113709240 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 113476936 # number of times the CC registers were written -system.cpu1.num_mem_refs 156073929 # number of memory refs -system.cpu1.num_load_insts 81768358 # Number of load instructions -system.cpu1.num_store_insts 74305571 # Number of store instructions -system.cpu1.num_idle_cycles 94082707842.004028 # Number of idle cycles -system.cpu1.num_busy_cycles 1049323853.995978 # Number of busy cycles -system.cpu1.not_idle_fraction 0.011030 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.988970 # Percentage of idle cycles -system.cpu1.Branches 96877428 # Number of branches fetched +system.cpu1.committedInsts 447645202 # Number of instructions committed +system.cpu1.committedOps 528119835 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 486291398 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 624474 # Number of float alu accesses +system.cpu1.num_func_calls 27450761 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 67545606 # number of instructions that are conditional controls +system.cpu1.num_int_insts 486291398 # number of integer instructions +system.cpu1.num_fp_insts 624474 # number of float instructions +system.cpu1.num_int_register_reads 698728829 # number of times the integer registers were read +system.cpu1.num_int_register_writes 384530758 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 985803 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 576512 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 114161169 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 113813296 # number of times the CC registers were written +system.cpu1.num_mem_refs 162934099 # number of memory refs +system.cpu1.num_load_insts 84972579 # Number of load instructions +system.cpu1.num_store_insts 77961520 # Number of store instructions +system.cpu1.num_idle_cycles 93770083152.566025 # Number of idle cycles +system.cpu1.num_busy_cycles 1026779384.433978 # Number of busy cycles +system.cpu1.not_idle_fraction 0.010831 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.989169 # Percentage of idle cycles +system.cpu1.Branches 100081816 # Number of branches fetched system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 354755827 69.28% 69.28% # Class of executed instruction -system.cpu1.op_class::IntMult 1081291 0.21% 69.49% # Class of executed instruction -system.cpu1.op_class::IntDiv 57437 0.01% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 66526 0.01% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::MemRead 81768358 15.97% 85.49% # Class of executed instruction -system.cpu1.op_class::MemWrite 74305571 14.51% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 364276895 68.94% 68.94% # Class of executed instruction +system.cpu1.op_class::IntMult 1051011 0.20% 69.14% # Class of executed instruction +system.cpu1.op_class::IntDiv 60606 0.01% 69.15% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 92495 0.02% 69.17% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.17% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.17% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.17% # Class of executed instruction +system.cpu1.op_class::MemRead 84972579 16.08% 85.25% # Class of executed instruction +system.cpu1.op_class::MemWrite 77961520 14.75% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 512035053 # Class of executed instruction +system.cpu1.op_class::total 528415149 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 13728 # number of quiesce instructions executed -system.cpu1.dcache.tags.replacements 5229569 # number of replacements -system.cpu1.dcache.tags.tagsinuse 446.555743 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 150635340 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5230081 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 28.801722 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8374220312000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 446.555743 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.872179 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.872179 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 13701 # number of quiesce instructions executed +system.cpu1.dcache.tags.replacements 5194711 # number of replacements +system.cpu1.dcache.tags.tagsinuse 457.134068 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 157559099 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5195223 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 30.327687 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8367548601000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 457.134068 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.892840 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.892840 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 408 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 415 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 317363377 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 317363377 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 76086699 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 76086699 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 70396756 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 70396756 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 188905 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 188905 # number of SoftPFReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 685307 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 685307 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1701097 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1701097 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1676869 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1676869 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 146483455 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 146483455 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 146672360 # number of overall hits -system.cpu1.dcache.overall_hits::total 146672360 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 2949268 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 2949268 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1324938 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1324938 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 648778 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 648778 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 170596 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 170596 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 193531 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 193531 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 4274206 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 4274206 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 4922984 # number of overall misses -system.cpu1.dcache.overall_misses::total 4922984 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 43925732439 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 43925732439 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 22816644952 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 22816644952 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2487645065 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2487645065 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4103865813 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4103865813 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1896000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1896000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 66742377391 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 66742377391 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 66742377391 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 66742377391 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 79035967 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 79035967 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 71721694 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 71721694 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 837683 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 837683 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 685307 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::total 685307 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1871693 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1871693 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1870400 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1870400 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 150757661 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 150757661 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 151595344 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 151595344 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037316 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.037316 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018473 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.018473 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.774491 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.774491 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.091145 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.091145 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103470 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103470 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.028352 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.028352 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.032475 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.032475 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14893.774468 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14893.774468 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17220.915207 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 17220.915207 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14582.083197 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14582.083197 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21205.211635 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21205.211635 # average StoreCondReq miss latency +system.cpu1.dcache.tags.tag_accesses 331059949 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 331059949 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 79405575 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 79405575 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 74066119 # 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number of overall hits +system.cpu1.dcache.overall_hits::total 153663583 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 2946837 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 2946837 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1283113 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1283113 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 571898 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 571898 # number of SoftPFReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 550709 # number of WriteInvalidateReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::total 550709 # number of WriteInvalidateReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 171203 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 171203 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 185528 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 185528 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 4229950 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 4229950 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 4801848 # number of overall misses +system.cpu1.dcache.overall_misses::total 4801848 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 41215882509 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 41215882509 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 19312866378 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 19312866378 # number of WriteReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 6595698094 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 6595698094 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2383654561 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2383654561 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3901847697 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 3901847697 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1095500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1095500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 60528748887 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 60528748887 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 60528748887 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 60528748887 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 82352412 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 82352412 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 75349232 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 75349232 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 763787 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 763787 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 748341 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::total 748341 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1840883 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1840883 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1839669 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1839669 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 157701644 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 157701644 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 158465431 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 158465431 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035783 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.035783 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.017029 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.017029 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.748766 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.748766 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.735906 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.735906 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.093000 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.093000 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100849 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100849 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026822 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.026822 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.030302 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.030302 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13986.481950 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13986.481950 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 15051.570967 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 15051.570967 # average WriteReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 11976.739247 # average WriteInvalidateReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 11976.739247 # average WriteInvalidateReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13922.971916 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13922.971916 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21031.044893 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21031.044893 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15615.152239 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15615.152239 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13557.301302 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 13557.301302 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14309.566044 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14309.566044 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12605.302976 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 12605.302976 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.fast_writes 685307 # number of fast writes performed +system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 2978181 # number of writebacks -system.cpu1.dcache.writebacks::total 2978181 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 23865 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 23865 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 515 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 515 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 45192 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 45192 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 24380 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 24380 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 24380 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 24380 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2925403 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2925403 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1324423 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1324423 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 648778 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 648778 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 125404 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 125404 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 193531 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 193531 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4249826 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4249826 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 4898604 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 4898604 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 36900792539 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 36900792539 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 20082419307 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 20082419307 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13833136236 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13833136236 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 30583171682 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 30583171682 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1453819204 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1453819204 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3706136187 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3706136187 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1808000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1808000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 56983211846 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 56983211846 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 70816348082 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 70816348082 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4114514480 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4114514480 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3994198470 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3994198470 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 8108712950 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 8108712950 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037014 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037014 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018466 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018466 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.774491 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.774491 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.067000 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.067000 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103470 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103470 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028190 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.028190 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032314 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.032314 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12613.917651 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12613.917651 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15163.145994 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15163.145994 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21321.833102 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21321.833102 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11593.084782 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11593.084782 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19150.090616 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19150.090616 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3397427 # number of writebacks +system.cpu1.dcache.writebacks::total 3397427 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 14736 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 14736 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 407 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 407 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 48814 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 48814 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 15143 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 15143 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 15143 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 15143 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2932101 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2932101 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1282706 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1282706 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 571898 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 571898 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 550709 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 550709 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 122389 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 122389 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 185528 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 185528 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4214807 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4214807 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4786705 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4786705 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 34665979416 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 34665979416 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 16693598628 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 16693598628 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 11612454284 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 11612454284 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 5490664906 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 5490664906 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1373965707 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1373965707 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3521472303 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3521472303 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1037500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1037500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 51359578044 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 51359578044 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 62972032328 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 62972032328 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3972621225 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3972621225 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3807943973 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3807943973 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 7780565198 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 7780565198 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035604 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035604 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017023 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017023 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.748766 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.748766 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.735906 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.735906 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.066484 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066484 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100849 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100849 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026726 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026726 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030207 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.030207 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11822.914496 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11822.914496 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13014.360756 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13014.360756 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20305.114346 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20305.114346 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 9970.174640 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 9970.174640 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11226.218917 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11226.218917 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 18980.813155 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 18980.813155 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13408.363506 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13408.363506 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14456.434544 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14456.434544 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12185.511233 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12185.511233 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13155.611705 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13155.611705 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1550,59 +1592,59 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 4838786 # number of replacements -system.cpu1.icache.tags.tagsinuse 496.335132 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 429634209 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 4839298 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 88.780275 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8374030789000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.335132 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969405 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.969405 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 5786522 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.339295 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 442153368 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5787034 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 76.404142 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8367526246000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.339295 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969413 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.969413 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 281 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 169 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 339 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 108 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 873786327 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 873786327 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 429634209 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 429634209 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 429634209 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 429634209 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 429634209 # number of overall hits -system.cpu1.icache.overall_hits::total 429634209 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 4839303 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 4839303 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 4839303 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 4839303 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 4839303 # 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number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 434473512 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 434473512 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011138 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.011138 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011138 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.011138 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011138 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.011138 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8720.563823 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8720.563823 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8720.563823 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8720.563823 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8720.563823 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8720.563823 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 901667853 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 901667853 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 442153368 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 442153368 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 442153368 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 442153368 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 442153368 # number of overall hits +system.cpu1.icache.overall_hits::total 442153368 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 5787039 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 5787039 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 5787039 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 5787039 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 5787039 # number of overall misses +system.cpu1.icache.overall_misses::total 5787039 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 50052191468 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 50052191468 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 50052191468 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 50052191468 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 50052191468 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 50052191468 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 447940407 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 447940407 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 447940407 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 447940407 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 447940407 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 447940407 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.012919 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.012919 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.012919 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.012919 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.012919 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.012919 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8649.015752 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8649.015752 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8649.015752 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8649.015752 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8649.015752 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8649.015752 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1611,367 +1653,384 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # 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number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 34939638885 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 34939638885 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8745500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8745500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8745500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 8745500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011138 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011138 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011138 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.011138 # 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number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 5787039 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 5787039 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 5787039 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 5787039 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 41368714588 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 41368714588 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 41368714588 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 41368714588 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 41368714588 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 41368714588 # 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mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7148.511456 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7148.511456 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7148.511456 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 7148.511456 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7148.511456 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 7148.511456 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # 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number of hwpf that were already in the prefetch queue system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 514 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 2394823 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 3842139 # number of hwpf spanning a virtual page +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 584 # number of hwpf removed because MSHR allocated +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 2737051 # number of hwpf issued +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 4557576 # number of hwpf spanning a virtual page system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 3029134 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13674.379805 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 10606046 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 3045261 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 3.482804 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 10454752865000 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 4179.016177 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 54.517433 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 70.326677 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 591.513668 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3188.927208 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 5590.078642 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.255067 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003327 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004292 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.036103 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.194637 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.341191 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.834618 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 8556 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 61 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 7510 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 76 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 438 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 3359 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 4072 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 611 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 24 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 28 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 34 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 492 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2836 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 3841 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 307 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.522217 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003723 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.458374 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 230495604 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 230495604 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 221576 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 129888 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 4667071 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 2714218 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 7732753 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 2978176 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 2978176 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 79936 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 79936 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 35720 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 35720 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 908771 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 908771 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 221576 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 129888 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 4667071 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3622989 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 8641524 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 221576 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 129888 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 4667071 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3622989 # number of overall hits -system.cpu1.l2cache.overall_hits::total 8641524 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12665 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 11221 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 172232 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 985367 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 1181485 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 109801 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 109801 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 157805 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 157805 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 6 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 226147 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 226147 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12665 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 11221 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 172232 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1211514 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 1407632 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12665 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 11221 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 172232 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1211514 # number of overall misses -system.cpu1.l2cache.overall_misses::total 1407632 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 578928201 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 733432437 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 4494366580 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 32191641510 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 37998368728 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2189702140 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 2189702140 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3225705678 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3225705678 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1763999 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1763999 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10153420884 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 10153420884 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 578928201 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 733432437 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 4494366580 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 42345062394 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 48151789612 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 578928201 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 733432437 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 4494366580 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 42345062394 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 48151789612 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 234241 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 141109 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 4839303 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3699585 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 8914238 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 2978176 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 2978176 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 189737 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 189737 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 193525 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 193525 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 6 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1134918 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1134918 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 234241 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 141109 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 4839303 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 4834503 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 10049156 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 234241 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 141109 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 4839303 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 4834503 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 10049156 # 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Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 11929802 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 3281353 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 3.635635 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 9719592338000 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 3548.297662 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 58.425503 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 65.675774 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 758.406628 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2477.157386 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6824.630764 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.216571 # 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Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2721 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 4842 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 395 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 15 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 20 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 810 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 3409 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2963 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 229 # 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number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 328936960 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 4835548618 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 34777443242 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 40281072290 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 339143470 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 328936960 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 4835548618 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 34777443242 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 40281072290 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 215560 # 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average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 65362.484360 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 26094.840564 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 32669.697189 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 32161.532925 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19942.460815 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19942.460815 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20441.086645 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20441.086645 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 293999.833333 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 293999.833333 # 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mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.578701 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.578701 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.815424 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.815424 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.087836 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.087836 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.591620 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.591620 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.808666 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.808666 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.193898 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.193898 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.054068 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.079520 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.030092 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.249149 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.136730 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.054068 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.079520 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.030092 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.249149 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.176371 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.176371 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.051364 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.057789 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026944 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.237888 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.119344 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.051364 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.057789 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026944 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.237888 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.375030 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 38635.792578 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 58242.408609 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 20916.075530 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 25591.835763 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25462.426584 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 29673.692721 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 29673.692721 # average HardPFReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17297.056375 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17297.056375 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13909.668705 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13909.668705 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 242666.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 242666.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36130.949722 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36130.949722 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 38635.792578 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 58242.408609 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 20916.075530 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27517.274791 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27171.053118 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 38635.792578 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 58242.408609 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 20916.075530 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27517.274791 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 29673.692721 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28761.268269 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.370592 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 23590.774025 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 26697.193393 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 21030.079325 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 22855.890509 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 22639.849443 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 25466.057437 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 25466.057437 # average HardPFReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 15325.803477 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 15325.803477 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16571.950039 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16571.950039 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13824.139322 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13824.139322 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 201375 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 201375 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 27369.696466 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27369.696466 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 23590.774025 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 26697.193393 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 21030.079325 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23632.313965 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23342.822566 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 23590.774025 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 26697.193393 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 21030.079325 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23632.313965 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 25466.057437 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24782.300723 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1981,65 +2040,65 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 12427806 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 9137324 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 23353 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 23353 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 2978176 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 3478890 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1679869 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 685307 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 370922 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 353849 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 446809 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 42 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 80 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1290596 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1141918 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9678826 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15042396 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 312565 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 544877 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 25578664 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 309715832 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 550341480 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1128872 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1873928 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 863060112 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 8621982 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 22555543 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.370325 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.482892 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 13482596 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 10019474 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 22090 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 22090 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 3397427 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 3948207 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 669175 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 549365 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 394300 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 332875 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 429984 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 28 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1203009 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1101184 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11574298 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 14922836 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 373561 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 511408 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 27382103 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 370370936 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 560535931 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1349320 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1724480 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 933980667 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 8332859 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 23404111 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.344949 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.475352 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 14202655 62.97% 62.97% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 8352888 37.03% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 15330876 65.51% 65.51% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 8073235 34.49% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 22555543 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 10801104660 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 23404111 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 11646725084 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 179932994 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 158989494 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 7260511142 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 8682146940 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7881710673 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7623277083 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 172097315 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 205120292 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 311084554 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 296049290 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40536 # Transaction distribution -system.iobus.trans_dist::ReadResp 40536 # Transaction distribution -system.iobus.trans_dist::WriteReq 137093 # Transaction distribution -system.iobus.trans_dist::WriteResp 137147 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 54 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48328 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40487 # Transaction distribution +system.iobus.trans_dist::ReadResp 40487 # Transaction distribution +system.iobus.trans_dist::WriteReq 137083 # Transaction distribution +system.iobus.trans_dist::WriteResp 30163 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 106920 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48390 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2049,18 +2108,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29756 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123470 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231816 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231816 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 123480 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231580 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231580 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 355366 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48348 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 355140 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48410 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2070,18 +2129,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17674 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156485 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7355616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156518 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7351088 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7351088 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7514187 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36745000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7509692 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36789000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2101,7 +2160,7 @@ system.iobus.reqLayer16.occupancy 12000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 22142000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 22103000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) @@ -2109,678 +2168,707 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 984235192 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 1044839337 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93310000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 93320000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179557795 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 179372271 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115889 # number of replacements -system.iocache.tags.tagsinuse 11.315870 # Cycle average of tags in use +system.iocache.tags.replacements 115786 # number of replacements +system.iocache.tags.tagsinuse 11.223287 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115905 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115802 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9130394779000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.824342 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.491528 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.239021 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.468221 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.707242 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9123835798000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.412555 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.810732 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.463285 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.238171 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.701455 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1043961 # Number of tag accesses -system.iocache.tags.data_accesses 1043961 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::realview.ide 106984 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 106984 # number of WriteInvalidateReq hits +system.iocache.tags.tag_accesses 1042467 # Number of tag accesses +system.iocache.tags.data_accesses 1042467 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8924 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8961 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8870 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8907 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 54 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 54 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 106920 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 106920 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8924 # number of demand (read+write) misses -system.iocache.demand_misses::total 8964 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8870 # number of demand (read+write) misses +system.iocache.demand_misses::total 8910 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8924 # number of overall misses -system.iocache.overall_misses::total 8964 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5707000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1957100855 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1962807855 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8870 # number of overall misses +system.iocache.overall_misses::total 8910 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5627000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1958941092 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1964568092 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 357000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 357000 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 6064000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1957100855 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1963164855 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 6064000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1957100855 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1963164855 # number of overall miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28897474974 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 28897474974 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5984000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1958941092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1964925092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5984000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1958941092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1964925092 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8924 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8961 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8870 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8907 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 107038 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 107038 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 106920 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 106920 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8924 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8964 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8870 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8910 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8924 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8964 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8870 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8910 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000504 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.000504 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154243.243243 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 219307.581242 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 219038.930365 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 152081.081081 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 220850.179481 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 220564.510161 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 119000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 119000 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 151600 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 219307.581242 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 219005.450134 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 151600 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 219307.581242 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 219005.450134 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 53861 # number of cycles access was blocked +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270271.932043 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 270271.932043 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 149600 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 220850.179481 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 220530.313356 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 149600 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 220850.179481 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 220530.313356 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 225288 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 5490 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27401 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.810747 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.221890 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 106984 # number of fast writes performed +system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 106886 # number of writebacks +system.iocache.writebacks::total 106886 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8924 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8961 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8870 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8907 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106920 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 106920 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8924 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8964 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8870 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8910 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8924 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8964 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3783000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1492924359 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1496707359 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8870 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8910 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3703000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1497575112 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1501278112 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 6628374628 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6628374628 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3984000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1492924359 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1496908359 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3984000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1492924359 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1496908359 # number of overall MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23337113496 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23337113496 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3904000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1497575112 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1501479112 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3904000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1497575112 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1501479112 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102243.243243 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 167293.182317 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 167024.590894 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 100081.081081 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 168835.976550 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 168550.366229 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 167293.182317 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 166991.115462 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 167293.182317 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 166991.115462 # average overall mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218267.054770 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218267.054770 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 97600 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 168835.976550 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 168516.174186 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 97600 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 168835.976550 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 168516.174186 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1086855 # number of replacements -system.l2c.tags.tagsinuse 64099.647179 # Cycle average of tags in use -system.l2c.tags.total_refs 6672114 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1148598 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 5.808920 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 9469.927163 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 51.211523 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 68.031290 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 696.373428 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3179.738420 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 17944.005062 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 291.904824 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 401.470147 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 563.131009 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 10017.603756 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 21416.250557 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.144500 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000781 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.001038 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.010626 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.048519 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.273804 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004454 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.006126 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.008593 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.152857 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.326786 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.978083 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 31587 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 309 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 29847 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 9 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 114 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 1585 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 4136 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 25743 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::1 9 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 33 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 47 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 219 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1360 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 9152 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 19154 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.481979 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.004715 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.455429 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 80637866 # Number of tag accesses -system.l2c.tags.data_accesses 80637866 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 6250 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4321 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 142068 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 620262 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 1618371 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 6096 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 4059 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 137369 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 611754 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 1545913 # number of ReadReq hits -system.l2c.ReadReq_hits::total 4696463 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1994497 # number of Writeback hits -system.l2c.Writeback_hits::total 1994497 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 23769 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 27954 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 51723 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 7971 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 7653 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 15624 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 52432 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 49853 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 102285 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6250 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4321 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 142068 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 672694 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 1618371 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6096 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4059 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 137369 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 661607 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 1545913 # number of demand (read+write) hits -system.l2c.demand_hits::total 4798748 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6250 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4321 # number of overall hits -system.l2c.overall_hits::cpu0.inst 142068 # number of overall hits -system.l2c.overall_hits::cpu0.data 672694 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 1618371 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6096 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4059 # number of overall hits -system.l2c.overall_hits::cpu1.inst 137369 # number of overall hits -system.l2c.overall_hits::cpu1.data 661607 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 1545913 # number of overall hits -system.l2c.overall_hits::total 4798748 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 3647 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 6386 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 8946 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 136148 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 441016 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 4242 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 6837 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 8364 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 140626 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 418325 # number of ReadReq misses -system.l2c.ReadReq_misses::total 1174537 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 34627 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 36381 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 71008 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 10699 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 11055 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 21754 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 78297 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 72282 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 150579 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 3647 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 6386 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 8946 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 214445 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 441016 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 4242 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 6837 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 8364 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 212908 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 418325 # number of demand (read+write) misses -system.l2c.demand_misses::total 1325116 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 3647 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 6386 # number of overall misses -system.l2c.overall_misses::cpu0.inst 8946 # number of overall misses -system.l2c.overall_misses::cpu0.data 214445 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 441016 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 4242 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 6837 # 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number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 5871000 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1994497 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1994497 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 58396 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 64335 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 122731 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 18670 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 18708 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 37378 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 130729 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 122135 # 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Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 56.991260 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 77.146603 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 791.679733 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4513.780403 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 23818.675732 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 150.211809 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 222.184258 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 784.998757 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 7219.989726 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 17043.373589 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.152562 # 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Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 38915 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 205 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 24150 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::0 26 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 26 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 487 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 8729 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 29647 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 188 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 550 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5282 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 18136 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.593796 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.003128 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.368500 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 74054042 # Number of tag accesses +system.l2c.tags.data_accesses 74054042 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 5514 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4407 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 131001 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 549137 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 1653135 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 7096 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6374 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 146834 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 607953 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 1853450 # number of ReadReq hits +system.l2c.ReadReq_hits::total 4964901 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 2477309 # number of Writeback hits +system.l2c.Writeback_hits::total 2477309 # number of Writeback hits +system.l2c.WriteInvalidateReq_hits::cpu0.data 3452 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::cpu1.data 4029 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::total 7481 # number of WriteInvalidateReq hits +system.l2c.UpgradeReq_hits::cpu0.data 31717 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 34608 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 66325 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 7299 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 8593 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 15892 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 45918 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 59655 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 105573 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 5514 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4407 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 131001 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 595055 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 1653135 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 7096 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 6374 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 146834 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 667608 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 1853450 # number of demand (read+write) hits +system.l2c.demand_hits::total 5070474 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 5514 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4407 # number of overall hits +system.l2c.overall_hits::cpu0.inst 131001 # number of overall hits +system.l2c.overall_hits::cpu0.data 595055 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 1653135 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 7096 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 6374 # number of overall hits +system.l2c.overall_hits::cpu1.inst 146834 # number of overall hits +system.l2c.overall_hits::cpu1.data 667608 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 1853450 # number of overall hits +system.l2c.overall_hits::total 5070474 # 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average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 78305.495326 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 66345.843103 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130959.913250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68277.223160 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 69117.242978 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75753.096273 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65448.777271 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104660.132462 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 110391.140090 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 69087.434095 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 73156.250000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 78305.495326 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 66345.843103 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130959.913250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68277.223160 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 69117.242978 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75753.096273 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65448.777271 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104660.132462 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 110391.140090 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -2795,58 +2883,58 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 1264717 # Transaction distribution -system.membus.trans_dist::ReadResp 1264717 # Transaction distribution -system.membus.trans_dist::WriteReq 38516 # Transaction distribution -system.membus.trans_dist::WriteResp 38516 # Transaction distribution -system.membus.trans_dist::Writeback 686491 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 1679861 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 1679861 # Transaction distribution -system.membus.trans_dist::UpgradeReq 316703 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 302467 # Transaction distribution -system.membus.trans_dist::UpgradeResp 96183 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 163141 # Transaction distribution -system.membus.trans_dist::ReadExResp 147161 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123470 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 1327465 # Transaction distribution +system.membus.trans_dist::ReadResp 1327465 # Transaction distribution +system.membus.trans_dist::WriteReq 37863 # Transaction distribution +system.membus.trans_dist::WriteResp 37863 # Transaction distribution +system.membus.trans_dist::Writeback 1017207 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 119813 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 119813 # Transaction distribution +system.membus.trans_dist::UpgradeReq 367379 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 281461 # Transaction distribution +system.membus.trans_dist::UpgradeResp 85028 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution +system.membus.trans_dist::ReadExReq 87184 # Transaction distribution +system.membus.trans_dist::ReadExResp 72708 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123480 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25330 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 7297543 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 7446435 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 230140 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 230140 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7676575 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156485 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 22714 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4395675 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4541961 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336541 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 336541 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4878502 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156518 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50660 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 229346740 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 229554089 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7308288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7308288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 236862377 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 540732 # Total snoops (count) -system.membus.snoop_fanout::samples 4331622 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 45428 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 143082804 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 143284954 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14125504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14125504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 157410458 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 581037 # Total snoops (count) +system.membus.snoop_fanout::samples 3119395 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 4331622 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3119395 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4331622 # Request fanout histogram -system.membus.reqLayer0.occupancy 101146499 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3119395 # Request fanout histogram +system.membus.reqLayer0.occupancy 101251489 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 55500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 22031996 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 19693498 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 23154905719 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 11963097483 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 14237686781 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 12443113804 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 187996205 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 187409729 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -2857,11 +2945,11 @@ system.realview.ethernet.descDMAReads 0 # Nu system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 162 # Total Bandwidth (bits/s) +system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 162 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -2890,45 +2978,45 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 6727338 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 6719778 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38516 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38516 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 1994497 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 1679869 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 1572877 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 365008 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 318091 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 683099 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 80 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 80 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 301724 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 301724 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10020344 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 9267363 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 19287707 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 322818441 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 297911776 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 620730217 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1454894 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 11304872 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.010257 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.100757 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 7096727 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 7089473 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 37863 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 37863 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 2477309 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 127465 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 20542 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 430421 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 297353 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 727774 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 53 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 228196 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 228196 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8832957 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8435767 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17268724 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 294458407 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 274483891 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 568942298 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1532220 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 10576474 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.010952 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.104077 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 11188916 98.97% 98.97% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115956 1.03% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 10460641 98.90% 98.90% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115833 1.10% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 11304872 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 19960086799 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 10576474 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 15316484616 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 6306000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 7440499 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 16653624789 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 16737915607 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 15972471023 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 16438547163 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |